121 lines
4.9 KiB
Plaintext
121 lines
4.9 KiB
Plaintext
/*!
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*****************************************************************************
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@file: AD5940_WGSin_LPDAC.c
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@author: $Author: nxu2 $
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@brief: Waveform generator(sin wave) example using LPDAC.
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@version: $Revision: 766 $
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@date: $Date: 2017-08-21 14:09:35 +0100 (Mon, 21 Aug 2017) $
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-----------------------------------------------------------------------------
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Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved.
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This software is proprietary to Analog Devices, Inc. and its licensors.
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By using this software you agree to the terms of the associated
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Analog Devices Software License Agreement.
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*****************************************************************************/
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#include "ad5940.h"
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#include <stdio.h>
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#include "string.h"
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/**
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* This example is to generate sin wave on pin CE0 using waveform generator and LPDAC.
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* Signal generator simpley generates digital codes. The code can route to both
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* HSDAC and LPDAC. So, we can generate sin wave using both DAC.
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*
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* @note: LPDAC has limited bandwidth, do not use it to generate signal above 300Hz,
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* otherwise, you will see significant performance drop.
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* The DAC update rate parameter is decided by register HSDACCON.Rate. This also true
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* when using LPDAC as data sink.
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*/
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#define SIN_AMPLITUDE 1100.0 /**< Signal amplitude in mV.*/
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#define SIN_FREQ 100.0 /**< 100Hz. Max is 300Hz */
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#define WG_CLOCK_HZ 32e3f /**< Waveform generator clock frequency. Equal to system clock. */
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void AD5940_Main(void)
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{
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AFERefCfg_Type aferef_cfg;
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CLKCfg_Type clk_cfg;
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LPDACCfg_Type lpdac_cfg;
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WGCfg_Type WgCfg;
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LPAmpCfg_Type lpamp_cfg;
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HSDACCfg_Type HsDacCfg;
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/* Use hardware reset */
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AD5940_HWReset();
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AD5940_Initialize();
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clk_cfg.ADCClkDiv = ADCCLKDIV_1;
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clk_cfg.ADCCLkSrc = ADCCLKSRC_HFOSC;
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clk_cfg.SysClkDiv = SYSCLKDIV_1;
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clk_cfg.SysClkSrc = SYSCLKSRC_HFOSC;
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clk_cfg.HfOSC32MHzMode = bFALSE;
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clk_cfg.HFOSCEn = bTRUE;
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clk_cfg.HFXTALEn = bFALSE;
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clk_cfg.LFOSCEn = bTRUE;
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AD5940_CLKCfg(&clk_cfg);
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aferef_cfg.HpBandgapEn = bTRUE;
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aferef_cfg.Hp1V1BuffEn = bTRUE;
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aferef_cfg.Hp1V8BuffEn = bTRUE;
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aferef_cfg.Disc1V1Cap = bFALSE;
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aferef_cfg.Disc1V8Cap = bFALSE;
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aferef_cfg.Hp1V8ThemBuff = bFALSE;
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aferef_cfg.Hp1V8Ilimit = bFALSE;
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aferef_cfg.Lp1V1BuffEn = bFALSE;
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aferef_cfg.Lp1V8BuffEn = bFALSE;
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/* LP reference control */
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aferef_cfg.LpBandgapEn = bTRUE;
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aferef_cfg.LpRefBufEn = bTRUE;
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aferef_cfg.LpRefBoostEn = bFALSE;
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AD5940_REFCfgS(&aferef_cfg);
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/* Configure LPDAC*/
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lpdac_cfg.LpdacSel = LPDAC0;
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lpdac_cfg.DataRst = bFALSE;
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lpdac_cfg.LpDacSW = LPDACSW_VBIAS2LPPA/*|LPDACSW_VBIAS2PIN*/|LPDACSW_VZERO2LPTIA/*|LPDACSW_VZERO2PIN*/;
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lpdac_cfg.LpDacRef = LPDACREF_2P5; /* Use internal 2.5V reference */
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lpdac_cfg.LpDacSrc = LPDACSRC_WG; /* Use data from waveform generator */
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lpdac_cfg.LpDacVbiasMux = LPDACVBIAS_12BIT;
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lpdac_cfg.LpDacVzeroMux = LPDACVZERO_6BIT; /* Use 6bit LPDAC for Vzero */
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lpdac_cfg.PowerEn = bTRUE; /* Enable LPDAC */
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lpdac_cfg.DacData12Bit = 0; /* Don't care, 12bit DAC data is from WG */
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lpdac_cfg.DacData6Bit = 32;
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AD5940_LPDACCfgS(&lpdac_cfg);
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/* Configure low power amplifiers */
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lpamp_cfg.LpAmpSel = LPAMP0;
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lpamp_cfg.LpAmpPwrMod = LPAMPPWR_NORM; /* Use normal power mode is enough */
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lpamp_cfg.LpPaPwrEn = bTRUE; /* Enable Potential amplifier */
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lpamp_cfg.LpTiaPwrEn = bFALSE; /* TIA is not used in this example */
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lpamp_cfg.LpTiaRf = LPTIARF_1M;
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lpamp_cfg.LpTiaRload = LPTIARLOAD_100R; /* don't care */
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lpamp_cfg.LpTiaRtia = LPTIARTIA_1K; /* don't care */
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lpamp_cfg.LpTiaSW = 0; /* don't care */
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AD5940_LPAMPCfgS(&lpamp_cfg);
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HsDacCfg.ExcitBufGain = EXCITBUFGAIN_2;
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HsDacCfg.HsDacGain = HSDACGAIN_1;
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HsDacCfg.HsDacUpdateRate = 7; /* DAC update rate equals to WG_CLK/HsDacUpdateRate */
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AD5940_HSDacCfgS(&HsDacCfg);
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/* Configure Waveform Generator */
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WgCfg.WgType = WGTYPE_SIN;
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WgCfg.GainCalEn = bFALSE;
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WgCfg.OffsetCalEn = bFALSE;
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WgCfg.SinCfg.SinFreqWord = AD5940_WGFreqWordCal(SIN_FREQ, WG_CLOCK_HZ);
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WgCfg.SinCfg.SinAmplitudeWord = (uint32_t)(SIN_AMPLITUDE/1100.0f*2047);
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WgCfg.SinCfg.SinOffsetWord = 0;
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WgCfg.SinCfg.SinPhaseWord = 0;
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AD5940_WGCfgS(&WgCfg);
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AD5940_AFEPwrBW(AFEPWR_LP, AFEBW_AUTOSET);
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AD5940_AFECtrlS(AFECTRL_WG, bTRUE);
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/* Change to 32kHz clock. LPDAC needs 32kHz clock for waveform generator */
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AD5940_LPModeEnS(bTRUE); /* Enter LP control mode. The registers are summarized to LPMODECON, so we can control some blocks conveniently */
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AD5940_LPModeClkS(LPMODECLK_LFOSC); /* Trigger switching system clock to 32kHz */
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AD5940_LPModeCtrlS(LPMODECTRL_NONE); /* Disable all */
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AD5940_LPModeCtrlS(LPMODECTRL_GLBBIASZ|LPMODECTRL_GLBBIASP|LPMODECTRL_HPREFPWR|LPMODECTRL_BUFHP1P8V|LPMODECTRL_BUFHP1P1V|LPMODECTRL_HFOSCEN);
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while(1);
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}
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