diff --git a/drv.min.h b/.drv.min.h similarity index 100% rename from drv.min.h rename to .drv.min.h diff --git a/.gitignore b/.gitignore index a8e89e0..96c3b29 100644 --- a/.gitignore +++ b/.gitignore @@ -6,7 +6,7 @@ build *.swp *.cmake requirements.txt -ad5940* +ad5940.c pico_sdk_import.cmake build* *.png diff --git a/CMakeLists.txt b/CMakeLists.txt index 7064e15..674e000 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,25 +1,23 @@ # File: CMakeLists.txt - cmake_minimum_required(VERSION 3.13) include(pico_sdk_import.cmake) project(EIS C CXX ASM) + set(CMAKE_C_STANDARD 11) set(CMAKE_CXX_STANDARD 17) pico_sdk_init() -# Add ad5940.c to the build +# Changed main.cpp to main.c add_executable(EIS main.c ad5940.c ) -# Define CHIPSEL_594X for the library target_compile_definitions(EIS PRIVATE CHIPSEL_594X) -# REQUIRED: Tell CMake where to find headers target_include_directories(EIS PRIVATE ${CMAKE_CURRENT_LIST_DIR}) target_link_libraries(EIS diff --git a/ad5940.h b/ad5940.h new file mode 100644 index 0000000..9ff35a3 --- /dev/null +++ b/ad5940.h @@ -0,0 +1,4950 @@ +/** + * @file ad5940.h + * @brief AD5940 library. This file contains all AD5940 library functions. + * @author ADI + * @date March 2019 + * @par Revision History: + * + * Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + * + * This software is proprietary to Analog Devices, Inc. and its licensors. + * By using this software you agree to the terms of the associated + * Analog Devices Software License Agreement. +**/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifndef _AD5940_H_ +#define _AD5940_H_ +#include "math.h" +#include "string.h" +#include "stdio.h" +/** @addtogroup AD5940_Library + * @{ + */ + +/** + * Select the correct chip. + * Recommend to define this in your compiler. + * */ +//#define CHIPSEL_M355 /**< ADuCM355 */ +//#define CHIPSEL_594X /**< AD5940 or AD5941 */ + +/* library version number */ +#define AD5940LIB_VER_MAJOR 0 /**< Major number */ +#define AD5940LIB_VER_MINOR 2 /**< Minor number */ +#define AD5940LIB_VER_PATCH 1 /**< Path number */ +#define AD5940LIB_VER (AD5940LIB_VER_MAJOR<<16)|(AD5940LIB_VER_MINOR<<8)|(AD5940LIB_VER_PATCH) + +#define ADI_DEBUG /**< Comment this line to remove debug info. */ + +#ifdef ADI_DEBUG +#define ADI_Print printf /**< Select the method to print out debug message */ +#endif + +#if defined(CHIPSEL_M355) && defined(CHIPSEL_594X) +#error Please select the correct chip by define CHIPSEL_M355 or CHIPSEL_594X. +#endif + +#if !defined(CHIPSEL_M355) && !defined(CHIPSEL_594X) +#error Please select the correct chip by define CHIPSEL_M355 or CHIPSEL_594X. +#endif + +/** + * @cond + * @defgroup AD5940RegistersBitfields + * @brief All AD5940 registers and bitfields definition. + * @{ +*/ +//#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +//#endif /* _LANGUAGE_C */ + +#ifndef __ADI_GENERATED_DEF_HEADERS__ +#define __ADI_GENERATED_DEF_HEADERS__ 1 +#endif + +#define __ADI_HAS_AGPIO__ 1 +#define __ADI_HAS_ALLON__ 1 +#define __ADI_HAS_INTC__ 1 +#define __ADI_HAS_AFECON__ 1 +#define __ADI_HAS_WUPTMR__ 1 +#define __ADI_HAS_AFE__ 1 + +/* ============================================================================================================================ + GPIO + ============================================================================================================================ */ + +/* ============================================================================================================================ + AGPIO + ============================================================================================================================ */ +#define REG_AGPIO_GP0CON_RESET 0x00000000 /* Reset Value for GP0CON */ +#define REG_AGPIO_GP0CON 0x00000000 /* AGPIO GPIO Port 0 Configuration */ +#define REG_AGPIO_GP0OEN_RESET 0x00000000 /* Reset Value for GP0OEN */ +#define REG_AGPIO_GP0OEN 0x00000004 /* AGPIO GPIO Port 0 Output Enable */ +#define REG_AGPIO_GP0PE_RESET 0x00000000 /* Reset Value for GP0PE */ +#define REG_AGPIO_GP0PE 0x00000008 /* AGPIO GPIO Port 0 Pullup/Pulldown Enable */ +#define REG_AGPIO_GP0IEN_RESET 0x00000000 /* Reset Value for GP0IEN */ +#define REG_AGPIO_GP0IEN 0x0000000C /* AGPIO GPIO Port 0 Input Path Enable */ +#define REG_AGPIO_GP0IN_RESET 0x00000000 /* Reset Value for GP0IN */ +#define REG_AGPIO_GP0IN 0x00000010 /* AGPIO GPIO Port 0 Registered Data Input */ +#define REG_AGPIO_GP0OUT_RESET 0x00000000 /* Reset Value for GP0OUT */ +#define REG_AGPIO_GP0OUT 0x00000014 /* AGPIO GPIO Port 0 Data Output */ +#define REG_AGPIO_GP0SET_RESET 0x00000000 /* Reset Value for GP0SET */ +#define REG_AGPIO_GP0SET 0x00000018 /* AGPIO GPIO Port 0 Data Out Set */ +#define REG_AGPIO_GP0CLR_RESET 0x00000000 /* Reset Value for GP0CLR */ +#define REG_AGPIO_GP0CLR 0x0000001C /* AGPIO GPIO Port 0 Data Out Clear */ +#define REG_AGPIO_GP0TGL_RESET 0x00000000 /* Reset Value for GP0TGL */ +#define REG_AGPIO_GP0TGL 0x00000020 /* AGPIO GPIO Port 0 Pin Toggle */ + +/* ============================================================================================================================ + AGPIO Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0CON_PIN7CFG 14 /* P0.7 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN6CFG 12 /* P0.6 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN5CFG 10 /* P0.5 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN4CFG 8 /* P0.4 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN3CFG 6 /* P0.3 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN2CFG 4 /* P0.2 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN1CFG 2 /* P0.1 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN0CFG 0 /* P0.0 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN7CFG 0x0000C000 /* P0.7 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN6CFG 0x00003000 /* P0.6 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN5CFG 0x00000C00 /* P0.5 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN4CFG 0x00000300 /* P0.4 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN3CFG 0x000000C0 /* P0.3 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN2CFG 0x00000030 /* P0.2 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN1CFG 0x0000000C /* P0.1 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN0CFG 0x00000003 /* P0.0 Configuration Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0OEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0OEN_OEN 0 /* Pin Output Drive Enable */ +#define BITM_AGPIO_GP0OEN_OEN 0x000000FF /* Pin Output Drive Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0PE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0PE_PE 0 /* Pin Pull Enable */ +#define BITM_AGPIO_GP0PE_PE 0x000000FF /* Pin Pull Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0IEN_IEN 0 /* Input Path Enable */ +#define BITM_AGPIO_GP0IEN_IEN 0x000000FF /* Input Path Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0IN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0IN_IN 0 /* Registered Data Input */ +#define BITM_AGPIO_GP0IN_IN 0x000000FF /* Registered Data Input */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0OUT_OUT 0 /* Data Out */ +#define BITM_AGPIO_GP0OUT_OUT 0x000000FF /* Data Out */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0SET_SET 0 /* Set the Output HIGH */ +#define BITM_AGPIO_GP0SET_SET 0x000000FF /* Set the Output HIGH */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0CLR_CLR 0 /* Set the Output LOW */ +#define BITM_AGPIO_GP0CLR_CLR 0x000000FF /* Set the Output LOW */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0TGL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0TGL_TGL 0 /* Toggle the Output */ +#define BITM_AGPIO_GP0TGL_TGL 0x000000FF /* Toggle the Output */ + + +/* ============================================================================================================================ + + ============================================================================================================================ */ + +/* ============================================================================================================================ + AFECON + ============================================================================================================================ */ +#define REG_AFECON_ADIID_RESET 0x00000000 /* Reset Value for ADIID */ +#define REG_AFECON_ADIID 0x00000400 /* AFECON ADI Identification */ +#define REG_AFECON_CHIPID_RESET 0x00000000 /* Reset Value for CHIPID */ +#define REG_AFECON_CHIPID 0x00000404 /* AFECON Chip Identification */ +#define REG_AFECON_CLKCON0_RESET 0x00000441 /* Reset Value for CLKCON0 */ +#define REG_AFECON_CLKCON0 0x00000408 /* AFECON Clock Divider Configuration */ +#define REG_AFECON_CLKEN1_RESET 0x000002C0 /* Reset Value for CLKEN1 */ +#define REG_AFECON_CLKEN1 0x00000410 /* AFECON Clock Gate Enable */ +#define REG_AFECON_CLKSEL_RESET 0x00000000 /* Reset Value for CLKSEL */ +#define REG_AFECON_CLKSEL 0x00000414 /* AFECON Clock Select */ +#define REG_AFECON_CLKCON0KEY_RESET 0x00000000 /* Reset Value for CLKCON0KEY */ +#define REG_AFECON_CLKCON0KEY 0x00000420 /* AFECON Enable Clock Division to 8Mhz,4Mhz and 2Mhz */ +#define REG_AFECON_SWRSTCON_RESET 0x00000001 /* Reset Value for SWRSTCON */ +#define REG_AFECON_SWRSTCON 0x00000424 /* AFECON Software Reset */ +#define REG_AFECON_TRIGSEQ_RESET 0x00000000 /* Reset Value for TRIGSEQ */ +#define REG_AFECON_TRIGSEQ 0x00000430 /* AFECON Trigger Sequence */ + +/* ============================================================================================================================ + AFECON Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_ADIID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_ADIID_ADIID 0 /* ADI Identifier. */ +#define BITM_AFECON_ADIID_ADIID 0x0000FFFF /* ADI Identifier. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CHIPID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_CHIPID_PARTID 4 /* Part Identifier */ +#define BITP_AFECON_CHIPID_REVISION 0 /* Silicon Revision Number */ +#define BITM_AFECON_CHIPID_PARTID 0x0000FFF0 /* Part Identifier */ +#define BITM_AFECON_CHIPID_REVISION 0x0000000F /* Silicon Revision Number */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKCON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_CLKCON0_SFFTCLKDIVCNT 10 /* SFFT Clock Divider Configuration */ +#define BITP_AFECON_CLKCON0_ADCCLKDIV 6 /* ADC Clock Divider Configuration */ +#define BITP_AFECON_CLKCON0_SYSCLKDIV 0 /* System Clock Divider Configuration */ +#define BITM_AFECON_CLKCON0_SFFTCLKDIVCNT 0x0000FC00 /* SFFT Clock Divider Configuration */ +#define BITM_AFECON_CLKCON0_ADCCLKDIV 0x000003C0 /* ADC Clock Divider Configuration */ +#define BITM_AFECON_CLKCON0_SYSCLKDIV 0x0000003F /* System Clock Divider Configuration */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKEN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_CLKEN1_GPT1DIS 7 /* GPT1 Clock Enable */ +#define BITP_AFECON_CLKEN1_GPT0DIS 6 /* GPT0 Clock Enable */ +#define BITP_AFECON_CLKEN1_ACLKDIS 5 /* ACLK Clock Enable */ +#define BITM_AFECON_CLKEN1_GPT1DIS 0x00000080 /* GPT1 Clock Enable */ +#define BITM_AFECON_CLKEN1_GPT0DIS 0x00000040 /* GPT0 Clock Enable */ +#define BITM_AFECON_CLKEN1_ACLKDIS 0x00000020 /* ACLK Clock Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKSEL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_CLKSEL_ADCCLKSEL 2 /* Select ADC Clock Source */ +#define BITP_AFECON_CLKSEL_SYSCLKSEL 0 /* Select System Clock Source */ +#define BITM_AFECON_CLKSEL_ADCCLKSEL 0x0000000C /* Select ADC Clock Source */ +#define BITM_AFECON_CLKSEL_SYSCLKSEL 0x00000003 /* Select System Clock Source */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKCON0KEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_CLKCON0KEY_DIVSYSCLK_ULP_EN 0 /* Enable Clock Division to 8Mhz,4Mhz and 2Mhz */ +#define BITM_AFECON_CLKCON0KEY_DIVSYSCLK_ULP_EN 0x0000FFFF /* Enable Clock Division to 8Mhz,4Mhz and 2Mhz */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_SWRSTCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_SWRSTCON_SWRSTL 0 /* Software Reset */ +#define BITM_AFECON_SWRSTCON_SWRSTL 0x0000FFFF /* Software Reset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_TRIGSEQ Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_TRIGSEQ_TRIG3 3 /* Trigger Sequence 3 */ +#define BITP_AFECON_TRIGSEQ_TRIG2 2 /* Trigger Sequence 2 */ +#define BITP_AFECON_TRIGSEQ_TRIG1 1 /* Trigger Sequence 1 */ +#define BITP_AFECON_TRIGSEQ_TRIG0 0 /* Trigger Sequence 0 */ +#define BITM_AFECON_TRIGSEQ_TRIG3 0x00000008 /* Trigger Sequence 3 */ +#define BITM_AFECON_TRIGSEQ_TRIG2 0x00000004 /* Trigger Sequence 2 */ +#define BITM_AFECON_TRIGSEQ_TRIG1 0x00000002 /* Trigger Sequence 1 */ +#define BITM_AFECON_TRIGSEQ_TRIG0 0x00000001 /* Trigger Sequence 0 */ + +/* ============================================================================================================================ + AFEWDT + ============================================================================================================================ */ +#define REG_AFEWDT_WDTLD 0x00000900 /* AFEWDT Watchdog Timer Load Value */ +#define REG_AFEWDT_WDTVALS 0x00000904 /* AFEWDT Current Count Value */ +#define REG_AFEWDT_WDTCON 0x00000908 /* AFEWDT Watchdog Timer Control Register */ +#define REG_AFEWDT_WDTCLRI 0x0000090C /* AFEWDT Refresh Watchdog Register */ +#define REG_AFEWDT_WDTSTA 0x00000918 /* AFEWDT Timer Status */ +#define REG_AFEWDT_WDTMINLD 0x0000091C /* AFEWDT Minimum Load Value */ + +/* ============================================================================================================================ + AFEWDT Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTLD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFEWDT_WDTLD_LOAD 0 /* WDT Load Value */ +#define BITM_AFEWDT_WDTLD_LOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* WDT Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTVALS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFEWDT_WDTVALS_CCOUNT 0 /* Current WDT Count Value. */ +#define BITM_AFEWDT_WDTVALS_CCOUNT (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Current WDT Count Value. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFEWDT_WDTCON_RESERVED_15_11 11 /* RESERVED */ +#define BITP_AFEWDT_WDTCON_WDTIRQEN 10 /* WDT Interrupt Enable */ +#define BITP_AFEWDT_WDTCON_MINLOAD_EN 9 /* Timer Window Control */ +#define BITP_AFEWDT_WDTCON_CLKDIV2 8 /* Clock Source */ +#define BITP_AFEWDT_WDTCON_RESERVED1_7 7 /* Reserved */ +#define BITP_AFEWDT_WDTCON_MDE 6 /* Timer Mode Select */ +#define BITP_AFEWDT_WDTCON_EN 5 /* Timer Enable */ +#define BITP_AFEWDT_WDTCON_PRE 2 /* Prescaler. */ +#define BITP_AFEWDT_WDTCON_IRQ 1 /* WDT Interrupt Enable */ +#define BITP_AFEWDT_WDTCON_PDSTOP 0 /* Power Down Stop Enable */ +#define BITM_AFEWDT_WDTCON_RESERVED_15_11 (_ADI_MSK_3(0x0000F800,0x0000F800U, uint16_t )) /* RESERVED */ +#define BITM_AFEWDT_WDTCON_WDTIRQEN (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* WDT Interrupt Enable */ +#define BITM_AFEWDT_WDTCON_MINLOAD_EN (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Timer Window Control */ +#define BITM_AFEWDT_WDTCON_CLKDIV2 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Clock Source */ +#define BITM_AFEWDT_WDTCON_RESERVED1_7 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Reserved */ +#define BITM_AFEWDT_WDTCON_MDE (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Mode Select */ +#define BITM_AFEWDT_WDTCON_EN (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Timer Enable */ +#define BITM_AFEWDT_WDTCON_PRE (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* Prescaler. */ +#define BITM_AFEWDT_WDTCON_IRQ (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* WDT Interrupt Enable */ +#define BITM_AFEWDT_WDTCON_PDSTOP (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Power Down Stop Enable */ +#define ENUM_AFEWDT_WDTCON_RESET (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* IRQ: Watchdog Timer timeout creates a reset. */ +#define ENUM_AFEWDT_WDTCON_INTERRUPT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* IRQ: Watchdog Timer timeout creates an interrupt instead of reset. */ +#define ENUM_AFEWDT_WDTCON_CONTINUE (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* PDSTOP: Continue Counting When In Hibernate */ +#define ENUM_AFEWDT_WDTCON_STOP (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PDSTOP: Stop Counter When In Hibernate. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTCLRI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFEWDT_WDTCLRI_CLRWDG 0 /* Refresh Register */ +#define BITM_AFEWDT_WDTCLRI_CLRWDG (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Refresh Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFEWDT_WDTSTA_RESERVED_15_7 7 /* RESERVED */ +#define BITP_AFEWDT_WDTSTA_TMINLD 6 /* WDTMINLD Write Status */ +#define BITP_AFEWDT_WDTSTA_OTPWRDONE 5 /* Reset Type Status */ +#define BITP_AFEWDT_WDTSTA_LOCK 4 /* Lock Status */ +#define BITP_AFEWDT_WDTSTA_CON 3 /* WDTCON Write Status */ +#define BITP_AFEWDT_WDTSTA_TLD 2 /* WDTVAL Write Status */ +#define BITP_AFEWDT_WDTSTA_CLRI 1 /* WDTCLRI Write Status */ +#define BITP_AFEWDT_WDTSTA_IRQ 0 /* WDT Interrupt */ +#define BITM_AFEWDT_WDTSTA_RESERVED_15_7 (_ADI_MSK_3(0x0000FF80,0x0000FF80U, uint16_t )) /* RESERVED */ +#define BITM_AFEWDT_WDTSTA_TMINLD (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* WDTMINLD Write Status */ +#define BITM_AFEWDT_WDTSTA_OTPWRDONE (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Reset Type Status */ +#define BITM_AFEWDT_WDTSTA_LOCK (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Lock Status */ +#define BITM_AFEWDT_WDTSTA_CON (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* WDTCON Write Status */ +#define BITM_AFEWDT_WDTSTA_TLD (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* WDTVAL Write Status */ +#define BITM_AFEWDT_WDTSTA_CLRI (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* WDTCLRI Write Status */ +#define BITM_AFEWDT_WDTSTA_IRQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* WDT Interrupt */ +#define ENUM_AFEWDT_WDTSTA_OPEN (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* LOCK: Timer Operation Not Locked */ +#define ENUM_AFEWDT_WDTSTA_LOCKED (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* LOCK: Timer Enabled and Locked */ +#define ENUM_AFEWDT_WDTSTA_SYNC_COMPLETE (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* TLD: Arm and AFE Watchdog Clock Domains WDTLD values match */ +#define ENUM_AFEWDT_WDTSTA_SYNC_IN_PROGRESS (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* TLD: Synchronize In Progress */ +#define ENUM_AFEWDT_WDTSTA_CLEARED (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* IRQ: Watchdog Timer Interrupt Not Pending */ +#define ENUM_AFEWDT_WDTSTA_PENDING (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* IRQ: Watchdog Timer Interrupt Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTMINLD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFEWDT_WDTMINLD_MIN_LOAD 0 /* WDT Min Load Value */ +#define BITM_AFEWDT_WDTMINLD_MIN_LOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* WDT Min Load Value */ + +/* ============================================================================================================================ + Wakeup Timer + ============================================================================================================================ */ + +/* ============================================================================================================================ + WUPTMR + ============================================================================================================================ */ +#define REG_WUPTMR_CON_RESET 0x00000000 /* Reset Value for CON */ +#define REG_WUPTMR_CON 0x00000800 /* WUPTMR Timer Control */ +#define REG_WUPTMR_SEQORDER_RESET 0x00000000 /* Reset Value for SEQORDER */ +#define REG_WUPTMR_SEQORDER 0x00000804 /* WUPTMR Order Control */ +#define REG_WUPTMR_SEQ0WUPL_RESET 0x0000FFFF /* Reset Value for SEQ0WUPL */ +#define REG_WUPTMR_SEQ0WUPL 0x00000808 /* WUPTMR SEQ0 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ0WUPH_RESET 0x0000000F /* Reset Value for SEQ0WUPH */ +#define REG_WUPTMR_SEQ0WUPH 0x0000080C /* WUPTMR SEQ0 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ0SLEEPL_RESET 0x0000FFFF /* Reset Value for SEQ0SLEEPL */ +#define REG_WUPTMR_SEQ0SLEEPL 0x00000810 /* WUPTMR SEQ0 STimeL (LSB) */ +#define REG_WUPTMR_SEQ0SLEEPH_RESET 0x0000000F /* Reset Value for SEQ0SLEEPH */ +#define REG_WUPTMR_SEQ0SLEEPH 0x00000814 /* WUPTMR SEQ0 STimeH (MSB) */ +#define REG_WUPTMR_SEQ1WUPL_RESET 0x0000FFFF /* Reset Value for SEQ1WUPL */ +#define REG_WUPTMR_SEQ1WUPL 0x00000818 /* WUPTMR SEQ1 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ1WUPH_RESET 0x0000000F /* Reset Value for SEQ1WUPH */ +#define REG_WUPTMR_SEQ1WUPH 0x0000081C /* WUPTMR SEQ1 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ1SLEEPL_RESET 0x0000FFFF /* Reset Value for SEQ1SLEEPL */ +#define REG_WUPTMR_SEQ1SLEEPL 0x00000820 /* WUPTMR SEQ1 STimeL (LSB) */ +#define REG_WUPTMR_SEQ1SLEEPH_RESET 0x0000000F /* Reset Value for SEQ1SLEEPH */ +#define REG_WUPTMR_SEQ1SLEEPH 0x00000824 /* WUPTMR SEQ1 STimeH (MSB) */ +#define REG_WUPTMR_SEQ2WUPL_RESET 0x0000FFFF /* Reset Value for SEQ2WUPL */ +#define REG_WUPTMR_SEQ2WUPL 0x00000828 /* WUPTMR SEQ2 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ2WUPH_RESET 0x0000000F /* Reset Value for SEQ2WUPH */ +#define REG_WUPTMR_SEQ2WUPH 0x0000082C /* WUPTMR SEQ2 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ2SLEEPL_RESET 0x0000FFFF /* Reset Value for SEQ2SLEEPL */ +#define REG_WUPTMR_SEQ2SLEEPL 0x00000830 /* WUPTMR SEQ2 STimeL (LSB) */ +#define REG_WUPTMR_SEQ2SLEEPH_RESET 0x0000000F /* Reset Value for SEQ2SLEEPH */ +#define REG_WUPTMR_SEQ2SLEEPH 0x00000834 /* WUPTMR SEQ2 STimeH (MSB) */ +#define REG_WUPTMR_SEQ3WUPL_RESET 0x0000FFFF /* Reset Value for SEQ3WUPL */ +#define REG_WUPTMR_SEQ3WUPL 0x00000838 /* WUPTMR SEQ3 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ3WUPH_RESET 0x0000000F /* Reset Value for SEQ3WUPH */ +#define REG_WUPTMR_SEQ3WUPH 0x0000083C /* WUPTMR SEQ3 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ3SLEEPL_RESET 0x0000FFFF /* Reset Value for SEQ3SLEEPL */ +#define REG_WUPTMR_SEQ3SLEEPL 0x00000840 /* WUPTMR SEQ3 STimeL (LSB) */ +#define REG_WUPTMR_SEQ3SLEEPH_RESET 0x0000000F /* Reset Value for SEQ3SLEEPH */ +#define REG_WUPTMR_SEQ3SLEEPH 0x00000844 /* WUPTMR SEQ3 STimeH (MSB) */ + +/* ============================================================================================================================ + WUPTMR Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_CON_MSKTRG 6 /* Mark Sequence Trigger from Sleep Wakeup Timer */ +#define BITP_WUPTMR_CON_CLKSEL 4 /* Clock Selection */ +#define BITP_WUPTMR_CON_ENDSEQ 1 /* End Sequence */ +#define BITP_WUPTMR_CON_EN 0 /* Sleep Wake Timer Enable Bit */ +#define BITM_WUPTMR_CON_MSKTRG 0x00000040 /* Mark Sequence Trigger from Sleep Wakeup Timer */ +#define BITM_WUPTMR_CON_CLKSEL 0x00000030 /* Clock Selection */ +#define BITM_WUPTMR_CON_ENDSEQ 0x0000000E /* End Sequence */ +#define BITM_WUPTMR_CON_EN 0x00000001 /* Sleep Wake Timer Enable Bit */ +#define ENUM_WUPTMR_CON_SWT32K0 0x00000000 /* CLKSEL: Internal 32kHz OSC */ +#define ENUM_WUPTMR_CON_SWTEXT0 0x00000010 /* CLKSEL: External Clock */ +#define ENUM_WUPTMR_CON_SWT32K 0x00000020 /* CLKSEL: Internal 32kHz OSC */ +#define ENUM_WUPTMR_CON_SWTEXT 0x00000030 /* CLKSEL: External Clock */ +#define ENUM_WUPTMR_CON_ENDSEQA 0x00000000 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqA And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQB 0x00000002 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqB And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQC 0x00000004 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqC And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQD 0x00000006 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqD And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQE 0x00000008 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqE And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQF 0x0000000A /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqF And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQG 0x0000000C /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqG And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQH 0x0000000E /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqH And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_SWTEN 0x00000000 /* EN: Enable Sleep Wakeup Timer */ +#define ENUM_WUPTMR_CON_SWTDIS 0x00000001 /* EN: Disable Sleep Wakeup Timer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQORDER Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQORDER_SEQH 14 /* SEQH Config */ +#define BITP_WUPTMR_SEQORDER_SEQG 12 /* SEQG Config */ +#define BITP_WUPTMR_SEQORDER_SEQF 10 /* SEQF Config */ +#define BITP_WUPTMR_SEQORDER_SEQE 8 /* SEQE Config */ +#define BITP_WUPTMR_SEQORDER_SEQD 6 /* SEQD Config */ +#define BITP_WUPTMR_SEQORDER_SEQC 4 /* SEQC Config */ +#define BITP_WUPTMR_SEQORDER_SEQB 2 /* SEQB Config */ +#define BITP_WUPTMR_SEQORDER_SEQA 0 /* SEQA Config */ +#define BITM_WUPTMR_SEQORDER_SEQH 0x0000C000 /* SEQH Config */ +#define BITM_WUPTMR_SEQORDER_SEQG 0x00003000 /* SEQG Config */ +#define BITM_WUPTMR_SEQORDER_SEQF 0x00000C00 /* SEQF Config */ +#define BITM_WUPTMR_SEQORDER_SEQE 0x00000300 /* SEQE Config */ +#define BITM_WUPTMR_SEQORDER_SEQD 0x000000C0 /* SEQD Config */ +#define BITM_WUPTMR_SEQORDER_SEQC 0x00000030 /* SEQC Config */ +#define BITM_WUPTMR_SEQORDER_SEQB 0x0000000C /* SEQB Config */ +#define BITM_WUPTMR_SEQORDER_SEQA 0x00000003 /* SEQA Config */ +#define ENUM_WUPTMR_SEQORDER_SEQH0 0x00000000 /* SEQH: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQH1 0x00004000 /* SEQH: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQH2 0x00008000 /* SEQH: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQH3 0x0000C000 /* SEQH: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG0 0x00000000 /* SEQG: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG1 0x00001000 /* SEQG: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG2 0x00002000 /* SEQG: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG3 0x00003000 /* SEQG: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF0 0x00000000 /* SEQF: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF1 0x00000400 /* SEQF: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF2 0x00000800 /* SEQF: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF3 0x00000C00 /* SEQF: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE0 0x00000000 /* SEQE: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE1 0x00000100 /* SEQE: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE2 0x00000200 /* SEQE: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE3 0x00000300 /* SEQE: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD0 0x00000000 /* SEQD: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD1 0x00000040 /* SEQD: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD2 0x00000080 /* SEQD: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD3 0x000000C0 /* SEQD: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC0 0x00000000 /* SEQC: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC1 0x00000010 /* SEQC: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC2 0x00000020 /* SEQC: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC3 0x00000030 /* SEQC: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB0 0x00000000 /* SEQB: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB1 0x00000004 /* SEQB: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB2 0x00000008 /* SEQB: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB3 0x0000000C /* SEQB: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA0 0x00000000 /* SEQA: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA1 0x00000001 /* SEQA: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA2 0x00000002 /* SEQA: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA3 0x00000003 /* SEQA: Fill SEQ3 In */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ0WUPL_WAKEUPTIME0 0 /* Sequence 0 Sleep Period */ +#define BITM_WUPTMR_SEQ0WUPL_WAKEUPTIME0 0x0000FFFF /* Sequence 0 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ0WUPH_WAKEUPTIME0 0 /* Sequence 0 Sleep Period */ +#define BITM_WUPTMR_SEQ0WUPH_WAKEUPTIME0 0x0000000F /* Sequence 0 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ0SLEEPL_SLEEPTIME0 0 /* Sequence 0 Active Period */ +#define BITM_WUPTMR_SEQ0SLEEPL_SLEEPTIME0 0x0000FFFF /* Sequence 0 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ0SLEEPH_SLEEPTIME0 0 /* Sequence 0 Active Period */ +#define BITM_WUPTMR_SEQ0SLEEPH_SLEEPTIME0 0x0000000F /* Sequence 0 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ1WUPL_WAKEUPTIME 0 /* Sequence 1 Sleep Period */ +#define BITM_WUPTMR_SEQ1WUPL_WAKEUPTIME 0x0000FFFF /* Sequence 1 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ1WUPH_WAKEUPTIME 0 /* Sequence 1 Sleep Period */ +#define BITM_WUPTMR_SEQ1WUPH_WAKEUPTIME 0x0000000F /* Sequence 1 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ1SLEEPL_SLEEPTIME1 0 /* Sequence 1 Active Period */ +#define BITM_WUPTMR_SEQ1SLEEPL_SLEEPTIME1 0x0000FFFF /* Sequence 1 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ1SLEEPH_SLEEPTIME1 0 /* Sequence 1 Active Period */ +#define BITM_WUPTMR_SEQ1SLEEPH_SLEEPTIME1 0x0000000F /* Sequence 1 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ2WUPL_WAKEUPTIME2 0 /* Sequence 2 Sleep Period */ +#define BITM_WUPTMR_SEQ2WUPL_WAKEUPTIME2 0x0000FFFF /* Sequence 2 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ2WUPH_WAKEUPTIME2 0 /* Sequence 2 Sleep Period */ +#define BITM_WUPTMR_SEQ2WUPH_WAKEUPTIME2 0x0000000F /* Sequence 2 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ2SLEEPL_SLEEPTIME2 0 /* Sequence 2 Active Period */ +#define BITM_WUPTMR_SEQ2SLEEPL_SLEEPTIME2 0x0000FFFF /* Sequence 2 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ2SLEEPH_SLEEPTIME2 0 /* Sequence 2 Active Period */ +#define BITM_WUPTMR_SEQ2SLEEPH_SLEEPTIME2 0x0000000F /* Sequence 2 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ3WUPL_WAKEUPTIME3 0 /* Sequence 3 Sleep Period */ +#define BITM_WUPTMR_SEQ3WUPL_WAKEUPTIME3 0x0000FFFF /* Sequence 3 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ3WUPH_WAKEUPTIME3 0 /* Sequence 3 Sleep Period */ +#define BITM_WUPTMR_SEQ3WUPH_WAKEUPTIME3 0x0000000F /* Sequence 3 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ3SLEEPL_SLEEPTIME3 0 /* Sequence 3 Active Period */ +#define BITM_WUPTMR_SEQ3SLEEPL_SLEEPTIME3 0x0000FFFF /* Sequence 3 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ3SLEEPH_SLEEPTIME3 0 /* Sequence 3 Active Period */ +#define BITM_WUPTMR_SEQ3SLEEPH_SLEEPTIME3 0x0000000F /* Sequence 3 Active Period */ + + +/* ============================================================================================================================ + Always On Register + ============================================================================================================================ */ + +/* ============================================================================================================================ + ALLON + ============================================================================================================================ */ +#define REG_ALLON_PWRMOD_RESET 0x00000001 /* Reset Value for PWRMOD */ +#define REG_ALLON_PWRMOD 0x00000A00 /* ALLON Power Modes */ +#define REG_ALLON_PWRKEY_RESET 0x00000000 /* Reset Value for PWRKEY */ +#define REG_ALLON_PWRKEY 0x00000A04 /* ALLON Key Protection for PWRMOD */ +#define REG_ALLON_OSCKEY_RESET 0x00000000 /* Reset Value for OSCKEY */ +#define REG_ALLON_OSCKEY 0x00000A0C /* ALLON Key Protection for OSCCON */ +#define REG_ALLON_OSCCON_RESET 0x00000003 /* Reset Value for OSCCON */ +#define REG_ALLON_OSCCON 0x00000A10 /* ALLON Oscillator Control */ +#define REG_ALLON_TMRCON_RESET 0x00000000 /* Reset Value for TMRCON */ +#define REG_ALLON_TMRCON 0x00000A1C /* ALLON Timer Wakeup Configuration */ +#define REG_ALLON_EI0CON_RESET 0x00000000 /* Reset Value for EI0CON */ +#define REG_ALLON_EI0CON 0x00000A20 /* ALLON External Interrupt Configuration 0 */ +#define REG_ALLON_EI1CON_RESET 0x00000000 /* Reset Value for EI1CON */ +#define REG_ALLON_EI1CON 0x00000A24 /* ALLON External Interrupt Configuration 1 */ +#define REG_ALLON_EI2CON_RESET 0x00000000 /* Reset Value for EI2CON */ +#define REG_ALLON_EI2CON 0x00000A28 /* ALLON External Interrupt Configuration 2 */ +#define REG_ALLON_EICLR_RESET 0x0000C000 /* Reset Value for EICLR */ +#define REG_ALLON_EICLR 0x00000A30 /* ALLON External Interrupt Clear */ +#define REG_ALLON_RSTSTA_RESET 0x00000000 /* Reset Value for RSTSTA */ +#define REG_ALLON_RSTSTA 0x00000A40 /* ALLON Reset Status */ +#define REG_ALLON_RSTCONKEY_RESET 0x00000000 /* Reset Value for RSTCONKEY */ +#define REG_ALLON_RSTCONKEY 0x00000A5C /* ALLON Key Protection for RSTCON Register */ +#define REG_ALLON_LOSCTST_RESET 0x0000008F /* Reset Value for LOSCTST */ +#define REG_ALLON_LOSCTST 0x00000A6C /* ALLON Internal LF Oscillator Test */ +#define REG_ALLON_CLKEN0_RESET 0x00000004 /* Reset Value for CLKEN0 */ +#define REG_ALLON_CLKEN0 0x00000A70 /* ALLON 32KHz Peripheral Clock Enable */ + +/* ============================================================================================================================ + ALLON Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_PWRMOD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_PWRMOD_RAMRETEN 15 /* Retention for RAM */ +#define BITP_ALLON_PWRMOD_ADCRETEN 14 /* Keep ADC Power Switch on in Hibernate */ +#define BITP_ALLON_PWRMOD_SEQSLPEN 3 /* Auto Sleep by Sequencer Command */ +#define BITP_ALLON_PWRMOD_TMRSLPEN 2 /* Auto Sleep by Sleep Wakeup Timer */ +#define BITP_ALLON_PWRMOD_PWRMOD 0 /* Power Mode Control Bits */ +#define BITM_ALLON_PWRMOD_RAMRETEN 0x00008000 /* Retention for RAM */ +#define BITM_ALLON_PWRMOD_ADCRETEN 0x00004000 /* Keep ADC Power Switch on in Hibernate */ +#define BITM_ALLON_PWRMOD_SEQSLPEN 0x00000008 /* Auto Sleep by Sequencer Command */ +#define BITM_ALLON_PWRMOD_TMRSLPEN 0x00000004 /* Auto Sleep by Sleep Wakeup Timer */ +#define BITM_ALLON_PWRMOD_PWRMOD 0x00000003 /* Power Mode Control Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_PWRKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_PWRKEY_PWRKEY 0 /* PWRMOD Key Register */ +#define BITM_ALLON_PWRKEY_PWRKEY 0x0000FFFF /* PWRMOD Key Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_OSCKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_OSCKEY_OSCKEY 0 /* Oscillator Control Key Register. */ +#define BITM_ALLON_OSCKEY_OSCKEY 0x0000FFFF /* Oscillator Control Key Register. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_OSCCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_OSCCON_HFXTALOK 10 /* Status of HFXTAL Oscillator */ +#define BITP_ALLON_OSCCON_HFOSCOK 9 /* Status of HFOSC Oscillator */ +#define BITP_ALLON_OSCCON_LFOSCOK 8 /* Status of LFOSC Oscillator */ +#define BITP_ALLON_OSCCON_HFXTALEN 2 /* High Frequency Crystal Oscillator Enable */ +#define BITP_ALLON_OSCCON_HFOSCEN 1 /* High Frequency Internal Oscillator Enable */ +#define BITP_ALLON_OSCCON_LFOSCEN 0 /* Low Frequency Internal Oscillator Enable */ +#define BITM_ALLON_OSCCON_HFXTALOK 0x00000400 /* Status of HFXTAL Oscillator */ +#define BITM_ALLON_OSCCON_HFOSCOK 0x00000200 /* Status of HFOSC Oscillator */ +#define BITM_ALLON_OSCCON_LFOSCOK 0x00000100 /* Status of LFOSC Oscillator */ +#define BITM_ALLON_OSCCON_HFXTALEN 0x00000004 /* High Frequency Crystal Oscillator Enable */ +#define BITM_ALLON_OSCCON_HFOSCEN 0x00000002 /* High Frequency Internal Oscillator Enable */ +#define BITM_ALLON_OSCCON_LFOSCEN 0x00000001 /* Low Frequency Internal Oscillator Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_TMRCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_TMRCON_TMRINTEN 0 /* Enable Wakeup Timer */ +#define BITM_ALLON_TMRCON_TMRINTEN 0x00000001 /* Enable Wakeup Timer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EI0CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_EI0CON_IRQ3EN 15 /* External Interrupt 3 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ3MDE 12 /* External Interrupt 3 Mode Registers */ +#define BITP_ALLON_EI0CON_IRQ2EN 11 /* External Interrupt 2 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ2MDE 8 /* External Interrupt 2 Mode Registers */ +#define BITP_ALLON_EI0CON_IRQ1EN 7 /* External Interrupt 1 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ1MDE 4 /* External Interrupt 1 Mode Registers */ +#define BITP_ALLON_EI0CON_IRQ0EN 3 /* External Interrupt 0 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ0MDE 0 /* External Interrupt 0 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ3EN 0x00008000 /* External Interrupt 3 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ3MDE 0x00007000 /* External Interrupt 3 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ2EN 0x00000800 /* External Interrupt 2 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ2MDE 0x00000700 /* External Interrupt 2 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ1EN 0x00000080 /* External Interrupt 1 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ1MDE 0x00000070 /* External Interrupt 1 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ0EN 0x00000008 /* External Interrupt 0 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ0MDE 0x00000007 /* External Interrupt 0 Mode Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EI1CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_EI1CON_IRQ7EN 15 /* External Interrupt 7 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ7MDE 12 /* External Interrupt 7 Mode Registers */ +#define BITP_ALLON_EI1CON_IRQ6EN 11 /* External Interrupt 6 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ6MDE 8 /* External Interrupt 6 Mode Registers */ +#define BITP_ALLON_EI1CON_IRQ5EN 7 /* External Interrupt 5 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ5MDE 4 /* External Interrupt 5 Mode Registers */ +#define BITP_ALLON_EI1CON_IRQ4EN 3 /* External Interrupt 4 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ4MDE 0 /* External Interrupt 4 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ7EN 0x00008000 /* External Interrupt 7 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ7MDE 0x00007000 /* External Interrupt 7 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ6EN 0x00000800 /* External Interrupt 6 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ6MDE 0x00000700 /* External Interrupt 6 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ5EN 0x00000080 /* External Interrupt 5 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ5MDE 0x00000070 /* External Interrupt 5 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ4EN 0x00000008 /* External Interrupt 4 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ4MDE 0x00000007 /* External Interrupt 4 Mode Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EI2CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_EI2CON_BUSINTEN 3 /* BUS Interrupt Detection Enable Bit */ +#define BITP_ALLON_EI2CON_BUSINTMDE 0 /* BUS Interrupt Detection Mode Registers */ +#define BITM_ALLON_EI2CON_BUSINTEN 0x00000008 /* BUS Interrupt Detection Enable Bit */ +#define BITM_ALLON_EI2CON_BUSINTMDE 0x00000007 /* BUS Interrupt Detection Mode Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EICLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_EICLR_AUTCLRBUSEN 15 /* Enable Auto Clear of Bus Interrupt */ +#define BITP_ALLON_EICLR_BUSINT 8 /* BUS Interrupt */ +#define BITM_ALLON_EICLR_AUTCLRBUSEN 0x00008000 /* Enable Auto Clear of Bus Interrupt */ +#define BITM_ALLON_EICLR_BUSINT 0x00000100 /* BUS Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_RSTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_RSTSTA_PINSWRST 4 /* Software Reset Pin */ +#define BITP_ALLON_RSTSTA_MMRSWRST 3 /* MMR Software Reset */ +#define BITP_ALLON_RSTSTA_WDRST 2 /* Watchdog Timeout */ +#define BITP_ALLON_RSTSTA_EXTRST 1 /* External Reset */ +#define BITP_ALLON_RSTSTA_POR 0 /* Power-on Reset */ +#define BITM_ALLON_RSTSTA_PINSWRST 0x00000010 /* Software Reset Pin */ +#define BITM_ALLON_RSTSTA_MMRSWRST 0x00000008 /* MMR Software Reset */ +#define BITM_ALLON_RSTSTA_WDRST 0x00000004 /* Watchdog Timeout */ +#define BITM_ALLON_RSTSTA_EXTRST 0x00000002 /* External Reset */ +#define BITM_ALLON_RSTSTA_POR 0x00000001 /* Power-on Reset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_RSTCONKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_RSTCONKEY_KEY 0 /* Reset Control Key Register */ +#define BITM_ALLON_RSTCONKEY_KEY 0x0000FFFF /* Reset Control Key Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_LOSCTST Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_LOSCTST_TRIM 0 /* Trim Caps to Adjust Frequency. */ +#define BITM_ALLON_LOSCTST_TRIM 0x0000000F /* Trim Caps to Adjust Frequency. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_CLKEN0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_CLKEN0_TIACHPDIS 2 /* TIA Chop Clock Disable */ +#define BITP_ALLON_CLKEN0_SLPWUTDIS 1 /* Sleep/Wakeup Timer Clock Disable */ +#define BITP_ALLON_CLKEN0_WDTDIS 0 /* Watch Dog Timer Clock Disable */ +#define BITM_ALLON_CLKEN0_TIACHPDIS 0x00000004 /* TIA Chop Clock Disable */ +#define BITM_ALLON_CLKEN0_SLPWUTDIS 0x00000002 /* Sleep/Wakeup Timer Clock Disable */ +#define BITM_ALLON_CLKEN0_WDTDIS 0x00000001 /* Watch Dog Timer Clock Disable */ + +/* ============================================================================================================================ + General Purpose Timer + ============================================================================================================================ */ + +/* ============================================================================================================================ + AGPT0 + ============================================================================================================================ */ +#define REG_AGPT0_LD0 0x00000D00 /* AGPT0 16-bit Load Value Register. */ +#define REG_AGPT0_VAL0 0x00000D04 /* AGPT0 16-Bit Timer Value Register. */ +#define REG_AGPT0_CON0 0x00000D08 /* AGPT0 Control Register. */ +#define REG_AGPT0_CLRI0 0x00000D0C /* AGPT0 Clear Interrupt Register. */ +#define REG_AGPT0_CAP0 0x00000D10 /* AGPT0 Capture Register. */ +#define REG_AGPT0_ALD0 0x00000D14 /* AGPT0 16-Bit Load Value, Asynchronous. */ +#define REG_AGPT0_AVAL0 0x00000D18 /* AGPT0 16-Bit Timer Value, Asynchronous Register. */ +#define REG_AGPT0_STA0 0x00000D1C /* AGPT0 Status Register. */ +#define REG_AGPT0_PWMCON0 0x00000D20 /* AGPT0 PWM Control Register. */ +#define REG_AGPT0_PWMMAT0 0x00000D24 /* AGPT0 PWM Match Value Register. */ +#define REG_AGPT0_INTEN 0x00000D28 /* AGPT0 Interrupt Enable */ + +/* ============================================================================================================================ + AGPT0 Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_LD0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_LD0_LOAD 0 /* Load Value */ +#define BITM_AGPT0_LD0_LOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_VAL0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_VAL0_VAL 0 /* Current Count */ +#define BITM_AGPT0_VAL0_VAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Current Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_CON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_CON0_SYNCBYP 15 /* Synchronization Bypass */ +#define BITP_AGPT0_CON0_RSTEN 14 /* Counter and Prescale Reset Enable */ +#define BITP_AGPT0_CON0_EVTEN 13 /* Event Select */ +#define BITP_AGPT0_CON0_EVENT 8 /* Event Select Range */ +#define BITP_AGPT0_CON0_RLD 7 /* Reload Control */ +#define BITP_AGPT0_CON0_CLK 5 /* Clock Select */ +#define BITP_AGPT0_CON0_ENABLE 4 /* Timer Enable */ +#define BITP_AGPT0_CON0_MOD 3 /* Timer Mode */ +#define BITP_AGPT0_CON0_UP 2 /* Count up */ +#define BITP_AGPT0_CON0_PRE 0 /* Prescaler */ +#define BITM_AGPT0_CON0_SYNCBYP (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization Bypass */ +#define BITM_AGPT0_CON0_RSTEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Counter and Prescale Reset Enable */ +#define BITM_AGPT0_CON0_EVTEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Event Select */ +#define BITM_AGPT0_CON0_EVENT (_ADI_MSK_3(0x00001F00,0x00001F00U, uint16_t )) /* Event Select Range */ +#define BITM_AGPT0_CON0_RLD (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Reload Control */ +#define BITM_AGPT0_CON0_CLK (_ADI_MSK_3(0x00000060,0x00000060U, uint16_t )) /* Clock Select */ +#define BITM_AGPT0_CON0_ENABLE (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Timer Enable */ +#define BITM_AGPT0_CON0_MOD (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Timer Mode */ +#define BITM_AGPT0_CON0_UP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Count up */ +#define BITM_AGPT0_CON0_PRE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Prescaler */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_CLRI0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_CLRI0_CAP 1 /* Clear Captured Event Interrupt */ +#define BITP_AGPT0_CLRI0_TMOUT 0 /* Clear Timeout Interrupt */ +#define BITM_AGPT0_CLRI0_CAP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear Captured Event Interrupt */ +#define BITM_AGPT0_CLRI0_TMOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Clear Timeout Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_CAP0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_CAP0_CAP 0 /* 16-bit Captured Value */ +#define BITM_AGPT0_CAP0_CAP (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* 16-bit Captured Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_ALD0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_ALD0_ALOAD 0 /* Load Value, Asynchronous */ +#define BITM_AGPT0_ALD0_ALOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Load Value, Asynchronous */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_AVAL0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_AVAL0_AVAL 0 /* Counter Value */ +#define BITM_AGPT0_AVAL0_AVAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Counter Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_STA0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_STA0_RSTCNT 8 /* Counter Reset Occurring */ +#define BITP_AGPT0_STA0_PDOK 7 /* Clear Interrupt Register Synchronization */ +#define BITP_AGPT0_STA0_BUSY 6 /* Timer Busy */ +#define BITP_AGPT0_STA0_CAP 1 /* Capture Event Pending */ +#define BITP_AGPT0_STA0_TMOUT 0 /* Timeout Event Occurred */ +#define BITM_AGPT0_STA0_RSTCNT (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Counter Reset Occurring */ +#define BITM_AGPT0_STA0_PDOK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Clear Interrupt Register Synchronization */ +#define BITM_AGPT0_STA0_BUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Busy */ +#define BITM_AGPT0_STA0_CAP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Capture Event Pending */ +#define BITM_AGPT0_STA0_TMOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Timeout Event Occurred */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_PWMCON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_PWMCON0_IDLE 1 /* PWM Idle State */ +#define BITP_AGPT0_PWMCON0_MATCHEN 0 /* PWM Match Enabled */ +#define BITM_AGPT0_PWMCON0_IDLE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* PWM Idle State */ +#define BITM_AGPT0_PWMCON0_MATCHEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PWM Match Enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_PWMMAT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_PWMMAT0_MATCHVAL 0 /* PWM Match Value */ +#define BITM_AGPT0_PWMMAT0_MATCHVAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* PWM Match Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_INTEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_INTEN_INTEN 0 /* Interrupt Enable */ +#define BITM_AGPT0_INTEN_INTEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Interrupt Enable */ + + +/* ============================================================================================================================ + General Purpose Timer + ============================================================================================================================ */ + +/* ============================================================================================================================ + AGPT1 + ============================================================================================================================ */ +#define REG_AGPT1_LD1 0x00000E00 /* AGPT1 16-bit Load Value Register */ +#define REG_AGPT1_VAL1 0x00000E04 /* AGPT1 16-bit Timer Value Register */ +#define REG_AGPT1_CON1 0x00000E08 /* AGPT1 Control Register */ +#define REG_AGPT1_CLRI1 0x00000E0C /* AGPT1 Clear Interrupt Register */ +#define REG_AGPT1_CAP1 0x00000E10 /* AGPT1 Capture Register */ +#define REG_AGPT1_ALD1 0x00000E14 /* AGPT1 16-bit Load Value, Asynchronous Register */ +#define REG_AGPT1_AVAL1 0x00000E18 /* AGPT1 16-bit Timer Value, Asynchronous Register */ +#define REG_AGPT1_STA1 0x00000E1C /* AGPT1 Status Register */ +#define REG_AGPT1_PWMCON1 0x00000E20 /* AGPT1 PWM Control Register */ +#define REG_AGPT1_PWMMAT1 0x00000E24 /* AGPT1 PWM Match Value Register */ +#define REG_AGPT1_INTEN1 0x00000E28 /* AGPT1 Interrupt Enable */ + +/* ============================================================================================================================ + AGPT1 Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_LD1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_LD1_LOAD 0 /* Load Value */ +#define BITM_AGPT1_LD1_LOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_VAL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_VAL1_VAL 0 /* Current Count */ +#define BITM_AGPT1_VAL1_VAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Current Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_CON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_CON1_SYNCBYP 15 /* Synchronization Bypass */ +#define BITP_AGPT1_CON1_RSTEN 14 /* Counter and Prescale Reset Enable */ +#define BITP_AGPT1_CON1_EVENTEN 13 /* Event Select */ +#define BITP_AGPT1_CON1_EVENT 8 /* Event Select Range */ +#define BITP_AGPT1_CON1_RLD 7 /* Reload Control */ +#define BITP_AGPT1_CON1_CLK 5 /* Clock Select */ +#define BITP_AGPT1_CON1_ENABLE 4 /* Timer Enable */ +#define BITP_AGPT1_CON1_MOD 3 /* Timer Mode */ +#define BITP_AGPT1_CON1_UP 2 /* Count up */ +#define BITP_AGPT1_CON1_PRE 0 /* Prescaler */ +#define BITM_AGPT1_CON1_SYNCBYP (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization Bypass */ +#define BITM_AGPT1_CON1_RSTEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Counter and Prescale Reset Enable */ +#define BITM_AGPT1_CON1_EVENTEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Event Select */ +#define BITM_AGPT1_CON1_EVENT (_ADI_MSK_3(0x00001F00,0x00001F00U, uint16_t )) /* Event Select Range */ +#define BITM_AGPT1_CON1_RLD (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Reload Control */ +#define BITM_AGPT1_CON1_CLK (_ADI_MSK_3(0x00000060,0x00000060U, uint16_t )) /* Clock Select */ +#define BITM_AGPT1_CON1_ENABLE (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Timer Enable */ +#define BITM_AGPT1_CON1_MOD (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Timer Mode */ +#define BITM_AGPT1_CON1_UP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Count up */ +#define BITM_AGPT1_CON1_PRE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Prescaler */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_CLRI1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_CLRI1_CAP 1 /* Clear Captured Event Interrupt */ +#define BITP_AGPT1_CLRI1_TMOUT 0 /* Clear Timeout Interrupt */ +#define BITM_AGPT1_CLRI1_CAP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear Captured Event Interrupt */ +#define BITM_AGPT1_CLRI1_TMOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Clear Timeout Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_CAP1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_CAP1_CAP 0 /* 16-bit Captured Value. */ +#define BITM_AGPT1_CAP1_CAP (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* 16-bit Captured Value. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_ALD1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_ALD1_ALOAD 0 /* Load Value, Asynchronous */ +#define BITM_AGPT1_ALD1_ALOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Load Value, Asynchronous */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_AVAL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_AVAL1_AVAL 0 /* Counter Value */ +#define BITM_AGPT1_AVAL1_AVAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Counter Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_STA1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_STA1_RSTCNT 8 /* Counter Reset Occurring */ +#define BITP_AGPT1_STA1_PDOK 7 /* Clear Interrupt Register Synchronization */ +#define BITP_AGPT1_STA1_BUSY 6 /* Timer Busy */ +#define BITP_AGPT1_STA1_CAP 1 /* Capture Event Pending */ +#define BITP_AGPT1_STA1_TMOUT 0 /* Timeout Event Occurred */ +#define BITM_AGPT1_STA1_RSTCNT (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Counter Reset Occurring */ +#define BITM_AGPT1_STA1_PDOK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Clear Interrupt Register Synchronization */ +#define BITM_AGPT1_STA1_BUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Busy */ +#define BITM_AGPT1_STA1_CAP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Capture Event Pending */ +#define BITM_AGPT1_STA1_TMOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Timeout Event Occurred */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_PWMCON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_PWMCON1_IDLE 1 /* PWM Idle State. */ +#define BITP_AGPT1_PWMCON1_MATCHEN 0 /* PWM Match Enabled. */ +#define BITM_AGPT1_PWMCON1_IDLE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* PWM Idle State. */ +#define BITM_AGPT1_PWMCON1_MATCHEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PWM Match Enabled. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_PWMMAT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_PWMMAT1_MATCHVAL 0 /* PWM Match Value */ +#define BITM_AGPT1_PWMMAT1_MATCHVAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* PWM Match Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_INTEN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_INTEN1_INTEN 0 /* Interrupt Enable */ +#define BITM_AGPT1_INTEN1_INTEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Interrupt Enable */ + + +/* ============================================================================================================================ + CRC Accelerator + ============================================================================================================================ */ + +/* ============================================================================================================================ + AFECRC + ============================================================================================================================ */ +#define REG_AFECRC_CTL 0x00001000 /* AFECRC CRC Control Register */ +#define REG_AFECRC_IPDATA 0x00001004 /* AFECRC Data Input. */ +#define REG_AFECRC_RESULT 0x00001008 /* AFECRC CRC Residue */ +#define REG_AFECRC_POLY 0x0000100C /* AFECRC CRC Reduction Polynomial */ +#define REG_AFECRC_IPBITS 0x00001010 /* AFECRC Input Data Bits */ +#define REG_AFECRC_IPBYTE 0x00001014 /* AFECRC Input Data Byte */ +#define REG_AFECRC_CRC_SIG_COMP 0x00001020 /* AFECRC CRC Signature Compare Data Input. */ +#define REG_AFECRC_CRCINTEN 0x00001024 /* AFECRC CRC Error Interrupt Enable Bit */ +#define REG_AFECRC_INTSTA 0x00001028 /* AFECRC CRC Error Interrupt Status Bit */ + +/* ============================================================================================================================ + AFECRC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_CTL_REVID 28 /* Revision ID */ +#define BITP_AFECRC_CTL_MON_EN 9 /* Enable Apb32/Apb16 to Get Address/Data for CRC Calculation */ +#define BITP_AFECRC_CTL_W16SWP 4 /* Word16 Swap Enabled. */ +#define BITP_AFECRC_CTL_BYTMIRR 3 /* Byte Mirroring. */ +#define BITP_AFECRC_CTL_BITMIRR 2 /* Bit Mirroring. */ +#define BITP_AFECRC_CTL_LSBFIRST 1 /* LSB First Calculation Order */ +#define BITP_AFECRC_CTL_EN 0 /* CRC Peripheral Enable */ +#define BITM_AFECRC_CTL_REVID (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t )) /* Revision ID */ +#define BITM_AFECRC_CTL_MON_EN (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* Enable Apb32/Apb16 to Get Address/Data for CRC Calculation */ +#define BITM_AFECRC_CTL_W16SWP (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Word16 Swap Enabled. */ +#define BITM_AFECRC_CTL_BYTMIRR (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Byte Mirroring. */ +#define BITM_AFECRC_CTL_BITMIRR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Bit Mirroring. */ +#define BITM_AFECRC_CTL_LSBFIRST (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* LSB First Calculation Order */ +#define BITM_AFECRC_CTL_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* CRC Peripheral Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_IPDATA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_IPDATA_VALUE 0 /* Data Input. */ +#define BITM_AFECRC_IPDATA_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFF, int32_t )) /* Data Input. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_RESULT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_RESULT_VALUE 0 /* CRC Residue */ +#define BITM_AFECRC_RESULT_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFF, int32_t )) /* CRC Residue */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_POLY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_POLY_VALUE 0 /* CRC Reduction Polynomial */ +#define BITM_AFECRC_POLY_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* CRC Reduction Polynomial */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_IPBITS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_IPBITS_DATA_BITS 0 /* Input Data Bits. */ +#define BITM_AFECRC_IPBITS_DATA_BITS (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t )) /* Input Data Bits. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_IPBYTE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_IPBYTE_DATA_BYTE 0 /* Input Data Byte. */ +#define BITM_AFECRC_IPBYTE_DATA_BYTE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t )) /* Input Data Byte. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_CRC_SIG_COMP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_CRC_SIG_COMP_CRC_SIG 0 /* CRC Signature Compare Data Input. */ +#define BITM_AFECRC_CRC_SIG_COMP_CRC_SIG (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* CRC Signature Compare Data Input. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_CRCINTEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_CRCINTEN_RESERVED_31_1 1 /* Reserved */ +#define BITP_AFECRC_CRCINTEN_CRC_ERR_EN 0 /* CRC Error Interrupt Enable Bit */ +#define BITM_AFECRC_CRCINTEN_RESERVED_31_1 (_ADI_MSK_3(0xFFFFFFFE,0xFFFFFFFEUL, uint32_t )) /* Reserved */ +#define BITM_AFECRC_CRCINTEN_CRC_ERR_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* CRC Error Interrupt Enable Bit */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_INTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_INTSTA_CRC_ERR_ST 0 /* CRC Error Interrupt Status Bit */ +#define BITM_AFECRC_INTSTA_CRC_ERR_ST (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* CRC Error Interrupt Status Bit */ + + +/* ============================================================================================================================ + + ============================================================================================================================ */ + +/* ============================================================================================================================ + AFE + ============================================================================================================================ */ +#define REG_AFE_AFECON_RESET 0x00080000 /* Reset Value for AFECON */ +#define REG_AFE_AFECON 0x00002000 /* AFE AFE Configuration */ +#define REG_AFE_SEQCON_RESET 0x00000002 /* Reset Value for SEQCON */ +#define REG_AFE_SEQCON 0x00002004 /* AFE Sequencer Configuration */ +#define REG_AFE_FIFOCON_RESET 0x00001010 /* Reset Value for FIFOCON */ +#define REG_AFE_FIFOCON 0x00002008 /* AFE FIFOs Configuration */ +#define REG_AFE_SWCON_RESET 0x0000FFFF /* Reset Value for SWCON */ +#define REG_AFE_SWCON 0x0000200C /* AFE Switch Matrix Configuration */ +#define REG_AFE_HSDACCON_RESET 0x0000001E /* Reset Value for HSDACCON */ +#define REG_AFE_HSDACCON 0x00002010 /* AFE High Speed DAC Configuration */ +#define REG_AFE_WGCON_RESET 0x00000030 /* Reset Value for WGCON */ +#define REG_AFE_WGCON 0x00002014 /* AFE Waveform Generator Configuration */ +#define REG_AFE_WGDCLEVEL1_RESET 0x00000000 /* Reset Value for WGDCLEVEL1 */ +#define REG_AFE_WGDCLEVEL1 0x00002018 /* AFE Waveform Generator - Trapezoid DC Level 1 */ +#define REG_AFE_WGDCLEVEL2_RESET 0x00000000 /* Reset Value for WGDCLEVEL2 */ +#define REG_AFE_WGDCLEVEL2 0x0000201C /* AFE Waveform Generator - Trapezoid DC Level 2 */ +#define REG_AFE_WGDELAY1_RESET 0x00000000 /* Reset Value for WGDELAY1 */ +#define REG_AFE_WGDELAY1 0x00002020 /* AFE Waveform Generator - Trapezoid Delay 1 Time */ +#define REG_AFE_WGSLOPE1_RESET 0x00000000 /* Reset Value for WGSLOPE1 */ +#define REG_AFE_WGSLOPE1 0x00002024 /* AFE Waveform Generator - Trapezoid Slope 1 Time */ +#define REG_AFE_WGDELAY2_RESET 0x00000000 /* Reset Value for WGDELAY2 */ +#define REG_AFE_WGDELAY2 0x00002028 /* AFE Waveform Generator - Trapezoid Delay 2 Time */ +#define REG_AFE_WGSLOPE2_RESET 0x00000000 /* Reset Value for WGSLOPE2 */ +#define REG_AFE_WGSLOPE2 0x0000202C /* AFE Waveform Generator - Trapezoid Slope 2 Time */ +#define REG_AFE_WGFCW_RESET 0x00000000 /* Reset Value for WGFCW */ +#define REG_AFE_WGFCW 0x00002030 /* AFE Waveform Generator - Sinusoid Frequency Control Word */ +#define REG_AFE_WGPHASE_RESET 0x00000000 /* Reset Value for WGPHASE */ +#define REG_AFE_WGPHASE 0x00002034 /* AFE Waveform Generator - Sinusoid Phase Offset */ +#define REG_AFE_WGOFFSET_RESET 0x00000000 /* Reset Value for WGOFFSET */ +#define REG_AFE_WGOFFSET 0x00002038 /* AFE Waveform Generator - Sinusoid Offset */ +#define REG_AFE_WGAMPLITUDE_RESET 0x00000000 /* Reset Value for WGAMPLITUDE */ +#define REG_AFE_WGAMPLITUDE 0x0000203C /* AFE Waveform Generator - Sinusoid Amplitude */ +#define REG_AFE_ADCFILTERCON_RESET 0x00000301 /* Reset Value for ADCFILTERCON */ +#define REG_AFE_ADCFILTERCON 0x00002044 /* AFE ADC Output Filters Configuration */ +#define REG_AFE_HSDACDAT_RESET 0x00000800 /* Reset Value for HSDACDAT */ +#define REG_AFE_HSDACDAT 0x00002048 /* AFE HS DAC Code */ +#define REG_AFE_LPREFBUFCON_RESET 0x00000000 /* Reset Value for LPREFBUFCON */ +#define REG_AFE_LPREFBUFCON 0x00002050 /* AFE LPREF_BUF_CON */ +#define REG_AFE_SYNCEXTDEVICE_RESET 0x00000000 /* Reset Value for SYNCEXTDEVICE */ +#define REG_AFE_SYNCEXTDEVICE 0x00002054 /* AFE SYNC External Devices */ +#define REG_AFE_SEQCRC_RESET 0x00000001 /* Reset Value for SEQCRC */ +#define REG_AFE_SEQCRC 0x00002060 /* AFE Sequencer CRC Value */ +#define REG_AFE_SEQCNT_RESET 0x00000000 /* Reset Value for SEQCNT */ +#define REG_AFE_SEQCNT 0x00002064 /* AFE Sequencer Command Count */ +#define REG_AFE_SEQTIMEOUT_RESET 0x00000000 /* Reset Value for SEQTIMEOUT */ +#define REG_AFE_SEQTIMEOUT 0x00002068 /* AFE Sequencer Timeout Counter */ +#define REG_AFE_DATAFIFORD_RESET 0x00000000 /* Reset Value for DATAFIFORD */ +#define REG_AFE_DATAFIFORD 0x0000206C /* AFE Data FIFO Read */ +#define REG_AFE_CMDFIFOWRITE_RESET 0x00000000 /* Reset Value for CMDFIFOWRITE */ +#define REG_AFE_CMDFIFOWRITE 0x00002070 /* AFE Command FIFO Write */ +#define REG_AFE_ADCDAT_RESET 0x00000000 /* Reset Value for ADCDAT */ +#define REG_AFE_ADCDAT 0x00002074 /* AFE ADC Raw Result */ +#define REG_AFE_DFTREAL_RESET 0x00000000 /* Reset Value for DFTREAL */ +#define REG_AFE_DFTREAL 0x00002078 /* AFE DFT Result, Real Part */ +#define REG_AFE_DFTIMAG_RESET 0x00000000 /* Reset Value for DFTIMAG */ +#define REG_AFE_DFTIMAG 0x0000207C /* AFE DFT Result, Imaginary Part */ +#define REG_AFE_SINC2DAT_RESET 0x00000000 /* Reset Value for SINC2DAT */ +#define REG_AFE_SINC2DAT 0x00002080 /* AFE Supply Rejection Filter Result */ +#define REG_AFE_TEMPSENSDAT_RESET 0x00000000 /* Reset Value for TEMPSENSDAT */ +#define REG_AFE_TEMPSENSDAT 0x00002084 /* AFE Temperature Sensor Result */ +#define REG_AFE_AFEGENINTSTA_RESET 0x00000000 /* Reset Value for AFEGENINTSTA */ +#define REG_AFE_AFEGENINTSTA 0x0000209C /* AFE Analog Generation Interrupt */ +#define REG_AFE_ADCMIN_RESET 0x00000000 /* Reset Value for ADCMIN */ +#define REG_AFE_ADCMIN 0x000020A8 /* AFE ADC Minimum Value Check */ +#define REG_AFE_ADCMINSM_RESET 0x00000000 /* Reset Value for ADCMINSM */ +#define REG_AFE_ADCMINSM 0x000020AC /* AFE ADCMIN Hysteresis Value */ +#define REG_AFE_ADCMAX_RESET 0x00000000 /* Reset Value for ADCMAX */ +#define REG_AFE_ADCMAX 0x000020B0 /* AFE ADC Maximum Value Check */ +#define REG_AFE_ADCMAXSMEN_RESET 0x00000000 /* Reset Value for ADCMAXSMEN */ +#define REG_AFE_ADCMAXSMEN 0x000020B4 /* AFE ADCMAX Hysteresis Value */ +#define REG_AFE_ADCDELTA_RESET 0x00000000 /* Reset Value for ADCDELTA */ +#define REG_AFE_ADCDELTA 0x000020B8 /* AFE ADC Delta Value */ +#define REG_AFE_HPOSCCON_RESET 0x00000024 /* Reset Value for HPOSCCON */ +#define REG_AFE_HPOSCCON 0x000020BC /* AFE HPOSC Configuration */ +#define REG_AFE_DFTCON_RESET 0x00000090 /* Reset Value for DFTCON */ +#define REG_AFE_DFTCON 0x000020D0 /* AFE AFE DSP Configuration */ +#define REG_AFE_LPTIASW1 0x000020E0 /* AFE ULPTIA Switch Configuration for Channel 1 */ +#define REG_AFE_LPTIASW0_RESET 0x00000000 /* Reset Value for LPTIASW0 */ +#define REG_AFE_LPTIACON1 0x000020E8 /* AFE ULPTIA Control Bits Channel 1 */ +#define REG_AFE_LPTIASW0 0x000020E4 /* AFE ULPTIA Switch Configuration for Channel 0 */ +#define REG_AFE_LPTIACON0_RESET 0x00000003 /* Reset Value for LPTIACON0 */ +#define REG_AFE_LPTIACON0 0x000020EC /* AFE ULPTIA Control Bits Channel 0 */ +#define REG_AFE_HSRTIACON_RESET 0x0000000F /* Reset Value for HSRTIACON */ +#define REG_AFE_HSRTIACON 0x000020F0 /* AFE High Power RTIA Configuration */ +#define REG_AFE_DE1RESCON 0x000020F4 /* AFE DE1 HSTIA Resistors Configuration */ +#define REG_AFE_DE0RESCON_RESET 0x000000FF /* Reset Value for DE0RESCON */ +#define REG_AFE_DE0RESCON 0x000020F8 /* AFE DE0 HSTIA Resistors Configuration */ +#define REG_AFE_HSTIACON_RESET 0x00000000 /* Reset Value for HSTIACON */ +#define REG_AFE_HSTIACON 0x000020FC /* AFE HSTIA Amplifier Configuration */ +#define REG_AFE_LPMODEKEY_RESET 0x00000000 /* Reset Value for LPMODEKEY */ +#define REG_AFE_LPMODEKEY 0x0000210C /* AFE LP Mode AFE Control Lock */ +#define REG_AFE_LPMODECLKSEL_RESET 0x00000000 /* Reset Value for LPMODECLKSEL */ +#define REG_AFE_LPMODECLKSEL 0x00002110 /* AFE LFSYSCLKEN */ +#define REG_AFE_LPMODECON_RESET 0x00000102 /* Reset Value for LPMODECON */ +#define REG_AFE_LPMODECON 0x00002114 /* AFE LPMODECON */ +#define REG_AFE_SEQSLPLOCK_RESET 0x00000000 /* Reset Value for SEQSLPLOCK */ +#define REG_AFE_SEQSLPLOCK 0x00002118 /* AFE Sequencer Sleep Control Lock */ +#define REG_AFE_SEQTRGSLP_RESET 0x00000000 /* Reset Value for SEQTRGSLP */ +#define REG_AFE_SEQTRGSLP 0x0000211C /* AFE Sequencer Trigger Sleep */ +#define REG_AFE_LPDACDAT0_RESET 0x00000000 /* Reset Value for LPDACDAT0 */ +#define REG_AFE_LPDACDAT0 0x00002120 /* AFE LPDAC Data-out */ +#define REG_AFE_LPDACSW0_RESET 0x00000000 /* Reset Value for LPDACSW0 */ +#define REG_AFE_LPDACSW0 0x00002124 /* AFE LPDAC0 Switch Control */ +#define REG_AFE_LPDACCON0_RESET 0x00000002 /* Reset Value for LPDACCON0 */ +#define REG_AFE_LPDACCON0 0x00002128 /* AFE LPDAC Control Bits */ +#define REG_AFE_LPDACDAT1 0x0000212C /* AFE Low Power DAC1 data register */ +#define REG_AFE_LPDACSW1 0x00002130 /* AFE Control register for switches to LPDAC1 */ +#define REG_AFE_LPDACCON1 0x00002134 /* AFE ULP_DACCON1 */ +#define REG_AFE_DSWFULLCON_RESET 0x00000000 /* Reset Value for DSWFULLCON */ +#define REG_AFE_DSWFULLCON 0x00002150 /* AFE Switch Matrix Full Configuration (D) */ +#define REG_AFE_NSWFULLCON_RESET 0x00000000 /* Reset Value for NSWFULLCON */ +#define REG_AFE_NSWFULLCON 0x00002154 /* AFE Switch Matrix Full Configuration (N) */ +#define REG_AFE_PSWFULLCON_RESET 0x00000000 /* Reset Value for PSWFULLCON */ +#define REG_AFE_PSWFULLCON 0x00002158 /* AFE Switch Matrix Full Configuration (P) */ +#define REG_AFE_TSWFULLCON_RESET 0x00000000 /* Reset Value for TSWFULLCON */ +#define REG_AFE_TSWFULLCON 0x0000215C /* AFE Switch Matrix Full Configuration (T) */ +#define REG_AFE_TEMPSENS_RESET 0x00000000 /* Reset Value for TEMPSENS */ +#define REG_AFE_TEMPSENS 0x00002174 /* AFE Temp Sensor Configuration */ +#define REG_AFE_BUFSENCON_RESET 0x00000037 /* Reset Value for BUFSENCON */ +#define REG_AFE_BUFSENCON 0x00002180 /* AFE HP and LP Buffer Control */ +#define REG_AFE_ADCCON_RESET 0x00000000 /* Reset Value for ADCCON */ +#define REG_AFE_ADCCON 0x000021A8 /* AFE ADC Configuration */ +#define REG_AFE_DSWSTA_RESET 0x00000000 /* Reset Value for DSWSTA */ +#define REG_AFE_DSWSTA 0x000021B0 /* AFE Switch Matrix Status (D) */ +#define REG_AFE_PSWSTA_RESET 0x00006000 /* Reset Value for PSWSTA */ +#define REG_AFE_PSWSTA 0x000021B4 /* AFE Switch Matrix Status (P) */ +#define REG_AFE_NSWSTA_RESET 0x00000C00 /* Reset Value for NSWSTA */ +#define REG_AFE_NSWSTA 0x000021B8 /* AFE Switch Matrix Status (N) */ +#define REG_AFE_TSWSTA_RESET 0x00000000 /* Reset Value for TSWSTA */ +#define REG_AFE_TSWSTA 0x000021BC /* AFE Switch Matrix Status (T) */ +#define REG_AFE_STATSVAR_RESET 0x00000000 /* Reset Value for STATSVAR */ +#define REG_AFE_STATSVAR 0x000021C0 /* AFE Variance Output */ +#define REG_AFE_STATSCON_RESET 0x00000000 /* Reset Value for STATSCON */ +#define REG_AFE_STATSCON 0x000021C4 /* AFE Statistics Control */ +#define REG_AFE_STATSMEAN_RESET 0x00000000 /* Reset Value for STATSMEAN */ +#define REG_AFE_STATSMEAN 0x000021C8 /* AFE Statistics Mean Output */ +#define REG_AFE_SEQ0INFO_RESET 0x00000000 /* Reset Value for SEQ0INFO */ +#define REG_AFE_SEQ0INFO 0x000021CC /* AFE Sequence 0 Info */ +#define REG_AFE_SEQ2INFO_RESET 0x00000000 /* Reset Value for SEQ2INFO */ +#define REG_AFE_SEQ2INFO 0x000021D0 /* AFE Sequence 2 Info */ +#define REG_AFE_CMDFIFOWADDR_RESET 0x00000000 /* Reset Value for CMDFIFOWADDR */ +#define REG_AFE_CMDFIFOWADDR 0x000021D4 /* AFE Command FIFO Write Address */ +#define REG_AFE_CMDDATACON_RESET 0x00000410 /* Reset Value for CMDDATACON */ +#define REG_AFE_CMDDATACON 0x000021D8 /* AFE Command Data Control */ +#define REG_AFE_DATAFIFOTHRES_RESET 0x00000000 /* Reset Value for DATAFIFOTHRES */ +#define REG_AFE_DATAFIFOTHRES 0x000021E0 /* AFE Data FIFO Threshold */ +#define REG_AFE_SEQ3INFO_RESET 0x00000000 /* Reset Value for SEQ3INFO */ +#define REG_AFE_SEQ3INFO 0x000021E4 /* AFE Sequence 3 Info */ +#define REG_AFE_SEQ1INFO_RESET 0x00000000 /* Reset Value for SEQ1INFO */ +#define REG_AFE_SEQ1INFO 0x000021E8 /* AFE Sequence 1 Info */ +#define REG_AFE_REPEATADCCNV_RESET 0x00000160 /* Reset Value for REPEATADCCNV */ +#define REG_AFE_REPEATADCCNV 0x000021F0 /* AFE REPEAT ADC Conversions */ +#define REG_AFE_FIFOCNTSTA_RESET 0x00000000 /* Reset Value for FIFOCNTSTA */ +#define REG_AFE_FIFOCNTSTA 0x00002200 /* AFE CMD and DATA FIFO INTERNAL DATA COUNT */ +#define REG_AFE_CALDATLOCK_RESET 0x00000000 /* Reset Value for CALDATLOCK */ +#define REG_AFE_CALDATLOCK 0x00002230 /* AFE Calibration Data Lock */ +#define REG_AFE_ADCOFFSETHSTIA_RESET 0x00000000 /* Reset Value for ADCOFFSETHSTIA */ +#define REG_AFE_ADCOFFSETHSTIA 0x00002234 /* AFE ADC Offset Calibration High Speed TIA Channel */ +#define REG_AFE_ADCGAINTEMPSENS0_RESET 0x00004000 /* Reset Value for ADCGAINTEMPSENS0 */ +#define REG_AFE_ADCGAINTEMPSENS0 0x00002238 /* AFE ADC Gain Calibration Temp Sensor Channel */ +#define REG_AFE_ADCOFFSETTEMPSENS0_RESET 0x00000000 /* Reset Value for ADCOFFSETTEMPSENS0 */ +#define REG_AFE_ADCOFFSETTEMPSENS0 0x0000223C /* AFE ADC Offset Calibration Temp Sensor Channel 0 */ +#define REG_AFE_ADCGAINGN1_RESET 0x00004000 /* Reset Value for ADCGAINGN1 */ +#define REG_AFE_ADCGAINGN1 0x00002240 /* AFE ADCPGAGN1: ADC Gain Calibration Auxiliary Input Channel */ +#define REG_AFE_ADCOFFSETGN1_RESET 0x00000000 /* Reset Value for ADCOFFSETGN1 */ +#define REG_AFE_ADCOFFSETGN1 0x00002244 /* AFE ADC Offset Calibration Auxiliary Channel (PGA Gain=1) */ +#define REG_AFE_DACGAIN_RESET 0x00000800 /* Reset Value for DACGAIN */ +#define REG_AFE_DACGAIN 0x00002260 /* AFE DACGAIN */ +#define REG_AFE_DACOFFSETATTEN_RESET 0x00000000 /* Reset Value for DACOFFSETATTEN */ +#define REG_AFE_DACOFFSETATTEN 0x00002264 /* AFE DAC Offset with Attenuator Enabled (LP Mode) */ +#define REG_AFE_DACOFFSET_RESET 0x00000000 /* Reset Value for DACOFFSET */ +#define REG_AFE_DACOFFSET 0x00002268 /* AFE DAC Offset with Attenuator Disabled (LP Mode) */ +#define REG_AFE_ADCGAINGN1P5_RESET 0x00004000 /* Reset Value for ADCGAINGN1P5 */ +#define REG_AFE_ADCGAINGN1P5 0x00002270 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=1.5) */ +#define REG_AFE_ADCGAINGN2_RESET 0x00004000 /* Reset Value for ADCGAINGN2 */ +#define REG_AFE_ADCGAINGN2 0x00002274 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=2) */ +#define REG_AFE_ADCGAINGN4_RESET 0x00004000 /* Reset Value for ADCGAINGN4 */ +#define REG_AFE_ADCGAINGN4 0x00002278 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=4) */ +#define REG_AFE_ADCPGAOFFSETCANCEL_RESET 0x00000000 /* Reset Value for ADCPGAOFFSETCANCEL */ +#define REG_AFE_ADCPGAOFFSETCANCEL 0x00002280 /* AFE ADC Offset Cancellation (Optional) */ +#define REG_AFE_ADCGNHSTIA_RESET 0x00004000 /* Reset Value for ADCGNHSTIA */ +#define REG_AFE_ADCGNHSTIA 0x00002284 /* AFE ADC Gain Calibration for HS TIA Channel */ +#define REG_AFE_ADCOFFSETLPTIA0_RESET 0x00000000 /* Reset Value for ADCOFFSETLPTIA0 */ +#define REG_AFE_ADCOFFSETLPTIA0 0x00002288 /* AFE ADC Offset Calibration ULP-TIA0 Channel */ +#define REG_AFE_ADCGNLPTIA0_RESET 0x00004000 /* Reset Value for ADCGNLPTIA0 */ +#define REG_AFE_ADCGNLPTIA0 0x0000228C /* AFE ADC GAIN Calibration for LP TIA0 Channel */ +#define REG_AFE_ADCPGAGN4OFCAL_RESET 0x00004000 /* Reset Value for ADCPGAGN4OFCAL */ +#define REG_AFE_ADCPGAGN4OFCAL 0x00002294 /* AFE ADC Gain Calibration with DC Cancellation(PGA G=4) */ +#define REG_AFE_ADCGAINGN9_RESET 0x00004000 /* Reset Value for ADCGAINGN9 */ +#define REG_AFE_ADCGAINGN9 0x00002298 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=9) */ +#define REG_AFE_ADCOFFSETEMPSENS1_RESET 0x00000000 /* Reset Value for ADCOFFSETEMPSENS1 */ +#define REG_AFE_ADCOFFSETEMPSENS1 0x000022A8 /* AFE ADC Offset Calibration Temp Sensor Channel 1 */ +#define REG_AFE_ADCGAINDIOTEMPSENS_RESET 0x00004000 /* Reset Value for ADCGAINDIOTEMPSENS */ +#define REG_AFE_ADCGAINDIOTEMPSENS 0x000022AC /* AFE ADC Gain Calibration Diode Temperature Sensor Channel */ +#define REG_AFE_DACOFFSETATTENHP_RESET 0x00000000 /* Reset Value for DACOFFSETATTENHP */ +#define REG_AFE_DACOFFSETATTENHP 0x000022B8 /* AFE DAC Offset with Attenuator Enabled (HP Mode) */ +#define REG_AFE_DACOFFSETHP_RESET 0x00000000 /* Reset Value for DACOFFSETHP */ +#define REG_AFE_DACOFFSETHP 0x000022BC /* AFE DAC Offset with Attenuator Disabled (HP Mode) */ +#define REG_AFE_ADCGNLPTIA1_RESET 0x00004000 /* Reset Value for ADCGNLPTIA1 */ +#define REG_AFE_ADCOFFSETLPTIA1 0x000022C0 /* AFE ADC Offset Calibration ULP-TIA0 Channel */ +#define REG_AFE_ADCGNLPTIA1 0x000022C4 /* AFE ADC GAIN Calibration for LP TIA1 Channel */ +#define REG_AFE_ADCOFFSETGN2_RESET 0x00000000 /* Reset Value for ADCOFFSETGN2 */ +#define REG_AFE_ADCOFFSETGN2 0x000022C8 /* AFE Offset Calibration Auxiliary Channel (PGA Gain =2) */ +#define REG_AFE_ADCOFFSETGN1P5_RESET 0x00000000 /* Reset Value for ADCOFFSETGN1P5 */ +#define REG_AFE_ADCOFFSETGN1P5 0x000022CC /* AFE Offset Calibration Auxiliary Channel (PGA Gain =1.5) */ +#define REG_AFE_ADCOFFSETGN9_RESET 0x00000000 /* Reset Value for ADCOFFSETGN9 */ +#define REG_AFE_ADCOFFSETGN9 0x000022D0 /* AFE Offset Calibration Auxiliary Channel (PGA Gain =9) */ +#define REG_AFE_ADCOFFSETGN4_RESET 0x00000000 /* Reset Value for ADCOFFSETGN4 */ +#define REG_AFE_ADCOFFSETGN4 0x000022D4 /* AFE Offset Calibration Auxiliary Channel (PGA Gain =4) */ +#define REG_AFE_PMBW_RESET 0x00088800 /* Reset Value for PMBW */ +#define REG_AFE_PMBW 0x000022F0 /* AFE Power Mode Configuration */ +#define REG_AFE_SWMUX_RESET 0x00000000 /* Reset Value for SWMUX */ +#define REG_AFE_SWMUX 0x0000235C /* AFE Switch Mux for ECG */ +#define REG_AFE_AFE_TEMPSEN_DIO_RESET 0x00020000 /* Reset Value for AFE_TEMPSEN_DIO */ +#define REG_AFE_AFE_TEMPSEN_DIO 0x00002374 /* AFE AFE_TEMPSEN_DIO */ +#define REG_AFE_ADCBUFCON_RESET 0x005F3D00 /* Reset Value for ADCBUFCON */ +#define REG_AFE_ADCBUFCON 0x0000238C /* AFE Configure ADC Input Buffer */ + +/* ============================================================================================================================ + AFE Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_AFECON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_AFECON_DACBUFEN 21 /* Enable DC DAC Buffer */ +#define BITP_AFE_AFECON_DACREFEN 20 /* High Speed DAC Reference Enable */ +#define BITP_AFE_AFECON_ALDOILIMITEN 19 /* Analog LDO Current Limiting Enable */ +#define BITP_AFE_AFECON_SINC2EN 16 /* ADC Output 50/60Hz Filter Enable */ +#define BITP_AFE_AFECON_DFTEN 15 /* DFT Hardware Accelerator Enable */ +#define BITP_AFE_AFECON_WAVEGENEN 14 /* Waveform Generator Enable */ +#define BITP_AFE_AFECON_TEMPCONVEN 13 /* ADC Temp Sensor Convert Enable */ +#define BITP_AFE_AFECON_TEMPSENSEN 12 /* ADC Temperature Sensor Channel Enable */ +#define BITP_AFE_AFECON_TIAEN 11 /* High Power TIA Enable */ +#define BITP_AFE_AFECON_INAMPEN 10 /* Enable Excitation Amplifier */ +#define BITP_AFE_AFECON_EXBUFEN 9 /* Enable Excitation Buffer */ +#define BITP_AFE_AFECON_ADCCONVEN 8 /* ADC Conversion Start Enable */ +#define BITP_AFE_AFECON_ADCEN 7 /* ADC Power Enable */ +#define BITP_AFE_AFECON_DACEN 6 /* High Power DAC Enable */ +#define BITP_AFE_AFECON_HPREFDIS 5 /* Disable High Power Reference */ +#define BITM_AFE_AFECON_DACBUFEN 0x00200000 /* Enable DC DAC Buffer */ +#define BITM_AFE_AFECON_DACREFEN 0x00100000 /* High Speed DAC Reference Enable */ +#define BITM_AFE_AFECON_ALDOILIMITEN 0x00080000 /* Analog LDO Current Limiting Enable */ +#define BITM_AFE_AFECON_SINC2EN 0x00010000 /* ADC Output 50/60Hz Filter Enable */ +#define BITM_AFE_AFECON_DFTEN 0x00008000 /* DFT Hardware Accelerator Enable */ +#define BITM_AFE_AFECON_WAVEGENEN 0x00004000 /* Waveform Generator Enable */ +#define BITM_AFE_AFECON_TEMPCONVEN 0x00002000 /* ADC Temp Sensor Convert Enable */ +#define BITM_AFE_AFECON_TEMPSENSEN 0x00001000 /* ADC Temperature Sensor Channel Enable */ +#define BITM_AFE_AFECON_TIAEN 0x00000800 /* High Power TIA Enable */ +#define BITM_AFE_AFECON_INAMPEN 0x00000400 /* Enable Excitation Amplifier */ +#define BITM_AFE_AFECON_EXBUFEN 0x00000200 /* Enable Excitation Buffer */ +#define BITM_AFE_AFECON_ADCCONVEN 0x00000100 /* ADC Conversion Start Enable */ +#define BITM_AFE_AFECON_ADCEN 0x00000080 /* ADC Power Enable */ +#define BITM_AFE_AFECON_DACEN 0x00000040 /* High Power DAC Enable */ +#define BITM_AFE_AFECON_HPREFDIS 0x00000020 /* Disable High Power Reference */ +#define ENUM_AFE_AFECON_OFF 0x00000000 /* DACEN: High Power DAC Disabled */ +#define ENUM_AFE_AFECON_ON 0x00000040 /* DACEN: High Power DAC Enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQCON_SEQWRTMR 8 /* Timer for Sequencer Write Commands */ +#define BITP_AFE_SEQCON_SEQHALT 4 /* Halt Seq */ +#define BITP_AFE_SEQCON_SEQHALTFIFOEMPTY 1 /* Halt Sequencer If Empty */ +#define BITP_AFE_SEQCON_SEQEN 0 /* Enable Sequencer */ +#define BITM_AFE_SEQCON_SEQWRTMR 0x0000FF00 /* Timer for Sequencer Write Commands */ +#define BITM_AFE_SEQCON_SEQHALT 0x00000010 /* Halt Seq */ +#define BITM_AFE_SEQCON_SEQHALTFIFOEMPTY 0x00000002 /* Halt Sequencer If Empty */ +#define BITM_AFE_SEQCON_SEQEN 0x00000001 /* Enable Sequencer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_FIFOCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_FIFOCON_DATAFIFOSRCSEL 13 /* Selects the Source for the Data FIFO. */ +#define BITP_AFE_FIFOCON_DATAFIFOEN 11 /* Data FIFO Enable. */ +#define BITM_AFE_FIFOCON_DATAFIFOSRCSEL 0x0000E000 /* Selects the Source for the Data FIFO. */ +#define BITM_AFE_FIFOCON_DATAFIFOEN 0x00000800 /* Data FIFO Enable. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SWCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SWCON_T11CON 19 /* Control of T[11] */ +#define BITP_AFE_SWCON_T10CON 18 /* Control of T[10] */ +#define BITP_AFE_SWCON_T9CON 17 /* Control of T[9] */ +#define BITP_AFE_SWCON_SWSOURCESEL 16 /* Switch Control Select */ +#define BITP_AFE_SWCON_TMUXCON 12 /* Control of T Switch MUX. */ +#define BITP_AFE_SWCON_NMUXCON 8 /* Control of N Switch MUX */ +#define BITP_AFE_SWCON_PMUXCON 4 /* Control of P Switch MUX */ +#define BITP_AFE_SWCON_DMUXCON 0 /* Control of D Switch MUX */ +#define BITM_AFE_SWCON_T11CON 0x00080000 /* Control of T[11] */ +#define BITM_AFE_SWCON_T10CON 0x00040000 /* Control of T[10] */ +#define BITM_AFE_SWCON_T9CON 0x00020000 /* Control of T[9] */ +#define BITM_AFE_SWCON_SWSOURCESEL 0x00010000 /* Switch Control Select */ +#define BITM_AFE_SWCON_TMUXCON 0x0000F000 /* Control of T Switch MUX. */ +#define BITM_AFE_SWCON_NMUXCON 0x00000F00 /* Control of N Switch MUX */ +#define BITM_AFE_SWCON_PMUXCON 0x000000F0 /* Control of P Switch MUX */ +#define BITM_AFE_SWCON_DMUXCON 0x0000000F /* Control of D Switch MUX */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSDACCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_HSDACCON_INAMPGNMDE 12 /* Excitation Amplifier Gain Control */ +#define BITP_AFE_HSDACCON_RATE 1 /* DAC Update Rate */ +#define BITP_AFE_HSDACCON_ATTENEN 0 /* PGA Stage Gain Attenuation */ +#define BITM_AFE_HSDACCON_INAMPGNMDE 0x00001000 /* Excitation Amplifier Gain Control */ +#define BITM_AFE_HSDACCON_RATE 0x000001FE /* DAC Update Rate */ +#define BITM_AFE_HSDACCON_ATTENEN 0x00000001 /* PGA Stage Gain Attenuation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGCON_DACGAINCAL 5 /* Bypass DAC Gain */ +#define BITP_AFE_WGCON_DACOFFSETCAL 4 /* Bypass DAC Offset */ +#define BITP_AFE_WGCON_TYPESEL 1 /* Selects the Type of Waveform */ +#define BITP_AFE_WGCON_TRAPRSTEN 0 /* Resets the Trapezoid Waveform Generator */ +#define BITM_AFE_WGCON_DACGAINCAL 0x00000020 /* Bypass DAC Gain */ +#define BITM_AFE_WGCON_DACOFFSETCAL 0x00000010 /* Bypass DAC Offset */ +#define BITM_AFE_WGCON_TYPESEL 0x00000006 /* Selects the Type of Waveform */ +#define BITM_AFE_WGCON_TRAPRSTEN 0x00000001 /* Resets the Trapezoid Waveform Generator */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDCLEVEL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGDCLEVEL1_TRAPDCLEVEL1 0 /* DC Level 1 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDCLEVEL1_TRAPDCLEVEL1 0x00000FFF /* DC Level 1 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDCLEVEL2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGDCLEVEL2_TRAPDCLEVEL2 0 /* DC Level 2 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDCLEVEL2_TRAPDCLEVEL2 0x00000FFF /* DC Level 2 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDELAY1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGDELAY1_DELAY1 0 /* Delay 1 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDELAY1_DELAY1 0x000FFFFF /* Delay 1 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGSLOPE1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGSLOPE1_SLOPE1 0 /* Slope 1 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGSLOPE1_SLOPE1 0x000FFFFF /* Slope 1 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDELAY2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGDELAY2_DELAY2 0 /* Delay 2 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDELAY2_DELAY2 0x000FFFFF /* Delay 2 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGSLOPE2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGSLOPE2_SLOPE2 0 /* Slope 2 Value for Trapezoid Waveform Generation. */ +#define BITM_AFE_WGSLOPE2_SLOPE2 0x000FFFFF /* Slope 2 Value for Trapezoid Waveform Generation. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGFCW Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGFCW_SINEFCW 0 /* Sinusoid Generator Frequency Control Word */ +#define BITM_AFE_WGFCW_SINEFCW 0x00FFFFFF /* Sinusoid Generator Frequency Control Word */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGPHASE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGPHASE_SINEOFFSET 0 /* Sinusoid Phase Offset */ +#define BITM_AFE_WGPHASE_SINEOFFSET 0x000FFFFF /* Sinusoid Phase Offset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGOFFSET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGOFFSET_SINEOFFSET 0 /* Sinusoid Offset */ +#define BITM_AFE_WGOFFSET_SINEOFFSET 0x00000FFF /* Sinusoid Offset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGAMPLITUDE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGAMPLITUDE_SINEAMPLITUDE 0 /* Sinusoid Amplitude */ +#define BITM_AFE_WGAMPLITUDE_SINEAMPLITUDE 0x000007FF /* Sinusoid Amplitude */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCFILTERCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCFILTERCON_AVRGNUM 14 /* Number of Samples Averaged */ +#define BITP_AFE_ADCFILTERCON_SINC3OSR 12 /* SINC3 OSR */ +#define BITP_AFE_ADCFILTERCON_SINC2OSR 8 /* SINC2 OSR */ +#define BITP_AFE_ADCFILTERCON_AVRGEN 7 /* Average Function Enable */ +#define BITP_AFE_ADCFILTERCON_SINC3BYP 6 /* SINC3 Filter Bypass */ +#define BITP_AFE_ADCFILTERCON_LPFBYPEN 4 /* 50/60Hz Low Pass Filter */ +#define BITP_AFE_ADCFILTERCON_ADCCLK 0 /* ADC Data Rate */ +#define BITM_AFE_ADCFILTERCON_AVRGNUM 0x0000C000 /* Number of Samples Averaged */ +#define BITM_AFE_ADCFILTERCON_SINC3OSR 0x00003000 /* SINC3 OSR */ +#define BITM_AFE_ADCFILTERCON_SINC2OSR 0x00000F00 /* SINC2 OSR */ +#define BITM_AFE_ADCFILTERCON_AVRGEN 0x00000080 /* Average Function Enable */ +#define BITM_AFE_ADCFILTERCON_SINC3BYP 0x00000040 /* SINC3 Filter Bypass */ +#define BITM_AFE_ADCFILTERCON_LPFBYPEN 0x00000010 /* 50/60Hz Low Pass Filter */ +#define BITM_AFE_ADCFILTERCON_ADCCLK 0x00000001 /* ADC Data Rate */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSDACDAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_HSDACDAT_DACDAT 0 /* DAC Code */ +#define BITM_AFE_HSDACDAT_DACDAT 0x00000FFF /* DAC Code */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPREFBUFCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPREFBUFCON_BOOSTCURRENT 2 /* Set: Drive 2 Dac ;Unset Drive 1 Dac, and Save Power */ +#define BITP_AFE_LPREFBUFCON_LPBUF2P5DIS 1 /* Low Power Bandgap's Output Buffer */ +#define BITP_AFE_LPREFBUFCON_LPREFDIS 0 /* Set This Bit Will Power Down Low Power Bandgap */ +#define BITM_AFE_LPREFBUFCON_BOOSTCURRENT 0x00000004 /* Set: Drive 2 Dac ;Unset Drive 1 Dac, and Save Power */ +#define BITM_AFE_LPREFBUFCON_LPBUF2P5DIS 0x00000002 /* Low Power Bandgap's Output Buffer */ +#define BITM_AFE_LPREFBUFCON_LPREFDIS 0x00000001 /* Set This Bit Will Power Down Low Power Bandgap */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SYNCEXTDEVICE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SYNCEXTDEVICE_SYNC 0 /* As Output Data of GPIO */ +#define BITM_AFE_SYNCEXTDEVICE_SYNC 0x000000FF /* As Output Data of GPIO */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQCRC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQCRC_CRC 0 /* Sequencer Command CRC Value. */ +#define BITM_AFE_SEQCRC_CRC 0x000000FF /* Sequencer Command CRC Value. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQCNT_COUNT 0 /* Sequencer Command Count */ +#define BITM_AFE_SEQCNT_COUNT 0x0000FFFF /* Sequencer Command Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQTIMEOUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQTIMEOUT_TIMEOUT 0 /* Current Value of the Sequencer Timeout Counter. */ +#define BITM_AFE_SEQTIMEOUT_TIMEOUT 0x3FFFFFFF /* Current Value of the Sequencer Timeout Counter. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DATAFIFORD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DATAFIFORD_DATAFIFOOUT 0 /* Data FIFO Read */ +#define BITM_AFE_DATAFIFORD_DATAFIFOOUT 0x0000FFFF /* Data FIFO Read */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CMDFIFOWRITE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_CMDFIFOWRITE_CMDFIFOIN 0 /* Command FIFO Write. */ +#define BITM_AFE_CMDFIFOWRITE_CMDFIFOIN 0xFFFFFFFF /* Command FIFO Write. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCDAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCDAT_DATA 0 /* ADC Result */ +#define BITM_AFE_ADCDAT_DATA 0x0000FFFF /* ADC Result */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DFTREAL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DFTREAL_DATA 0 /* DFT Real */ +#define BITM_AFE_DFTREAL_DATA 0x0003FFFF /* DFT Real */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DFTIMAG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DFTIMAG_DATA 0 /* DFT Imaginary */ +#define BITM_AFE_DFTIMAG_DATA 0x0003FFFF /* DFT Imaginary */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SINC2DAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SINC2DAT_DATA 0 /* LPF Result */ +#define BITM_AFE_SINC2DAT_DATA 0x0000FFFF /* LPF Result */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TEMPSENSDAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_TEMPSENSDAT_DATA 0 /* Temp Sensor */ +#define BITM_AFE_TEMPSENSDAT_DATA 0x0000FFFF /* Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_AFEGENINTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ3 3 /* Custom IRQ 3. */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ2 2 /* Custom IRQ 2 */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ1 1 /* Custom IRQ 1. */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ0 0 /* Custom IRQ 0 */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ3 0x00000008 /* Custom IRQ 3. */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ2 0x00000004 /* Custom IRQ 2 */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ1 0x00000002 /* Custom IRQ 1. */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ0 0x00000001 /* Custom IRQ 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMIN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCMIN_MINVAL 0 /* ADC Minimum Value Threshold */ +#define BITM_AFE_ADCMIN_MINVAL 0x0000FFFF /* ADC Minimum Value Threshold */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMINSM Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCMINSM_MINCLRVAL 0 /* ADCMIN Hysteresis Value */ +#define BITM_AFE_ADCMINSM_MINCLRVAL 0x0000FFFF /* ADCMIN Hysteresis Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMAX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCMAX_MAXVAL 0 /* ADC Max Threshold */ +#define BITM_AFE_ADCMAX_MAXVAL 0x0000FFFF /* ADC Max Threshold */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMAXSMEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCMAXSMEN_MAXSWEN 0 /* ADCMAX Hysteresis Value */ +#define BITM_AFE_ADCMAXSMEN_MAXSWEN 0x0000FFFF /* ADCMAX Hysteresis Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCDELTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCDELTA_DELTAVAL 0 /* ADCDAT Code Differences Limit Option */ +#define BITM_AFE_ADCDELTA_DELTAVAL 0x0000FFFF /* ADCDAT Code Differences Limit Option */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HPOSCCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_HPOSCCON_CLK32MHZEN 2 /* 16M/32M Output Selector Signal. */ +#define BITM_AFE_HPOSCCON_CLK32MHZEN 0x00000004 /* 16M/32M Output Selector Signal. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DFTCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DFTCON_DFTINSEL 20 /* DFT Input Select */ +#define BITP_AFE_DFTCON_DFTNUM 4 /* ADC Samples Used */ +#define BITP_AFE_DFTCON_HANNINGEN 0 /* Hanning Window Enable */ +#define BITM_AFE_DFTCON_DFTINSEL 0x00300000 /* DFT Input Select */ +#define BITM_AFE_DFTCON_DFTNUM 0x000000F0 /* ADC Samples Used */ +#define BITM_AFE_DFTCON_HANNINGEN 0x00000001 /* Hanning Window Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIASW1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPTIASW1_TIABIASSEL 13 /* TIA SW13 Control. Active High */ +#define BITP_AFE_LPTIASW1_PABIASSEL 12 /* TIA SW12 Control. Active High */ +#define BITP_AFE_LPTIASW1_TIASWCON 0 /* TIA SW[11:0] Control */ +#define BITM_AFE_LPTIASW1_TIABIASSEL (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* TIA SW13 Control. Active High */ +#define BITM_AFE_LPTIASW1_PABIASSEL (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* TIA SW12 Control. Active High */ +#define BITM_AFE_LPTIASW1_TIASWCON (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t )) /* TIA SW[11:0] Control */ +#define ENUM_AFE_LPTIASW1_CAPA_LP (_ADI_MSK_3(0x00000014,0x00000014UL, uint32_t )) /* TIASWCON: CAPA test with LP TIA */ +#define ENUM_AFE_LPTIASW1_NORM (_ADI_MSK_3(0x0000002C,0x0000002CUL, uint32_t )) /* TIASWCON: Normal work mode */ +#define ENUM_AFE_LPTIASW1_DIO (_ADI_MSK_3(0x0000002D,0x0000002DUL, uint32_t )) /* TIASWCON: Normal work mode with back-back diode enabled. */ +#define ENUM_AFE_LPTIASW1_SHORTSW (_ADI_MSK_3(0x0000002E,0x0000002EUL, uint32_t )) /* TIASWCON: Work mode with short switch protection */ +#define ENUM_AFE_LPTIASW1_LOWNOISE (_ADI_MSK_3(0x0000006C,0x0000006CUL, uint32_t )) /* TIASWCON: Work mode, vzero-vbias=0. */ +#define ENUM_AFE_LPTIASW1_CAPA_RAMP_H (_ADI_MSK_3(0x00000094,0x00000094UL, uint32_t )) /* TIASWCON: CAPA test or Ramp test with HP TIA */ +#define ENUM_AFE_LPTIASW1_BUFDIS (_ADI_MSK_3(0x00000180,0x00000180UL, uint32_t )) /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW1_BUFEN (_ADI_MSK_3(0x000001A4,0x000001A4UL, uint32_t )) /* TIASWCON: Set PA/TIA as unity gain buffer. Connect amp's output to CE1 & RC11. */ +#define ENUM_AFE_LPTIASW1_TWOLEAD (_ADI_MSK_3(0x0000042C,0x0000042CUL, uint32_t )) /* TIASWCON: Two lead sensor, set PA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW1_BUFEN2 (_ADI_MSK_3(0x000004A4,0x000004A4UL, uint32_t )) /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW1_SESHORTRE (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* TIASWCON: Close SW11 - Short SE1 to RE1, */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIASW0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPTIASW0_RECAL 15 /* TIA SW15 Control. Active High */ +#define BITP_AFE_LPTIASW0_VZEROSHARE 14 /* TIA SW14 Control. Active High */ +#define BITP_AFE_LPTIASW0_TIABIASSEL 13 /* TIA SW13 Control. Active High */ +#define BITP_AFE_LPTIASW0_PABIASSEL 12 /* TIA SW12 Control. Active High */ +#define BITP_AFE_LPTIASW0_TIASWCON 0 /* TIA SW[11:0] Control */ +#define BITM_AFE_LPTIASW0_RECAL 0x00008000 /* TIA SW15 Control. Active High */ +#define BITM_AFE_LPTIASW0_VZEROSHARE 0x00004000 /* TIA SW14 Control. Active High */ +#define BITM_AFE_LPTIASW0_TIABIASSEL 0x00002000 /* TIA SW13 Control. Active High */ +#define BITM_AFE_LPTIASW0_PABIASSEL 0x00001000 /* TIA SW12 Control. Active High */ +#define BITM_AFE_LPTIASW0_TIASWCON 0x00000FFF /* TIA SW[11:0] Control */ +#define ENUM_AFE_LPTIASW0_11 0x00000014 /* TIASWCON: CAPA test with LP TIA */ +#define ENUM_AFE_LPTIASW0_NORM 0x0000002C /* TIASWCON: Normal work mode */ +#define ENUM_AFE_LPTIASW0_DIO 0x0000002D /* TIASWCON: Normal work mode with back-back diode enabled. */ +#define ENUM_AFE_LPTIASW0_SHORTSW 0x0000002E /* TIASWCON: Work mode with short switch protection */ +#define ENUM_AFE_LPTIASW0_LOWNOISE 0x0000006C /* TIASWCON: Work mode, vzero-vbias=0. */ +#define ENUM_AFE_LPTIASW0_1 0x00000094 /* TIASWCON: CAPA test or Ramp test with HP TIA */ +#define ENUM_AFE_LPTIASW0_BUFDIS 0x00000180 /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW0_BUFEN 0x000001A4 /* TIASWCON: Set PA/TIA as unity gain buffer. Connect amp's output to CE0 & RC01. */ +#define ENUM_AFE_LPTIASW0_TWOLEAD 0x0000042C /* TIASWCON: Two lead sensor, set PA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW0_BUFEN2 0x000004A4 /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW0_SESHORTRE 0x00000800 /* TIASWCON: Close SW11 - Short SE0 to RE0. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIACON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPTIACON1_CHOPEN 16 /* Chopping Enable */ +#define BITP_AFE_LPTIACON1_TIARF 13 /* Set LPF Resistor */ +#define BITP_AFE_LPTIACON1_TIARL 10 /* Set RLOAD */ +#define BITP_AFE_LPTIACON1_TIAGAIN 5 /* Set RTIA Gain Resistor */ +#define BITP_AFE_LPTIACON1_IBOOST 3 /* Current Boost Control */ +#define BITP_AFE_LPTIACON1_HALFPWR 2 /* Half Power Mode Select */ +#define BITP_AFE_LPTIACON1_PAPDEN 1 /* PA Power Down */ +#define BITP_AFE_LPTIACON1_TIAPDEN 0 /* TIA Power Down */ +#define BITM_AFE_LPTIACON1_CHOPEN (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t )) /* Chopping Enable */ +#define BITM_AFE_LPTIACON1_TIARF (_ADI_MSK_3(0x0000E000,0x0000E000UL, uint32_t )) /* Set LPF Resistor */ +#define BITM_AFE_LPTIACON1_TIARL (_ADI_MSK_3(0x00001C00,0x00001C00UL, uint32_t )) /* Set RLOAD */ +#define BITM_AFE_LPTIACON1_TIAGAIN (_ADI_MSK_3(0x000003E0,0x000003E0UL, uint32_t )) /* Set RTIA Gain Resistor */ +#define BITM_AFE_LPTIACON1_IBOOST (_ADI_MSK_3(0x00000018,0x00000018UL, uint32_t )) /* Current Boost Control */ +#define BITM_AFE_LPTIACON1_HALFPWR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Half Power Mode Select */ +#define BITM_AFE_LPTIACON1_PAPDEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* PA Power Down */ +#define BITM_AFE_LPTIACON1_TIAPDEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* TIA Power Down */ +#define ENUM_AFE_LPTIACON1_DISCONRF (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* TIARF: Disconnect TIA output from LPF pin */ +#define ENUM_AFE_LPTIACON1_BYPRF (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* TIARF: Bypass resistor */ +#define ENUM_AFE_LPTIACON1_RF20K (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* TIARF: 20k Ohm */ +#define ENUM_AFE_LPTIACON1_RF100K (_ADI_MSK_3(0x00006000,0x00006000UL, uint32_t )) /* TIARF: 100k Ohm */ +#define ENUM_AFE_LPTIACON1_RF200K (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* TIARF: 200k Ohm */ +#define ENUM_AFE_LPTIACON1_RF400K (_ADI_MSK_3(0x0000A000,0x0000A000UL, uint32_t )) /* TIARF: 400k Ohm */ +#define ENUM_AFE_LPTIACON1_RF600K (_ADI_MSK_3(0x0000C000,0x0000C000UL, uint32_t )) /* TIARF: 600k Ohm */ +#define ENUM_AFE_LPTIACON1_RF1MOHM (_ADI_MSK_3(0x0000E000,0x0000E000UL, uint32_t )) /* TIARF: 1Meg Ohm */ +#define ENUM_AFE_LPTIACON1_RL0 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* TIARL: 0 ohm */ +#define ENUM_AFE_LPTIACON1_RL10 (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* TIARL: 10 ohm */ +#define ENUM_AFE_LPTIACON1_RL30 (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* TIARL: 30 ohm */ +#define ENUM_AFE_LPTIACON1_RL50 (_ADI_MSK_3(0x00000C00,0x00000C00UL, uint32_t )) /* TIARL: 50 ohm */ +#define ENUM_AFE_LPTIACON1_RL100 (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* TIARL: 100 ohm */ +#define ENUM_AFE_LPTIACON1_RL1P6K (_ADI_MSK_3(0x00001400,0x00001400UL, uint32_t )) /* TIARL: 1.6kohm */ +#define ENUM_AFE_LPTIACON1_RL3P1K (_ADI_MSK_3(0x00001800,0x00001800UL, uint32_t )) /* TIARL: 3.1kohm */ +#define ENUM_AFE_LPTIACON1_RL3P5K (_ADI_MSK_3(0x00001C00,0x00001C00UL, uint32_t )) /* TIARL: 3.6kohm */ +#define ENUM_AFE_LPTIACON1_DISCONTIA (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* TIAGAIN: Disconnect TIA Gain resistor */ +#define ENUM_AFE_LPTIACON1_TIAGAIN200 (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* TIAGAIN: 200 Ohm */ +#define ENUM_AFE_LPTIACON1_TIAGAIN1K (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* TIAGAIN: 1k ohm */ +#define ENUM_AFE_LPTIACON1_TIAGAIN2K (_ADI_MSK_3(0x00000060,0x00000060UL, uint32_t )) /* TIAGAIN: 2k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN3K (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* TIAGAIN: 3k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN4K (_ADI_MSK_3(0x000000A0,0x000000A0UL, uint32_t )) /* TIAGAIN: 4k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN6K (_ADI_MSK_3(0x000000C0,0x000000C0UL, uint32_t )) /* TIAGAIN: 6k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN8K (_ADI_MSK_3(0x000000E0,0x000000E0UL, uint32_t )) /* TIAGAIN: 8k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN10K (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* TIAGAIN: 10k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN12K (_ADI_MSK_3(0x00000120,0x00000120UL, uint32_t )) /* TIAGAIN: 12k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN16K (_ADI_MSK_3(0x00000140,0x00000140UL, uint32_t )) /* TIAGAIN: 16k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN20K (_ADI_MSK_3(0x00000160,0x00000160UL, uint32_t )) /* TIAGAIN: 20k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN24K (_ADI_MSK_3(0x00000180,0x00000180UL, uint32_t )) /* TIAGAIN: 24k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN30K (_ADI_MSK_3(0x000001A0,0x000001A0UL, uint32_t )) /* TIAGAIN: 30k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN32K (_ADI_MSK_3(0x000001C0,0x000001C0UL, uint32_t )) /* TIAGAIN: 32k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN40K (_ADI_MSK_3(0x000001E0,0x000001E0UL, uint32_t )) /* TIAGAIN: 40k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN48K (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* TIAGAIN: 48k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN64K (_ADI_MSK_3(0x00000220,0x00000220UL, uint32_t )) /* TIAGAIN: 64k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN85K (_ADI_MSK_3(0x00000240,0x00000240UL, uint32_t )) /* TIAGAIN: 85k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN96K (_ADI_MSK_3(0x00000260,0x00000260UL, uint32_t )) /* TIAGAIN: 96k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN100K (_ADI_MSK_3(0x00000280,0x00000280UL, uint32_t )) /* TIAGAIN: 100k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN120K (_ADI_MSK_3(0x000002A0,0x000002A0UL, uint32_t )) /* TIAGAIN: 120k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN128K (_ADI_MSK_3(0x000002C0,0x000002C0UL, uint32_t )) /* TIAGAIN: 128k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN160K (_ADI_MSK_3(0x000002E0,0x000002E0UL, uint32_t )) /* TIAGAIN: 160k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN196K (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* TIAGAIN: 196k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN256K (_ADI_MSK_3(0x00000320,0x00000320UL, uint32_t )) /* TIAGAIN: 256k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN512K (_ADI_MSK_3(0x00000340,0x00000340UL, uint32_t )) /* TIAGAIN: 512k */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIACON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPTIACON0_CHOPEN 16 /* Chopping Enable */ +#define BITP_AFE_LPTIACON0_TIARF 13 /* Set LPF Resistor */ +#define BITP_AFE_LPTIACON0_TIARL 10 /* Set RLOAD */ +#define BITP_AFE_LPTIACON0_TIAGAIN 5 /* Set RTIA */ +#define BITP_AFE_LPTIACON0_IBOOST 3 /* Current Boost Control */ +#define BITP_AFE_LPTIACON0_HALFPWR 2 /* Half Power Mode Select */ +#define BITP_AFE_LPTIACON0_PAPDEN 1 /* PA Power Down */ +#define BITP_AFE_LPTIACON0_TIAPDEN 0 /* TIA Power Down */ +#define BITM_AFE_LPTIACON0_CHOPEN 0x00030000 /* Chopping Enable */ +#define BITM_AFE_LPTIACON0_TIARF 0x0000E000 /* Set LPF Resistor */ +#define BITM_AFE_LPTIACON0_TIARL 0x00001C00 /* Set RLOAD */ +#define BITM_AFE_LPTIACON0_TIAGAIN 0x000003E0 /* Set RTIA */ +#define BITM_AFE_LPTIACON0_IBOOST 0x00000018 /* Current Boost Control */ +#define BITM_AFE_LPTIACON0_HALFPWR 0x00000004 /* Half Power Mode Select */ +#define BITM_AFE_LPTIACON0_PAPDEN 0x00000002 /* PA Power Down */ +#define BITM_AFE_LPTIACON0_TIAPDEN 0x00000001 /* TIA Power Down */ +#define ENUM_AFE_LPTIACON0_DISCONRF 0x00000000 /* TIARF: Disconnect TIA output from LPF pin */ +#define ENUM_AFE_LPTIACON0_BYPRF 0x00002000 /* TIARF: Bypass resistor */ +#define ENUM_AFE_LPTIACON0_RF20K 0x00004000 /* TIARF: 20k Ohm */ +#define ENUM_AFE_LPTIACON0_RF100K 0x00006000 /* TIARF: 100k Ohm */ +#define ENUM_AFE_LPTIACON0_RF200K 0x00008000 /* TIARF: 200k Ohm */ +#define ENUM_AFE_LPTIACON0_RF400K 0x0000A000 /* TIARF: 400k Ohm */ +#define ENUM_AFE_LPTIACON0_RF600K 0x0000C000 /* TIARF: 600k Ohm */ +#define ENUM_AFE_LPTIACON0_RF1MOHM 0x0000E000 /* TIARF: 1Meg Ohm */ +#define ENUM_AFE_LPTIACON0_RL0 0x00000000 /* TIARL: 0 ohm */ +#define ENUM_AFE_LPTIACON0_RL10 0x00000400 /* TIARL: 10 ohm */ +#define ENUM_AFE_LPTIACON0_RL30 0x00000800 /* TIARL: 30 ohm */ +#define ENUM_AFE_LPTIACON0_RL50 0x00000C00 /* TIARL: 50 ohm */ +#define ENUM_AFE_LPTIACON0_RL100 0x00001000 /* TIARL: 100 ohm */ +#define ENUM_AFE_LPTIACON0_RL1P6K 0x00001400 /* TIARL: 1.6kohm */ +#define ENUM_AFE_LPTIACON0_RL3P1K 0x00001800 /* TIARL: 3.1kohm */ +#define ENUM_AFE_LPTIACON0_RL3P5K 0x00001C00 /* TIARL: 3.6kohm */ +#define ENUM_AFE_LPTIACON0_DISCONTIA 0x00000000 /* TIAGAIN: Disconnect TIA Gain resistor */ +#define ENUM_AFE_LPTIACON0_TIAGAIN200 0x00000020 /* TIAGAIN: 200 Ohm */ +#define ENUM_AFE_LPTIACON0_TIAGAIN1K 0x00000040 /* TIAGAIN: 1k ohm */ +#define ENUM_AFE_LPTIACON0_TIAGAIN2K 0x00000060 /* TIAGAIN: 2k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN3K 0x00000080 /* TIAGAIN: 3k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN4K 0x000000A0 /* TIAGAIN: 4k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN6K 0x000000C0 /* TIAGAIN: 6k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN8K 0x000000E0 /* TIAGAIN: 8k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN10K 0x00000100 /* TIAGAIN: 10k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN12K 0x00000120 /* TIAGAIN: 12k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN16K 0x00000140 /* TIAGAIN: 16k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN20K 0x00000160 /* TIAGAIN: 20k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN24K 0x00000180 /* TIAGAIN: 24k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN30K 0x000001A0 /* TIAGAIN: 30k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN32K 0x000001C0 /* TIAGAIN: 32k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN40K 0x000001E0 /* TIAGAIN: 40k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN48K 0x00000200 /* TIAGAIN: 48k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN64K 0x00000220 /* TIAGAIN: 64k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN85K 0x00000240 /* TIAGAIN: 85k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN96K 0x00000260 /* TIAGAIN: 96k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN100K 0x00000280 /* TIAGAIN: 100k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN120K 0x000002A0 /* TIAGAIN: 120k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN128K 0x000002C0 /* TIAGAIN: 128k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN160K 0x000002E0 /* TIAGAIN: 160k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN196K 0x00000300 /* TIAGAIN: 196k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN256K 0x00000320 /* TIAGAIN: 256k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN512K 0x00000340 /* TIAGAIN: 512k */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSRTIACON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_HSRTIACON_CTIACON 5 /* Configure Capacitor in Parallel with RTIA */ +#define BITP_AFE_HSRTIACON_TIASW6CON 4 /* SW6 Control */ +#define BITP_AFE_HSRTIACON_RTIACON 0 /* Configure General RTIA Value */ +#define BITM_AFE_HSRTIACON_CTIACON 0x00001FE0 /* Configure Capacitor in Parallel with RTIA */ +#define BITM_AFE_HSRTIACON_TIASW6CON 0x00000010 /* SW6 Control */ +#define BITM_AFE_HSRTIACON_RTIACON 0x0000000F /* Configure General RTIA Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DE1RESCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DE1RESCON_DE1RCON 0 /* DE1 RLOAD RTIA Setting */ +#define BITM_AFE_DE1RESCON_DE1RCON (_ADI_MSK_3(0x000000FF,0x000000FFUL, uint32_t )) /* DE1 RLOAD RTIA Setting */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DE0RESCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DE0RESCON_DE0RCON 0 /* DE0 RLOAD RTIA Setting */ +#define BITM_AFE_DE0RESCON_DE0RCON 0x000000FF /* DE0 RLOAD RTIA Setting */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSTIACON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_HSTIACON_VBIASSEL 0 /* Select HSTIA Positive Input */ +#define BITM_AFE_HSTIACON_VBIASSEL 0x00000003 /* Select HSTIA Positive Input */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACDCBUFCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DACDCBUFCON_CHANSEL 1 /* DAC DC Channel Selection */ +#define BITP_AFE_DACDCBUFCON_RESERVED_0 0 /* Reserved */ +#define BITM_AFE_DACDCBUFCON_CHANSEL (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* DAC DC Channel Selection */ +#define BITM_AFE_DACDCBUFCON_RESERVED_0 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Reserved */ +#define ENUM_AFE_DACDCBUFCON_CHAN0 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* CHANSEL: ULPDAC0 Sets DC level */ +#define ENUM_AFE_DACDCBUFCON_CHAN1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* CHANSEL: ULPDAC1 Sets DC level */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPMODEKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPMODEKEY_KEY 0 /* LP Key */ +#define BITM_AFE_LPMODEKEY_KEY 0x000FFFFF /* LP Key */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPMODECLKSEL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPMODECLKSEL_LFSYSCLKEN 0 /* Enable Switching System Clock to 32KHz by Sequencer */ +#define BITM_AFE_LPMODECLKSEL_LFSYSCLKEN 0x00000001 /* Enable Switching System Clock to 32KHz by Sequencer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPMODECON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPMODECON_ALDOEN 8 /* Set High to Power Down of Analog LDO */ +#define BITP_AFE_LPMODECON_V1P1HPADCEN 7 /* Set High to Enable 1.1V HP CM Buffer */ +#define BITP_AFE_LPMODECON_V1P8HPADCEN 6 /* Set High to Enable HP 1.8V Reference Buffer */ +#define BITP_AFE_LPMODECON_PTATEN 5 /* Set to High to Generate Ptat Current Bias */ +#define BITP_AFE_LPMODECON_ZTATEN 4 /* Set High to Generate Ztat Current Bias */ +#define BITP_AFE_LPMODECON_REPEATADCCNVEN_P 3 /* Set High to Enable Repeat ADC Conversion */ +#define BITP_AFE_LPMODECON_ADCCONVEN 2 /* Set High to Enable ADC Conversion */ +#define BITP_AFE_LPMODECON_HPREFDIS 1 /* Set High to Power Down HP Reference */ +#define BITP_AFE_LPMODECON_HFOSCPD 0 /* Set High to Power Down HP Power Oscillator */ +#define BITM_AFE_LPMODECON_ALDOEN 0x00000100 /* Set High to Power Down of Analog LDO */ +#define BITM_AFE_LPMODECON_V1P1HPADCEN 0x00000080 /* Set High to Enable 1.1V HP CM Buffer */ +#define BITM_AFE_LPMODECON_V1P8HPADCEN 0x00000040 /* Set High to Enable HP 1.8V Reference Buffer */ +#define BITM_AFE_LPMODECON_PTATEN 0x00000020 /* Set to High to Generate Ptat Current Bias */ +#define BITM_AFE_LPMODECON_ZTATEN 0x00000010 /* Set High to Generate Ztat Current Bias */ +#define BITM_AFE_LPMODECON_REPEATADCCNVEN_P 0x00000008 /* Set High to Enable Repeat ADC Conversion */ +#define BITM_AFE_LPMODECON_ADCCONVEN 0x00000004 /* Set High to Enable ADC Conversion */ +#define BITM_AFE_LPMODECON_HPREFDIS 0x00000002 /* Set High to Power Down HP Reference */ +#define BITM_AFE_LPMODECON_HFOSCPD 0x00000001 /* Set High to Power Down HP Power Oscillator */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQSLPLOCK Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQSLPLOCK_SEQ_SLP_PW 0 /* Password for SLPBYSEQ Register */ +#define BITM_AFE_SEQSLPLOCK_SEQ_SLP_PW 0x000FFFFF /* Password for SLPBYSEQ Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQTRGSLP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQTRGSLP_TRGSLP 0 /* Trigger Sleep by Sequencer */ +#define BITM_AFE_SEQTRGSLP_TRGSLP 0x00000001 /* Trigger Sleep by Sequencer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACDAT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPDACDAT0_DACIN6 12 /* 6BITVAL, 1LSB=34.375mV */ +#define BITP_AFE_LPDACDAT0_DACIN12 0 /* 12BITVAL, 1LSB=537uV */ +#define BITM_AFE_LPDACDAT0_DACIN6 0x0003F000 /* 6BITVAL, 1LSB=34.375mV */ +#define BITM_AFE_LPDACDAT0_DACIN12 0x00000FFF /* 12BITVAL, 1LSB=537uV */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACSW0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPDACSW0_LPMODEDIS 5 /* Switch Control */ +#define BITP_AFE_LPDACSW0_LPDACSW 0 /* LPDAC0 Switches Matrix */ +#define BITM_AFE_LPDACSW0_LPMODEDIS 0x00000020 /* Switch Control */ +#define BITM_AFE_LPDACSW0_LPDACSW 0x0000001F /* LPDAC0 Switches Matrix */ +#define ENUM_AFE_LPDACSW0_DACCONBIT5 0x00000000 /* LPMODEDIS: REG_AFE_LPDACDAT0 Switch controlled by REG_AFE_LPDACDAT0CON0 bit 5 */ +#define ENUM_AFE_LPDACSW0_OVRRIDE 0x00000020 /* LPMODEDIS: REG_AFE_LPDACDAT0 Switches override */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACCON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPDACCON0_WAVETYPE 6 /* LPDAC Data Source */ +#define BITP_AFE_LPDACCON0_DACMDE 5 /* LPDAC0 Switch Settings */ +#define BITP_AFE_LPDACCON0_VZEROMUX 4 /* VZERO MUX Select */ +#define BITP_AFE_LPDACCON0_VBIASMUX 3 /* VBIAS MUX Select */ +#define BITP_AFE_LPDACCON0_REFSEL 2 /* Reference Select Bit */ +#define BITP_AFE_LPDACCON0_PWDEN 1 /* LPDAC0 Power Down */ +#define BITP_AFE_LPDACCON0_RSTEN 0 /* Enable Writes to REG_AFE_LPDACDAT00 */ +#define BITM_AFE_LPDACCON0_WAVETYPE 0x00000040 /* LPDAC Data Source */ +#define BITM_AFE_LPDACCON0_DACMDE 0x00000020 /* LPDAC0 Switch Settings */ +#define BITM_AFE_LPDACCON0_VZEROMUX 0x00000010 /* VZERO MUX Select */ +#define BITM_AFE_LPDACCON0_VBIASMUX 0x00000008 /* VBIAS MUX Select */ +#define BITM_AFE_LPDACCON0_REFSEL 0x00000004 /* Reference Select Bit */ +#define BITM_AFE_LPDACCON0_PWDEN 0x00000002 /* LPDAC0 Power Down */ +#define BITM_AFE_LPDACCON0_RSTEN 0x00000001 /* Enable Writes to REG_AFE_LPDACDAT00 */ +#define ENUM_AFE_LPDACCON0_MMR 0x00000000 /* WAVETYPE: Direct from REG_AFE_LPDACDAT0DAT0 */ +#define ENUM_AFE_LPDACCON0_WAVEGEN 0x00000040 /* WAVETYPE: Waveform generator */ +#define ENUM_AFE_LPDACCON0_NORM 0x00000000 /* DACMDE: REG_AFE_LPDACDAT00 switches set for normal mode */ +#define ENUM_AFE_LPDACCON0_DIAG 0x00000020 /* DACMDE: REG_AFE_LPDACDAT00 switches set for Diagnostic mode */ +#define ENUM_AFE_LPDACCON0_BITS6 0x00000000 /* VZEROMUX: VZERO 6BIT */ +#define ENUM_AFE_LPDACCON0_BITS12 0x00000010 /* VZEROMUX: VZERO 12BIT */ +#define ENUM_AFE_LPDACCON0_12BIT 0x00000000 /* VBIASMUX: Output 12Bit */ +#define ENUM_AFE_LPDACCON0_EN 0x00000008 /* VBIASMUX: output 6Bit */ +#define ENUM_AFE_LPDACCON0_ULPREF 0x00000000 /* REFSEL: ULP2P5V Ref */ +#define ENUM_AFE_LPDACCON0_AVDD 0x00000004 /* REFSEL: AVDD Reference */ +#define ENUM_AFE_LPDACCON0_PWREN 0x00000000 /* PWDEN: REG_AFE_LPDACDAT00 Powered On */ +#define ENUM_AFE_LPDACCON0_PWRDIS 0x00000002 /* PWDEN: REG_AFE_LPDACDAT00 Powered Off */ +#define ENUM_AFE_LPDACCON0_WRITEDIS 0x00000000 /* RSTEN: Disable REG_AFE_LPDACDAT00 Writes */ +#define ENUM_AFE_LPDACCON0_WRITEEN 0x00000001 /* RSTEN: Enable REG_AFE_LPDACDAT00 Writes */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACDAT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPDACDAT1_DACIN6 12 /* 6BITVAL, 1LSB=34.375mV */ +#define BITP_AFE_LPDACDAT1_DACIN12 0 /* 12BITVAL, 1LSB=537uV */ +#define BITM_AFE_LPDACDAT1_DACIN6 (_ADI_MSK_3(0x0003F000,0x0003F000UL, uint32_t )) /* 6BITVAL, 1LSB=34.375mV */ +#define BITM_AFE_LPDACDAT1_DACIN12 (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t )) /* 12BITVAL, 1LSB=537uV */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACSW1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPDACSW1_LPMODEDIS 5 /* Switch Control */ +#define BITP_AFE_LPDACSW1_LPDACSW 0 /* ULPDAC0 Switches Matrix */ +#define BITM_AFE_LPDACSW1_LPMODEDIS (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Switch Control */ +#define BITM_AFE_LPDACSW1_LPDACSW (_ADI_MSK_3(0x0000001F,0x0000001FUL, uint32_t )) /* ULPDAC0 Switches Matrix */ +#define ENUM_AFE_LPDACSW1_DACCONBIT5 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LPMODEDIS: ULPDAC Switch controlled by ULPDACCON1 bit 5 */ +#define ENUM_AFE_LPDACSW1_OVRRIDE (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* LPMODEDIS: ULPDAC Switches override */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACCON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPDACCON1_WAVETYPE 6 /* DAC Input Source */ +#define BITP_AFE_LPDACCON1_DACMDE 5 /* LPDAC1 Switch Settings */ +#define BITP_AFE_LPDACCON1_VZEROMUX 4 /* VZEROOUT */ +#define BITP_AFE_LPDACCON1_VBIASMUX 3 /* BITSEL */ +#define BITP_AFE_LPDACCON1_REFSEL 2 /* REFSEL */ +#define BITP_AFE_LPDACCON1_PWDEN 1 /* ULPDAC0 Power */ +#define BITP_AFE_LPDACCON1_RSTEN 0 /* Enable Writes to ULPDAC1 */ +#define BITM_AFE_LPDACCON1_WAVETYPE (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* DAC Input Source */ +#define BITM_AFE_LPDACCON1_DACMDE (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* LPDAC1 Switch Settings */ +#define BITM_AFE_LPDACCON1_VZEROMUX (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* VZEROOUT */ +#define BITM_AFE_LPDACCON1_VBIASMUX (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* BITSEL */ +#define BITM_AFE_LPDACCON1_REFSEL (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* REFSEL */ +#define BITM_AFE_LPDACCON1_PWDEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* ULPDAC0 Power */ +#define BITM_AFE_LPDACCON1_RSTEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Writes to ULPDAC1 */ +#define ENUM_AFE_LPDACCON1_NORM (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* DACMDE: ULPDAC1 switches set for normal mode */ +#define ENUM_AFE_LPDACCON1_DIAG (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* DACMDE: ULPDAC1 switches set for Diagnostic mode */ +#define ENUM_AFE_LPDACCON1_BITS6 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* VZEROMUX: VZERO 6BIT */ +#define ENUM_AFE_LPDACCON1_BITS12 (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* VZEROMUX: VZERO 12BIT */ +#define ENUM_AFE_LPDACCON1_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* VBIASMUX: 12BIT Output */ +#define ENUM_AFE_LPDACCON1_EN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* VBIASMUX: 6BIT Output */ +#define ENUM_AFE_LPDACCON1_ULPREF (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) +#define ENUM_AFE_LPDACCON1_AVDD (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) +#define ENUM_AFE_LPDACCON1_PWREN (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* PWDEN: ULPDAC1 Powered On */ +#define ENUM_AFE_LPDACCON1_PWRDIS (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* PWDEN: ULPDAC1 Powered Off */ +#define ENUM_AFE_LPDACCON1_WRITEDIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* RSTEN: Disable ULPDAC1 Writes */ +#define ENUM_AFE_LPDACCON1_WRITEEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* RSTEN: Enable ULPDAC1 Writes */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DSWFULLCON_D8 7 /* Control of D8 Switch. */ +#define BITP_AFE_DSWFULLCON_D7 6 /* Control of D7 Switch. */ +#define BITP_AFE_DSWFULLCON_D6 5 /* Control of D6 Switch. */ +#define BITP_AFE_DSWFULLCON_D5 4 /* Control of D5 Switch. */ +#define BITP_AFE_DSWFULLCON_D4 3 /* Control of D4 Switch. */ +#define BITP_AFE_DSWFULLCON_D3 2 /* Control of D3 Switch. */ +#define BITP_AFE_DSWFULLCON_D2 1 /* Control of D2 Switch. */ +#define BITP_AFE_DSWFULLCON_DR0 0 /* Control of Dr0 Switch. */ +#define BITM_AFE_DSWFULLCON_D8 0x00000080 /* Control of D8 Switch. */ +#define BITM_AFE_DSWFULLCON_D7 0x00000040 /* Control of D7 Switch. */ +#define BITM_AFE_DSWFULLCON_D6 0x00000020 /* Control of D6 Switch. */ +#define BITM_AFE_DSWFULLCON_D5 0x00000010 /* Control of D5 Switch. */ +#define BITM_AFE_DSWFULLCON_D4 0x00000008 /* Control of D4 Switch. */ +#define BITM_AFE_DSWFULLCON_D3 0x00000004 /* Control of D3 Switch. */ +#define BITM_AFE_DSWFULLCON_D2 0x00000002 /* Control of D2 Switch. */ +#define BITM_AFE_DSWFULLCON_DR0 0x00000001 /* Control of Dr0 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_NSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_NSWFULLCON_NL2 11 /* Control of NL2 Switch. */ +#define BITP_AFE_NSWFULLCON_NL 10 /* Control of NL Switch. */ +#define BITP_AFE_NSWFULLCON_NR1 9 /* Control of Nr1 Switch. Set Will Close Nr1, Unset Open */ +#define BITP_AFE_NSWFULLCON_N9 8 /* Control of N9 Switch. Set Will Close N9, Unset Open */ +#define BITP_AFE_NSWFULLCON_N8 7 /* Control of N8 Switch. Set Will Close N8, Unset Open */ +#define BITP_AFE_NSWFULLCON_N7 6 /* Control of N7 Switch. Set Will Close N7, Unset Open */ +#define BITP_AFE_NSWFULLCON_N6 5 /* Control of N6 Switch. Set Will Close N6, Unset Open */ +#define BITP_AFE_NSWFULLCON_N5 4 /* Control of N5 Switch. Set Will Close N5, Unset Open */ +#define BITP_AFE_NSWFULLCON_N4 3 /* Control of N4 Switch. Set Will Close N4, Unset Open */ +#define BITP_AFE_NSWFULLCON_N3 2 /* Control of N3 Switch. Set Will Close N3, Unset Open */ +#define BITP_AFE_NSWFULLCON_N2 1 /* Control of N2 Switch. Set Will Close N2, Unset Open */ +#define BITP_AFE_NSWFULLCON_N1 0 /* Control of N1 Switch. Set Will Close N1, Unset Open */ +#define BITM_AFE_NSWFULLCON_NL2 0x00000800 /* Control of NL2 Switch. */ +#define BITM_AFE_NSWFULLCON_NL 0x00000400 /* Control of NL Switch. */ +#define BITM_AFE_NSWFULLCON_NR1 0x00000200 /* Control of Nr1 Switch. Set Will Close Nr1, Unset Open */ +#define BITM_AFE_NSWFULLCON_N9 0x00000100 /* Control of N9 Switch. Set Will Close N9, Unset Open */ +#define BITM_AFE_NSWFULLCON_N8 0x00000080 /* Control of N8 Switch. Set Will Close N8, Unset Open */ +#define BITM_AFE_NSWFULLCON_N7 0x00000040 /* Control of N7 Switch. Set Will Close N7, Unset Open */ +#define BITM_AFE_NSWFULLCON_N6 0x00000020 /* Control of N6 Switch. Set Will Close N6, Unset Open */ +#define BITM_AFE_NSWFULLCON_N5 0x00000010 /* Control of N5 Switch. Set Will Close N5, Unset Open */ +#define BITM_AFE_NSWFULLCON_N4 0x00000008 /* Control of N4 Switch. Set Will Close N4, Unset Open */ +#define BITM_AFE_NSWFULLCON_N3 0x00000004 /* Control of N3 Switch. Set Will Close N3, Unset Open */ +#define BITM_AFE_NSWFULLCON_N2 0x00000002 /* Control of N2 Switch. Set Will Close N2, Unset Open */ +#define BITM_AFE_NSWFULLCON_N1 0x00000001 /* Control of N1 Switch. Set Will Close N1, Unset Open */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_PSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_PSWFULLCON_PL2 14 /* PL2 Switch Control */ +#define BITP_AFE_PSWFULLCON_PL 13 /* PL Switch Control */ +#define BITP_AFE_PSWFULLCON_P12 11 /* Control of P12 Switch. Set Will Close P12, Unset Open */ +#define BITP_AFE_PSWFULLCON_P11 10 /* Control of P11 Switch. Set Will Close P11, Unset Open */ +#define BITP_AFE_PSWFULLCON_P10 9 /* P10 Switch Control */ +#define BITP_AFE_PSWFULLCON_P9 8 /* Control of P9 Switch. Set Will Close P9, Unset Open */ +#define BITP_AFE_PSWFULLCON_P8 7 /* Control of P8 Switch. Set Will Close P8, Unset Open */ +#define BITP_AFE_PSWFULLCON_P7 6 /* Control of P7 Switch. Set Will Close P7, Unset Open */ +#define BITP_AFE_PSWFULLCON_P6 5 /* Control of P6 Switch. Set Will Close P6, Unset Open */ +#define BITP_AFE_PSWFULLCON_P5 4 /* Control of P5 Switch. Set Will Close P5, Unset Open */ +#define BITP_AFE_PSWFULLCON_P4 3 /* Control of P4 Switch. Set Will Close P4, Unset Open */ +#define BITP_AFE_PSWFULLCON_P3 2 /* Control of P3 Switch. Set Will Close P3, Unset Open */ +#define BITP_AFE_PSWFULLCON_P2 1 /* Control of P2 Switch. Set Will Close P2, Unset Open */ +#define BITP_AFE_PSWFULLCON_PR0 0 /* PR0 Switch Control */ +#define BITM_AFE_PSWFULLCON_PL2 0x00004000 /* PL2 Switch Control */ +#define BITM_AFE_PSWFULLCON_PL 0x00002000 /* PL Switch Control */ +#define BITM_AFE_PSWFULLCON_P12 0x00000800 /* Control of P12 Switch. Set Will Close P12, Unset Open */ +#define BITM_AFE_PSWFULLCON_P11 0x00000400 /* Control of P11 Switch. Set Will Close P11, Unset Open */ +#define BITM_AFE_PSWFULLCON_P10 0x00000200 /* P10 Switch Control */ +#define BITM_AFE_PSWFULLCON_P9 0x00000100 /* Control of P9 Switch. Set Will Close P9, Unset Open */ +#define BITM_AFE_PSWFULLCON_P8 0x00000080 /* Control of P8 Switch. Set Will Close P8, Unset Open */ +#define BITM_AFE_PSWFULLCON_P7 0x00000040 /* Control of P7 Switch. Set Will Close P7, Unset Open */ +#define BITM_AFE_PSWFULLCON_P6 0x00000020 /* Control of P6 Switch. Set Will Close P6, Unset Open */ +#define BITM_AFE_PSWFULLCON_P5 0x00000010 /* Control of P5 Switch. Set Will Close P5, Unset Open */ +#define BITM_AFE_PSWFULLCON_P4 0x00000008 /* Control of P4 Switch. Set Will Close P4, Unset Open */ +#define BITM_AFE_PSWFULLCON_P3 0x00000004 /* Control of P3 Switch. Set Will Close P3, Unset Open */ +#define BITM_AFE_PSWFULLCON_P2 0x00000002 /* Control of P2 Switch. Set Will Close P2, Unset Open */ +#define BITM_AFE_PSWFULLCON_PR0 0x00000001 /* PR0 Switch Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_TSWFULLCON_TR1 11 /* Control of Tr1 Switch. Set Will Close Tr1, Unset Open */ +#define BITP_AFE_TSWFULLCON_T11 10 /* Control of T11 Switch. Set Will Close T11, Unset Open */ +#define BITP_AFE_TSWFULLCON_T10 9 /* Control of T10 Switch. Set Will Close T10, Unset Open */ +#define BITP_AFE_TSWFULLCON_T9 8 /* Control of T9 Switch. Set Will Close T9, Unset Open */ +#define BITP_AFE_TSWFULLCON_T7 6 /* Control of T7 Switch. Set Will Close T7, Unset Open */ +#define BITP_AFE_TSWFULLCON_T5 4 /* Control of T5 Switch. Set Will Close T5, Unset Open */ +#define BITP_AFE_TSWFULLCON_T4 3 /* Control of T4 Switch. Set Will Close T4, Unset Open */ +#define BITP_AFE_TSWFULLCON_T3 2 /* Control of T3 Switch. Set Will Close T3, Unset Open */ +#define BITP_AFE_TSWFULLCON_T2 1 /* Control of T2 Switch. Set Will Close T2, Unset Open */ +#define BITP_AFE_TSWFULLCON_T1 0 /* Control of T1 Switch. Set Will Close T1, Unset Open */ +#define BITM_AFE_TSWFULLCON_TR1 0x00000800 /* Control of Tr1 Switch. Set Will Close Tr1, Unset Open */ +#define BITM_AFE_TSWFULLCON_T11 0x00000400 /* Control of T11 Switch. Set Will Close T11, Unset Open */ +#define BITM_AFE_TSWFULLCON_T10 0x00000200 /* Control of T10 Switch. Set Will Close T10, Unset Open */ +#define BITM_AFE_TSWFULLCON_T9 0x00000100 /* Control of T9 Switch. Set Will Close T9, Unset Open */ +#define BITM_AFE_TSWFULLCON_T7 0x00000040 /* Control of T7 Switch. Set Will Close T7, Unset Open */ +#define BITM_AFE_TSWFULLCON_T5 0x00000010 /* Control of T5 Switch. Set Will Close T5, Unset Open */ +#define BITM_AFE_TSWFULLCON_T4 0x00000008 /* Control of T4 Switch. Set Will Close T4, Unset Open */ +#define BITM_AFE_TSWFULLCON_T3 0x00000004 /* Control of T3 Switch. Set Will Close T3, Unset Open */ +#define BITM_AFE_TSWFULLCON_T2 0x00000002 /* Control of T2 Switch. Set Will Close T2, Unset Open */ +#define BITM_AFE_TSWFULLCON_T1 0x00000001 /* Control of T1 Switch. Set Will Close T1, Unset Open */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TEMPSENS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_TEMPSENS_CHOPFRESEL 2 /* Chop Mode Frequency Setting */ +#define BITP_AFE_TEMPSENS_CHOPCON 1 /* Temp Sensor Chop Mode */ +#define BITP_AFE_TEMPSENS_ENABLE 0 /* Unused */ +#define BITM_AFE_TEMPSENS_CHOPFRESEL 0x0000000C /* Chop Mode Frequency Setting */ +#define BITM_AFE_TEMPSENS_CHOPCON 0x00000002 /* Temp Sensor Chop Mode */ +#define BITM_AFE_TEMPSENS_ENABLE 0x00000001 /* Unused */ +#define ENUM_AFE_TEMPSENS_DIS 0x00000000 /* CHOPCON: Disable chop */ +#define ENUM_AFE_TEMPSENS_EN 0x00000002 /* CHOPCON: Enable chop */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_BUFSENCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_BUFSENCON_V1P8THERMSTEN 8 /* Buffered Reference Output */ +#define BITP_AFE_BUFSENCON_V1P1LPADCCHGDIS 6 /* Controls Decoupling Cap Discharge Switch */ +#define BITP_AFE_BUFSENCON_V1P1LPADCEN 5 /* ADC 1.1V LP Buffer */ +#define BITP_AFE_BUFSENCON_V1P1HPADCEN 4 /* Enable 1.1V HP CM Buffer */ +#define BITP_AFE_BUFSENCON_V1P8HPADCCHGDIS 3 /* Controls Decoupling Cap Discharge Switch */ +#define BITP_AFE_BUFSENCON_V1P8LPADCEN 2 /* ADC 1.8V LP Reference Buffer */ +#define BITP_AFE_BUFSENCON_V1P8HPADCILIMITEN 1 /* HP ADC Input Current Limit */ +#define BITP_AFE_BUFSENCON_V1P8HPADCEN 0 /* HP 1.8V Reference Buffer */ +#define BITM_AFE_BUFSENCON_V1P8THERMSTEN 0x00000100 /* Buffered Reference Output */ +#define BITM_AFE_BUFSENCON_V1P1LPADCCHGDIS 0x00000040 /* Controls Decoupling Cap Discharge Switch */ +#define BITM_AFE_BUFSENCON_V1P1LPADCEN 0x00000020 /* ADC 1.1V LP Buffer */ +#define BITM_AFE_BUFSENCON_V1P1HPADCEN 0x00000010 /* Enable 1.1V HP CM Buffer */ +#define BITM_AFE_BUFSENCON_V1P8HPADCCHGDIS 0x00000008 /* Controls Decoupling Cap Discharge Switch */ +#define BITM_AFE_BUFSENCON_V1P8LPADCEN 0x00000004 /* ADC 1.8V LP Reference Buffer */ +#define BITM_AFE_BUFSENCON_V1P8HPADCILIMITEN 0x00000002 /* HP ADC Input Current Limit */ +#define BITM_AFE_BUFSENCON_V1P8HPADCEN 0x00000001 /* HP 1.8V Reference Buffer */ +#define ENUM_AFE_BUFSENCON_DIS 0x00000000 /* V1P8THERMSTEN: Disable 1.8V Buffered Reference output */ +#define ENUM_AFE_BUFSENCON_EN 0x00000100 /* V1P8THERMSTEN: Enable 1.8V Buffered Reference output */ +#define ENUM_AFE_BUFSENCON_ENCHRG 0x00000000 /* V1P1LPADCCHGDIS: Open switch */ +#define ENUM_AFE_BUFSENCON_DISCHRG 0x00000040 /* V1P1LPADCCHGDIS: Close Switch */ +#define ENUM_AFE_BUFSENCON_DISABLE 0x00000000 /* V1P1LPADCEN: Disable ADC 1.8V LP Reference Buffer */ +#define ENUM_AFE_BUFSENCON_ENABLE 0x00000020 /* V1P1LPADCEN: Enable ADC 1.8V LP Reference Buffer */ +#define ENUM_AFE_BUFSENCON_OFF 0x00000000 /* V1P1HPADCEN: Disable 1.1V HP Common Mode Buffer */ +#define ENUM_AFE_BUFSENCON_ON 0x00000010 /* V1P1HPADCEN: Enable 1.1V HP Common Mode Buffer */ +#define ENUM_AFE_BUFSENCON_OPEN 0x00000000 /* V1P8HPADCCHGDIS: Open switch */ +#define ENUM_AFE_BUFSENCON_CLOSED 0x00000008 /* V1P8HPADCCHGDIS: Close Switch */ +#define ENUM_AFE_BUFSENCON_LPADCREF_DIS 0x00000000 /* V1P8LPADCEN: Disable LP 1.8V Reference Buffer */ +#define ENUM_AFE_BUFSENCON_LPADCREF_EN 0x00000004 /* V1P8LPADCEN: Enable LP 1.8V Reference Buffer */ +#define ENUM_AFE_BUFSENCON_LIMIT_DIS 0x00000000 /* V1P8HPADCILIMITEN: Disable buffer Current Limit */ +#define ENUM_AFE_BUFSENCON_LIMIT_EN 0x00000002 /* V1P8HPADCILIMITEN: Enable buffer Current Limit */ +#define ENUM_AFE_BUFSENCON_HPBUF_DIS 0x00000000 /* V1P8HPADCEN: Disable 1.8V HP ADC Reference Buffer */ +#define ENUM_AFE_BUFSENCON_HPBUF_EN 0x00000001 /* V1P8HPADCEN: Enable 1.8V HP ADC Reference Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCCON_GNPGA 16 /* PGA Gain Setup */ +#define BITP_AFE_ADCCON_GNOFSELPGA 15 /* Internal Offset/Gain Cancellation */ +#define BITP_AFE_ADCCON_GNOFFSEL 13 /* Obsolete */ +#define BITP_AFE_ADCCON_MUXSELN 8 /* Select Negative Input */ +#define BITP_AFE_ADCCON_MUXSELP 0 /* Select Positive Input */ +#define BITM_AFE_ADCCON_GNPGA 0x00070000 /* PGA Gain Setup */ +#define BITM_AFE_ADCCON_GNOFSELPGA 0x00008000 /* Internal Offset/Gain Cancellation */ +#define BITM_AFE_ADCCON_GNOFFSEL 0x00006000 /* Obsolete */ +#define BITM_AFE_ADCCON_MUXSELN 0x00001F00 /* Select Negative Input */ +#define BITM_AFE_ADCCON_MUXSELP 0x0000003F /* Select Positive Input */ +#define ENUM_AFE_ADCCON_RESERVED 0x00000011 /* MUXSELP: Reserved */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DSWSTA_D8STA 7 /* Status of D8 Switch. */ +#define BITP_AFE_DSWSTA_D7STA 6 /* Status of D7 Switch. */ +#define BITP_AFE_DSWSTA_D6STA 5 /* Status of D6 Switch. */ +#define BITP_AFE_DSWSTA_D5STA 4 /* Status of D5 Switch. */ +#define BITP_AFE_DSWSTA_D4STA 3 /* Status of D4 Switch. */ +#define BITP_AFE_DSWSTA_D3STA 2 /* Status of D3 Switch. */ +#define BITP_AFE_DSWSTA_D2STA 1 /* Status of D2 Switch. */ +#define BITP_AFE_DSWSTA_D1STA 0 /* Status of Dr0 Switch. */ +#define BITM_AFE_DSWSTA_D8STA 0x00000080 /* Status of D8 Switch. */ +#define BITM_AFE_DSWSTA_D7STA 0x00000040 /* Status of D7 Switch. */ +#define BITM_AFE_DSWSTA_D6STA 0x00000020 /* Status of D6 Switch. */ +#define BITM_AFE_DSWSTA_D5STA 0x00000010 /* Status of D5 Switch. */ +#define BITM_AFE_DSWSTA_D4STA 0x00000008 /* Status of D4 Switch. */ +#define BITM_AFE_DSWSTA_D3STA 0x00000004 /* Status of D3 Switch. */ +#define BITM_AFE_DSWSTA_D2STA 0x00000002 /* Status of D2 Switch. */ +#define BITM_AFE_DSWSTA_D1STA 0x00000001 /* Status of Dr0 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_PSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_PSWSTA_PL2STA 14 /* PL Switch Control */ +#define BITP_AFE_PSWSTA_PLSTA 13 /* PL Switch Control */ +#define BITP_AFE_PSWSTA_P13STA 12 /* Status of P13 Switch. */ +#define BITP_AFE_PSWSTA_P12STA 11 /* Status of P12 Switch. */ +#define BITP_AFE_PSWSTA_P11STA 10 /* Status of P11 Switch. */ +#define BITP_AFE_PSWSTA_P10STA 9 /* Status of P10 Switch. */ +#define BITP_AFE_PSWSTA_P9STA 8 /* Status of P9 Switch. */ +#define BITP_AFE_PSWSTA_P8STA 7 /* Status of P8 Switch. */ +#define BITP_AFE_PSWSTA_P7STA 6 /* Status of P7 Switch. */ +#define BITP_AFE_PSWSTA_P6STA 5 /* Status of P6 Switch. */ +#define BITP_AFE_PSWSTA_P5STA 4 /* Status of P5 Switch. */ +#define BITP_AFE_PSWSTA_P4STA 3 /* Status of P4 Switch. */ +#define BITP_AFE_PSWSTA_P3STA 2 /* Status of P3 Switch. */ +#define BITP_AFE_PSWSTA_P2STA 1 /* Status of P2 Switch. */ +#define BITP_AFE_PSWSTA_PR0STA 0 /* PR0 Switch Control */ +#define BITM_AFE_PSWSTA_PL2STA 0x00004000 /* PL Switch Control */ +#define BITM_AFE_PSWSTA_PLSTA 0x00002000 /* PL Switch Control */ +#define BITM_AFE_PSWSTA_P13STA 0x00001000 /* Status of P13 Switch. */ +#define BITM_AFE_PSWSTA_P12STA 0x00000800 /* Status of P12 Switch. */ +#define BITM_AFE_PSWSTA_P11STA 0x00000400 /* Status of P11 Switch. */ +#define BITM_AFE_PSWSTA_P10STA 0x00000200 /* Status of P10 Switch. */ +#define BITM_AFE_PSWSTA_P9STA 0x00000100 /* Status of P9 Switch. */ +#define BITM_AFE_PSWSTA_P8STA 0x00000080 /* Status of P8 Switch. */ +#define BITM_AFE_PSWSTA_P7STA 0x00000040 /* Status of P7 Switch. */ +#define BITM_AFE_PSWSTA_P6STA 0x00000020 /* Status of P6 Switch. */ +#define BITM_AFE_PSWSTA_P5STA 0x00000010 /* Status of P5 Switch. */ +#define BITM_AFE_PSWSTA_P4STA 0x00000008 /* Status of P4 Switch. */ +#define BITM_AFE_PSWSTA_P3STA 0x00000004 /* Status of P3 Switch. */ +#define BITM_AFE_PSWSTA_P2STA 0x00000002 /* Status of P2 Switch. */ +#define BITM_AFE_PSWSTA_PR0STA 0x00000001 /* PR0 Switch Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_NSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_NSWSTA_NL2STA 11 /* Status of NL2 Switch. */ +#define BITP_AFE_NSWSTA_NLSTA 10 /* Status of NL Switch. */ +#define BITP_AFE_NSWSTA_NR1STA 9 /* Status of NR1 Switch. */ +#define BITP_AFE_NSWSTA_N9STA 8 /* Status of N9 Switch. */ +#define BITP_AFE_NSWSTA_N8STA 7 /* Status of N8 Switch. */ +#define BITP_AFE_NSWSTA_N7STA 6 /* Status of N7 Switch. */ +#define BITP_AFE_NSWSTA_N6STA 5 /* Status of N6 Switch. */ +#define BITP_AFE_NSWSTA_N5STA 4 /* Status of N5 Switch. */ +#define BITP_AFE_NSWSTA_N4STA 3 /* Status of N4 Switch. */ +#define BITP_AFE_NSWSTA_N3STA 2 /* Status of N3 Switch. */ +#define BITP_AFE_NSWSTA_N2STA 1 /* Status of N2 Switch. */ +#define BITP_AFE_NSWSTA_N1STA 0 /* Status of N1 Switch. */ +#define BITM_AFE_NSWSTA_NL2STA 0x00000800 /* Status of NL2 Switch. */ +#define BITM_AFE_NSWSTA_NLSTA 0x00000400 /* Status of NL Switch. */ +#define BITM_AFE_NSWSTA_NR1STA 0x00000200 /* Status of NR1 Switch. */ +#define BITM_AFE_NSWSTA_N9STA 0x00000100 /* Status of N9 Switch. */ +#define BITM_AFE_NSWSTA_N8STA 0x00000080 /* Status of N8 Switch. */ +#define BITM_AFE_NSWSTA_N7STA 0x00000040 /* Status of N7 Switch. */ +#define BITM_AFE_NSWSTA_N6STA 0x00000020 /* Status of N6 Switch. */ +#define BITM_AFE_NSWSTA_N5STA 0x00000010 /* Status of N5 Switch. */ +#define BITM_AFE_NSWSTA_N4STA 0x00000008 /* Status of N4 Switch. */ +#define BITM_AFE_NSWSTA_N3STA 0x00000004 /* Status of N3 Switch. */ +#define BITM_AFE_NSWSTA_N2STA 0x00000002 /* Status of N2 Switch. */ +#define BITM_AFE_NSWSTA_N1STA 0x00000001 /* Status of N1 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_TSWSTA_TR1STA 11 /* Status of TR1 Switch. */ +#define BITP_AFE_TSWSTA_T11STA 10 /* Status of T11 Switch. */ +#define BITP_AFE_TSWSTA_T10STA 9 /* Status of T10 Switch. */ +#define BITP_AFE_TSWSTA_T9STA 8 /* Status of T9 Switch. */ +#define BITP_AFE_TSWSTA_T8STA 7 /* Status of T8 Switch. */ +#define BITP_AFE_TSWSTA_T7STA 6 /* Status of T7 Switch. */ +#define BITP_AFE_TSWSTA_T6STA 5 /* Status of T6 Switch. */ +#define BITP_AFE_TSWSTA_T5STA 4 /* Status of T5 Switch. */ +#define BITP_AFE_TSWSTA_T4STA 3 /* Status of T4 Switch. */ +#define BITP_AFE_TSWSTA_T3STA 2 /* Status of T3 Switch. */ +#define BITP_AFE_TSWSTA_T2STA 1 /* Status of T2 Switch. */ +#define BITP_AFE_TSWSTA_T1STA 0 /* Status of T1 Switch. */ +#define BITM_AFE_TSWSTA_TR1STA 0x00000800 /* Status of TR1 Switch. */ +#define BITM_AFE_TSWSTA_T11STA 0x00000400 /* Status of T11 Switch. */ +#define BITM_AFE_TSWSTA_T10STA 0x00000200 /* Status of T10 Switch. */ +#define BITM_AFE_TSWSTA_T9STA 0x00000100 /* Status of T9 Switch. */ +#define BITM_AFE_TSWSTA_T8STA 0x00000080 /* Status of T8 Switch. */ +#define BITM_AFE_TSWSTA_T7STA 0x00000040 /* Status of T7 Switch. */ +#define BITM_AFE_TSWSTA_T6STA 0x00000020 /* Status of T6 Switch. */ +#define BITM_AFE_TSWSTA_T5STA 0x00000010 /* Status of T5 Switch. */ +#define BITM_AFE_TSWSTA_T4STA 0x00000008 /* Status of T4 Switch. */ +#define BITM_AFE_TSWSTA_T3STA 0x00000004 /* Status of T3 Switch. */ +#define BITM_AFE_TSWSTA_T2STA 0x00000002 /* Status of T2 Switch. */ +#define BITM_AFE_TSWSTA_T1STA 0x00000001 /* Status of T1 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_STATSVAR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_STATSVAR_VARIANCE 0 /* Statistical Variance Value */ +#define BITM_AFE_STATSVAR_VARIANCE 0x7FFFFFFF /* Statistical Variance Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_STATSCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_STATSCON_STDDEV 7 /* Standard Deviation Configuration */ +#define BITP_AFE_STATSCON_SAMPLENUM 4 /* Sample Size */ +#define BITP_AFE_STATSCON_RESRVED 1 /* Reserved */ +#define BITP_AFE_STATSCON_STATSEN 0 /* Statistics Enable */ +#define BITM_AFE_STATSCON_STDDEV 0x00000F80 /* Standard Deviation Configuration */ +#define BITM_AFE_STATSCON_SAMPLENUM 0x00000070 /* Sample Size */ +#define BITM_AFE_STATSCON_RESRVED 0x0000000E /* Reserved */ +#define BITM_AFE_STATSCON_STATSEN 0x00000001 /* Statistics Enable */ +#define ENUM_AFE_STATSCON_DIS 0x00000000 /* STATSEN: Disable Statistics */ +#define ENUM_AFE_STATSCON_EN 0x00000001 /* STATSEN: Enable Statistics */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_STATSMEAN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_STATSMEAN_MEAN 0 /* Mean Output */ +#define BITM_AFE_STATSMEAN_MEAN 0x0000FFFF /* Mean Output */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ0INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQ0INFO_LEN 16 /* SEQ0 Instruction Number */ +#define BITP_AFE_SEQ0INFO_ADDR 0 /* SEQ0 Start Address */ +#define BITM_AFE_SEQ0INFO_LEN 0x07FF0000 /* SEQ0 Instruction Number */ +#define BITM_AFE_SEQ0INFO_ADDR 0x000007FF /* SEQ0 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ2INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQ2INFO_LEN 16 /* SEQ2 Instruction Number */ +#define BITP_AFE_SEQ2INFO_ADDR 0 /* SEQ2 Start Address */ +#define BITM_AFE_SEQ2INFO_LEN 0x07FF0000 /* SEQ2 Instruction Number */ +#define BITM_AFE_SEQ2INFO_ADDR 0x000007FF /* SEQ2 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CMDFIFOWADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_CMDFIFOWADDR_WADDR 0 /* Write Address */ +#define BITM_AFE_CMDFIFOWADDR_WADDR 0x000007FF /* Write Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CMDDATACON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_CMDDATACON_DATAMEMMDE 9 /* Data FIFO Mode Select */ +#define BITP_AFE_CMDDATACON_DATA_MEM_SEL 6 /* Data FIFO Size Select */ +#define BITP_AFE_CMDDATACON_CMDMEMMDE 3 /* This is Command Fifo Mode Register */ +#define BITP_AFE_CMDDATACON_CMD_MEM_SEL 0 /* Command Memory Select */ +#define BITM_AFE_CMDDATACON_DATAMEMMDE 0x00000E00 /* Data FIFO Mode Select */ +#define BITM_AFE_CMDDATACON_DATA_MEM_SEL 0x000001C0 /* Data FIFO Size Select */ +#define BITM_AFE_CMDDATACON_CMDMEMMDE 0x00000038 /* This is Command Fifo Mode Register */ +#define BITM_AFE_CMDDATACON_CMD_MEM_SEL 0x00000007 /* Command Memory Select */ +#define ENUM_AFE_CMDDATACON_DFIFO 0x00000400 /* DATAMEMMDE: FIFO MODE */ +#define ENUM_AFE_CMDDATACON_DSTM 0x00000600 /* DATAMEMMDE: STREAM MODE */ +#define ENUM_AFE_CMDDATACON_DMEM32B 0x00000000 /* DATA_MEM_SEL: 32B_1 Local Memory */ +#define ENUM_AFE_CMDDATACON_DMEM2K 0x00000040 /* DATA_MEM_SEL: 2K_2 SRAM */ +#define ENUM_AFE_CMDDATACON_DMEM4K 0x00000080 /* DATA_MEM_SEL: 2K_2~1 SRAM */ +#define ENUM_AFE_CMDDATACON_DMEM6K 0x000000C0 /* DATA_MEM_SEL: 2K_2~0 SRAM */ +#define ENUM_AFE_CMDDATACON_CMEM 0x00000008 /* CMDMEMMDE: MEMORY MODE */ +#define ENUM_AFE_CMDDATACON_CFIFO 0x00000010 /* CMDMEMMDE: FIFO MODE */ +#define ENUM_AFE_CMDDATACON_CSTM 0x00000018 /* CMDMEMMDE: STREAM MODE */ +#define ENUM_AFE_CMDDATACON_CMEM32B 0x00000000 /* CMD_MEM_SEL: 32B_0 Local Memory */ +#define ENUM_AFE_CMDDATACON_CMEM2K 0x00000001 /* CMD_MEM_SEL: 2K_0 SRAM */ +#define ENUM_AFE_CMDDATACON_CMEM4K 0x00000002 /* CMD_MEM_SEL: 2K_0~1 SRAM */ +#define ENUM_AFE_CMDDATACON_CMEM6K 0x00000003 /* CMD_MEM_SEL: 2K_0~2 SRAM */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DATAFIFOTHRES Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DATAFIFOTHRES_HIGHTHRES 16 /* High Threshold */ +#define BITM_AFE_DATAFIFOTHRES_HIGHTHRES 0x07FF0000 /* High Threshold */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ3INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQ3INFO_LEN 16 /* SEQ3 Instruction Number */ +#define BITP_AFE_SEQ3INFO_ADDR 0 /* SEQ3 Start Address */ +#define BITM_AFE_SEQ3INFO_LEN 0x07FF0000 /* SEQ3 Instruction Number */ +#define BITM_AFE_SEQ3INFO_ADDR 0x000007FF /* SEQ3 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ1INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQ1INFO_LEN 16 /* SEQ1 Instruction Number */ +#define BITP_AFE_SEQ1INFO_ADDR 0 /* SEQ1 Start Address */ +#define BITM_AFE_SEQ1INFO_LEN 0x07FF0000 /* SEQ1 Instruction Number */ +#define BITM_AFE_SEQ1INFO_ADDR 0x000007FF /* SEQ1 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_REPEATADCCNV Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_REPEATADCCNV_NUM 4 /* Repeat Value */ +#define BITP_AFE_REPEATADCCNV_EN 0 /* Enable Repeat ADC Conversions */ +#define BITM_AFE_REPEATADCCNV_NUM 0x00000FF0 /* Repeat Value */ +#define BITM_AFE_REPEATADCCNV_EN 0x00000001 /* Enable Repeat ADC Conversions */ +#define ENUM_AFE_REPEATADCCNV_DIS 0x00000000 /* EN: Disable Repeat ADC Conversions */ +#define ENUM_AFE_REPEATADCCNV_EN 0x00000001 /* EN: Enable Repeat ADC Conversions */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_FIFOCNTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_FIFOCNTSTA_DATAFIFOCNTSTA 16 /* Current Number of Words in the Data FIFO */ +#define BITM_AFE_FIFOCNTSTA_DATAFIFOCNTSTA 0x07FF0000 /* Current Number of Words in the Data FIFO */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CALDATLOCK Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_CALDATLOCK_KEY 0 /* Password for Calibration Data Registers */ +#define BITM_AFE_CALDATLOCK_KEY 0xFFFFFFFF /* Password for Calibration Data Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETHSTIA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETHSTIA_VALUE 0 /* HSTIA Offset Calibration */ +#define BITM_AFE_ADCOFFSETHSTIA_VALUE 0x00007FFF /* HSTIA Offset Calibration */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINTEMPSENS0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGAINTEMPSENS0_VALUE 0 /* Gain Calibration Temp Sensor Channel */ +#define BITM_AFE_ADCGAINTEMPSENS0_VALUE 0x00007FFF /* Gain Calibration Temp Sensor Channel */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETTEMPSENS0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETTEMPSENS0_VALUE 0 /* Offset Calibration Temp Sensor */ +#define BITM_AFE_ADCOFFSETTEMPSENS0_VALUE 0x00007FFF /* Offset Calibration Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGAINGN1_VALUE 0 /* Gain Calibration PGA Gain 1x */ +#define BITM_AFE_ADCGAINGN1_VALUE 0x00007FFF /* Gain Calibration PGA Gain 1x */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETGN1_VALUE 0 /* Offset Calibration Gain1 */ +#define BITM_AFE_ADCOFFSETGN1_VALUE 0x00007FFF /* Offset Calibration Gain1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACGAIN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DACGAIN_VALUE 0 /* HS DAC Gain Correction Factor */ +#define BITM_AFE_DACGAIN_VALUE 0x00000FFF /* HS DAC Gain Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSETATTEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DACOFFSETATTEN_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSETATTEN_VALUE 0x00000FFF /* DAC Offset Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DACOFFSET_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSET_VALUE 0x00000FFF /* DAC Offset Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN1P5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGAINGN1P5_VALUE 0 /* Gain Calibration PGA Gain 1.5x */ +#define BITM_AFE_ADCGAINGN1P5_VALUE 0x00007FFF /* Gain Calibration PGA Gain 1.5x */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGAINGN2_VALUE 0 /* Gain Calibration PGA Gain 2x */ +#define BITM_AFE_ADCGAINGN2_VALUE 0x00007FFF /* Gain Calibration PGA Gain 2x */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGAINGN4_VALUE 0 /* Gain Calibration PGA Gain 4x */ +#define BITM_AFE_ADCGAINGN4_VALUE 0x00007FFF /* Gain Calibration PGA Gain 4x */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCPGAOFFSETCANCEL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCPGAOFFSETCANCEL_OFFSETCANCEL 0 /* Offset Cancellation */ +#define BITM_AFE_ADCPGAOFFSETCANCEL_OFFSETCANCEL 0x00007FFF /* Offset Cancellation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGNHSTIA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGNHSTIA_VALUE 0 /* Gain Error Calibration HS TIA Channel */ +#define BITM_AFE_ADCGNHSTIA_VALUE 0x00007FFF /* Gain Error Calibration HS TIA Channel */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETLPTIA0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETLPTIA0_VALUE 0 /* Offset Calibration for ULP-TIA0 */ +#define BITM_AFE_ADCOFFSETLPTIA0_VALUE 0x00007FFF /* Offset Calibration for ULP-TIA0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGNLPTIA0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGNLPTIA0_VALUE 0 /* Gain Error Calibration ULPTIA0 */ +#define BITM_AFE_ADCGNLPTIA0_VALUE 0x00007FFF /* Gain Error Calibration ULPTIA0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCPGAGN4OFCAL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCPGAGN4OFCAL_ADCGAINAUX 0 /* DC Calibration Gain=4 */ +#define BITM_AFE_ADCPGAGN4OFCAL_ADCGAINAUX 0x00007FFF /* DC Calibration Gain=4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN9 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGAINGN9_VALUE 0 /* Gain Calibration PGA Gain 9x */ +#define BITM_AFE_ADCGAINGN9_VALUE 0x00007FFF /* Gain Calibration PGA Gain 9x */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETEMPSENS1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETEMPSENS1_VALUE 0 /* Offset Calibration Temp Sensor */ +#define BITM_AFE_ADCOFFSETEMPSENS1_VALUE 0x00007FFF /* Offset Calibration Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINDIOTEMPSENS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGAINDIOTEMPSENS_VALUE 0 /* Gain Calibration for Diode Temp Sensor */ +#define BITM_AFE_ADCGAINDIOTEMPSENS_VALUE 0x00007FFF /* Gain Calibration for Diode Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSETATTENHP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DACOFFSETATTENHP_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSETATTENHP_VALUE 0x00000FFF /* DAC Offset Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSETHP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DACOFFSETHP_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSETHP_VALUE 0x00000FFF /* DAC Offset Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETLPTIA1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETLPTIA1_VALUE 0 /* Offset Calibration for ULP-TIA1 */ +#define BITM_AFE_ADCOFFSETLPTIA1_VALUE (_ADI_MSK_3(0x00007FFF,0x00007FFFUL, uint32_t )) /* Offset Calibration for ULP-TIA1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGNLPTIA1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGNLPTIA1_ULPTIA1GN 0 /* Gain Calibration ULP-TIA1 */ +#define BITM_AFE_ADCGNLPTIA1_ULPTIA1GN 0x00007FFF /* Gain Calibration ULP-TIA1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETGN2_VALUE 0 /* Offset Calibration Auxiliary Channel (PGA Gain =2) */ +#define BITM_AFE_ADCOFFSETGN2_VALUE 0x00007FFF /* Offset Calibration Auxiliary Channel (PGA Gain =2) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN1P5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETGN1P5_VALUE 0 /* Offset Calibration Gain1.5 */ +#define BITM_AFE_ADCOFFSETGN1P5_VALUE 0x00007FFF /* Offset Calibration Gain1.5 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN9 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETGN9_VALUE 0 /* Offset Calibration Gain9 */ +#define BITM_AFE_ADCOFFSETGN9_VALUE 0x00007FFF /* Offset Calibration Gain9 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETGN4_VALUE 0 /* Offset Calibration Gain4 */ +#define BITM_AFE_ADCOFFSETGN4_VALUE 0x00007FFF /* Offset Calibration Gain4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_PMBW Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_PMBW_SYSBW 2 /* Configure System Bandwidth */ +#define BITP_AFE_PMBW_SYSHP 0 /* Set High Speed DAC and ADC in High Power Mode */ +#define BITM_AFE_PMBW_SYSBW 0x0000000C /* Configure System Bandwidth */ +#define BITM_AFE_PMBW_SYSHP 0x00000001 /* Set High Speed DAC and ADC in High Power Mode */ +#define ENUM_AFE_PMBW_BWNA 0x00000000 /* SYSBW: no action for system configuration */ +#define ENUM_AFE_PMBW_BW50 0x00000004 /* SYSBW: 50kHz -3dB bandwidth */ +#define ENUM_AFE_PMBW_BW100 0x00000008 /* SYSBW: 100kHz -3dB bandwidth */ +#define ENUM_AFE_PMBW_BW250 0x0000000C /* SYSBW: 250kHz -3dB bandwidth */ +#define ENUM_AFE_PMBW_LP 0x00000000 /* SYSHP: LP mode */ +#define ENUM_AFE_PMBW_HP 0x00000001 /* SYSHP: HP mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SWMUX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SWMUX_CMMUX 3 /* CM Resistor Select for Ain2, Ain3 */ +#define BITM_AFE_SWMUX_CMMUX 0x00000008 /* CM Resistor Select for Ain2, Ain3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_AFE_TEMPSEN_DIO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_AFE_TEMPSEN_DIO_TSDIO_PD 17 /* Power Down Control */ +#define BITP_AFE_AFE_TEMPSEN_DIO_TSDIO_EN 16 /* Test Signal Enable */ +#define BITP_AFE_AFE_TEMPSEN_DIO_TSDIO_CON 0 /* Bias Current Selection */ +#define BITM_AFE_AFE_TEMPSEN_DIO_TSDIO_PD 0x00020000 /* Power Down Control */ +#define BITM_AFE_AFE_TEMPSEN_DIO_TSDIO_EN 0x00010000 /* Test Signal Enable */ +#define BITM_AFE_AFE_TEMPSEN_DIO_TSDIO_CON 0x0000FFFF /* Bias Current Selection */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCBUFCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCBUFCON_AMPDIS 4 /* Disable OpAmp. */ +#define BITP_AFE_ADCBUFCON_CHOPDIS 0 /* Disable Chop */ +#define BITM_AFE_ADCBUFCON_AMPDIS 0x000001F0 /* Disable OpAmp. */ +#define BITM_AFE_ADCBUFCON_CHOPDIS 0x0000000F /* Disable Chop */ + + +/* ============================================================================================================================ + Interrupt Controller Register Map + ============================================================================================================================ */ + +/* ============================================================================================================================ + INTC + ============================================================================================================================ */ +#define REG_INTC_INTCPOL_RESET 0x00000000 /* Reset Value for INTCPOL */ +#define REG_INTC_INTCPOL 0x00003000 /* INTC Interrupt Polarity Register */ +#define REG_INTC_INTCCLR_RESET 0x00000000 /* Reset Value for INTCCLR */ +#define REG_INTC_INTCCLR 0x00003004 /* INTC Interrupt Clear Register */ +#define REG_INTC_INTCSEL0_RESET 0x00002000 /* Reset Value for INTCSEL0 */ +#define REG_INTC_INTCSEL0 0x00003008 /* INTC INT0 Select Register */ +#define REG_INTC_INTCSEL1_RESET 0x00000000 /* Reset Value for INTCSEL1 */ +#define REG_INTC_INTCSEL1 0x0000300C /* INTC INT1 Select Register */ +#define REG_INTC_INTCFLAG0_RESET 0x00000000 /* Reset Value for INTCFLAG0 */ +#define REG_INTC_INTCFLAG0 0x00003010 /* INTC INT0 FLAG Register */ +#define REG_INTC_INTCFLAG1_RESET 0x00000000 /* Reset Value for INTCFLAG1 */ +#define REG_INTC_INTCFLAG1 0x00003014 /* INTC INT1 FLAG Register */ + +/* ============================================================================================================================ + INTC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCPOL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_INTC_INTCPOL_INTPOL 0 +#define BITM_INTC_INTCPOL_INTPOL 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCCLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_INTC_INTCCLR_INTCLR31 31 +#define BITP_INTC_INTCCLR_INTCLR30 30 +#define BITP_INTC_INTCCLR_INTCLR29 29 +#define BITP_INTC_INTCCLR_INTCLR28 28 +#define BITP_INTC_INTCCLR_INTCLR27 27 +#define BITP_INTC_INTCCLR_INTCLR26 26 +#define BITP_INTC_INTCCLR_INTCLR25 25 +#define BITP_INTC_INTCCLR_INTCLR24 24 +#define BITP_INTC_INTCCLR_INTCLR23 23 +#define BITP_INTC_INTCCLR_INTCLR22 22 +#define BITP_INTC_INTCCLR_INTCLR21 21 +#define BITP_INTC_INTCCLR_INTCLR20 20 +#define BITP_INTC_INTCCLR_INTCLR19 19 +#define BITP_INTC_INTCCLR_INTCLR18 18 +#define BITP_INTC_INTCCLR_INTCLR17 17 +#define BITP_INTC_INTCCLR_INTCLR16 16 +#define BITP_INTC_INTCCLR_INTCLR15 15 +#define BITP_INTC_INTCCLR_INTCLR14 14 +#define BITP_INTC_INTCCLR_INTCLR13 13 +#define BITP_INTC_INTCCLR_INTCLR12 12 /* Custom IRQ 3. Write 1 to clear. */ +#define BITP_INTC_INTCCLR_INTCLR11 11 /* Custom IRQ 2. Write 1 to clear. */ +#define BITP_INTC_INTCCLR_INTCLR10 10 /* Custom IRQ 1. Write 1 to clear. */ +#define BITP_INTC_INTCCLR_INTCLR9 9 /* Custom IRQ 0. Write 1 to clear */ +#define BITP_INTC_INTCCLR_INTCLR8 8 +#define BITP_INTC_INTCCLR_INTCLR7 7 +#define BITP_INTC_INTCCLR_INTCLR6 6 +#define BITP_INTC_INTCCLR_INTCLR5 5 +#define BITP_INTC_INTCCLR_INTCLR4 4 +#define BITP_INTC_INTCCLR_INTCLR3 3 +#define BITP_INTC_INTCCLR_INTCLR2 2 +#define BITP_INTC_INTCCLR_INTCLR1 1 +#define BITP_INTC_INTCCLR_INTCLR0 0 +#define BITM_INTC_INTCCLR_INTCLR31 0x80000000 +#define BITM_INTC_INTCCLR_INTCLR30 0x40000000 +#define BITM_INTC_INTCCLR_INTCLR29 0x20000000 +#define BITM_INTC_INTCCLR_INTCLR28 0x10000000 +#define BITM_INTC_INTCCLR_INTCLR27 0x08000000 +#define BITM_INTC_INTCCLR_INTCLR26 0x04000000 +#define BITM_INTC_INTCCLR_INTCLR25 0x02000000 +#define BITM_INTC_INTCCLR_INTCLR24 0x01000000 +#define BITM_INTC_INTCCLR_INTCLR23 0x00800000 +#define BITM_INTC_INTCCLR_INTCLR22 0x00400000 +#define BITM_INTC_INTCCLR_INTCLR21 0x00200000 +#define BITM_INTC_INTCCLR_INTCLR20 0x00100000 +#define BITM_INTC_INTCCLR_INTCLR19 0x00080000 +#define BITM_INTC_INTCCLR_INTCLR18 0x00040000 +#define BITM_INTC_INTCCLR_INTCLR17 0x00020000 +#define BITM_INTC_INTCCLR_INTCLR16 0x00010000 +#define BITM_INTC_INTCCLR_INTCLR15 0x00008000 +#define BITM_INTC_INTCCLR_INTCLR14 0x00004000 +#define BITM_INTC_INTCCLR_INTCLR13 0x00002000 +#define BITM_INTC_INTCCLR_INTCLR12 0x00001000 /* Custom IRQ 3. Write 1 to clear. */ +#define BITM_INTC_INTCCLR_INTCLR11 0x00000800 /* Custom IRQ 2. Write 1 to clear. */ +#define BITM_INTC_INTCCLR_INTCLR10 0x00000400 /* Custom IRQ 1. Write 1 to clear. */ +#define BITM_INTC_INTCCLR_INTCLR9 0x00000200 /* Custom IRQ 0. Write 1 to clear */ +#define BITM_INTC_INTCCLR_INTCLR8 0x00000100 +#define BITM_INTC_INTCCLR_INTCLR7 0x00000080 +#define BITM_INTC_INTCCLR_INTCLR6 0x00000040 +#define BITM_INTC_INTCCLR_INTCLR5 0x00000020 +#define BITM_INTC_INTCCLR_INTCLR4 0x00000010 +#define BITM_INTC_INTCCLR_INTCLR3 0x00000008 +#define BITM_INTC_INTCCLR_INTCLR2 0x00000004 +#define BITM_INTC_INTCCLR_INTCLR1 0x00000002 +#define BITM_INTC_INTCCLR_INTCLR0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCSEL0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_INTC_INTCSEL0_INTSEL31 31 +#define BITP_INTC_INTCSEL0_INTSEL30 30 +#define BITP_INTC_INTCSEL0_INTSEL29 29 +#define BITP_INTC_INTCSEL0_INTSEL28 28 +#define BITP_INTC_INTCSEL0_INTSEL27 27 +#define BITP_INTC_INTCSEL0_INTSEL26 26 +#define BITP_INTC_INTCSEL0_INTSEL25 25 +#define BITP_INTC_INTCSEL0_INTSEL24 24 +#define BITP_INTC_INTCSEL0_INTSEL23 23 +#define BITP_INTC_INTCSEL0_INTSEL22 22 +#define BITP_INTC_INTCSEL0_INTSEL21 21 +#define BITP_INTC_INTCSEL0_INTSEL20 20 +#define BITP_INTC_INTCSEL0_INTSEL19 19 +#define BITP_INTC_INTCSEL0_INTSEL18 18 +#define BITP_INTC_INTCSEL0_INTSEL17 17 +#define BITP_INTC_INTCSEL0_INTSEL16 16 +#define BITP_INTC_INTCSEL0_INTSEL15 15 +#define BITP_INTC_INTCSEL0_INTSEL14 14 +#define BITP_INTC_INTCSEL0_INTSEL13 13 +#define BITP_INTC_INTCSEL0_INTSEL12 12 /* Custom IRQ 3 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL11 11 /* Custom IRQ 2 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL10 10 /* Custom IRQ 1 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL9 9 /* Custom IRQ 0 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL8 8 +#define BITP_INTC_INTCSEL0_INTSEL7 7 +#define BITP_INTC_INTCSEL0_INTSEL6 6 +#define BITP_INTC_INTCSEL0_INTSEL5 5 +#define BITP_INTC_INTCSEL0_INTSEL4 4 +#define BITP_INTC_INTCSEL0_INTSEL3 3 +#define BITP_INTC_INTCSEL0_INTSEL2 2 +#define BITP_INTC_INTCSEL0_INTSEL1 1 +#define BITP_INTC_INTCSEL0_INTSEL0 0 +#define BITM_INTC_INTCSEL0_INTSEL31 0x80000000 +#define BITM_INTC_INTCSEL0_INTSEL30 0x40000000 +#define BITM_INTC_INTCSEL0_INTSEL29 0x20000000 +#define BITM_INTC_INTCSEL0_INTSEL28 0x10000000 +#define BITM_INTC_INTCSEL0_INTSEL27 0x08000000 +#define BITM_INTC_INTCSEL0_INTSEL26 0x04000000 +#define BITM_INTC_INTCSEL0_INTSEL25 0x02000000 +#define BITM_INTC_INTCSEL0_INTSEL24 0x01000000 +#define BITM_INTC_INTCSEL0_INTSEL23 0x00800000 +#define BITM_INTC_INTCSEL0_INTSEL22 0x00400000 +#define BITM_INTC_INTCSEL0_INTSEL21 0x00200000 +#define BITM_INTC_INTCSEL0_INTSEL20 0x00100000 +#define BITM_INTC_INTCSEL0_INTSEL19 0x00080000 +#define BITM_INTC_INTCSEL0_INTSEL18 0x00040000 +#define BITM_INTC_INTCSEL0_INTSEL17 0x00020000 +#define BITM_INTC_INTCSEL0_INTSEL16 0x00010000 +#define BITM_INTC_INTCSEL0_INTSEL15 0x00008000 +#define BITM_INTC_INTCSEL0_INTSEL14 0x00004000 +#define BITM_INTC_INTCSEL0_INTSEL13 0x00002000 +#define BITM_INTC_INTCSEL0_INTSEL12 0x00001000 /* Custom IRQ 3 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL11 0x00000800 /* Custom IRQ 2 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL10 0x00000400 /* Custom IRQ 1 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL9 0x00000200 /* Custom IRQ 0 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL8 0x00000100 +#define BITM_INTC_INTCSEL0_INTSEL7 0x00000080 +#define BITM_INTC_INTCSEL0_INTSEL6 0x00000040 +#define BITM_INTC_INTCSEL0_INTSEL5 0x00000020 +#define BITM_INTC_INTCSEL0_INTSEL4 0x00000010 +#define BITM_INTC_INTCSEL0_INTSEL3 0x00000008 +#define BITM_INTC_INTCSEL0_INTSEL2 0x00000004 +#define BITM_INTC_INTCSEL0_INTSEL1 0x00000002 +#define BITM_INTC_INTCSEL0_INTSEL0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCSEL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_INTC_INTCSEL1_INTSEL31 31 +#define BITP_INTC_INTCSEL1_INTSEL30 30 +#define BITP_INTC_INTCSEL1_INTSEL29 29 +#define BITP_INTC_INTCSEL1_INTSEL28 28 +#define BITP_INTC_INTCSEL1_INTSEL27 27 +#define BITP_INTC_INTCSEL1_INTSEL26 26 +#define BITP_INTC_INTCSEL1_INTSEL25 25 +#define BITP_INTC_INTCSEL1_INTSEL24 24 +#define BITP_INTC_INTCSEL1_INTSEL23 23 +#define BITP_INTC_INTCSEL1_INTSEL22 22 +#define BITP_INTC_INTCSEL1_INTSEL21 21 +#define BITP_INTC_INTCSEL1_INTSEL20 20 +#define BITP_INTC_INTCSEL1_INTSEL19 19 +#define BITP_INTC_INTCSEL1_INTSEL18 18 +#define BITP_INTC_INTCSEL1_INTSEL17 17 +#define BITP_INTC_INTCSEL1_INTSEL16 16 +#define BITP_INTC_INTCSEL1_INTSEL15 15 +#define BITP_INTC_INTCSEL1_INTSEL14 14 +#define BITP_INTC_INTCSEL1_INTSEL13 13 +#define BITP_INTC_INTCSEL1_INTSEL12 12 /* Custom IRQ 3 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL11 11 /* Custom IRQ 2 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL10 10 /* Custom IRQ 1 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL9 9 /* Custom IRQ 0 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL8 8 +#define BITP_INTC_INTCSEL1_INTSEL7 7 +#define BITP_INTC_INTCSEL1_INTSEL6 6 +#define BITP_INTC_INTCSEL1_INTSEL5 5 +#define BITP_INTC_INTCSEL1_INTSEL4 4 +#define BITP_INTC_INTCSEL1_INTSEL3 3 +#define BITP_INTC_INTCSEL1_INTSEL2 2 +#define BITP_INTC_INTCSEL1_INTSEL1 1 +#define BITP_INTC_INTCSEL1_INTSEL0 0 +#define BITM_INTC_INTCSEL1_INTSEL31 0x80000000 +#define BITM_INTC_INTCSEL1_INTSEL30 0x40000000 +#define BITM_INTC_INTCSEL1_INTSEL29 0x20000000 +#define BITM_INTC_INTCSEL1_INTSEL28 0x10000000 +#define BITM_INTC_INTCSEL1_INTSEL27 0x08000000 +#define BITM_INTC_INTCSEL1_INTSEL26 0x04000000 +#define BITM_INTC_INTCSEL1_INTSEL25 0x02000000 +#define BITM_INTC_INTCSEL1_INTSEL24 0x01000000 +#define BITM_INTC_INTCSEL1_INTSEL23 0x00800000 +#define BITM_INTC_INTCSEL1_INTSEL22 0x00400000 +#define BITM_INTC_INTCSEL1_INTSEL21 0x00200000 +#define BITM_INTC_INTCSEL1_INTSEL20 0x00100000 +#define BITM_INTC_INTCSEL1_INTSEL19 0x00080000 +#define BITM_INTC_INTCSEL1_INTSEL18 0x00040000 +#define BITM_INTC_INTCSEL1_INTSEL17 0x00020000 +#define BITM_INTC_INTCSEL1_INTSEL16 0x00010000 +#define BITM_INTC_INTCSEL1_INTSEL15 0x00008000 +#define BITM_INTC_INTCSEL1_INTSEL14 0x00004000 +#define BITM_INTC_INTCSEL1_INTSEL13 0x00002000 +#define BITM_INTC_INTCSEL1_INTSEL12 0x00001000 /* Custom IRQ 3 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL11 0x00000800 /* Custom IRQ 2 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL10 0x00000400 /* Custom IRQ 1 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL9 0x00000200 /* Custom IRQ 0 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL8 0x00000100 +#define BITM_INTC_INTCSEL1_INTSEL7 0x00000080 +#define BITM_INTC_INTCSEL1_INTSEL6 0x00000040 +#define BITM_INTC_INTCSEL1_INTSEL5 0x00000020 +#define BITM_INTC_INTCSEL1_INTSEL4 0x00000010 +#define BITM_INTC_INTCSEL1_INTSEL3 0x00000008 +#define BITM_INTC_INTCSEL1_INTSEL2 0x00000004 +#define BITM_INTC_INTCSEL1_INTSEL1 0x00000002 +#define BITM_INTC_INTCSEL1_INTSEL0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCFLAG0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_INTC_INTCFLAG0_FLAG31 31 +#define BITP_INTC_INTCFLAG0_FLAG30 30 +#define BITP_INTC_INTCFLAG0_FLAG29 29 +#define BITP_INTC_INTCFLAG0_FLAG28 28 +#define BITP_INTC_INTCFLAG0_FLAG27 27 +#define BITP_INTC_INTCFLAG0_FLAG26 26 +#define BITP_INTC_INTCFLAG0_FLAG25 25 +#define BITP_INTC_INTCFLAG0_FLAG24 24 +#define BITP_INTC_INTCFLAG0_FLAG23 23 +#define BITP_INTC_INTCFLAG0_FLAG22 22 +#define BITP_INTC_INTCFLAG0_FLAG21 21 +#define BITP_INTC_INTCFLAG0_FLAG20 20 +#define BITP_INTC_INTCFLAG0_FLAG19 19 +#define BITP_INTC_INTCFLAG0_FLAG18 18 +#define BITP_INTC_INTCFLAG0_FLAG17 17 +#define BITP_INTC_INTCFLAG0_FLAG16 16 +#define BITP_INTC_INTCFLAG0_FLAG15 15 +#define BITP_INTC_INTCFLAG0_FLAG14 14 +#define BITP_INTC_INTCFLAG0_FLAG13 13 +#define BITP_INTC_INTCFLAG0_FLAG12 12 /* Custom IRQ 3 Status */ +#define BITP_INTC_INTCFLAG0_FLAG11 11 /* Custom IRQ 2 Status */ +#define BITP_INTC_INTCFLAG0_FLAG10 10 /* Custom IRQ 1 Status */ +#define BITP_INTC_INTCFLAG0_FLAG9 9 /* Custom IRQ 0 Status */ +#define BITP_INTC_INTCFLAG0_FLAG8 8 /* Variance IRQ status. */ +#define BITP_INTC_INTCFLAG0_FLAG7 7 +#define BITP_INTC_INTCFLAG0_FLAG6 6 +#define BITP_INTC_INTCFLAG0_FLAG5 5 +#define BITP_INTC_INTCFLAG0_FLAG4 4 +#define BITP_INTC_INTCFLAG0_FLAG3 3 +#define BITP_INTC_INTCFLAG0_FLAG2 2 +#define BITP_INTC_INTCFLAG0_FLAG1 1 +#define BITP_INTC_INTCFLAG0_FLAG0 0 +#define BITM_INTC_INTCFLAG0_FLAG31 0x80000000 +#define BITM_INTC_INTCFLAG0_FLAG30 0x40000000 +#define BITM_INTC_INTCFLAG0_FLAG29 0x20000000 +#define BITM_INTC_INTCFLAG0_FLAG28 0x10000000 +#define BITM_INTC_INTCFLAG0_FLAG27 0x08000000 +#define BITM_INTC_INTCFLAG0_FLAG26 0x04000000 +#define BITM_INTC_INTCFLAG0_FLAG25 0x02000000 +#define BITM_INTC_INTCFLAG0_FLAG24 0x01000000 +#define BITM_INTC_INTCFLAG0_FLAG23 0x00800000 +#define BITM_INTC_INTCFLAG0_FLAG22 0x00400000 +#define BITM_INTC_INTCFLAG0_FLAG21 0x00200000 +#define BITM_INTC_INTCFLAG0_FLAG20 0x00100000 +#define BITM_INTC_INTCFLAG0_FLAG19 0x00080000 +#define BITM_INTC_INTCFLAG0_FLAG18 0x00040000 +#define BITM_INTC_INTCFLAG0_FLAG17 0x00020000 +#define BITM_INTC_INTCFLAG0_FLAG16 0x00010000 +#define BITM_INTC_INTCFLAG0_FLAG15 0x00008000 +#define BITM_INTC_INTCFLAG0_FLAG14 0x00004000 +#define BITM_INTC_INTCFLAG0_FLAG13 0x00002000 +#define BITM_INTC_INTCFLAG0_FLAG12 0x00001000 /* Custom IRQ 3 Status */ +#define BITM_INTC_INTCFLAG0_FLAG11 0x00000800 /* Custom IRQ 2 Status */ +#define BITM_INTC_INTCFLAG0_FLAG10 0x00000400 /* Custom IRQ 1 Status */ +#define BITM_INTC_INTCFLAG0_FLAG9 0x00000200 /* Custom IRQ 0 Status */ +#define BITM_INTC_INTCFLAG0_FLAG8 0x00000100 /* Variance IRQ status. */ +#define BITM_INTC_INTCFLAG0_FLAG7 0x00000080 +#define BITM_INTC_INTCFLAG0_FLAG6 0x00000040 +#define BITM_INTC_INTCFLAG0_FLAG5 0x00000020 +#define BITM_INTC_INTCFLAG0_FLAG4 0x00000010 +#define BITM_INTC_INTCFLAG0_FLAG3 0x00000008 +#define BITM_INTC_INTCFLAG0_FLAG2 0x00000004 +#define BITM_INTC_INTCFLAG0_FLAG1 0x00000002 +#define BITM_INTC_INTCFLAG0_FLAG0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCFLAG1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_INTC_INTCFLAG1_FLAG31 31 +#define BITP_INTC_INTCFLAG1_FLAG30 30 +#define BITP_INTC_INTCFLAG1_FLAG29 29 +#define BITP_INTC_INTCFLAG1_FLAG28 28 +#define BITP_INTC_INTCFLAG1_FLAG27 27 +#define BITP_INTC_INTCFLAG1_FLAG26 26 +#define BITP_INTC_INTCFLAG1_FLAG25 25 +#define BITP_INTC_INTCFLAG1_FLAG24 24 +#define BITP_INTC_INTCFLAG1_FLAG23 23 +#define BITP_INTC_INTCFLAG1_FLAG22 22 +#define BITP_INTC_INTCFLAG1_FLAG21 21 +#define BITP_INTC_INTCFLAG1_FLAG20 20 +#define BITP_INTC_INTCFLAG1_FLAG19 19 +#define BITP_INTC_INTCFLAG1_FLAG18 18 +#define BITP_INTC_INTCFLAG1_FLAG17 17 +#define BITP_INTC_INTCFLAG1_FLAG16 16 +#define BITP_INTC_INTCFLAG1_FLAG15 15 +#define BITP_INTC_INTCFLAG1_FLAG14 14 +#define BITP_INTC_INTCFLAG1_FLAG13 13 +#define BITP_INTC_INTCFLAG1_FLAG12 12 /* Custom IRQ 3 Status */ +#define BITP_INTC_INTCFLAG1_FLAG11 11 /* Custom IRQ 2 Status */ +#define BITP_INTC_INTCFLAG1_FLAG10 10 /* Custom IRQ 1 Status */ +#define BITP_INTC_INTCFLAG1_FLAG9 9 /* Custom IRQ 0 Status */ +#define BITP_INTC_INTCFLAG1_FLAG8 8 /* Variance IRQ status. */ +#define BITP_INTC_INTCFLAG1_FLAG7 7 +#define BITP_INTC_INTCFLAG1_FLAG6 6 +#define BITP_INTC_INTCFLAG1_FLAG5 5 +#define BITP_INTC_INTCFLAG1_FLAG4 4 +#define BITP_INTC_INTCFLAG1_FLAG3 3 +#define BITP_INTC_INTCFLAG1_FLAG2 2 +#define BITP_INTC_INTCFLAG1_FLAG1 1 +#define BITP_INTC_INTCFLAG1_FLAG0 0 +#define BITM_INTC_INTCFLAG1_FLAG31 0x80000000 +#define BITM_INTC_INTCFLAG1_FLAG30 0x40000000 +#define BITM_INTC_INTCFLAG1_FLAG29 0x20000000 +#define BITM_INTC_INTCFLAG1_FLAG28 0x10000000 +#define BITM_INTC_INTCFLAG1_FLAG27 0x08000000 +#define BITM_INTC_INTCFLAG1_FLAG26 0x04000000 +#define BITM_INTC_INTCFLAG1_FLAG25 0x02000000 +#define BITM_INTC_INTCFLAG1_FLAG24 0x01000000 +#define BITM_INTC_INTCFLAG1_FLAG23 0x00800000 +#define BITM_INTC_INTCFLAG1_FLAG22 0x00400000 +#define BITM_INTC_INTCFLAG1_FLAG21 0x00200000 +#define BITM_INTC_INTCFLAG1_FLAG20 0x00100000 +#define BITM_INTC_INTCFLAG1_FLAG19 0x00080000 +#define BITM_INTC_INTCFLAG1_FLAG18 0x00040000 +#define BITM_INTC_INTCFLAG1_FLAG17 0x00020000 +#define BITM_INTC_INTCFLAG1_FLAG16 0x00010000 +#define BITM_INTC_INTCFLAG1_FLAG15 0x00008000 +#define BITM_INTC_INTCFLAG1_FLAG14 0x00004000 +#define BITM_INTC_INTCFLAG1_FLAG13 0x00002000 +#define BITM_INTC_INTCFLAG1_FLAG12 0x00001000 /* Custom IRQ 3 Status */ +#define BITM_INTC_INTCFLAG1_FLAG11 0x00000800 /* Custom IRQ 2 Status */ +#define BITM_INTC_INTCFLAG1_FLAG10 0x00000400 /* Custom IRQ 1 Status */ +#define BITM_INTC_INTCFLAG1_FLAG9 0x00000200 /* Custom IRQ 0 Status */ +#define BITM_INTC_INTCFLAG1_FLAG8 0x00000100 /* Variance IRQ status. */ +#define BITM_INTC_INTCFLAG1_FLAG7 0x00000080 +#define BITM_INTC_INTCFLAG1_FLAG6 0x00000040 +#define BITM_INTC_INTCFLAG1_FLAG5 0x00000020 +#define BITM_INTC_INTCFLAG1_FLAG4 0x00000010 +#define BITM_INTC_INTCFLAG1_FLAG3 0x00000008 +#define BITM_INTC_INTCFLAG1_FLAG2 0x00000004 +#define BITM_INTC_INTCFLAG1_FLAG1 0x00000002 +#define BITM_INTC_INTCFLAG1_FLAG0 0x00000001 +/** + * @} AD5940RegistersBitfields + * @endcond + * */ + +/** + * @addtogroup SPI_Block + * @{ + * @defgroup SPI_Block_Const + * @{ + * +*/ +#define SPICMD_SETADDR 0x20 /**< set the register address that is going to operate. */ +#define SPICMD_READREG 0x6d /**< command to read register */ +#define SPICMD_WRITEREG 0x2d /**< command to write register */ +#define SPICMD_READFIFO 0x5f /**< command to read FIFO */ +/** + * @} SPI_Block_Const + * @} SPI_Block +*/ + +/** + * @addtogroup AFE_Control + * @{ + * */ + +/** + * @defgroup AFE_Control_Const + * @{ + * */ + +/** + * @defgroup AFEINTC_Const + * @brief AD5940 has two interrupt controller INTC0 and INTC1. Both of them have ability to generate interrupt signal from GPIO. + * @{ + * */ +/* AFE Interrupt controller selection */ +#define AFEINTC_0 0 /**< Interrupt controller 0 */ +#define AFEINTC_1 1 /**< Interrupt controller 1 */ +/** @} */ + +/** + * @defgroup AFEINTC_SRC_Const + * @brief Interrupt source selection. These sources are defined as bit mask. They are available for register INTCCLR, INTCSEL0/1, INTCFLAG0/1 + * @{ + * */ +#define AFEINTSRC_ADCRDY 0x00000001 /**< Bit0, ADC Result Ready Status */ +#define AFEINTSRC_DFTRDY 0x00000002 /**< Bit1, DFT Result Ready Status */ +#define AFEINTSRC_SINC2RDY 0x00000004 /**< Bit2, SINC2/Low Pass Filter Result Status */ +#define AFEINTSRC_TEMPRDY 0x00000008 /**< Bit3, Temp Sensor Result Ready */ +#define AFEINTSRC_ADCMINERR 0x00000010 /**< Bit4, ADC Minimum Value */ +#define AFEINTSRC_ADCMAXERR 0x00000020 /**< Bit5, ADC Maximum Value */ +#define AFEINTSRC_ADCDIFFERR 0x00000040 /**< Bit6, ADC Delta Ready */ +#define AFEINTSRC_MEANRDY 0x00000080 /**< Bit7, Mean Result Ready */ +#define AFEINTSRC_VARRDY 0x00000100 /**< Bit8, Variance Result Ready */ +#define AFEINTSRC_CUSTOMINT0 0x00000200 /**< Bit9, Custom interrupt source 0. It happens when **sequencer** writes 1 to register AFEGENINTSTA.BIT0 */ +#define AFEINTSRC_CUSTOMINT1 0x00000400 /**< Bit10, Custom interrupt source 1. It happens when **sequencer** writes 1 to register AFEGENINTSTA.BIT1*/ +#define AFEINTSRC_CUSTOMINT2 0x00000800 /**< Bit11, Custom interrupt source 2. It happens when **sequencer** writes 1 to register AFEGENINTSTA.BIT2 */ +#define AFEINTSRC_CUSTOMINT3 0x00001000 /**< Bit12, Custom interrupt source 3. It happens when **sequencer** writes 1 to register AFEGENINTSTA.BIT3 */ +#define AFEINTSRC_BOOTLDDONE 0x00002000 /**< Bit13, OTP Boot Loading Done */ +#define AFEINTSRC_WAKEUP 0x00004000 /**< Bit14, AFE Woken up*/ +#define AFEINTSRC_ENDSEQ 0x00008000 /**< Bit15, End of Sequence Interrupt. */ +#define AFEINTSRC_SEQTIMEOUT 0x00010000 /**< Bit16, Sequencer Timeout Command Finished. */ +#define AFEINTSRC_SEQTIMEOUTERR 0x00020000 /**< Bit17, Sequencer Timeout Command Error. */ +#define AFEINTSRC_CMDFIFOFULL 0x00040000 /**< Bit18, Command FIFO Full Interrupt. */ +#define AFEINTSRC_CMDFIFOEMPTY 0x00080000 /**< Bit19, Command FIFO Empty */ +#define AFEINTSRC_CMDFIFOTHRESH 0x00100000 /**< Bit20, Command FIFO Threshold Interrupt. */ +#define AFEINTSRC_CMDFIFOOF 0x00200000 /**< Bit21, Command FIFO Overflow Interrupt. */ +#define AFEINTSRC_CMDFIFOUF 0x00400000 /**< Bit22, Command FIFO Underflow Interrupt. */ +#define AFEINTSRC_DATAFIFOFULL 0x00800000 /**< Bit23, Data FIFO Full Interrupt. */ +#define AFEINTSRC_DATAFIFOEMPTY 0x01000000 /**< Bit24, Data FIFO Empty */ +#define AFEINTSRC_DATAFIFOTHRESH 0x02000000 /**< Bit25, Data FIFO Threshold Interrupt. */ +#define AFEINTSRC_DATAFIFOOF 0x04000000 /**< Bit26, Data FIFO Overflow Interrupt. */ +#define AFEINTSRC_DATAFIFOUF 0x08000000 /**< Bit27, Data FIFO Underflow Interrupt. */ +#define AFEINTSRC_WDTIRQ 0x10000000 /**< Bit28, WDT Timeout Interrupt. */ +#define AFEINTSRC_CRC_OUTLIER 0x20000000 /**< Bit29, CRC interrupt for M355, Outlier Int for AD5940 */ +#define AFEINTSRC_GPT0INT_SLPWUT 0x40000000 /**< Bit30, Gneral Pupose Timer0 IRQ for M355. Sleep or Wakeup Tiemr timeout for AD5940*/ +#define AFEINTSRC_GPT1INT_TRYBRK 0x80000000 /**< Bit31, Gneral Pupose Timer1 IRQ for M355. Tried to Break IRQ for AD5940*/ +#define AFEINTSRC_ALLINT 0xffffffff /**< mask of all interrupt */ +/** @} */ + +/** + * @defgroup AFEPWR_Const + * @brief AFE power mode. + * @details It will set the whole analog system power mode include HSDAC, Excitation Buffer, HSTIA, ADC front-buffer etc. + * @{ +*/ +#define AFEPWR_LP 0 /**< Set AFE to Low Power mode. For signal <80kHz, use it. */ +#define AFEPWR_HP 1 /**< Set AFE to High Power mode. For signal >80kHz, use it. */ +/** + * @} +*/ + +/** + * @defgroup AFEBW_Const + * @brief AFE system bandwidth. + * @details It will set the whole analog bandwidth include HSDAC, Excitation Buffer, HSTIA, ADC front-buffer etc. + * @{ +*/ +#define AFEBW_AUTOSET 0 /**< Set the bandwidth automatically based on WGFCW frequency word. */ +#define AFEBW_50KHZ 1 /**< 50kHZ system bandwidth(DAC/ADC) */ +#define AFEBW_100KHZ 2 /**< 100kHZ system bandwidth(DAC/ADC) */ +#define AFEBW_250KHZ 3 /**< 250kHZ system bandwidth(DAC/ADC) */ +/** + * @} +*/ + +/** + * @defgroup AFECTRL_Const + * @brief AFE Control signal set. Bit masks for register AFECON. + * @details This is all the available control signal for function @ref AD5940_AFECtrlS + * @warning Bit field in register AFECON has some opposite meaning as below definitions. We use all positive word here + * like HPREF instead of HPREFDIS. This set is only used in function @ref AD5940_AFECtrlS, the second parameter + * decides whether enable it or disable it. + * @{ +*/ +#define AFECTRL_HPREFPWR (1L<<5) /**< High power reference on-off control */ +#define AFECTRL_HSDACPWR (1L<<6) /**< High speed DAC on-off control */ +#define AFECTRL_ADCPWR (1L<<7) /**< ADC power on-off control */ +#define AFECTRL_ADCCNV (1L<<8) /**< Start ADC convert enable */ +#define AFECTRL_EXTBUFPWR (1L<<9) /**< Excitation buffer power control */ +#define AFECTRL_INAMPPWR (1L<<10) /**< Excitation loop input amplifier before P/N node power control */ +#define AFECTRL_HSTIAPWR (1L<<11) /**< High speed TIA amplifier power control */ +#define AFECTRL_TEMPSPWR (1L<<12) /**< Temperature sensor power */ +#define AFECTRL_TEMPCNV (1L<<13) /**< Start Temperature sensor convert */ +#define AFECTRL_WG (1L<<14) /**< Waveform generator on-off control */ +#define AFECTRL_DFT (1L<<15) /**< DFT engine on-off control */ +#define AFECTRL_SINC2NOTCH (1L<<16) /**< SIN2+Notch block on-off control */ +#define AFECTRL_ALDOLIMIT (1L<<19) /**< ALDO current limit on-off control */ +#define AFECTRL_DACREFPWR (1L<<20) /**< DAC reference buffer power control */ +#define AFECTRL_DCBUFPWR (1L<<21) /**< Excitation loop DC offset buffer sourced from LPDAC power control */ +#define AFECTRL_ALL 0x39ffe0 /**< All control signals */ +/** + * @} +*/ + +/** + * @defgroup LPMODECTRL_Const + * @brief LP Control signal(bit mask) for register LPMODECON + * @details This is all the available control signal for function @ref AD5940_LPModeCtrlS + * @warning Bit field in register LPMODECON has some opposite meaning as below definitions. We use all positive word here + * like HPREFPWR instead of HPREFDIS. This set is only used in function @ref AD5940_AFECtrlS, the second parameter + * decides whether enable or disable selected block(s). + * @{ +*/ +#define LPMODECTRL_HFOSCEN (1<<0) /**< Enable internal HFOSC. Note: the register defination is set this bit to 1 to disable it. */ +#define LPMODECTRL_HPREFPWR (1<<1) /**< High power reference power EN. Note: the register defination is set this bit to 1 to disable it. */ +#define LPMODECTRL_ADCCNV (1<<2) /**< Start ADC convert enable */ +#define LPMODECTRL_REPEATEN (1<<3) /**< Enable repeat convert function. This will enable ADC power automatically */ +#define LPMODECTRL_GLBBIASZ (1<<4) /**< Enable Global ZTAT bias. Disable it to save more power */ +#define LPMODECTRL_GLBBIASP (1<<5) /**< Enable Global PTAT bias. Disable it to save more power */ +#define LPMODECTRL_BUFHP1P8V (1<<6) /**< High power 1.8V reference buffer */ +#define LPMODECTRL_BUFHP1P1V (1<<7) /**< High power 1.1V reference buffer */ +#define LPMODECTRL_ALDOPWR (1<<8) /**< Enable ALDO. Note: register defination is set this bit to 1 to disable ALDO. */ +#define LPMODECTRL_ALL 0x1ff /**< All Control signal Or'ed together*/ +#define LPMODECTRL_NONE 0 /**< No blocks selected */ +/** @} */ + +/** + * @defgroup AFERESULT_Const + * @brief The available AFE results type. Used for function @ref AD5940_ReadAfeResult + * @{ +*/ +#define AFERESULT_SINC3 0 /**< SINC3 result */ +#define AFERESULT_SINC2 1 /**< SINC2+NOTCH result */ +#define AFERESULT_TEMPSENSOR 2 /**< Temperature sensor result */ +#define AFERESULT_DFTREAL 3 /**< DFT Real result */ +#define AFERESULT_DFTIMAGE 4 /**< DFT Imaginary result */ +#define AFERESULT_STATSMEAN 5 /**< Statistic Mean result */ +#define AFERESULT_STATSVAR 6 /**< Statistic Variance result */ +/** @} */ + +/** + * @} AFE_Control_Const + * @} AFE_Control + * */ + +/** + * @addtogroup High_Speed_Loop + * @{ + * @defgroup High_Speed_Loop_Const + * @{ +*/ + +/** + * @defgroup Switch_Matrix_Block_Const + * @{ + * @defgroup SWD_Const + * @brief Switch D set. This is bit mask for register DSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type + * The bit masks can be OR'ed together. For example + * - `SWD_AIN1|SWD_RCAL0` means close SWD_AIN1 and SWD_RCAL0 in same time, and open all other D switches. + * - `SWD_AIN2` means close SWD_AIN2 and open all other D switches. + * @{ +*/ +#define SWD_OPEN (0<<0) /**< Open all D switch. */ +#define SWD_RCAL0 (1<<0) /**< pin RCAL0 */ +#define SWD_AIN1 (1<<1) /**< Pin AIN1 */ +#define SWD_AIN2 (1<<2) /**< Pin AIN2 */ +#define SWD_AIN3 (1<<3) /**< Pin AIN3 */ +#define SWD_CE0 (1<<4) /**< Pin CE0 */ +#define SWD_CE1 (1<<5) /**< CE1 in ADuCM355 */ +#define SWD_AFE1 (1<<5) /**< AFE1 in AD594x */ +#define SWD_SE0 (1<<6) /**< Pin SE0 */ +#define SWD_SE1 (1<<7) /**< SE1 in ADuCM355 */ +#define SWD_AFE3 (1<<7) /**< AFE3 in AD594x */ +/** @} */ + +/** + * @defgroup SWP_Const + * @brief Switch P set. This is bit mask for register PSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type. + * The bit masks can be OR'ed together. For example + * - `SWP_RCAL0|SWP_AIN1` means close SWP_RCAL0 and SWP_AIN1 in same time, and open all other P switches. + * - `SWP_SE0` means close SWP_SE0 and open all other P switches. + * @{ +*/ +#define SWP_OPEN 0 /**< Open all P switches */ +#define SWP_RCAL0 (1<<0) /**< Pin RCAL0 */ +#define SWP_AIN1 (1<<1) /**< Pin AIN1 */ +#define SWP_AIN2 (1<<2) /**< Pin AIN2 */ +#define SWP_AIN3 (1<<3) /**< Pin AIN3 */ +#define SWP_RE0 (1<<4) /**< Pin RE0 */ +#define SWP_RE1 (1<<5) /**< RE1 in ADuCM355 */ +#define SWP_AFE2 (1<<5) /**< AFE2 in AD5940 */ +#define SWP_SE0 (1<<6) /**< Pin SE0 */ +#define SWP_DE0 (1<<7) /**< Pin DE0 */ +#define SWP_SE1 (1<<8) /**< SE1 in ADuCM355 */ +#define SWP_AFE3 (1<<8) /**< AFE3 in AD5940 */ +#define SWP_DE1 (1<<9) /**< ADuCM355 Only. */ +#define SWP_CE0 (1<<10) /**< Pin CE0 */ +#define SWP_CE1 (1<<11) /**< CE1 in ADuCM355 */ +#define SWP_AFE1 (1<<11) /**< AFE1 in AD5940 */ +#define SWP_PL (1<<13) /**< Internal PL switch */ +#define SWP_PL2 (1<<14) /**< Internal PL2 switch */ +/** @} */ + +/** + * @defgroup SWN_Const + * @brief Switch N set. This is bit mask for register NSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type. + * The bit masks can be OR'ed together. For example + * - `SWN_RCAL0|SWN_AIN1` means close SWN_RCAL0 and SWN_AIN1 in same time, and open all other N switches. + * - `SWN_SE0` means close SWN_SE0 and open all other N switches. + * @{ +*/ +#define SWN_OPEN 0 /**< Open all N switches */ +#define SWN_RCAL1 (1<<9) /**< Pin RCAL1 */ +#define SWN_AIN0 (1<<0) /**< Pin AIN0 */ +#define SWN_AIN1 (1<<1) /**< Pin AIN1 */ +#define SWN_AIN2 (1<<2) /**< Pin AIN2 */ +#define SWN_AIN3 (1<<3) /**< Pin AIN3 */ +#define SWN_SE0LOAD (1<<4) /**< SE0_LOAD is different from PIN SE0. It's the point after 100Ohm load resistor */ +#define SWN_DE0LOAD (1<<5) /**< DE0_Load is after Rload resistor */ +#define SWN_SE1LOAD (1<<6) /**< SE1_LOAD in ADuCM355 */ +#define SWN_AFE3LOAD (1<<6) /**< AFE3LOAD in ADuCM355 */ +#define SWN_DE1LOAD (1<<7) /**< ADuCM355 Only*/ +#define SWN_SE0 (1<<8) /**< SE0 here means the PIN SE0. */ +#define SWN_NL (1<<10) /**< Internal NL switch */ +#define SWN_NL2 (1<<11) /**< Internal NL2 switch */ +/** @} */ + +/** + * @defgroup SWT_Const + * @brief Switch T set. This is bit mask for register TSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type. + * The bit masks can be OR'ed together. For example + * - SWT_RCAL0|SWT_AIN1 means close SWT_RCAL0 and SWT_AIN1 in same time, and open all other T switches. + * - SWT_SE0LOAD means close SWT_SE0LOAD and open all other T switches. + * @{ +*/ +#define SWT_OPEN 0 /**< Open all T switches */ +#define SWT_RCAL1 (1<<11) /**< Pin RCAL1 */ +#define SWT_AIN0 (1<<0) /**< Pin AIN0 */ +#define SWT_AIN1 (1<<1) /**< Pin AIN1 */ +#define SWT_AIN2 (1<<2) /**< Pin AIN2 */ +#define SWT_AIN3 (1<<3) /**< Pin AIN3 */ +#define SWT_SE0LOAD (1<<4) /**< SE0_LOAD is different from PIN SE0. It's the point after 100Ohm load resistor */ +#define SWT_DE0 (1<<5) /**< DE0 pin. */ +#define SWT_SE1LOAD (1<<6) /**< SE1_LOAD on ADuCM355*/ +#define SWT_AFE3LOAD (1<<6) /**< AFE3_LOAD on ADuCM355*/ +#define SWT_DE1 (1<<7) /**< ADuCM355 Only*/ +#define SWT_TRTIA (1<<8) /**< T9 switch. Connect RTIA to T matrix */ +#define SWT_DE0LOAD (1<<9) /**< DE0Load is the position after Rload Resisor */ +#define SWT_DE1LOAD (1<<10) /**< DE1Load is the position after Rload Resisor */ +/** @} */ + +/** @} Switch_Matrix_Block_Const */ + + +/** + * @defgroup Waveform_Generator_Block_Const + * @{ +*/ +/** + * @defgroup WGTYPE_Const + * @brief Waveform generator signal type + * @{ +*/ +#define WGTYPE_MMR 0 /**< Direct write to DAC using register */ +#define WGTYPE_SIN 2 /**< Sine wave generator */ +#define WGTYPE_TRAPZ 3 /**< Trapezoid generator */ +/** @} */ +/** @} Waveform_Generator_Block_Const */ + +/** + * @defgroup HSDAC_Block_Const + * @{ +*/ +/* Excitation buffer gain selection */ +/** + * @defgroup EXCITBUFGAIN_Const + * @{ +*/ +#define EXCITBUFGAIN_2 0 /**< Excitation buffer gain is x2 */ +#define EXCITBUFGAIN_0P25 1 /**< Excitation buffer gain is x1/4 */ +/** @} */ + +/** + * @defgroup HSDACGAIN_Const + * @{ +*/ +/* HSDAC PGA Gain selection(DACCON.BIT0) */ +#define HSDACGAIN_1 0 /**< Gain is x1 */ +#define HSDACGAIN_0P2 1 /**< Gain is x1/5 */ +/** @} */ +/** @} */ //HSDAC_Block_Const + +/** + * @defgroup HSTIA_Block_Const + * @{ + * */ +/* HSTIA Amplifier Positive Input selection */ + +/** + * @defgroup HSTIABIAS_Const + * @warning When select Vzero0 as bias, close LPDAC switch + * @{ +*/ +#define HSTIABIAS_1P1 0 /**< Internal 1.1V common voltage from internal 1.1V reference buffer */ +#define HSTIABIAS_VZERO0 1 /**< From LPDAC0 Vzero0 output */ +#define HSTIABIAS_VZERO1 2 /**< From LPDAC1 Vzero1 output. Only available on ADuCM355. */ +/** @} */ + + +/* HSTIA Internal RTIA selection */ + +/** + * @defgroup HSTIARTIA_Const + * @{ +*/ +#define HSTIARTIA_200 0 /**< HSTIA Internal RTIA resistor 200 */ +#define HSTIARTIA_1K 1 /**< HSTIA Internal RTIA resistor 1K */ +#define HSTIARTIA_5K 2 /**< HSTIA Internal RTIA resistor 5K */ +#define HSTIARTIA_10K 3 /**< HSTIA Internal RTIA resistor 10K */ +#define HSTIARTIA_20K 4 /**< HSTIA Internal RTIA resistor 20K */ +#define HSTIARTIA_40K 5 /**< HSTIA Internal RTIA resistor 40K */ +#define HSTIARTIA_80K 6 /**< HSTIA Internal RTIA resistor 80K */ +#define HSTIARTIA_160K 7 /**< HSTIA Internal RTIA resistor 160K */ +#define HSTIARTIA_OPEN 8 /**< Open internal resistor */ +/** @} */ + +/** + * @defgroup HSTIADERTIA_Const + * @{ +*/ +#define HSTIADERTIA_50 0 /**< 50Ohm Settings depends on RLOAD resistor. */ +#define HSTIADERTIA_100 1 /**< 100Ohm Settings depends on RLOAD resistor.*/ +#define HSTIADERTIA_200 2 /**< 200Ohm Settings depends on RLOAD resistor.*/ +#define HSTIADERTIA_1K 3 /**< set bit[7:3] to 0x0b(11) */ +#define HSTIADERTIA_5K 4 /**< set bit[7:3] to 0x0c(12) */ +#define HSTIADERTIA_10K 5 /**< set bit[7:3] to 0x0d(13) */ +#define HSTIADERTIA_20K 6 /**< set bit[7:3] to 0x0e(14) */ +#define HSTIADERTIA_40K 7 /**< set bit[7:3] to 0x0f(15) */ +#define HSTIADERTIA_80K 8 /**< set bit[7:3] to 0x10(16) */ +#define HSTIADERTIA_160K 9 /**< set bit[7:3] to 0x11(17) */ +#define HSTIADERTIA_TODE 10 /**< short HSTIA output to DE0 pin. set bit[7:3] to 0x12(18) */ +#define HSTIADERTIA_OPEN 11 /**< Default state is set to OPEN RTIA by setting bit[7:3] to 0x1f */ +/** @} */ + +/* HSTIA DE0 Terminal internal RLOAD selection */ +/** + * @defgroup HSTIADERLOAD_Const + * @{ +*/ +#define HSTIADERLOAD_0R 0 /**< set bit[2:0] to 0x00 */ +#define HSTIADERLOAD_10R 1 /**< set bit[2:0] to 0x01 */ +#define HSTIADERLOAD_30R 2 /**< set bit[2:0] to 0x02 */ +#define HSTIADERLOAD_50R 3 /**< set bit[2:0] to 0x03 */ +#define HSTIADERLOAD_100R 4 /**< set bit[2:0] to 0x04 */ +#define HSTIADERLOAD_OPEN 5 /**< RLOAD open means open switch between HSTIA negative input and Rload resistor().Default state is OPEN RLOAD by setting HSTIARES03CON[2:0] to 0x5, 0x6 or 0x7 */ +/** @} */ + +/** + * @defgroup HSTIAPWRMOE_Const + * @{ +*/ +#define HSTIAPWRMOE_LP 0 /**< HSTIA in LP mode */ +#define HSTIAPWRMOE_HP 1 /**< HSTIA in HP mode */ +/** @} */ + + +/** @} HSTIA_Block_Const */ +/** + * @} High_Speed_Loop_Const + * @} High_Speed_Loop +*/ + +/** + * @addtogroup Low_Power_Loop + * Low power includes low power DAC and two low power amplifiers(PA and TIA) + * @{ + * @defgroup Low_Power_Loop_Const + * The constant used in Low power loop. + * @{ +*/ + +/** + * @defgroup LPDAC_Block_Const + * @{ + * */ +/** + * @defgroup LPDAC_Const + * Select which LPDAC is accessing. + * @note This parameter must be configured correctly + * @{ +*/ +#define LPDAC0 0 /**< LPDAC0 */ +#define LPDAC1 1 /**< LPDAC1, ADuCM355 Only */ +/** @} */ +/** + * @defgroup LPDACSRC_Const + * LPDAC data source selection. Either from MMR or from waveform generator. + * @{ +*/ +#define LPDACSRC_MMR 0 /**< Get data from register REG_AFE_LPDACDAT0DATA0 */ +#define LPDACSRC_WG 1 /**< Get data from waveform generator */ +/** @} */ + +/** + * @defgroup LPDACSW_Const + * @brief LPDAC switch settings + * @{ +*/ +#define LPDACSW_VBIAS2LPPA 0x10 /**< switch between LPDAC Vbias output and LPPA(low power PA(Potential Amplifier)) */ +#define LPDACSW_VBIAS2PIN 0x08 /**< Switch between LPDAC Vbias output and Vbias pin */ +#define LPDACSW_VZERO2LPTIA 0x04 /**< Switch between LPDAC Vzero output and LPTIA positive input */ +#define LPDACSW_VZERO2PIN 0x02 /**< Switch between LPDAC Vzero output and Vzero pin */ +#define LPDACSW_VZERO2HSTIA 0x01 /**< Switch between LPDAC Vzero output and HSTIA positive input MUX */ +/** @} */ + +/** + * @defgroup LPDACVZERO_Const + * @brief Vzero MUX selection + * @{ +*/ +#define LPDACVZERO_6BIT 0 /**< Connect Vzero to 6bit LPDAC output */ +#define LPDACVZERO_12BIT 1 /**< Connect Vzero to 12bit LPDAC output */ +/** @} */ + +/** + * @defgroup LPDACVBIAS_Const + * @brief Vbias MUX selection + * @{ +*/ +#define LPDACVBIAS_6BIT 1 /**< Connect Vbias to 6bit LPDAC output */ +#define LPDACVBIAS_12BIT 0 /**< Connect Vbias to 12bit LPDAC output */ +/** @} */ + + +/** + * @defgroup LPDACREF_Const + * @brief LPDAC reference selection + * @{ +*/ +#define LPDACREF_2P5 0 /**< Internal 2.5V reference */ +#define LPDACREF_AVDD 1 /**< Use AVDD as reference */ +/** @} */ + +/** @} */ //LPDAC_Block_Const + +/** + * @defgroup LPAMP_Block_Const + * @brief Low power amplifies include potential-state amplifier(PA in short) and TIA. + * @{ + * */ + +/** + * @defgroup LPTIA_Const + * @brief LPTIA selecion + * @{ + * */ +#define LPTIA0 0 /**< LPTIA0 */ +#define LPTIA1 1 /**< LPTIA1, ADuCM355 Only */ +/** @} */ + +/** + * @defgroup LPTIARF_Const + * @brief LPTIA LPF Resistor selection + * @{ + * */ +#define LPTIARF_OPEN 0 /**< Disconnect Rf resistor */ +#define LPTIARF_SHORT 1 /**< Bypass Rf resistor */ +#define LPTIARF_20K 2 /**< 20kOhm Rf */ +#define LPTIARF_100K 3 /**< Rf resistor 100kOhm */ +#define LPTIARF_200K 4 /**< Rf resistor 200kOhm */ +#define LPTIARF_400K 5 /**< Rf resistor 400kOhm */ +#define LPTIARF_600K 6 /**< Rf resistor 600kOhm */ +#define LPTIARF_1M 7 /**< Rf resistor 1MOhm */ +/** @} */ + +/** + * @defgroup LPTIARLOAD_Const + * @brief LPTIA Rload Selection + * @{ +*/ +#define LPTIARLOAD_SHORT 0 /**< 0Ohm Rload */ +#define LPTIARLOAD_10R 1 /**< 10Ohm Rload */ +#define LPTIARLOAD_30R 2 /**< Rload resistor 30Ohm */ +#define LPTIARLOAD_50R 3 /**< Rload resistor 50Ohm */ +#define LPTIARLOAD_100R 4 /**< Rload resistor 100Ohm */ +#define LPTIARLOAD_1K6 5 /**< Only available when RTIA setting >= 2KOHM */ +#define LPTIARLOAD_3K1 6 /**< Only available when RTIA setting >= 4KOHM */ +#define LPTIARLOAD_3K6 7 /**< Only available when RTIA setting >= 4KOHM */ +/** @} */ + +/** + * @defgroup LPTIARTIA_Const + * @brief LPTIA RTIA Selection + * @note The real RTIA resistor value dependents on Rload settings. + * @{ +*/ +#define LPTIARTIA_OPEN 0 /**< Disconnect LPTIA Internal RTIA */ +#define LPTIARTIA_200R 1 /**< 200Ohm Internal RTIA */ +#define LPTIARTIA_1K 2 /**< 1KOHM */ +#define LPTIARTIA_2K 3 /**< 2KOHM */ +#define LPTIARTIA_3K 4 /**< 3KOHM */ +#define LPTIARTIA_4K 5 /**< 4KOHM */ +#define LPTIARTIA_6K 6 /**< 6KOHM */ +#define LPTIARTIA_8K 7 /**< 8KOHM */ +#define LPTIARTIA_10K 8 /**< 10KOHM */ +#define LPTIARTIA_12K 9 /**< 12KOHM */ +#define LPTIARTIA_16K 10 /**< 16KOHM */ +#define LPTIARTIA_20K 11 /**< 20KOHM */ +#define LPTIARTIA_24K 12 /**< 24KOHM */ +#define LPTIARTIA_30K 13 /**< 30KOHM */ +#define LPTIARTIA_32K 14 /**< 32KOHM */ +#define LPTIARTIA_40K 15 /**< 40KOHM */ +#define LPTIARTIA_48K 16 /**< 48KOHM */ +#define LPTIARTIA_64K 17 /**< 64KOHM */ +#define LPTIARTIA_85K 18 /**< 85KOHM */ +#define LPTIARTIA_96K 19 /**< 96KOHM */ +#define LPTIARTIA_100K 20 /**< 100KOHM */ +#define LPTIARTIA_120K 21 /**< 120KOHM */ +#define LPTIARTIA_128K 22 /**< 128KOHM */ +#define LPTIARTIA_160K 23 /**< 160KOHM */ +#define LPTIARTIA_196K 24 /**< 196KOHM */ +#define LPTIARTIA_256K 25 /**< 256KOHM */ +#define LPTIARTIA_512K 26 /**< 512KOHM */ +/** @} */ + +/** + * @defgroup LPAMP_Const + * LPAMP selecion. On AD594x, only LPAMP0 is available. + * @note This parameter must be configured correctly. + * @{ + * */ +#define LPAMP0 0 /**< LPAMP0, AMP include both LPTIA and Potentio-stat amplifiers */ +#define LPAMP1 1 /**< LPAMP1, ADuCM355 Only */ +/** @} */ + +/** + * @defgroup LPAMPPWR_Const + * @brief Low power amplifier(PA and TIA) power mode selection. + * @{ +*/ +#define LPAMPPWR_NORM 0 /**< Normal Power mode */ +#define LPAMPPWR_BOOST1 1 /**< Boost power to level 1 */ +#define LPAMPPWR_BOOST2 2 /**< Boost power to level 2 */ +#define LPAMPPWR_BOOST3 3 /**< Boost power to level 3 */ +#define LPAMPPWR_HALF 4 /**< Put PA and TIA in half power mode */ +/** @} */ + +#define LPTIASW(n) (1L<>2)&0x7f)<<24) \ + |(((uint32_t)(data))&0xffffff)) + +/* Some commands used frequently */ +#define SEQ_NOP() SEQ_WAIT(0) /**< SEQ_NOP is just a simple wait command that wait one system clock */ +#define SEQ_HALT() SEQ_WR(REG_AFE_SEQCON,0x12) /**< Can halt sequencer. Used for debug */ +#define SEQ_STOP() SEQ_WR(REG_AFE_SEQCON,0x00) /**< Disable sequencer, this will generate End of Sequence interrupt */ + +#define SEQ_SLP() SEQ_WR(REG_AFE_SEQTRGSLP, 1) /**< Trigger sleep. If sleep is allowed, AFE will go to sleep/hibernate mode */ + +#define SEQ_INT0() SEQ_WR(REG_AFE_AFEGENINTSTA, (1L<<0)) /**< Generate custom interrupt 0 */ +#define SEQ_INT1() SEQ_WR(REG_AFE_AFEGENINTSTA, (1L<<1)) /**< Generate custom interrupt 1 */ +#define SEQ_INT2() SEQ_WR(REG_AFE_AFEGENINTSTA, (1L<<2)) /**< Generate custom interrupt 2 */ +#define SEQ_INT3() SEQ_WR(REG_AFE_AFEGENINTSTA, (1L<<3)) /**< Generate custom interrupt 3 */ + +/* Helper to calculate sequence length in array */ +#define SEQ_LEN(n) (sizeof(n)/4) /**< Calculate how many commands are in sepecified array. */ +/** @} */ //Sequencer_Helper + +/* FIFO */ +/** + * @defgroup FIFOMODE_Const + * @{ +*/ +#define FIFOMODE_FIFO 2 /**< Standard FIFO mode. If FIFO is full, reject all comming data and put FIFO to fault state, report interrupt if enabled */ +#define FIFOMODE_STREAM 3 /**< Stream mode. If FIFO is full, discard older data. Report FIFO full interrupt if enabled */ +/** @} */ + +/** + * @defgroup FIFOSRC_Const + * @{ +*/ +#define FIFOSRC_SINC3 0 /**< SINC3 data */ +#define FIFOSRC_DFT 2 /**< DFT real and imaginary part */ +#define FIFOSRC_SINC2NOTCH 3 /**< SINC2+NOTCH block. Notch can be bypassed, so SINC2 data can be feed to FIFO */ +#define FIFOSRC_VAR 4 /**< Statistic variarance output */ +#define FIFOSRC_MEAN 5 /**< Statistic mean output */ +/** @} */ + +/** + * @defgroup FIFO_Helper + * @{ +*/ +/** + * Method to identify FIFO channel ID: + * [31:25][24:23][22:16][15:0] + * [ ECC ][SEQID][CH_ID][DATA] + * + * CH_ID: [22:16] 7bit in total: + * xxxxx_xx + * 11111_xx : DFT results + * 11110_xx : Mean of statistic block + * 11101_xx : Variance of statistic block + * 1xxxx_xx : Notch filter result, where xxx_xx is the ADC MUX P settings(6bits of reg ADCCON[5:0]). + * 0xxxx_xx : SINC3 filter result, where xxx_xx is the ADC MUX P settings(6bits of reg ADCCON[5:0]). +*/ +#define FIFO_SEQID(data) ((((uint32_t)data)>>23)&0x3) /**< Return seqid of this FIFO result */ +#define FIFO_ECC(data) ((((uint32_t)data)>>25)&0x7f) /**< Return ECC of this FIFO result */ +#define FIFO_CHANID(data) ((((uint32_t)data)>>16)&0x7f) /**< Return Channel ID */ +#define FIFOCHANID_MUXP(data) ((((uint32_t)data)>>16)&0x3f) /**< Return the ADC MUXP selection */ + +#define ISCHANID_DFT(data) ((((((uint32_t)data)>>18)&0x1f)==0x1f)?bTRUE:bFALSE) /**< If the channel id is DFT */ +#define ISCHANID_MEAN(data) ((((((uint32_t)data)>>18)&0x1f)==0x1e)?bTRUE:bFALSE) /**< If the channel id is MEAN */ +#define ISCHANID_VAR(data) ((((((uint32_t)data)>>18)&0x1f)==0x1d)?bTRUE:bFALSE) /**< If the channel id is Variance */ +#define ISCHANID_SINC3(data) ((((((uint32_t)data)>>18)&0x1f)< 0x10)?bTRUE:bFALSE) /**< If the channel id is SINC3 */ +#define ISCHANID_NOTCH(data) ((((((uint32_t)data)>>18)&0x1f)>=0x10)&&(((((uint32_t)data>>18)&0x1f) < 0x1d)?bTRUE:bFALSE)) /**< If the channel id is Notch */ +/** @} */ + +/** + * @defgroup FIFOSIZE_Const + * @brief Set FIFO size. + * @warning The total available SRAM is 6kB. It's shared by FIFO and sequencer. + * @{ +*/ +#define FIFOSIZE_32B 0 /**< The selfbuild in 32Byte for data FIFO. All 6kB SRAM for sequencer */ +#define FIFOSIZE_2KB 1 /**< DATA FIFO use 2kB. The reset 4kB is used for sequencer */ +#define FIFOSIZE_4KB 2 /**< 4kB for Data FIFO. 2kB for sequencer */ +#define FIFOSIZE_6KB 3 /**< All 6kB for Data FIFO. Build in 32Bytes memory for sequencer */ +/** @} */ + +/* Wake up timer */ +/** + * @defgroup WUPTENDSEQ_Const + * @{ +*/ +#define WUPTENDSEQ_A 0 /**< End at slot A */ +#define WUPTENDSEQ_B 1 /**< End at slot B */ +#define WUPTENDSEQ_C 2 /**< End at slot C */ +#define WUPTENDSEQ_D 3 /**< End at slot D */ +#define WUPTENDSEQ_E 4 /**< End at slot E */ +#define WUPTENDSEQ_F 5 /**< End at slot F */ +#define WUPTENDSEQ_G 6 /**< End at slot G */ +#define WUPTENDSEQ_H 7 /**< End at slot H */ +/** @} */ + +/** + * @} End of sequencer_and_FIFO block + * @} Sequencer_FIFO + * */ + +/** + * @addtogroup MISC_Block + * @{ + * @defgroup MISC_Block_Const + * @brief This block includes clock, GPIO, configuration. + * @{ +*/ + +/* Helper for calculate clocks needed for various of data type */ +/** + * @defgroup DATATYPE_Const + * @{ +*/ +#define DATATYPE_ADCRAW 0 /**< ADC raw data */ +#define DATATYPE_SINC3 1 /**< SINC3 data */ +#define DATATYPE_SINC2 2 /**< SINC2 Data */ +#define DATATYPE_DFT 3 /**< DFT */ +#define DATATYPE_NOTCH 4 /**< Notch filter output. (when notch is not bypassed) */ +//#define DATATYPE_MEAN +/** @} */ + + +/** + * @defgroup SLPKEY_Const + * @{ +*/ +#define SLPKEY_LOCK 0 /**< any incorrect value will lock the key */ +#define SLPKEY_UNLOCK 0xa47e5 /**< The correct key for register SEQSLPLOCK */ +/** @} */ + +/** + * @defgroup HPOSCOUT_Const + * @brief Set HPOSC output clock frequency, 16MHz or 32MHz. + * @{ +*/ +#define HPOSCOUT_32MHZ 0 /**< Configure internal HFOSC output 32MHz clock */ +#define HPOSCOUT_16MHZ 1 /**< 16MHz Clock */ +/** @} */ + +/* GPIO */ +/** + * @defgroup AGPIOPIN_Const + * @brief The pin masks for register GP0OEN, GP0PE, GP0IEN,..., GP0TGL + * @{ +*/ +#define AGPIO_Pin0 0x01 /**< AFE GPIO0, only available on AD5940 and AD5941, not ADuCM355 */ +#define AGPIO_Pin1 0x02 /**< AFE GPIO1, only available on AD5940 and AD5941, not ADuCM355 */ +#define AGPIO_Pin2 0x04 /**< AFE GPIO2, only available on AD5940 and AD5941, not ADuCM355 */ +#define AGPIO_Pin3 0x08 /**< AFE GPIO3, only available on AD5941. */ +#define AGPIO_Pin4 0x10 /**< AFE GPIO4, only available on AD5941. */ +#define AGPIO_Pin5 0x20 /**< AFE GPIO5, only available on AD5941. */ +#define AGPIO_Pin6 0x40 /**< AFE GPIO6, only available on AD5941. */ +#define AGPIO_Pin7 0x80 /**< AFE GPIO7, only available on AD5941. */ +/** @} */ + +/** + * @defgroup GP0FUNC_Const + * @{ +*/ +#define GP0_INT 0 /**< Interrupt Controller 0 output */ +#define GP0_TRIG 1 /**< Sequence0 trigger */ +#define GP0_SYNC 2 /**< Use Sequencer to controll GP0 output level */ +#define GP0_GPIO 3 /**< Normal GPIO function */ +/** @} */ + +/** + * @defgroup GP1FUNC_Const + * @{ +*/ +#define GP1_GPIO (0<<2) /**< Normal GPIO function */ +#define GP1_TRIG (1<<2) /**< Sequence1 trigger */ +#define GP1_SYNC (2<<2) /**< Use Sequencer to controll GP1 output level */ +#define GP1_SLEEP (3<<2) /**< Internal Sleep Signal */ +/** @} */ + +/** + * @defgroup GP2FUNC_Const + * @{ +*/ +#define GP2_PORB (0<<4) /**< Internal Power ON reset signal */ +#define GP2_TRIG (1<<4) /**< Sequence1 trigger */ +#define GP2_SYNC (2<<4) /**< Use Sequencer to controll GP2 output level */ +#define GP2_EXTCLK (3<<4) /**< External Clock input(32kHz/16MHz/32MHz) */ +/** @} */ + +/** + * @defgroup GP3FUNC_Const + * @{ +*/ +#define GP3_GPIO (0<<6) /**< Normal GPIO function */ +#define GP3_TRIG (1<<6) /**< Sequence3 trigger */ +#define GP3_SYNC (2<<6) /**< Use Sequencer to controll GP3 output level */ +#define GP3_INT0 (3<<6) /**< Interrupt Controller 0 output */ +/** @} */ + +/** + * @defgroup GP4FUNC_Const + * @note GP4 (Not available on AD5941) + * @{ +*/ +#define GP4_GPIO (0<<8) /**< Normal GPIO function */ +#define GP4_TRIG (1<<8) /**< Sequence0 trigger */ +#define GP4_SYNC (2<<8) /**< Use Sequencer to controll GP4 output level */ +#define GP4_INT1 (3<<8) /**< Interrupt Controller 1 output */ +/** @} */ + +/** + * @defgroup GP5FUNC_Const + * @note GP5 (Not available on AD5941) + * @{ +*/ +#define GP5_GPIO (0<<10) /**< Internal Power ON reset signal */ +#define GP5_TRIG (1<<10) /**< Sequence1 trigger */ +#define GP5_SYNC (2<<10) /**< Use Sequencer to controll GP5 output level */ +#define GP5_EXTCLK (3<<10) /**< External Clock input(32kHz/16MHz/32MHz) */ +/** @} */ + +/** + * @defgroup GP6FUNC_Const + * @note GP6 (Not available on AD5941) + * @{ +*/ +#define GP6_GPIO (0<<12) /**< Normal GPIO function */ +#define GP6_TRIG (1<<12) /**< Sequence2 trigger */ +#define GP6_SYNC (2<<12) /**< Use Sequencer to controll GP6 output level */ +#define GP6_INT0 (3<<12) /**< Interrupt Controller 0 output */ +/** @} */ + +/** + * @defgroup GP7FUNC_Const + * @note GP7 (Not available on AD5941) + * @{ +*/ +#define GP7_GPIO (0<<14) /**< Normal GPIO function */ +#define GP7_TRIG (1<<14) /**< Sequence2 trigger */ +#define GP7_SYNC (2<<14) /**< Use Sequencer to controll GP7 output level */ +#define GP7_INT (3<<14) /**< Interrupt Controller 1 output */ +/** @} */ + +//LPModeClk +/** + * @defgroup LPMODECLK_Const + * @{ +*/ +#define LPMODECLK_HFOSC 0 /**< Use HFOSC 16MHz/32MHz clock as system clock */ +#define LPMODECLK_LFOSC 1 /**< Use LFOSC 32kHz clock as system clock */ +/** @} */ + +/* Clock */ +/** + * @defgroup SYSCLKSRC_Const + * @brief Select system clock source. The clock must be available. If unavailable clock is selected, we can reset AD5940. + * The system clock should be limited to 32MHz. If external clock or XTAL is faster than 16MHz, we use system clock divider to ensure it's always in range of 16MHz. + * @warning Maximum SPI clock has relation with system clock. Limit the SPI clock to ensure SPI clock is slower than system clock. + * @{ +*/ +#define SYSCLKSRC_HFOSC 0 /**< Internal HFOSC. CLock is 16MHz or 32MHz configurable. Set clock divider to ensure system clock is always 16MHz */ +#define SYSCLKSRC_XTAL 1 /**< External crystal. It can be 16MHz or 32MHz.Set clock divider to ensure system clock is always 16MHz */ +#define SYSCLKSRC_LFOSC 2 /**< Internal 32kHz clock. Note the SPI clock also sourced with 32kHz so the register read/write frequency is lower down. */ +#define SYSCLKSRC_EXT 3 /**< External clock from GPIO, AD594x Only */ +/** @} */ + +/** + * @defgroup ADCCLKSRC_Const + * @brief Select ADC clock source. + * The maximum clock is 32MHz. + * @warning The ADC raw data update rate is equal to ADCClock/20. When ADC clock is 32MHz, sample rate is 1.6MSPS. + * The SINC3 filter clock are sourced from ADC clock and should be limited to 16MHz. When ADC clock is set to 32MHz. Clear bit ADCFILTERCON.BIT0 + * to enable the SINC3 clock divider. + * @{ +*/ +#define ADCCLKSRC_HFOSC 0 /**< Internal HFOSC. 16MHz or 32MHz which is configurable */ +#define ADCCLKSRC_XTAL 1 /**< External crystal. Set ADC clock divider to get either 16MHz or 32MHz clock */ +//#define ADCCLKSRC_LFOSC 2 /**< Do not use */ +#define ADCCLKSRC_EXT 3 /**< External clock from GPIO. Set ADC clock divider to get the clock you want */ +/** @} */ + + +/** + * @defgroup ADCCLKDIV_Const + * @brief The divider for ADC clock. ADC clock = ClockSrc/Divider. + * @{ +*/ +#define ADCCLKDIV_1 1 /**< Divider ADCClk = ClkSrc/1 */ +#define ADCCLKDIV_2 2 /**< Divider ADCClk = ClkSrc/2 */ +/** @} */ + +/** + * @defgroup SYSCLKDV_Const + * @brief The divider for system clock. System clock = ClockSrc/Divider. + * @{ +*/ +#define SYSCLKDIV_1 1 /**< Divider SysClk = ClkSrc/1 */ +#define SYSCLKDIV_2 2 /**< Divider SysClk = ClkSrc/2 */ +/** @} */ + +/** + * @defgroup PGACALTYPE_Const + * @brief Calibration Type + * @{ +*/ +#define PGACALTYPE_OFFSET 0 /**< Calibrate offset */ +#define PGACALTYPE_GAIN 1 /**< Calibrate gain */ +#define PGACALTYPE_OFFSETGAIN 2 /**< Calibrate offset and gain */ +/** @} */ + +/** + * @defgroup AD5940ERR_Const + * @brief AD5940 error code used by library and example codes. + * @{ +*/ +#define AD5940ERR_OK 0 /**< No error */ +#define AD5940ERR_ERROR -1 /**< General error message */ +#define AD5940ERR_PARA -2 /**< Parameter is illegal */ +#define AD5940ERR_NULLP -3 /**< Null pointer */ +#define AD5940ERR_BUFF -4 /**< Buffer limited. */ +#define AD5940ERR_ADDROR -5 /**< Out of Range. Register address is out of range. */ +#define AD5940ERR_SEQGEN -6 /**< Sequence generator error */ +#define AD5940ERR_SEQREG -7 /**< Register info is not found */ +#define AD5940ERR_SEQLEN -8 /**< Sequence length is too long. */ +#define AD5940ERR_WAKEUP -9 /**< Unable to wakeup AFE in specified time */ +#define AD5940ERR_TIMEOUT -10 /**< Time out error. */ +#define AD5940ERR_CALOR -11 /**< calibration out of range. */ +#define AD5940ERR_APPERROR -100 /**< Used in example code to indicated the application has not been initialized. */ +/** @} */ + +#ifndef NULL + #define NULL (void *) 0 /**< Null, if it's not defined. */ +#endif +#define MATH_PI 3.1415926f /**< Pi defination. */ + +#define AD5940_ADIID 0x4144 /**< ADIID is fixed to 0x4144 */ +#define AD5940_CHIPID 0x0000 /**< CHIPID is changing with silicon version */ +#define M355_ADIID 0x4144 /**< ADIID is fixed to 0x4144 */ +#define M355_CHIPID 0x0000 /**< CHIPID is changing with silicon version */ + +#define AD5940_SWRST 0xa158 /**< AD594x only. The value to perform software reset via reigster SWRSTCON */ +#define KEY_OSCCON 0xcb14 /**< key of register OSCCON. The key is auto locked after writing to any other register */ +#define KEY_CALDATLOCK 0xde87a5af /**< Calibration key. */ +#define KEY_LPMODEKEY 0xc59d6 /**< LP mode key */ + +#define PARA_CHECK(n) /** add parameter check, Add DEBUG switch */ + +/** + * @} MISC_Block_Const + * @} MISC_Block + * */ +/** + * @defgroup TypeDefinitions + * @{ +*/ + +typedef int32_t AD5940Err; /**< error number defination */ + +/** + * bool definition for ad5940lib. +*/ +typedef enum +{ + bFALSE = 0, bTRUE = !bFALSE, /**< True and False definition*/ +}BoolFlag; + +typedef struct +{ + /* ADC/DAC/TIA reference and buffer */ + BoolFlag HpBandgapEn; /**< Enable High power band-gap. Clear bit AFECON.HPREFDIS will enable Bandgap, while set this bit will disable bandgap */ + BoolFlag Hp1V8BuffEn; /**< High power 1.8V reference buffer enable */ + BoolFlag Hp1V1BuffEn; /**< High power 1.1V reference buffer enable */ + BoolFlag Lp1V8BuffEn; /**< Low power 1.8V reference buffer enable */ + BoolFlag Lp1V1BuffEn; /**< Low power 1.1V reference buffer enable */ + /* Low bandwidth loop reference and buffer */ + BoolFlag LpBandgapEn; /**< Enable Low power band-gap. */ + BoolFlag LpRefBufEn; /**< Enable the 2.5V low power reference buffer */ + BoolFlag LpRefBoostEn; /**< Boost buffer current */ + /* DAC Reference Buffer */ + BoolFlag HSDACRefEn; /**< Enable DAC reference buffer from HP Bandgap */ + /* Misc. control */ + BoolFlag Hp1V8ThemBuff; /**< Thermal Buffer for internal 1.8V reference to AIN3 pin */ + BoolFlag Hp1V8Ilimit; /**< Current limit for High power 1.8V reference buffer */ + BoolFlag Disc1V8Cap; /**< Discharge 1.8V capacitor. Short external 1.8V decouple capacitor to ground. Be careful when use this bit */ + BoolFlag Disc1V1Cap; /**< Discharge 1.1V capacitor. Short external 1.1V decouple capacitor to ground. Be careful when use this bit */ +}AFERefCfg_Type; + +/** + * @defgroup ADC_BlockType + * @{ +*/ + +/** + * Structure for ADC Basic settings include MUX and PGA. +*/ +typedef struct +{ + uint32_t ADCMuxP; /**< ADC Positive input channel selection. select from @ref ADCMUXP */ + uint32_t ADCMuxN; /**< ADC negative input channel selection. select from @ref ADCMUXN */ + uint32_t ADCPga; /**< ADC PGA settings, select from @ref ADCPGA */ +}ADCBaseCfg_Type; + +/** + * Structure for ADC filter settings. +*/ +typedef struct +{ + uint32_t ADCSinc3Osr; + uint32_t ADCSinc2Osr; + uint32_t ADCAvgNum; /**< Average filter is enabled when DFT source is @ref DFTSRC_AVG in function @ref AD5940_DFTCfgS. This average filter is only used by DFT engine. */ + uint32_t ADCRate; /**< ADC Core sample rate */ + BoolFlag BpNotch; /**< Bypass Notch filter in SINC2+Notch block, so only SINC2 is used. ADCFILTERCON.BIT4 */ + BoolFlag BpSinc3; /**< Bypass SINC3 Module */ + BoolFlag Sinc3ClkEnable; /**< Enable SINC3 clock */ + BoolFlag Sinc2NotchClkEnable; /**< Enable SINC2+Notch clock */ + BoolFlag Sinc2NotchEnable; /**< Enable SINC2+Notch block */ + BoolFlag DFTClkEnable; /**< Enable DFT clock */ + BoolFlag WGClkEnable; /**< Enable Waveform Generator clock */ +}ADCFilterCfg_Type; +/** @} */ + +/** + * DFT Configuration structure. +*/ +typedef struct +{ + uint32_t DftNum; /**< DFT number */ + uint32_t DftSrc; /**< DFT Source */ + BoolFlag HanWinEn; /**< Enable Hanning window */ +}DFTCfg_Type; + +/** + * ADC digital comparator +*/ +typedef struct +{ + uint16_t ADCMin; /**< The ADC code minimum limit value */ + uint16_t ADCMinHys; + uint16_t ADCMax; /**< The ADC code maximum limit value */ + uint16_t ADCMaxHys; +}ADCDigComp_Type; + +/** + * Statistic function +*/ +typedef struct +{ + uint32_t StatDev; /**< Statistic standard deviation configure */ + uint32_t StatSample; /**< Sample size */ + BoolFlag StatEnable; /**< Set true to enable statistic block */ +}StatCfg_Type; + +/** + * Switch matrix configure */ +typedef struct +{ + uint32_t Dswitch; /**< D switch settings. Select from @ref SWD_Const*/ + uint32_t Pswitch; /**< P switch settings. Select from @ref SWP_Const */ + uint32_t Nswitch; /**< N switch settings. Select from @ref SWN_Const */ + uint32_t Tswitch; /**< T switch settings. Select from @ref SWT_Const */ +}SWMatrixCfg_Type; + +/** HSTIA Configure */ +typedef struct +{ + uint32_t HstiaBias; /**< When select Vzero as bias, the related switch(VZERO2HSTIA) at LPDAC should be closed */ + uint32_t HstiaRtiaSel; /**< RTIA selection @ref HSTIARTIA_Const */ + uint32_t ExtRtia; /**< Value of external RTIA*/ + uint32_t HstiaCtia; /**< Set internal CTIA value from 1 to 32 pF */ + BoolFlag DiodeClose; /**< Close the switch for internal back to back diode */ + uint32_t HstiaDeRtia; /**< DE0 node RTIA selection @ref HSTIADERTIA_Const */ + uint32_t HstiaDeRload; /**< DE0 node Rload selection @ref HSTIADERLOAD_Const */ + uint32_t HstiaDe1Rtia; /**< (ADuCM355 only, ignored on AD594x)DE1 node RTIA selection @ref HSTIADERTIA_Const */ + uint32_t HstiaDe1Rload; /**< (ADuCM355 only)DE1 node Rload selection @ref HSTIADERLOAD_Const */ +}HSTIACfg_Type; + +/** HSDAC Configure */ +typedef struct +{ + uint32_t ExcitBufGain; /**< Select from EXCITBUFGAIN_2, EXCITBUFGAIN_0P25 */ + uint32_t HsDacGain; /**< Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + uint32_t HsDacUpdateRate; /**< Divider for DAC update. Available range is 7~255. */ +}HSDACCfg_Type; + +/** LPDAC Configure + * @note The LPDAC structure: + * @code + * Switch to select DAC output to Vzero and Vbias nodes. Vzero and Vbias can select from DAC6BIT and DAC12BIT output freely. + * LPDAC >DAC6BIT ---- Vzero LPDACVZERO_12BIT + * \--- Vbias LPDACVBIAS_6BIT + * >DAC12BIT---- Vzero LPDACVZERO_6BIT + * \--- Vbias LPDACVBIAS_12BIT + * Vzero/Vbias switch, controlled by @ref LPDACCfg_Type LpDacSW + * Vzero ------PIN + * \-----LPTIA LPDACSW_VZERO2LPTIA. LPTIA positive input + * \----HSTIA LPDACSW_VZERO2LPAMP. HSTIA positive input. Note, there is a MUX on HSTIA positive input pin to select the bias voltage between Vzero and 1.1V fixed internal reference. + * Vbias ------PIN LPDACSW_VBIAS2PIN + * \-----LPAMP LPDACSW_VBIAS2LPAMP positive input. The potential state amplifier input, or called LPAMP or PA(potential amplifier). + * @endcode +*/ +typedef struct +{ + uint32_t LpdacSel; /**< Selectr from LPDAC0 or LPDAC1. LPDAC1 is only available on ADuCM355. */ + uint32_t LpDacSrc; /**< LPDACSRC_MMR or LPDACSRC_WG. Note: HSDAC is always connects to WG. Disable HSDAC if there is need. */ + uint32_t LpDacVzeroMux; /**< Select which DAC output connects to Vzero. 6Bit or 12Bit DAC */ + uint32_t LpDacVbiasMux; /**< Select which DAC output connects to Vbias */ + uint32_t LpDacSW; /**< LPDAC switch set. Only available from Si2 */ + uint32_t LpDacRef; /**< Reference selection. Either internal 2.5V LPRef or AVDD. select from @ref LPDACREF_Const*/ + BoolFlag DataRst; /**< Keep Reset register REG_AFE_LPDACDAT0DATA */ + BoolFlag PowerEn; /**< Power up REG_AFE_LPDACDAT0 */ + uint16_t DacData12Bit; /**< Data for 12bit DAC */ + uint16_t DacData6Bit; /**< Data for 6bit DAC */ +}LPDACCfg_Type; + +/** + * Low power amplifiers(PA and TIA) +*/ +typedef struct +{ + uint32_t LpAmpSel; /**< Select from LPAMP0 and LPAMP1. LPAMP1 is only available on ADuCM355. */ + uint32_t LpTiaRf; /**< The one order RC filter resistor selection. Select from @ref LPTIARF_Const */ + uint32_t LpTiaRload; /**< The Rload resistor right in front of LPTIA negative input terminal. Select from @ref LPTIARLOAD_Const*/ + uint32_t LpTiaRtia; /**< LPTIA RTIA resistor selection. Set it to open(@ref LPTIARTIA_Const) when use external resistor. */ + uint32_t LpAmpPwrMod; /**< Power mode for LP PA and LPTIA */ + uint32_t LpTiaSW; /**< Set of switches, using macro LPTIASW() to close switch */ + BoolFlag LpPaPwrEn; /**< Enable(bTRUE) or disable(bFALSE) power of PA(potential amplifier) */ + BoolFlag LpTiaPwrEn; /**< Enable(bTRUE) or Disable(bFALSE) power of LPTIA amplifier */ +}LPAmpCfg_Type; + +/** + * @brief Trapezoid Generator parameters + * The definition of the Trapezoid waveform is shown below. Note the Delay and Slope are all in clock unit. + * @code + * + * DCLevel2 _________ + * / \ + * / \ + * DCLevel1 _____/ \______ + * | | | | | + * Delay1|S1|Delay2 |S2| Delay1 repeat... + * Where S1 is slope1 and S2 is slop2 + * @endcode + * The DAC update rate from Trapezoid generator is SystemClock/50. The default SystemClock + * is internal HFOSC 16MHz. So the update rate is 320kHz. + * The time parameter specifies in clock number. + * For example, if Delay1 is set to 10, S1 is set 20, the time for Delay1 period is 10/320kHz = 31.25us, + * and time for S1 period is 20/320kHz = 62.5us. +*/ +typedef struct +{ + uint32_t WGTrapzDCLevel1; /**< Trapezoid generator DC level1, this value is written directly to corresponding register */ + uint32_t WGTrapzDCLevel2; /**< DC level2, similar to DCLevel1 */ + uint32_t WGTrapzDelay1; /**< Trapezoid generator delay 1 */ + uint32_t WGTrapzDelay2; /**< Trapezoid generator delay 2 */ + uint32_t WGTrapzSlope1; /**< Trapezoid generator Slope 1 */ + uint32_t WGTrapzSlope2; /**< Trapezoid generator Slope 2 */ +}WGTrapzCfg_Type; + +/** + * Sin wave generator parameters +*/ +typedef struct +{ + uint32_t SinFreqWord; /**< Frequency word */ + uint32_t SinAmplitudeWord; /**< Amplitude word, range is 0 to 2047. Amplitude range is 0 to 800mV */ + uint32_t SinOffsetWord; /**< Offset word, range is -2048 to 2047. Offset voltage range is -800 to +800mV */ + uint32_t SinPhaseWord; /**< the start phase of sine wave. Use to tune start phase of signal. */ +}WGSinCfg_Type; + +/** + * Waveform generator configuration +*/ +typedef struct +{ + uint32_t WgType; /**< Select from WGTYPE_MMR, WGTYPE_SIN, WGTYPE_TRAPZ. HSDAC is always connected to WG. */ + BoolFlag GainCalEn; /**< Enable Gain calibration */ + BoolFlag OffsetCalEn; /**< Enable offset calibration */ + WGTrapzCfg_Type TrapzCfg; /**< Configure Trapezoid generator */ + WGSinCfg_Type SinCfg; /**< Configure Sine wave generator */ + uint32_t WgCode; /**< The 12bit data WG will move to DAC data register. */ +}WGCfg_Type; + +/** + * High speed loop configuration + * */ +typedef struct +{ + SWMatrixCfg_Type SWMatCfg; /**< switch matrix configuration. */ + HSDACCfg_Type HsDacCfg; /**< HSDAC configuration. */ + WGCfg_Type WgCfg; /**< Waveform generator configuration. */ + HSTIACfg_Type HsTiaCfg; /**< HSTIA configuration. */ +}HSLoopCfg_Type; + +/** + * Low power loop Configure + * */ +typedef struct +{ + LPDACCfg_Type LpDacCfg; /**< LPDAC configuration. @note Must select LPDAC0 or LPDAC1 in structure. */ + LPAmpCfg_Type LpAmpCfg; /**< LPAMP(LPTIA and PA) configuration. @note Must select LPAMP0 or LPAMP1 in structure. */ +}LPLoopCfg_Type; + +/** + * DSP Configure + * */ +typedef struct +{ + ADCBaseCfg_Type ADCBaseCfg; /**< ADC base configuration */ + ADCFilterCfg_Type ADCFilterCfg; /**< ADC filter configuration include SINC3/SINC2/Notch/Average(for DFT only) */ + ADCDigComp_Type ADCDigCompCfg; /**< ADC digital comparator */ + DFTCfg_Type DftCfg; /**< DFT configuration include data source, DFT number and Hanning Window */ + StatCfg_Type StatCfg; /**< Statistic block */ +}DSPCfg_Type; + +/** + * GPIO Configure + * */ +typedef struct +{ + uint32_t FuncSet; /**< AGP0 to AGP7 function sets */ + uint32_t OutputEnSet; /**< AGPIO_Pin0|AGPIO_Pin1|...|AGPIO_Pin7, Enable output of selected pins, disable other pins */ + uint32_t InputEnSet; /**< Enable input of selected pins, disable other pins */ + uint32_t PullEnSet; /**< Enable pull up or down on selected pin. disable other pins */ + uint32_t OutVal; /**< Value for GPIOOUT register */ +}AGPIOCfg_Type; + +/** + * FIFO configure +*/ +typedef struct +{ + BoolFlag FIFOEn; /**< Enable DATAFIFO. Disable FIFO will reset FIFO */ + uint32_t FIFOMode; /**< Stream mode or standard FIFO mode */ + uint32_t FIFOSize; /**< How to allocate the internal 6kB SRAM. Data FIFO and sequencer share all 6kB SRAM */ + uint32_t FIFOSrc; /**< Select which data source will be stored to FIFO */ + uint32_t FIFOThresh; /**< FIFO threshold value, 0 to 1023. Threshold can be used to generate interrupt so MCU can read back data before FIFO is full */ +}FIFOCfg_Type; + +/** + * Sequencer configure +*/ +typedef struct +{ + uint32_t SeqMemSize; /**< Sequencer memory size. SRAM is used by both FIFO and Sequencer. Make sure the total SRAM used is less than 6kB. */ + BoolFlag SeqEnable; /**< Enable sequencer. Only with valid trigger, sequencer can run */ + BoolFlag SeqBreakEn; /**< Do not use it */ + BoolFlag SeqIgnoreEn; /**< Do not use it */ + BoolFlag SeqCntCRCClr; /**< Clear sequencer count and CRC */ + uint32_t SeqWrTimer; /**< Set wait how much clocks after every commands executed */ +}SEQCfg_Type; + +/** + * Sequence info structure +*/ +typedef struct +{ + uint32_t SeqId; /**< The Sequence ID @ref SEQID_Const */ + uint32_t SeqRamAddr; /**< The start address that in AF5940 SRAM */ + uint32_t SeqLen; /**< Sequence length */ + BoolFlag WriteSRAM; /**< Write command to SRAM or not. */ + const uint32_t *pSeqCmd; /**< Pointer to the sequencer commands that stored in MCU */ +}SEQInfo_Type; + +typedef struct +{ + uint32_t PinSel; /**< Select which pin are going to be configured. @ref AGPIOPIN_Const */ + uint32_t SeqPinTrigMode; /**< The pin detect mode. Select from @ref SEQPINTRIGMODE_Const */ + BoolFlag bEnable; /**< Allow detected pin action to trigger corresponding sequence. */ +}SeqGpioTrig_Cfg; + +/** + * Wakeup Timer Configure + * */ +typedef struct +{ + uint32_t WuptEndSeq; /**< end sequence selection @ref WUPTENDSEQ_Const. Wupt will go back to slot A after this one is executed. */ + uint32_t WuptOrder[8]; /**< The 8 slots for WakeupTimer. Place @ref SEQID_Const to this array. */ + uint32_t SeqxSleepTime[4]; /**< Time before put AFE to sleep. 0 to 0x000f_ffff. We normally don't use this feature and it's disabled in @ref AD5940_Initialize */ + uint32_t SeqxWakeupTime[4]; /**< Time before Wakeup AFE. */ + BoolFlag WuptEn; /**< Timer enable. Once enabled, it starts to run. */ +}WUPTCfg_Type; + +/** + * Clock configure +*/ +typedef struct +{ + uint32_t SysClkSrc; /**< System clock source @ref SYSCLKSRC_Const */ + uint32_t ADCCLkSrc; /**< ADC clock source @ref ADCCLKSRC_Const */ + uint32_t SysClkDiv; /**< System clock divider. Use this to ensure System clock < 16MHz. */ + uint32_t ADCClkDiv; /**< ADC control clock divider. ADC core clock is @ADCCLkSrc, but control clock should be <16MHz. */ + BoolFlag HFOSCEn; /**< Enable internal 16MHz/32MHz HFOSC */ + BoolFlag HfOSC32MHzMode; /**< Enable internal HFOSC to output 32MHz */ + BoolFlag LFOSCEn; /**< Enable internal 32kHZ OSC */ + BoolFlag HFXTALEn; /**< Enable XTAL driver */ +}CLKCfg_Type; + +/** + * HSTIA internal RTIA calibration structure + * @note ADC filter settings and DFT should be configured properly based on signal frequency. +*/ +typedef struct +{ + float fFreq; /**< Calibration frequency */ + float fRcal; /**< Rcal resistor value in Ohm*/ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + + HSTIACfg_Type HsTiaCfg; /**< HSTIA configuration */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + DFTCfg_Type DftCfg; /**< DFT configuration. */ + uint32_t bPolarResult; /**< bTRUE-Polar coordinate:Return results in Magnitude and Phase. bFALSE-Cartesian coordinate: Return results in Real part and Imaginary Part */ +}HSRTIACal_Type; + +/** + * LPTIA internal RTIA calibration structure +*/ +typedef struct +{ + float fFreq; /**< Calibration frequency. Set it to 0.0 for DC calibration */ + float fRcal; /**< Rcal resistor value in Ohm*/ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + + uint32_t LpAmpSel; /**< Select from LPAMP0 and LPAMP1. LPAMP1 is only available on ADuCM355. */ + BoolFlag bWithCtia; /**< Connect external CTIA or not. */ + uint32_t LpTiaRtia; /**< LPTIA RTIA selection. */ + uint32_t LpAmpPwrMod; /**< Amplifiers power mode setting */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + DFTCfg_Type DftCfg; /**< DFT configuration */ + uint32_t bPolarResult; /**< bTRUE-Polar coordinate:Return results in Magnitude and Phase. bFALSE-Cartesian coordinate: Return results in Real part and Imaginary Part */ +}LPRTIACal_Type; + +/** + * HSDAC calibration structure. +*/ +typedef struct +{ + float fRcal; /**< Rcal resistor value in Ohm*/ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + + uint32_t AfePwrMode; /**< Calibrate DAC in High power mode */ + uint32_t ExcitBufGain; /**< Select from EXCITBUFGAIN_2, EXCITBUFGAIN_0P25 */ + uint32_t HsDacGain; /**< Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ +}HSDACCal_Type; + +/** + * LPDAC calibration structure. +*/ +typedef struct +{ + uint32_t LpdacSel; /**< Select from LPDAC0 and LPDAC1. LPDAC1 is ADuCM355 only. */ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + float ADCRefVolt; /**< ADC reference voltage. Default is 1.82V*/ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC2 OSR settings. */ + int32_t SettleTime10us; /**< Wait how much time after TIA is enabled? */ + int32_t TimeOut10us; /**< ADC converts signal need time. Specify the maximum time allowed. Timeout in 10us. negative number means wait no time. */ +}LPDACCal_Type; + +/** + * LPDAC parameters: LPDAC code to voltage transfer function. + * Voltage(mV) = kC2V_DACxB * Code + bC2V_DACxB; + * where x is 12 or 6 represent 12Bit DAC and 6Bit DAC. C2V means code to voltage. + * Code is the data register value for LPDAC. The equation gives real output voltage of LPDAC. + * Similarly, Code(LSB) = kV2C_DACxB * Voltage(mV) + bV2C_DACxB; + * + * Apparently, kV2C_DACxB = 1/kC2V_DACxB; + * bV2C_DACxB = -bC2V_DACxB/kC2V_DACxB; +*/ +typedef struct +{ + /* Code to voltage equation parameters */ + float kC2V_DAC12B; /**< the k factor of code to voltage(in mV) transfer function */ + float bC2V_DAC12B; /**< the offset of code to voltage transfer function. It's the voltage in mV when code is zero. */ + float kC2V_DAC6B; /**< the k factor for LPDAC 6 bit output. */ + float bC2V_DAC6B; /**< the offset for LPDAC 6 bit output. */ + /* Code to voltage equation parameters */ + float kV2C_DAC12B; /**< the k factor for converting voltage to code for LPDAC 12bit output. */ + float bV2C_DAC12B; /**< the offset for converting voltage to code for LPDAC 12bit output. */ + float kV2C_DAC6B; /**< the k factor for converting voltage to code for LPDAC 6bit output. */ + float bV2C_DAC6B; /**< the offset for converting voltage to code for LPDAC 6bit output. */ +}LPDACPara_Type; + +/** + * LFOSC frequency measure structure +*/ +typedef struct +{ + uint32_t CalSeqAddr; /**< Sequence start address */ + float CalDuration; /**< Time can be used for calibration in unit of ms. Recommend to use tens of millisecond like 10ms */ + float SystemClkFreq; /**< System clock frequency. */ +}LFOSCMeasure_Type; + +/** + * ADC PGA calibration type +*/ +typedef struct +{ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + float VRef1p82; /**< The real voltage of 1.82 reference. Unit is volt. */ + float VRef1p11; /**< The real voltage of 1.1 reference. Unit is volt. */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCPga; /**< Which PGA gain we are going to calibrate? */ + uint32_t PGACalType; /**< Calibrate gain of offset or gain+offset? */ + int32_t TimeOut10us; /**< Timeout in 10us. -1 means no time-out*/ +}ADCPGACal_Type; + +/** + * LPTIA Offset calibration type +*/ +typedef struct +{ + uint32_t LpAmpSel; /**< Select from LPAMP0 and LPAMP1. LPAMP1 is only available on ADuCM355. */ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCPga; /**< PGA Gain selection */ + uint32_t DacData12Bit; /**< 12Bit DAC data */ + uint32_t DacData6Bit; /**< 6Bit DAC data */ + uint32_t LpDacVzeroMux; /**< Vzero is used as LPTIA bias voltage, select 12Bit/6Bit DAC */ + uint32_t LpAmpPwrMod; /**< LP amplifiers power mode, select from LPAMPPWR_NORM, LPAMPPWR_BOOSTn*/ + uint32_t LpTiaSW; /**< Switch configuration for LPTIA. Normally for SW(5) and SW(9).*/ + uint32_t LpTiaRtia; /**< LPTIA RTIA resistor selection. */ + int32_t SettleTime10us; /**< Wait how much time after TIA is enabled? */ + int32_t TimeOut10us; /**< ADC converts signal need time. Specify the maximum time allowed. Timeout in 10us. negative number means wait no time. */ +}LPTIAOffsetCal_Type; + +/** + * Structure for calculating how much system clocks needed for specified number of data +*/ +typedef struct +{ + uint32_t DataType; /**< The final data output selection. @ref DATATYPE_Const */ + uint32_t DataCount; /**< How many data you want. */ + uint32_t ADCSinc3Osr; /**< ADC SINC3 filter OSR setting */ + uint32_t ADCSinc2Osr; /**< ADC SINC2 filter OSR setting */ + uint32_t ADCAvgNum; /**< Average number for DFT engine. Only used when data type is DATATYPE_DFT and DftSrc is DFTSRC_AVG */ + uint32_t DftSrc; /**< The DFT source. Only used when data type is DATATYPE_DFT */ + uint8_t ADCRate; /**< ADCRate @ref ADCRATE_Const. Only used when data type is DATATYPE_NOTCH */ + BoolFlag BpNotch; /**< Bypass notch filter or not. Only used when data type is DATATYPE_DFT and DftSrc is DFTSRC_SINC2NOTCH */ + float RatioSys2AdcClk; /**< Ratio of system clock to ADC clock frequency */ +}ClksCalInfo_Type; + +/** + * Software controlled Sweep Function + * */ +typedef struct +{ + BoolFlag SweepEn; /**< Software can automatically sweep frequency from following parameters. Set value to 1 to enable it. */ + float SweepStart; /**< Sweep start frequency. Software will go back to the start frequency when it reaches SWEEP_STOP */ + float SweepStop; /**< Sweep end frequency. */ + uint32_t SweepPoints; /**< How many points from START to STOP frequency */ + BoolFlag SweepLog; /**< The step is linear or logarithmic. 0: Linear, 1: Logarithmic*/ + uint32_t SweepIndex; /**< Current position of sweep */ +}SoftSweepCfg_Type; + +/** + * Impedance result in Polar coordinate +*/ +typedef struct +{ + float Magnitude; /**< The magnitude in polar coordinate */ + float Phase; /**< The phase in polar coordinate */ +}fImpPol_Type; //Polar + +/** + * Impedance result in Cartesian coordinate +*/ +typedef struct +{ + float Real; /**< The real part in Cartesian coordinate */ + float Image; /**< The imaginary in Cartesian coordinate */ +}fImpCar_Type; //Cartesian + +/** + * int32_t type Impedance result in Cartesian coordinate +*/ +typedef struct +{ + int32_t Real; /**< The real part in Cartesian coordinate */ + int32_t Image; /**< The real imaginary in Cartesian coordinate */ +}iImpCar_Type; + +/** + * FreqParams_Type - Structure to store optimum filter settings +*/ +typedef struct +{ + BoolFlag HighPwrMode; + uint32_t DftNum; + uint32_t DftSrc; + uint32_t ADCSinc3Osr; + uint32_t ADCSinc2Osr; + uint32_t NumClks; +}FreqParams_Type; + +/** + * @} TypeDefinitions +*/ + +/** + * @defgroup Exported_Functions + * @{ +*/ +/* 1. Basic SPI functions */ +void AD5940_WriteReg(uint16_t RegAddr, uint32_t RegData); +uint32_t AD5940_ReadReg(uint16_t RegAddr); +void AD5940_FIFORd(uint32_t *pBuffer,uint32_t uiReadCount); + +/* 2. AD5940 Top Control functions */ +void AD5940_Initialize(void); /* Call this function firstly once AD5940 power on or come from soft reset */ +void AD5940_AFECtrlS(uint32_t AfeCtrlSet, BoolFlag State); +AD5940Err AD5940_LPModeCtrlS(uint32_t EnSet); +void AD5940_AFEPwrBW(uint32_t AfePwr, uint32_t AfeBw); /* AFE power mode and system bandwidth control */ +void AD5940_REFCfgS(AFERefCfg_Type *pBufCfg); + +/* 3. High_Speed_Loop Functions */ +void AD5940_HSLoopCfgS(HSLoopCfg_Type *pHsLoopCfg); +void AD5940_SWMatrixCfgS(SWMatrixCfg_Type *pSwMatrix); +void AD5940_HSDacCfgS(HSDACCfg_Type *pHsDacCfg); +AD5940Err AD5940_HSTIACfgS(HSTIACfg_Type *pHsTiaCfg); +void AD5940_HSRTIACfgS(uint32_t HSTIARtia); +void __AD5940_SetDExRTIA(uint32_t DExPin, uint32_t DeRtia, uint32_t DeRload); + +/* 4. Low_Power_Loop Functions*/ +void AD5940_LPLoopCfgS(LPLoopCfg_Type *pLpLoopCfg); +void AD5940_LPDACCfgS(LPDACCfg_Type *pLpDacCfg); +//void AD5940_LPDACWriteS(uint16_t Data12Bit, uint8_t Data6Bit); +void AD5940_LPDAC0WriteS(uint16_t Data12Bit, uint8_t Data6Bit); +void AD5940_LPDAC1WriteS(uint16_t Data12Bit, uint8_t Data6Bit); +void AD5940_LPAMPCfgS(LPAmpCfg_Type *pLpAmpCfg); + +/* 5. DSP_Block_Functions */ +void AD5940_DSPCfgS(DSPCfg_Type *pDSPCfg); +uint32_t AD5940_ReadAfeResult(uint32_t AfeResultSel); +/* 5.1 ADC Block */ +void AD5940_ADCBaseCfgS(ADCBaseCfg_Type *pADCInit); +void AD5940_ADCFilterCfgS(ADCFilterCfg_Type *pFiltCfg); +void AD5940_ADCPowerCtrlS(BoolFlag State); +void AD5940_ADCConvtCtrlS(BoolFlag State); +void AD5940_ADCMuxCfgS(uint32_t ADCMuxP, uint32_t ADCMuxN); +void AD5940_ADCDigCompCfgS(ADCDigComp_Type *pCompCfg); +void AD5940_StatisticCfgS(StatCfg_Type *pStatCfg); +void AD5940_ADCRepeatCfgS(uint32_t Number); +void AD5940_DFTCfgS(DFTCfg_Type *pDftCfg); +/* 5.2 Waveform Generator Block */ +void AD5940_WGCfgS(WGCfg_Type *pWGInit); +AD5940Err AD5940_WGDACCodeS(uint32_t code); /* Directly write DAC Code */ +void AD5940_WGFreqCtrlS(float SinFreqHz, float WGClock); +uint32_t AD5940_WGFreqWordCal(float SinFreqHz, float WGClock); +//uint32_t AD5940_WGAmpWordCal(float Amp, BoolFlag DacGain, BoolFlag ExcitGain); + +/* 6. Sequencer_FIFO */ +void AD5940_FIFOCfg(FIFOCfg_Type *pFifoCfg); +AD5940Err AD5940_FIFOGetCfg(FIFOCfg_Type *pFifoCfg); /* Read back current configuration */ +void AD5940_FIFOCtrlS(uint32_t FifoSrc, BoolFlag FifoEn); /* Configure FIFO data source. And disable/enable it.*/ +void AD5940_FIFOThrshSet(uint32_t FIFOThresh); +uint32_t AD5940_FIFOGetCnt(void); /* Get current FIFO count */ +void AD5940_SEQCfg(SEQCfg_Type *pSeqCfg); +AD5940Err AD5940_SEQGetCfg(SEQCfg_Type *pSeqCfg); /* Read back current configuration */ +void AD5940_SEQCtrlS(BoolFlag SeqEn); +void AD5940_SEQHaltS(void); +void AD5940_SEQMmrTrig(uint32_t SeqId); /* Manually trigger sequence */ +void AD5940_SEQCmdWrite(uint32_t StartAddr, const uint32_t *pCommand, uint32_t CmdCnt); +void AD5940_SEQInfoCfg(SEQInfo_Type *pSeq); +AD5940Err AD5940_SEQInfoGet(uint32_t SeqId, SEQInfo_Type *pSeqInfo); +void AD5940_SEQGpioCtrlS(uint32_t GpioSet); /* Sequencer can control GPIO0~7 if the GPIO function is set to SYNC */ +uint32_t AD5940_SEQTimeOutRd(void); /* Read back current sequence time out value */ +AD5940Err AD5940_SEQGpioTrigCfg(SeqGpioTrig_Cfg *pSeqGpioTrigCfg); +void AD5940_WUPTCfg(WUPTCfg_Type *pWuptCfg); +void AD5940_WUPTCtrl(BoolFlag Enable); /* Enable or disable Wakeup timer */ +AD5940Err AD5940_WUPTTime(uint32_t SeqId, uint32_t SleepTime, uint32_t WakeupTime); + +/* 7. MISC_Block */ +/* 7.1 Clock system */ +void AD5940_CLKCfg(CLKCfg_Type *pClkCfg); +void AD5940_HFOSC32MHzCtrl(BoolFlag Mode32MHz); +void AD5940_HPModeEn(BoolFlag Enable); /* Switch system clocks to high power mode for EIS >80kHz)*/ +/* 7.2 AFE Interrupt */ +void AD5940_INTCCfg(uint32_t AfeIntcSel, uint32_t AFEIntSrc, BoolFlag State); +uint32_t AD5940_INTCGetCfg(uint32_t AfeIntcSel); +void AD5940_INTCClrFlag(uint32_t AfeIntSrcSel); +BoolFlag AD5940_INTCTestFlag(uint32_t AfeIntcSel, uint32_t AfeIntSrcSel); /* Check if selected interrupt happened */ +uint32_t AD5940_INTCGetFlag(uint32_t AfeIntcSel); /* Get current INTC interrupt flag */ +/* 7.3 GPIO */ +void AD5940_AGPIOCfg(AGPIOCfg_Type *pAgpioCfg); +void AD5940_AGPIOFuncCfg(uint32_t uiCfgSet); +void AD5940_AGPIOOen(uint32_t uiPinSet); +void AD5940_AGPIOIen(uint32_t uiPinSet); +uint32_t AD5940_AGPIOIn(void); +void AD5940_AGPIOPen(uint32_t uiPinSet); +void AD5940_AGPIOSet(uint32_t uiPinSet); +void AD5940_AGPIOClr(uint32_t uiPinSet); +void AD5940_AGPIOToggle(uint32_t uiPinSet); + +/* 7.4 LPMODE */ +AD5940Err AD5940_LPModeEnS(BoolFlag LPModeEn); /* Enable LP mode or disable it. */ +void AD5940_LPModeClkS(uint32_t LPModeClk); +void AD5940_ADCRepeatCfg(uint32_t Number); +/* 7.5 Power */ +void AD5940_SleepKeyCtrlS(uint32_t SlpKey); /* enter the correct key to allow AFE to enter sleep mode */ +void AD5940_EnterSleepS(void); /* Put AFE to hibernate/sleep mode and keep LP loop as the default settings. */ +void AD5940_ShutDownS(void); /* Unlock the key, turn off LP loop and enter sleep/hibernate mode */ +uint32_t AD5940_WakeUp(int32_t TryCount); /* Try to wakeup AFE by read register */ +uint32_t AD5940_GetADIID(void); /* Read ADIID */ +uint32_t AD5940_GetChipID(void); /* Read Chip ID */ +AD5940Err AD5940_SoftRst(void); +void AD5940_HWReset(void); /* Do hardware reset to AD5940 using RESET pin */ +/* Calibration functions */ +/* 8. Calibration */ +AD5940Err AD5940_ADCPGACal(ADCPGACal_Type *ADCPGACal); +AD5940Err AD5940_LPDACCal(LPDACCal_Type *pCalCfg, LPDACPara_Type *pResult); +AD5940Err AD5940_LPTIAOffsetCal(LPTIAOffsetCal_Type *pLPTIAOffsetCal); +AD5940Err AD5940_HSRtiaCal(HSRTIACal_Type *pCalCfg, void *pResult); +AD5940Err AD5940_HSDACCal(HSDACCal_Type *pCalCfg); +AD5940Err AD5940_LPRtiaCal(LPRTIACal_Type *pCalCfg, void *pResult); +AD5940Err AD5940_LFOSCMeasure(LFOSCMeasure_Type *pCfg, float *pFreq); +//void AD5940_LFOSCTrim(uint32_t TrimValue); /* TrimValue: 0 to 15 */ +//void AD5940_HFOSC16MHzTrim(uint32_t TrimValue); +//void AD5940_HFOSC32MHzTrim(uint32_t TrimValue); + +/* 9. Pure software functions. Functions with no register access. These functions are helpers */ + /* Sequence Generator */ +void AD5940_SEQGenInit(uint32_t *pBuffer, uint32_t BufferSize);/* Initialize sequence generator workspace */ +void AD5940_SEQGenCtrl(BoolFlag bFlag); /* Enable or disable sequence generator */ +void AD5940_SEQGenInsert(uint32_t CmdWord); /* Manually insert a sequence command */ +AD5940Err AD5940_SEQGenFetchSeq(const uint32_t **ppSeqCmd, uint32_t *pSeqCount); /* Fetch generated sequence and start a new sequence */ +void AD5940_ClksCalculate(ClksCalInfo_Type *pFilterInfo, uint32_t *pClocks); +uint32_t AD5940_SEQCycleTime(void); +void AD5940_SweepNext(SoftSweepCfg_Type *pSweepCfg, float *pNextFreq); +void AD5940_StructInit(void *pStruct, uint32_t StructSize); +float AD5940_ADCCode2Volt(uint32_t code, uint32_t ADCPga, float VRef1p82); /* Calculate ADC code to voltage */ +BoolFlag AD5940_Notch50HzAvailable(ADCFilterCfg_Type *pFilterInfo, uint8_t *dl); +BoolFlag AD5940_Notch60HzAvailable(ADCFilterCfg_Type *pFilterInfo, uint8_t *dl); +fImpCar_Type AD5940_ComplexDivFloat(fImpCar_Type *a, fImpCar_Type *b); +fImpCar_Type AD5940_ComplexMulFloat(fImpCar_Type *a, fImpCar_Type *b); +fImpCar_Type AD5940_ComplexAddFloat(fImpCar_Type *a, fImpCar_Type *b); +fImpCar_Type AD5940_ComplexSubFloat(fImpCar_Type *a, fImpCar_Type *b); + +fImpCar_Type AD5940_ComplexDivInt(iImpCar_Type *a, iImpCar_Type *b); +fImpCar_Type AD5940_ComplexMulInt(iImpCar_Type *a, iImpCar_Type *b); +float AD5940_ComplexMag(fImpCar_Type *a); +float AD5940_ComplexPhase(fImpCar_Type *a); +FreqParams_Type AD5940_GetFreqParameters(float freq); +/** + * @} Exported_Functions +*/ + +/** + * @defgroup Library_Interface + * The functions user should provide for specific MCU platform + * @{ +*/ +void AD5940_CsClr(void); +void AD5940_CsSet(void); +void AD5940_RstClr(void); +void AD5940_RstSet(void); +void AD5940_Delay10us(uint32_t time); +/* (Not used for now.)AD5940 has 8 GPIOs, some of them are connected to MCU. MCU can set or read the status of these pins. */ +void AD5940_MCUGpioWrite(uint32_t data); /* */ +uint32_t AD5940_MCUGpioRead(uint32_t); +void AD5940_MCUGpioCtrl(uint32_t, BoolFlag); +void AD5940_ReadWriteNBytes(unsigned char *pSendBuffer,unsigned char *pRecvBuff,unsigned long length); +/* Below functions are frequently used in example code but not necessary for library */ +uint32_t AD5940_GetMCUIntFlag(void); +uint32_t AD5940_ClrMCUIntFlag(void); +uint32_t AD5940_MCUResourceInit(void *pCfg); +/** + * @} Library_Interface +*/ + + +/** + * @} AD5940_Library + */ + +#endif + + +#ifdef __cplusplus +} +#endif diff --git a/examples/AD5940_ADC/AD5940_ADCMeanFIFO.c b/examples/AD5940_ADC/AD5940_ADCMeanFIFO.c new file mode 100644 index 0000000..ecff7bc --- /dev/null +++ b/examples/AD5940_ADC/AD5940_ADCMeanFIFO.c @@ -0,0 +1,103 @@ +/*! + ***************************************************************************** + @file: AD5940_ADCMeanFIFO.c + @author: $Author: nxu2 $ + @brief: Use FIFO to read statistic block mean result. + @version: $Revision: 766 $ + @date: $Date: 2017-08-21 14:09:35 +0100 (Mon, 21 Aug 2017) $ + ----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*****************************************************************************/ +/** @addtogroup AD5940_Standard_Examples + * @{ + @defgroup ADC_MEAN_FIFO_Example + @{ + */ + +#include "ad5940.h" +#include + +uint32_t ADCBuff[256]; +void AD5940_Main(void) +{ + ADCBaseCfg_Type adc_base; + ADCFilterCfg_Type adc_filter; + StatCfg_Type stat_cfg; + FIFOCfg_Type fifo_cfg; + + /* Use hardware reset */ + AD5940_HWReset(); + /* Firstly call this function after reset to initialize AFE registers. */ + AD5940_Initialize(); + /* Configure AFE power mode and bandwidth */ + AD5940_AFEPwrBW(AFEPWR_LP, AFEBW_250KHZ); + /* Initialize ADC basic function */ + adc_base.ADCMuxP = ADCMUXP_AVDD_2; + adc_base.ADCMuxN = ADCMUXN_VSET1P1; + adc_base.ADCPga = ADCPGA_1; + AD5940_ADCBaseCfgS(&adc_base); + + /* Initialize ADC filters ADCRawData-->SINC3-->SINC2+NOTCH-->StatisticBlock */ + adc_filter.ADCSinc3Osr = ADCSINC3OSR_4; + adc_filter.ADCSinc2Osr = ADCSINC2OSR_1333; + adc_filter.ADCAvgNum = ADCAVGNUM_2; /* Don't care about it. Average function is only used for DFT */ + adc_filter.ADCRate = ADCRATE_800KHZ; /* If ADC clock is 32MHz, then set it to ADCRATE_1P6MHZ. Default is 16MHz, use ADCRATE_800KHZ. */ + adc_filter.BpNotch = bTRUE; /* SINC2+Notch is one block, when bypass notch filter, we can get fresh data from SINC2 filter. */ + adc_filter.BpSinc3 = bFALSE; /* We use SINC3 filter. */ + adc_filter.Sinc2NotchEnable = bTRUE; /* Enable the SINC2+Notch block. You can also use function AD5940_AFECtrlS */ + AD5940_ADCFilterCfgS(&adc_filter); + + /** + * Statistic block receive data from SINC2+Notch block. Note the diagram in datasheet page 51 PrM. + * The SINC3 can be bypassed optionally. SINC2 cannot be bypassed. + * */ + stat_cfg.StatDev = STATDEV_1; /* Not used. */ + stat_cfg.StatEnable = bTRUE; + stat_cfg.StatSample = STATSAMPLE_128; /* Sample 128 points and calculate mean. */ + AD5940_StatisticCfgS(&stat_cfg); + fifo_cfg.FIFOEn = bTRUE; + fifo_cfg.FIFOMode = FIFOMODE_FIFO; + fifo_cfg.FIFOSize = FIFOSIZE_4KB; + fifo_cfg.FIFOSrc = FIFOSRC_MEAN; + fifo_cfg.FIFOThresh = 2; + AD5940_FIFOCfg(&fifo_cfg); + + /* Enable all interrupt at Interrupt Controller 1. So we can check the interrupt flag */ + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_ALLINT, bTRUE); + AD5940_INTCCfg(AFEINTC_0, AFEINTSRC_DATAFIFOTHRESH, bTRUE); /* Enable FIFO threshold interrupt. */ + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + AD5940_ClrMCUIntFlag(); /* Clear the MCU interrupt flag which will be set in ISR. */ + + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_SINC2NOTCH, bTRUE); + AD5940_AFECtrlS(AFECTRL_ADCCNV, bTRUE); + while(1) + { + uint32_t FifoCnt; + if(AD5940_GetMCUIntFlag()) + { + AD5940_ClrMCUIntFlag(); /* Clear this flag */ + if(AD5940_INTCTestFlag(AFEINTC_0, AFEINTSRC_DATAFIFOTHRESH) == bTRUE) + { + FifoCnt = AD5940_FIFOGetCnt(); + AD5940_FIFORd((uint32_t *)ADCBuff, FifoCnt); + AD5940_INTCClrFlag(AFEINTSRC_DATAFIFOTHRESH); + printf("Get %d data, ADC Code[0]:%d\n",FifoCnt, ADCBuff[0]&0xffff); + /*!!!!!NOTE!!!!!*/ + /* The mean result already removed 32768. So to calculate the voltage, assume mean result is n, use below equation. + Voltage = n/32768*Vref + */ + } + } + } +} + +/** + * @} + * @} + * */ diff --git a/examples/AD5940_ADC/AD5940_ADCNotchTest.c b/examples/AD5940_ADC/AD5940_ADCNotchTest.c new file mode 100644 index 0000000..0140dae --- /dev/null +++ b/examples/AD5940_ADC/AD5940_ADCNotchTest.c @@ -0,0 +1,205 @@ +/*! + ***************************************************************************** + @file: AD5940_ADCNotchTest.c + @author: Neo Xu + @brief: Notch filter test. + ----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*****************************************************************************/ +/** @addtogroup AD5940_Standard_Examples + * @{ + @defgroup ADC_Notch_Test_Example + @{ + */ + +#include "ad5940.h" +#include + +#ifdef ADI_DEBUG +#undef ADI_DEBUG +#endif + +void ad5940_sequencer_init(uint8_t adc_rate, uint8_t sinc3osr, uint8_t sinc2osr){ + FIFOCfg_Type fifo_cfg; + SEQCfg_Type seq_cfg; + /* Step2. Configure FIFO and Sequencer*/ + fifo_cfg.FIFOEn = bFALSE; + fifo_cfg.FIFOMode = FIFOMODE_FIFO; + fifo_cfg.FIFOSize = FIFOSIZE_4KB; /* 4kB for FIFO, The reset 2kB for sequencer */ + fifo_cfg.FIFOSrc = FIFOSRC_SINC2NOTCH; + fifo_cfg.FIFOThresh = 1; + AD5940_FIFOCfg(&fifo_cfg); /* Disable to reset FIFO. */ + fifo_cfg.FIFOEn = bTRUE; + AD5940_FIFOCfg(&fifo_cfg); /* Enable FIFO here */ + /* Configure sequencer and stop it */ + seq_cfg.SeqMemSize = SEQMEMSIZE_2KB; + seq_cfg.SeqBreakEn = bFALSE; + seq_cfg.SeqIgnoreEn = bFALSE; + seq_cfg.SeqCntCRCClr = bTRUE; + seq_cfg.SeqEnable = bFALSE; + seq_cfg.SeqWrTimer = 0; + AD5940_SEQCfg(&seq_cfg); + + uint32_t WaitClks; + uint8_t dl_60, dl_50, dl=0; + ADCFilterCfg_Type filter; + filter.ADCSinc3Osr = sinc3osr; + filter.ADCSinc2Osr = sinc2osr; + filter.ADCRate = adc_rate; + const uint32_t sinc2osr_table[] = {22,44,89,178,267,533,640,667,800,889,1067,1333,0}; + const uint32_t sinc3osr_table[] = {5,4,2,0}; + printf("SINC3:OSR%d, SINC2:OSR%d, ", sinc3osr_table[sinc3osr], sinc2osr_table[sinc2osr]); + if(AD5940_Notch50HzAvailable(&filter, &dl_50)){ + printf("NOTCH50: DL:%d, %dHz ", dl_50, (uint32_t)((adc_rate==ADCRATE_1P6MHZ?1.6e6:800000.0)/sinc3osr_table[sinc3osr]/sinc2osr_table[sinc2osr]/dl_50 + .5)); + dl += dl_50-1; + } + if(AD5940_Notch60HzAvailable(&filter, &dl_60)){ + printf("NOTCH60: DL:%d, %dHz ", dl_60, (uint32_t)((adc_rate==ADCRATE_1P6MHZ?1.6e6:800000.0)/sinc3osr_table[sinc3osr]/sinc2osr_table[sinc2osr]/dl_60 + .5)); + dl += dl_60-1; + } + ClksCalInfo_Type clks_cal; + clks_cal.DataType = DATATYPE_NOTCH; + clks_cal.ADCRate = adc_rate; + clks_cal.DataCount = 1; /* Sample one data when wakeup */ + clks_cal.ADCSinc2Osr = sinc2osr; + clks_cal.ADCSinc3Osr = sinc3osr; + clks_cal.ADCAvgNum = 0; + clks_cal.RatioSys2AdcClk = adc_rate==ADCRATE_1P6MHZ?.5:1; + AD5940_ClksCalculate(&clks_cal, &WaitClks); + + static uint32_t buff[128]; + AD5940_SEQGenInit(buff, 128); + AD5940_SEQGenCtrl(bTRUE); + + AD5940_SEQGpioCtrlS(AGPIO_Pin1); + AD5940_AFECtrlS(AFECTRL_ADCPWR, bTRUE); + AD5940_SEQGenInsert(SEQ_WAIT(16*250)); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_SINC2NOTCH, bTRUE); /* Start ADC convert */ + AD5940_SEQGenInsert(SEQ_WAIT(WaitClks)); + //wait for first data ready + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_ADCPWR|AFECTRL_SINC2NOTCH, bFALSE); /* Stop ADC convert and DFT */ + AD5940_SEQGpioCtrlS(0); + AD5940_SEQGenCtrl(bFALSE); /* Stop sequencer generator */ + + SEQInfo_Type seqinfo; + AD5940_SEQGenFetchSeq(&seqinfo.pSeqCmd, &seqinfo.SeqLen); + seqinfo.SeqId = SEQID_0; + seqinfo.SeqRamAddr = 0; + seqinfo.WriteSRAM = bTRUE; + AD5940_SEQInfoCfg(&seqinfo); + + AGPIOCfg_Type gpio_cfg; + gpio_cfg.FuncSet = GP6_SYNC|GP5_SYNC|GP2_TRIG|GP1_SYNC|GP0_INT; + gpio_cfg.InputEnSet = AGPIO_Pin2; + gpio_cfg.OutputEnSet = AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin5|AGPIO_Pin6; + gpio_cfg.OutVal = 0; + gpio_cfg.PullEnSet = AGPIO_Pin2; + AD5940_AGPIOCfg(&gpio_cfg); +} + +uint32_t ad5940_notch_test(uint8_t adc_rate, uint8_t sinc3osr, uint8_t sinc2osr){ + ADCBaseCfg_Type adc_base; + ADCFilterCfg_Type adc_filter; + + /* Use hardware reset */ + AD5940_HWReset(); + + /* Firstly call this function after reset to initialize AFE registers. */ + AD5940_Initialize(); + + CLKCfg_Type clk_cfg; + clk_cfg.ADCClkDiv = ADCCLKDIV_1; + clk_cfg.ADCCLkSrc = ADCCLKSRC_HFOSC; + clk_cfg.SysClkDiv = adc_rate==ADCRATE_1P6MHZ?SYSCLKDIV_2:SYSCLKDIV_1; + clk_cfg.SysClkSrc = SYSCLKSRC_HFOSC; + clk_cfg.HfOSC32MHzMode = adc_rate==ADCRATE_1P6MHZ?bTRUE:bFALSE; + clk_cfg.HFOSCEn = bTRUE; + clk_cfg.HFXTALEn = bFALSE; + clk_cfg.LFOSCEn = bTRUE; + AD5940_CLKCfg(&clk_cfg); + + /* Configure AFE power mode and bandwidth */ + AD5940_AFEPwrBW(AFEPWR_LP, AFEBW_250KHZ); + + /* Initialize ADC basic function */ + adc_base.ADCMuxP = ADCMUXP_VREF1P8DAC; + adc_base.ADCMuxN = ADCMUXN_VSET1P1; + adc_base.ADCPga = ADCPGA_1P5; + AD5940_ADCBaseCfgS(&adc_base); + AD5940_AFECtrlS(AFECTRL_DACREFPWR|AFECTRL_HSDACPWR, bTRUE); + /* Initialize ADC filters ADCRawData-->SINC3-->SINC2+NOTCH */ + adc_filter.ADCSinc3Osr = sinc3osr; + adc_filter.ADCSinc2Osr = sinc2osr; + adc_filter.ADCAvgNum = ADCAVGNUM_2; /* Don't care about it. Average function is only used for DFT */ + adc_filter.ADCRate = adc_rate; /* If ADC clock is 32MHz, then set it to ADCRATE_1P6MHZ. Default is 16MHz, use ADCRATE_800KHZ. */ + adc_filter.BpNotch = bFALSE; /* SINC2+Notch is one block, when bypass notch filter, we can get fresh data from SINC2 filter. */ + adc_filter.BpSinc3 = bFALSE; /* We use SINC3 filter. */ + adc_filter.Sinc2NotchEnable = bTRUE; /* Enable the SINC2+Notch block. You can also use function AD5940_AFECtrlS */ + AD5940_ADCFilterCfgS(&adc_filter); + + /* Enable all interrupt at Interrupt Controller 1. So we can check the interrupt flag */ + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_ALLINT, bTRUE); + AD5940_INTCCfg(AFEINTC_0, AFEINTSRC_DATAFIFOTHRESH, bTRUE); + + ad5940_sequencer_init(adc_rate, sinc3osr, sinc2osr); + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + AD5940_SEQCtrlS(bTRUE); + AD5940_ClrMCUIntFlag(); + AD5940_SEQMmrTrig(SEQID_0); + while(1) + { + {int32_t i = 1000000;while(i--);} + if(AD5940_GetMCUIntFlag()) + { + AD5940_ClrMCUIntFlag(); + uint32_t fifo_count = AD5940_FIFOGetCnt(); + if(fifo_count == 1){ + int32_t rd; + AD5940_FIFORd((uint32_t*)&rd, 1); + rd &= 0xffff; + float volt = AD5940_ADCCode2Volt(rd, ADCPGA_1P5, 1.82)+1.11; + volt -= 1.82; + if(volt < 0) volt = -volt; + if(volt > 0.0005){ + printf("FAILED:CODE:rd:%d\n", rd); + return 1; + } + printf("PASS\n"); + return 0; + } + else{ + printf("FAILED:%d\n", fifo_count); + return 1; + } + } + } +} + +void AD5940_Main(void) +{ + uint32_t failed = 0; + uint8_t sinc3=0, sinc2=0; + uint8_t adc_rate=0; + for(;adc_rate<=1;adc_rate++){ + sinc3=0; + for(;sinc3<=ADCSINC3OSR_2;sinc3++){ + sinc2=0; + for(;sinc2<=ADCSINC2OSR_1333;sinc2++){ + failed |= ad5940_notch_test(adc_rate, sinc3, sinc2); + } + } + } + printf("Test Done with status: %s\n",failed?"FAILED":"SUCCEED"); + while(1); +} + +/** + * @} + * @} + * */ diff --git a/examples/AD5940_ADC/AD5940_ADCPolling.c b/examples/AD5940_ADC/AD5940_ADCPolling.c new file mode 100644 index 0000000..42def98 --- /dev/null +++ b/examples/AD5940_ADC/AD5940_ADCPolling.c @@ -0,0 +1,110 @@ +/*! + ***************************************************************************** + @file: AD5940_ADCPolling.c + @author: $Author: nxu2 $ + @brief: ADC Polling mode example + @version: $Revision: 766 $ + @date: $Date: 2017-08-21 14:09:35 +0100 (Mon, 21 Aug 2017) $ + ----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*****************************************************************************/ +/** @addtogroup AD5940_Standard_Examples + * @{ + @defgroup ADC_Polling_Example + @{ + */ + +#include "ad5940.h" +#include + +#define ADCPGA_GAIN_SEL ADCPGA_1P5 +static void AD5940_PGA_Calibration(void){ + AD5940Err err; + ADCPGACal_Type pgacal; + pgacal.AdcClkFreq = 16e6; + pgacal.ADCSinc2Osr = ADCSINC2OSR_178; + pgacal.ADCSinc3Osr = ADCSINC3OSR_4; + pgacal.SysClkFreq = 16e6; + pgacal.TimeOut10us = 1000; + pgacal.VRef1p11 = 1.11f; + pgacal.VRef1p82 = 1.82f; + pgacal.PGACalType = PGACALTYPE_OFFSETGAIN; + pgacal.ADCPga = ADCPGA_GAIN_SEL; + err = AD5940_ADCPGACal(&pgacal); + if(err != AD5940ERR_OK){ + printf("AD5940 PGA calibration failed."); + } +} + +void AD5940_Main(void) +{ + ADCBaseCfg_Type adc_base; + ADCFilterCfg_Type adc_filter; + + /* Use hardware reset */ + AD5940_HWReset(); + + /* Firstly call this function after reset to initialize AFE registers. */ + AD5940_Initialize(); + + AD5940_PGA_Calibration(); + /* Configure AFE power mode and bandwidth */ + AD5940_AFEPwrBW(AFEPWR_LP, AFEBW_250KHZ); + + /* Initialize ADC basic function */ + AD5940_AFECtrlS(AFECTRL_DACREFPWR|AFECTRL_HSDACPWR, bTRUE); //We are going to measure DAC 1.82V reference. + adc_base.ADCMuxP = ADCMUXP_VREF1P8DAC; + adc_base.ADCMuxN = ADCMUXN_VSET1P1; + adc_base.ADCPga = ADCPGA_GAIN_SEL; + AD5940_ADCBaseCfgS(&adc_base); + + /* Initialize ADC filters ADCRawData-->SINC3-->SINC2+NOTCH */ + adc_filter.ADCSinc3Osr = ADCSINC3OSR_4; + adc_filter.ADCSinc2Osr = ADCSINC2OSR_1333; + adc_filter.ADCAvgNum = ADCAVGNUM_2; /* Don't care about it. Average function is only used for DFT */ + adc_filter.ADCRate = ADCRATE_800KHZ; /* If ADC clock is 32MHz, then set it to ADCRATE_1P6MHZ. Default is 16MHz, use ADCRATE_800KHZ. */ + adc_filter.BpNotch = bTRUE; /* SINC2+Notch is one block, when bypass notch filter, we can get fresh data from SINC2 filter. */ + adc_filter.BpSinc3 = bFALSE; /* We use SINC3 filter. */ + adc_filter.Sinc2NotchEnable = bTRUE; /* Enable the SINC2+Notch block. You can also use function AD5940_AFECtrlS */ + AD5940_ADCFilterCfgS(&adc_filter); + + //AD5940_ADCMuxCfgS(ADCMUXP_AIN2, ADCMUXN_VSET1P1); /* Optionally, you can change ADC MUX with this function */ + + /* Enable all interrupt at Interrupt Controller 1. So we can check the interrupt flag */ + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_ALLINT, bTRUE); + + //AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_SINC2NOTCH, bTRUE); + //AD5940_AFECtrlS(AFECTRL_ADCCNV, bTRUE); + AD5940_ADCPowerCtrlS(bTRUE); + AD5940_ADCConvtCtrlS(bTRUE); + + while(1) + { + uint32_t rd; + if(AD5940_INTCTestFlag(AFEINTC_1,AFEINTSRC_SINC2RDY)) + { + static uint32_t count; + AD5940_INTCClrFlag(AFEINTSRC_SINC2RDY); + rd = AD5940_ReadAfeResult(AFERESULT_SINC2); + count ++; + /* ADC Sample rate is 800kSPS. SINC3 OSR is 4, SINC2 OSR is 1333. So the final output data rate is 800kSPS/4/1333 = 150.0375Hz */ + if(count == 150) /* Print data @1Hz */ + { + count = 0; + float diff_volt = AD5940_ADCCode2Volt(rd, ADCPGA_GAIN_SEL, 1.82); + printf("ADC Code:%d, diff-volt: %.4f, volt:%.4f\n",rd, diff_volt, diff_volt+1.11); + } + } + } +} + +/** + * @} + * @} + * */ diff --git a/examples/AD5940_ECSns_EIS/AD5940Main.c b/examples/AD5940_ECSns_EIS/AD5940Main.c new file mode 100644 index 0000000..8e06cc0 --- /dev/null +++ b/examples/AD5940_ECSns_EIS/AD5940Main.c @@ -0,0 +1,151 @@ +/*! + ***************************************************************************** + @file: AD5940Main.c + @author: Neo Xu + @brief: Electrochemical impedance spectroscopy based on example AD5940_Impedance + This project is optomized for 3-lead electrochemical sensors that typically have + an impedance <200ohm. For optimum performance RCAL should be close to + impedance of the sensor. + ----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*****************************************************************************/ +#include "Impedance.h" + +#define APPBUFF_SIZE 512 +uint32_t AppBuff[APPBUFF_SIZE]; + +int32_t ImpedanceShowResult(uint32_t *pData, uint32_t DataCount) +{ + float freq; + + fImpPol_Type *pImp = (fImpPol_Type*)pData; + AppIMPCtrl(IMPCTRL_GETFREQ, &freq); + + printf("Freq:%.2f ", freq); + /*Process data*/ + for(int i=0;iSeqStartAddr = 0; + pImpedanceCfg->MaxSeqLen = 512; /* @todo add checker in function */ + + pImpedanceCfg->RcalVal = 200.0; + pImpedanceCfg->FifoThresh = 6; + pImpedanceCfg->SinFreq = 1000.0; + + /* Configure Excitation Waveform + * + * Output waveform = DacVoltPP * ExcitBufGain * HsDacGain + * + * = 300 * 0.25 * 0.2 = 15mV pk-pk + * + */ + pImpedanceCfg->DacVoltPP = 300; /* Maximum value is 600mV*/ + pImpedanceCfg->ExcitBufGain = EXCITBUFGAIN_0P25; + pImpedanceCfg->HsDacGain = HSDACGAIN_0P2; + + /* Set switch matrix to onboard(EVAL-AD5940ELECZ) gas sensor. */ + pImpedanceCfg->DswitchSel = SWD_CE0; + pImpedanceCfg->PswitchSel = SWP_RE0; + pImpedanceCfg->NswitchSel = SWN_SE0LOAD; + pImpedanceCfg->TswitchSel = SWT_SE0LOAD; + /* The dummy sensor is as low as 5kOhm. We need to make sure RTIA is small enough that HSTIA won't be saturated. */ + pImpedanceCfg->HstiaRtiaSel = HSTIARTIA_200; + pImpedanceCfg->BiasVolt = 0.0; + /* Configure the sweep function. */ + pImpedanceCfg->SweepCfg.SweepEn = bFALSE; + pImpedanceCfg->SweepCfg.SweepStart = 100.0f; /* Start from 1kHz */ + pImpedanceCfg->SweepCfg.SweepStop = 100e3f; /* Stop at 100kHz */ + pImpedanceCfg->SweepCfg.SweepPoints = 101; /* Points is 101 */ + pImpedanceCfg->SweepCfg.SweepLog = bTRUE; + /* Configure Power Mode. Use HP mode if frequency is higher than 80kHz. */ + pImpedanceCfg->PwrMod = AFEPWR_LP; + /* Configure filters if necessary */ + pImpedanceCfg->ADCSinc3Osr = ADCSINC3OSR_4; /* Sample rate is 800kSPS/2 = 400kSPS */ + pImpedanceCfg->DftNum = DFTNUM_16384; + pImpedanceCfg->DftSrc = DFTSRC_SINC3; +} + +void AD5940_Main(void) +{ + uint32_t temp; + AD5940PlatformCfg(); + AD5940ImpedanceStructInit(); + + AppIMPInit(AppBuff, APPBUFF_SIZE); /* Initialize IMP application. Provide a buffer, which is used to store sequencer commands */ + AppIMPCtrl(IMPCTRL_START, 0); /* Control IMP measurement to start. Second parameter has no meaning with this command. */ + + while(1) + { + if(AD5940_GetMCUIntFlag()) + { + AD5940_ClrMCUIntFlag(); + temp = APPBUFF_SIZE; + AppIMPISR(AppBuff, &temp); + ImpedanceShowResult(AppBuff, temp); + } + } +} + diff --git a/examples/AD5940_ECSns_EIS/Impedance.c b/examples/AD5940_ECSns_EIS/Impedance.c new file mode 100644 index 0000000..10323fe --- /dev/null +++ b/examples/AD5940_ECSns_EIS/Impedance.c @@ -0,0 +1,678 @@ +/*! + ***************************************************************************** + @file: Impedance.c + @author: Neo Xu + @brief: Electrochemical impedance spectroscopy based on example AD5940_Impedance + ----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*****************************************************************************/ +#include "AD5940.H" +#include +#include "string.h" +#include "math.h" +#include "Impedance.h" + +/* Default LPDAC resolution(2.5V internal reference). */ +#define DAC12BITVOLT_1LSB (2200.0f/4095) //mV +#define DAC6BITVOLT_1LSB (DAC12BITVOLT_1LSB*64) //mV + +/* + Application configuration structure. Specified by user from template. + The variables are usable in this whole application. + It includes basic configuration for sequencer generator and application related parameters +*/ +AppIMPCfg_Type AppIMPCfg = +{ + .bParaChanged = bFALSE, + .SeqStartAddr = 0, + .MaxSeqLen = 0, + + .SeqStartAddrCal = 0, + .MaxSeqLenCal = 0, + + .ImpODR = 20.0, /* 20.0 Hz*/ + .NumOfData = -1, + .SysClkFreq = 16000000.0, + .WuptClkFreq = 32000.0, + .AdcClkFreq = 16000000.0, + .RcalVal = 10000.0, + + .DswitchSel = SWD_CE0, + .PswitchSel = SWP_CE0, + .NswitchSel = SWN_AIN1, + .TswitchSel = SWT_AIN1, + + .PwrMod = AFEPWR_LP, + + .LptiaRtiaSel = LPTIARTIA_4K, /* COnfigure RTIA */ + .LpTiaRf = LPTIARF_1M, /* Configure LPF resistor */ + .LpTiaRl = LPTIARLOAD_100R, + + .HstiaRtiaSel = HSTIARTIA_1K, + .ExcitBufGain = EXCITBUFGAIN_0P25, + .HsDacGain = HSDACGAIN_0P2, + .HsDacUpdateRate = 0x1B, + .DacVoltPP = 300.0, + .BiasVolt = -0.0f, + + .SinFreq = 100000.0, /* 1000Hz */ + + .DftNum = DFTNUM_16384, + .DftSrc = DFTSRC_SINC3, + .HanWinEn = bTRUE, + + .AdcPgaGain = ADCPGA_1, + .ADCSinc3Osr = ADCSINC3OSR_2, + .ADCSinc2Osr = ADCSINC2OSR_22, + + .ADCAvgNum = ADCAVGNUM_16, + + .SweepCfg.SweepEn = bTRUE, + .SweepCfg.SweepStart = 1000, + .SweepCfg.SweepStop = 100000.0, + .SweepCfg.SweepPoints = 101, + .SweepCfg.SweepLog = bFALSE, + .SweepCfg.SweepIndex = 0, + + .FifoThresh = 4, + .IMPInited = bFALSE, + .StopRequired = bFALSE, +}; + +/** + This function is provided for upper controllers that want to change + application parameters specially for user defined parameters. +*/ +int32_t AppIMPGetCfg(void *pCfg) +{ + if(pCfg) + { + *(AppIMPCfg_Type**)pCfg = &AppIMPCfg; + return AD5940ERR_OK; + } + return AD5940ERR_PARA; +} + +int32_t AppIMPCtrl(uint32_t Command, void *pPara) +{ + + switch (Command) + { + case IMPCTRL_START: + { + WUPTCfg_Type wupt_cfg; + + if(AD5940_WakeUp(10) > 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + if(AppIMPCfg.IMPInited == bFALSE) + return AD5940ERR_APPERROR; + /* Start it */ + wupt_cfg.WuptEn = bTRUE; + wupt_cfg.WuptEndSeq = WUPTENDSEQ_A; + wupt_cfg.WuptOrder[0] = SEQID_0; + wupt_cfg.SeqxSleepTime[SEQID_0] = 4; + wupt_cfg.SeqxWakeupTime[SEQID_0] = (uint32_t)(AppIMPCfg.WuptClkFreq/AppIMPCfg.ImpODR)-4; + AD5940_WUPTCfg(&wupt_cfg); + + AppIMPCfg.FifoDataCount = 0; /* restart */ + break; + } + case IMPCTRL_STOPNOW: + { + if(AD5940_WakeUp(10) > 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + /* Start Wupt right now */ + AD5940_WUPTCtrl(bFALSE); + AD5940_WUPTCtrl(bFALSE); + break; + } + case IMPCTRL_STOPSYNC: + { + AppIMPCfg.StopRequired = bTRUE; + break; + } + case IMPCTRL_GETFREQ: + { + if(pPara == 0) + return AD5940ERR_PARA; + if(AppIMPCfg.SweepCfg.SweepEn == bTRUE) + *(float*)pPara = AppIMPCfg.FreqofData; + else + *(float*)pPara = AppIMPCfg.SinFreq; + } + break; + case IMPCTRL_SHUTDOWN: + { + AppIMPCtrl(IMPCTRL_STOPNOW, 0); /* Stop the measurement if it's running. */ + /* Turn off LPloop related blocks which are not controlled automatically by hibernate operation */ + AFERefCfg_Type aferef_cfg; + LPLoopCfg_Type lploop_cfg; + memset(&aferef_cfg, 0, sizeof(aferef_cfg)); + AD5940_REFCfgS(&aferef_cfg); + memset(&lploop_cfg, 0, sizeof(lploop_cfg)); + AD5940_LPLoopCfgS(&lploop_cfg); + AD5940_EnterSleepS(); /* Enter Hibernate */ + } + break; + default: + break; + } + return AD5940ERR_OK; +} + +/* generated code snnipet */ +float AppIMPGetCurrFreq(void) +{ + if(AppIMPCfg.SweepCfg.SweepEn == bTRUE) + return AppIMPCfg.FreqofData; + else + return AppIMPCfg.SinFreq; +} + +/* Application initialization */ +static AD5940Err AppIMPSeqCfgGen(void) +{ + AD5940Err error = AD5940ERR_OK; + const uint32_t *pSeqCmd; + uint32_t SeqLen; + AFERefCfg_Type aferef_cfg; + HSLoopCfg_Type HsLoopCfg; + LPLoopCfg_Type lploop_cfg; + DSPCfg_Type dsp_cfg; + float sin_freq; + + /* Start sequence generator here */ + AD5940_SEQGenCtrl(bTRUE); + + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Init all to disable state */ + + aferef_cfg.HpBandgapEn = bTRUE; + aferef_cfg.Hp1V1BuffEn = bTRUE; + aferef_cfg.Hp1V8BuffEn = bTRUE; + aferef_cfg.Disc1V1Cap = bFALSE; + aferef_cfg.Disc1V8Cap = bFALSE; + aferef_cfg.Hp1V8ThemBuff = bFALSE; + aferef_cfg.Hp1V8Ilimit = bFALSE; + aferef_cfg.Lp1V1BuffEn = bFALSE; + aferef_cfg.Lp1V8BuffEn = bFALSE; + aferef_cfg.LpBandgapEn = bTRUE; + aferef_cfg.LpRefBufEn = bTRUE; + aferef_cfg.LpRefBoostEn = bFALSE; + AD5940_REFCfgS(&aferef_cfg); + + lploop_cfg.LpDacCfg.LpDacSrc = LPDACSRC_MMR; + lploop_cfg.LpDacCfg.LpDacSW = LPDACSW_VBIAS2LPPA|LPDACSW_VBIAS2PIN|LPDACSW_VZERO2LPTIA|LPDACSW_VZERO2PIN; + lploop_cfg.LpDacCfg.LpDacVzeroMux = LPDACVZERO_6BIT; + lploop_cfg.LpDacCfg.LpDacVbiasMux = LPDACVBIAS_12BIT; + lploop_cfg.LpDacCfg.LpDacRef = LPDACREF_2P5; + lploop_cfg.LpDacCfg.DataRst = bFALSE; + lploop_cfg.LpDacCfg.PowerEn = bTRUE; + lploop_cfg.LpDacCfg.DacData6Bit = (uint32_t)((AppIMPCfg.Vzero-200)/DAC6BITVOLT_1LSB); + lploop_cfg.LpDacCfg.DacData12Bit =(int32_t)((AppIMPCfg.BiasVolt)/DAC12BITVOLT_1LSB) + lploop_cfg.LpDacCfg.DacData6Bit*64; + if(lploop_cfg.LpDacCfg.DacData12Bit>lploop_cfg.LpDacCfg.DacData6Bit*64) + lploop_cfg.LpDacCfg.DacData12Bit--; + lploop_cfg.LpAmpCfg.LpAmpPwrMod = LPAMPPWR_NORM; + lploop_cfg.LpAmpCfg.LpPaPwrEn = bTRUE; + lploop_cfg.LpAmpCfg.LpTiaPwrEn = bTRUE; + lploop_cfg.LpAmpCfg.LpTiaRf = AppIMPCfg.LpTiaRf; + lploop_cfg.LpAmpCfg.LpTiaRload = AppIMPCfg.LpTiaRl; + lploop_cfg.LpAmpCfg.LpTiaRtia = AppIMPCfg.LptiaRtiaSel; + lploop_cfg.LpAmpCfg.LpTiaSW = LPTIASW(5)|LPTIASW(2)|LPTIASW(4)|LPTIASW(12)|LPTIASW(13); + + AD5940_LPLoopCfgS(&lploop_cfg); + + HsLoopCfg.HsDacCfg.ExcitBufGain = AppIMPCfg.ExcitBufGain; + HsLoopCfg.HsDacCfg.HsDacGain = AppIMPCfg.HsDacGain; + HsLoopCfg.HsDacCfg.HsDacUpdateRate = AppIMPCfg.HsDacUpdateRate; + + HsLoopCfg.HsTiaCfg.DiodeClose = bFALSE; + HsLoopCfg.HsTiaCfg.HstiaBias = HSTIABIAS_1P1; + HsLoopCfg.HsTiaCfg.HstiaCtia = 31; /* 31pF + 2pF */ + HsLoopCfg.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_OPEN; + HsLoopCfg.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_OPEN; + HsLoopCfg.HsTiaCfg.HstiaRtiaSel = AppIMPCfg.HstiaRtiaSel; + + HsLoopCfg.SWMatCfg.Dswitch = AppIMPCfg.DswitchSel; + HsLoopCfg.SWMatCfg.Pswitch = AppIMPCfg.PswitchSel; + HsLoopCfg.SWMatCfg.Nswitch = AppIMPCfg.NswitchSel; + HsLoopCfg.SWMatCfg.Tswitch = SWT_TRTIA|AppIMPCfg.TswitchSel; + + HsLoopCfg.WgCfg.WgType = WGTYPE_SIN; + HsLoopCfg.WgCfg.GainCalEn = bTRUE; + HsLoopCfg.WgCfg.OffsetCalEn = bTRUE; + if(AppIMPCfg.SweepCfg.SweepEn == bTRUE) + { + AppIMPCfg.FreqofData = AppIMPCfg.SweepCfg.SweepStart; + AppIMPCfg.SweepCurrFreq = AppIMPCfg.SweepCfg.SweepStart; + AD5940_SweepNext(&AppIMPCfg.SweepCfg, &AppIMPCfg.SweepNextFreq); + sin_freq = AppIMPCfg.SweepCurrFreq; + } + else + { + sin_freq = AppIMPCfg.SinFreq; + AppIMPCfg.FreqofData = sin_freq; + } + HsLoopCfg.WgCfg.SinCfg.SinFreqWord = AD5940_WGFreqWordCal(sin_freq, AppIMPCfg.SysClkFreq); + HsLoopCfg.WgCfg.SinCfg.SinAmplitudeWord = (uint32_t)(AppIMPCfg.DacVoltPP/800.0f*2047 + 0.5f); + HsLoopCfg.WgCfg.SinCfg.SinOffsetWord = 0; + HsLoopCfg.WgCfg.SinCfg.SinPhaseWord = 0; + AD5940_HSLoopCfgS(&HsLoopCfg); + + dsp_cfg.ADCBaseCfg.ADCMuxN = ADCMUXN_HSTIA_N; + dsp_cfg.ADCBaseCfg.ADCMuxP = ADCMUXP_HSTIA_P; + dsp_cfg.ADCBaseCfg.ADCPga = AppIMPCfg.AdcPgaGain; + + memset(&dsp_cfg.ADCDigCompCfg, 0, sizeof(dsp_cfg.ADCDigCompCfg)); + + dsp_cfg.ADCFilterCfg.ADCAvgNum = AppIMPCfg.ADCAvgNum; + dsp_cfg.ADCFilterCfg.ADCRate = ADCRATE_800KHZ; /* Tell filter block clock rate of ADC*/ + dsp_cfg.ADCFilterCfg.ADCSinc2Osr = AppIMPCfg.ADCSinc2Osr; + dsp_cfg.ADCFilterCfg.ADCSinc3Osr = AppIMPCfg.ADCSinc3Osr; + dsp_cfg.ADCFilterCfg.BpNotch = bTRUE; + dsp_cfg.ADCFilterCfg.BpSinc3 = bFALSE; + dsp_cfg.ADCFilterCfg.Sinc2NotchEnable = bTRUE; + dsp_cfg.DftCfg.DftNum = AppIMPCfg.DftNum; + dsp_cfg.DftCfg.DftSrc = AppIMPCfg.DftSrc; + dsp_cfg.DftCfg.HanWinEn = AppIMPCfg.HanWinEn; + + memset(&dsp_cfg.StatCfg, 0, sizeof(dsp_cfg.StatCfg)); + AD5940_DSPCfgS(&dsp_cfg); + + /* Enable all of them. They are automatically turned off during hibernate mode to save power */ + if(AppIMPCfg.BiasVolt == 0.0f) + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\ + AFECTRL_WG|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|\ + AFECTRL_SINC2NOTCH, bTRUE); + else + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\ + AFECTRL_WG|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|\ + AFECTRL_SINC2NOTCH|AFECTRL_DCBUFPWR, bTRUE); + /* Sequence end. */ + AD5940_SEQGenInsert(SEQ_STOP()); /* Add one extra command to disable sequencer for initialization sequence because we only want it to run one time. */ + + /* Stop here */ + error = AD5940_SEQGenFetchSeq(&pSeqCmd, &SeqLen); + AD5940_SEQGenCtrl(bFALSE); /* Stop sequencer generator */ + if(error == AD5940ERR_OK) + { + AppIMPCfg.InitSeqInfo.SeqId = SEQID_1; + AppIMPCfg.InitSeqInfo.SeqRamAddr = AppIMPCfg.SeqStartAddr; + AppIMPCfg.InitSeqInfo.pSeqCmd = pSeqCmd; + AppIMPCfg.InitSeqInfo.SeqLen = SeqLen; + /* Write command to SRAM */ + AD5940_SEQCmdWrite(AppIMPCfg.InitSeqInfo.SeqRamAddr, pSeqCmd, SeqLen); + } + else + return error; /* Error */ + return AD5940ERR_OK; +} + + +static AD5940Err AppIMPSeqMeasureGen(void) +{ + AD5940Err error = AD5940ERR_OK; + const uint32_t *pSeqCmd; + uint32_t SeqLen; + + uint32_t WaitClks; + SWMatrixCfg_Type sw_cfg; + ClksCalInfo_Type clks_cal; + LPAmpCfg_Type LpAmpCfg; + + /* Calculate number of clocks to get data to FIFO */ + clks_cal.DataType = DATATYPE_DFT; + clks_cal.DftSrc = AppIMPCfg.DftSrc; + clks_cal.DataCount = 1L<<(AppIMPCfg.DftNum+2); /* 2^(DFTNUMBER+2) */ + clks_cal.ADCSinc2Osr = AppIMPCfg.ADCSinc2Osr; + clks_cal.ADCSinc3Osr = AppIMPCfg.ADCSinc3Osr; + clks_cal.ADCAvgNum = AppIMPCfg.ADCAvgNum; + clks_cal.RatioSys2AdcClk = AppIMPCfg.SysClkFreq/AppIMPCfg.AdcClkFreq; + AD5940_ClksCalculate(&clks_cal, &WaitClks); + + /* Start Sequence Generator */ + AD5940_SEQGenCtrl(bTRUE); + AD5940_SEQGpioCtrlS(AGPIO_Pin2); /* Set GPIO1, clear others that under control */ + AD5940_SEQGenInsert(SEQ_WAIT(16*250)); /* @todo wait 250us? */ + + /* Disconnect SE0 from LPTIA*/ + LpAmpCfg.LpAmpPwrMod = LPAMPPWR_NORM; + LpAmpCfg.LpPaPwrEn = bTRUE; + LpAmpCfg.LpTiaPwrEn = bTRUE; + LpAmpCfg.LpTiaRf = AppIMPCfg.LpTiaRf; + LpAmpCfg.LpTiaRload = AppIMPCfg.LpTiaRl; + LpAmpCfg.LpTiaRtia = LPTIARTIA_OPEN; /* Disconnect Rtia to avoid RC filter discharge */ + LpAmpCfg.LpTiaSW = LPTIASW(7)|LPTIASW(8)|LPTIASW(12)|LPTIASW(13); + AD5940_LPAMPCfgS(&LpAmpCfg); + /* Sensor + Rload Measurement */ + sw_cfg.Dswitch = AppIMPCfg.DswitchSel; + sw_cfg.Pswitch = AppIMPCfg.PswitchSel; + sw_cfg.Nswitch = AppIMPCfg.NswitchSel; + sw_cfg.Tswitch = SWT_TRTIA|AppIMPCfg.TswitchSel; + AD5940_SWMatrixCfgS(&sw_cfg); + + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\ + AFECTRL_WG|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|\ + AFECTRL_SINC2NOTCH, bTRUE); + + + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_SINC2NOTCH, bTRUE); /* Enable Waveform generator */ + //delay for signal settling DFT_WAIT + AD5940_SEQGenInsert(SEQ_WAIT(16*10)); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT, bTRUE); /* Start ADC convert and DFT */ + AD5940_SEQGenInsert(SEQ_WAIT(WaitClks)); + //wait for first data ready + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\ + AFECTRL_WG|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|\ + AFECTRL_SINC2NOTCH|AFECTRL_DFT|AFECTRL_ADCCNV, bFALSE); + + /* RLOAD Measurement */ + sw_cfg.Dswitch = SWD_SE0; + sw_cfg.Pswitch = SWP_SE0; + sw_cfg.Nswitch = SWN_SE0LOAD; + sw_cfg.Tswitch = SWT_SE0LOAD|SWT_TRTIA; + AD5940_SWMatrixCfgS(&sw_cfg); + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\ + AFECTRL_WG|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|AFECTRL_SINC2NOTCH, bTRUE); + AD5940_SEQGenInsert(SEQ_WAIT(16*10)); //delay for signal settling DFT_WAIT + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT, bTRUE); /* Start ADC convert and DFT */ + AD5940_SEQGenInsert(SEQ_WAIT(WaitClks)); /* wait for first data ready */ + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\ + AFECTRL_WG|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|\ + AFECTRL_SINC2NOTCH|AFECTRL_ADCCNV, bFALSE); + + /* RCAL Measurement */ + sw_cfg.Dswitch = SWD_RCAL0; + sw_cfg.Pswitch = SWP_RCAL0; + sw_cfg.Nswitch = SWN_RCAL1; + sw_cfg.Tswitch = SWT_RCAL1|SWT_TRTIA; + AD5940_SWMatrixCfgS(&sw_cfg); + /* Reconnect LP loop */ + LpAmpCfg.LpTiaRtia = AppIMPCfg.LptiaRtiaSel; /* Disconnect Rtia to avoid RC filter discharge */ + LpAmpCfg.LpTiaSW = LPTIASW(5)|LPTIASW(2)|LPTIASW(4)|LPTIASW(12)|LPTIASW(13); + AD5940_LPAMPCfgS(&LpAmpCfg); + + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\ + AFECTRL_WG|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|AFECTRL_SINC2NOTCH, bTRUE); + AD5940_SEQGenInsert(SEQ_WAIT(16*10)); //delay for signal settling DFT_WAIT + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT/*|AFECTRL_SINC2NOTCH*/, bTRUE); /* Start ADC convert and DFT */ + AD5940_SEQGenInsert(SEQ_WAIT(WaitClks)); /* wait for first data ready */ + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT|AFECTRL_WG|AFECTRL_ADCPWR, bFALSE); /* Stop ADC convert and DFT */ + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\ + AFECTRL_WG|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|\ + AFECTRL_SINC2NOTCH, bFALSE); + AD5940_SEQGpioCtrlS(0); /* Clr GPIO1 */ + + sw_cfg.Dswitch = SWD_OPEN; + sw_cfg.Pswitch = SWP_OPEN; + sw_cfg.Nswitch = SWN_OPEN; + sw_cfg.Tswitch = SWT_OPEN; + AD5940_SWMatrixCfgS(&sw_cfg); + + //AD5940_EnterSleepS();/* Goto hibernate */ + + /* Sequence end. */ + error = AD5940_SEQGenFetchSeq(&pSeqCmd, &SeqLen); + AD5940_SEQGenCtrl(bFALSE); /* Stop sequencer generator */ + + if(error == AD5940ERR_OK) + { + AppIMPCfg.MeasureSeqInfo.SeqId = SEQID_0; + AppIMPCfg.MeasureSeqInfo.SeqRamAddr = AppIMPCfg.InitSeqInfo.SeqRamAddr + AppIMPCfg.InitSeqInfo.SeqLen ; + AppIMPCfg.MeasureSeqInfo.pSeqCmd = pSeqCmd; + AppIMPCfg.MeasureSeqInfo.SeqLen = SeqLen; + /* Write command to SRAM */ + AD5940_SEQCmdWrite(AppIMPCfg.MeasureSeqInfo.SeqRamAddr, pSeqCmd, SeqLen); + } + else + return error; /* Error */ + return AD5940ERR_OK; +} + + +/* This function provide application initialize. It can also enable Wupt that will automatically trigger sequence. Or it can configure */ +int32_t AppIMPInit(uint32_t *pBuffer, uint32_t BufferSize) +{ + AD5940Err error = AD5940ERR_OK; + SEQCfg_Type seq_cfg; + FIFOCfg_Type fifo_cfg; + + if(AD5940_WakeUp(10) > 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + + /* Configure sequencer and stop it */ + seq_cfg.SeqMemSize = SEQMEMSIZE_2KB; /* 2kB SRAM is used for sequencer, others for data FIFO */ + seq_cfg.SeqBreakEn = bFALSE; + seq_cfg.SeqIgnoreEn = bTRUE; + seq_cfg.SeqCntCRCClr = bTRUE; + seq_cfg.SeqEnable = bFALSE; + seq_cfg.SeqWrTimer = 0; + AD5940_SEQCfg(&seq_cfg); + + /* Reconfigure FIFO */ + AD5940_FIFOCtrlS(FIFOSRC_DFT, bFALSE); /* Disable FIFO firstly */ + fifo_cfg.FIFOEn = bTRUE; + fifo_cfg.FIFOMode = FIFOMODE_FIFO; + fifo_cfg.FIFOSize = FIFOSIZE_4KB; /* 4kB for FIFO, The reset 2kB for sequencer */ + fifo_cfg.FIFOSrc = FIFOSRC_DFT; + fifo_cfg.FIFOThresh = AppIMPCfg.FifoThresh; /* DFT result. One pair for RCAL, another for Rz. One DFT result have real part and imaginary part */ + AD5940_FIFOCfg(&fifo_cfg); + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + + /* Start sequence generator */ + /* Initialize sequencer generator */ + if((AppIMPCfg.IMPInited == bFALSE)||\ + (AppIMPCfg.bParaChanged == bTRUE)) + { + if(pBuffer == 0) return AD5940ERR_PARA; + if(BufferSize == 0) return AD5940ERR_PARA; + AD5940_SEQGenInit(pBuffer, BufferSize); + + /* Generate initialize sequence */ + error = AppIMPSeqCfgGen(); /* Application initialization sequence using either MCU or sequencer */ + if(error != AD5940ERR_OK) return error; + + /* Generate measurement sequence */ + error = AppIMPSeqMeasureGen(); + if(error != AD5940ERR_OK) return error; + + AppIMPCfg.bParaChanged = bFALSE; /* Clear this flag as we already implemented the new configuration */ + } + + /* Initialization sequencer */ + AppIMPCfg.InitSeqInfo.WriteSRAM = bFALSE; + AD5940_SEQInfoCfg(&AppIMPCfg.InitSeqInfo); + seq_cfg.SeqEnable = bTRUE; + AD5940_SEQCfg(&seq_cfg); /* Enable sequencer */ + AD5940_SEQMmrTrig(AppIMPCfg.InitSeqInfo.SeqId); + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_ENDSEQ) == bFALSE); + + /* Measurement sequence */ + AppIMPCfg.MeasureSeqInfo.WriteSRAM = bFALSE; + AD5940_SEQInfoCfg(&AppIMPCfg.MeasureSeqInfo); + + seq_cfg.SeqEnable = bTRUE; + AD5940_SEQCfg(&seq_cfg); /* Enable sequencer, and wait for trigger */ + AD5940_ClrMCUIntFlag(); /* Clear interrupt flag generated before */ + + AD5940_AFEPwrBW(AppIMPCfg.PwrMod, AFEBW_250KHZ); + + AD5940_WriteReg(REG_AFE_LPTIASW0, 0x3180); + AppIMPCfg.IMPInited = bTRUE; /* IMP application has been initialized. */ + return AD5940ERR_OK; +} + +/* Modify registers when AFE wakeup */ +int32_t AppIMPRegModify(int32_t * const pData, uint32_t *pDataCount) +{ + if(AppIMPCfg.NumOfData > 0) + { + AppIMPCfg.FifoDataCount += *pDataCount/4; + if(AppIMPCfg.FifoDataCount >= AppIMPCfg.NumOfData) + { + AD5940_WUPTCtrl(bFALSE); + return AD5940ERR_OK; + } + } + if(AppIMPCfg.StopRequired == bTRUE) + { + AD5940_WUPTCtrl(bFALSE); + return AD5940ERR_OK; + } + if(AppIMPCfg.SweepCfg.SweepEn) /* Need to set new frequency and set power mode */ + { + /* Check frequency and update FIlter settings */ + AD5940_WGFreqCtrlS(AppIMPCfg.SweepNextFreq, AppIMPCfg.SysClkFreq); + } + return AD5940ERR_OK; +} + +/* Depending on the data type, do appropriate data pre-process before return back to controller */ +int32_t AppIMPDataProcess(int32_t * const pData, uint32_t *pDataCount) +{ + uint32_t DataCount = *pDataCount; + uint32_t ImpResCount = DataCount/6; + + fImpPol_Type * const pOut = (fImpPol_Type*)pData; + iImpCar_Type * pSrcData = (iImpCar_Type*)pData; + + *pDataCount = 0; + + DataCount = (DataCount/6)*6;/* We expect Rz+Rload, Rload and RCAL data, . One DFT result has two data in FIFO, real part and imaginary part. */ + + /* Convert DFT result to int32_t type */ + for(uint32_t i=0; iReal; + DftRzRload.Image = -pSrcData->Image; + pSrcData++; + DftRload.Real = pSrcData->Real; + DftRload.Image = -pSrcData->Image; + pSrcData++; + DftRcal.Real = pSrcData->Real; + DftRcal.Image = -pSrcData->Image; + pSrcData++; + /** + Rz = RloadRz - Rload + RloadRz = DftRcal/DftRzRload*RCAL; + Rload = DftRcal/DftRload*RCAL; + Rz = RloadRz - Rload = + (1/DftRzRload - 1/DftRload)*DftRcal*RCAL; + where RCAL is the RCAL resistor value in Ohm. + */ + //temp1 = 1/DftRzRload; + //temp2 = 1/DftRload; + temp1 = AD5940_ComplexDivFloat(&DftConst1, &DftRzRload); + temp2 = AD5940_ComplexDivFloat(&DftConst1, &DftRload); + res = AD5940_ComplexSubFloat(&temp1, &temp2); + res = AD5940_ComplexMulFloat(&res, &DftRcal); + pOut[i].Magnitude = AD5940_ComplexMag(&res)*AppIMPCfg.RcalVal; + pOut[i].Phase = AD5940_ComplexPhase(&res); + } + else + { + iImpCar_Type *pDftRcal, *pDftRzRload, *pDftRload; + + pDftRzRload = pSrcData++; + pDftRload = pSrcData++; + pDftRcal = pSrcData++; + + float RzRloadMag, RzRloadPhase; + float RloadMag, RloadPhase; + float RzMag,RzPhase; + float RcalMag, RcalPhase; + float RzReal, RzImage; + + RzReal = pDftRload->Real - pDftRzRload->Real; + RzImage = pDftRload->Image - pDftRzRload->Image; + + RzRloadMag = sqrt((float)pDftRzRload->Real*pDftRzRload->Real+(float)pDftRzRload->Image*pDftRzRload->Image); + RzRloadPhase = atan2(-pDftRzRload->Image,pDftRzRload->Real); + RcalMag = sqrt((float)pDftRcal->Real*pDftRcal->Real+(float)pDftRcal->Image*pDftRcal->Image); + RcalPhase = atan2(-pDftRcal->Image,pDftRcal->Real); + RzMag = sqrt((float)RzReal*RzReal+(float)RzImage*RzImage); + RzPhase = atan2(-RzImage,RzReal); + RloadMag = sqrt((float)pDftRload->Real*pDftRload->Real+(float)pDftRload->Image*pDftRload->Image); + RloadPhase = atan2(-pDftRload->Image,pDftRload->Real); + + RzMag = (AppIMPCfg.RcalVal*RcalMag*RzMag)/(RzRloadMag*RloadMag); + RzPhase = -(RcalPhase + RzPhase - RloadPhase - RzRloadPhase); + // RzPhase = (RcalPhase + RzPhase - RloadPhase - RzRloadPhase); + + + pOut[i].Magnitude = RzMag; + pOut[i].Phase = RzPhase; + } + } + *pDataCount = ImpResCount; + AppIMPCfg.FreqofData = AppIMPCfg.SweepCurrFreq; + /* Calculate next frequency point */ + if(AppIMPCfg.SweepCfg.SweepEn == bTRUE) + { + AppIMPCfg.FreqofData = AppIMPCfg.SweepCurrFreq; + AppIMPCfg.SweepCurrFreq = AppIMPCfg.SweepNextFreq; + AD5940_SweepNext(&AppIMPCfg.SweepCfg, &AppIMPCfg.SweepNextFreq); + } + + return 0; +} + +/** + +*/ +int32_t AppIMPISR(void *pBuff, uint32_t *pCount) +{ + uint32_t BuffCount; + uint32_t FifoCnt; + BuffCount = *pCount; + + *pCount = 0; + + if(AD5940_WakeUp(10) > 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + AD5940_SleepKeyCtrlS(SLPKEY_LOCK); /* Prohibit AFE to enter sleep mode. */ + + if(AD5940_INTCTestFlag(AFEINTC_0, AFEINTSRC_DATAFIFOTHRESH) == bTRUE) + { + /* Now there should be 4 data in FIFO */ + FifoCnt = (AD5940_FIFOGetCnt()/6)*6; + + if(FifoCnt > BuffCount) + { + ///@todo buffer is limited. + } + AD5940_FIFORd((uint32_t *)pBuff, FifoCnt); + AD5940_INTCClrFlag(AFEINTSRC_DATAFIFOTHRESH); + AppIMPRegModify(pBuff, &FifoCnt); /* If there is need to do AFE re-configure, do it here when AFE is in active state */ + //AD5940_EnterSleepS(); /* Manually put AFE back to hibernate mode. This operation only takes effect when register value is ACTIVE previously */ + AD5940_SleepKeyCtrlS(SLPKEY_UNLOCK); /* Allow AFE to enter sleep mode. */ + /* Process data */ + AppIMPDataProcess((int32_t*)pBuff,&FifoCnt); + *pCount = FifoCnt; + return 0; + } + + return 0; +} + + diff --git a/examples/AD5940_ECSns_EIS/Impedance.h b/examples/AD5940_ECSns_EIS/Impedance.h new file mode 100644 index 0000000..e7d5425 --- /dev/null +++ b/examples/AD5940_ECSns_EIS/Impedance.h @@ -0,0 +1,91 @@ +/*! + ***************************************************************************** + @file: Impedance.h + @author: Neo Xu + @brief: Electrochemical impedance spectroscopy based on example AD5940_Impedance + ----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*****************************************************************************/ +#ifndef _IMPEDANCESEQUENCES_H_ +#define _IMPEDANCESEQUENCES_H_ +#include "AD5940.H" +#include +#include "string.h" +#include "math.h" + +typedef struct +{ +/* Common configurations for all kinds of Application. */ + BoolFlag bParaChanged; /* Indicate to generate sequence again. It's auto cleared by AppBIAInit */ + uint32_t SeqStartAddr; /* Initialaztion sequence start address in SRAM of AD5940 */ + uint32_t MaxSeqLen; /* Limit the maximum sequence. */ + uint32_t SeqStartAddrCal; /* Measurement sequence start address in SRAM of AD5940 */ + uint32_t MaxSeqLenCal; +/* Application related parameters */ + float ImpODR; /* */ + int32_t NumOfData; /* By default it's '-1'. If you want the engine stops after get NumofData, then set the value here. Otherwise, set it to '-1' which means never stop. */ + float WuptClkFreq; /* The clock frequency of Wakeup Timer in Hz. Typically it's 32kHz. Leave it here in case we calibrate clock in software method */ + float SysClkFreq; /* The real frequency of system clock */ + float AdcClkFreq; /* The real frequency of ADC clock */ + float RcalVal; /* Rcal value in Ohm */ + /* Switch Configuration */ + uint32_t DswitchSel; + uint32_t PswitchSel; + uint32_t NswitchSel; + uint32_t TswitchSel; + uint32_t PwrMod; /* Control Chip power mode(LP/HP) */ + uint32_t HstiaRtiaSel; /* Use internal RTIA, select from RTIA_INT_200, RTIA_INT_1K, RTIA_INT_5K, RTIA_INT_10K, RTIA_INT_20K, RTIA_INT_40K, RTIA_INT_80K, RTIA_INT_160K */ + uint32_t ExcitBufGain; /* Select from EXCTBUFGAIN_2, EXCTBUFGAIN_0P25 */ + uint32_t HsDacGain; /* Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + uint32_t HsDacUpdateRate; + float DacVoltPP; /* DAC output voltage in mV peak to peak. Maximum value is 600mVpp. Peak to peak voltage */ + float BiasVolt; /* The excitation signal is DC+AC. This parameter decides the DC value in mV unit. 0.0mV means no DC bias.*/ + float SinFreq; /* Frequency of excitation signal */ + uint32_t DftNum; /* DFT number */ + uint32_t DftSrc; /* DFT Source */ + BoolFlag HanWinEn; /* Enable Hanning window */ + uint32_t AdcPgaGain; /* PGA Gain select from GNPGA_1, GNPGA_1_5, GNPGA_2, GNPGA_4, GNPGA_9 !!! We must ensure signal is in range of +-1.5V which is limited by ADC input stage */ + uint8_t ADCSinc3Osr; + uint8_t ADCSinc2Osr; + uint8_t ADCAvgNum; + uint8_t ADC_Rate; + + uint32_t LptiaRtiaSel; /* Use internal RTIA, select from RTIA_INT_200, RTIA_INT_1K, RTIA_INT_5K, RTIA_INT_10K, RTIA_INT_20K, RTIA_INT_40K, RTIA_INT_80K, RTIA_INT_160K */ + uint32_t LpTiaRf; /* Rfilter select */ + uint32_t LpTiaRl; /* SE0 Rload select */ + float Vzero; /* Voltage on SE0 pin and Vzero, optimumly 1100mV*/ + float Vbias; /* Voltage on CE0 and PA */ + /* Sweep Function Control */ + SoftSweepCfg_Type SweepCfg; + uint32_t FifoThresh; /* FIFO threshold. Should be N*4 */ +/* Private variables for internal usage */ +/* Private variables for internal usage */ + float SweepCurrFreq; + float SweepNextFreq; + float FreqofData; /* The frequency of latest data sampled */ + BoolFlag IMPInited; /* If the program run firstly, generated sequence commands */ + SEQInfo_Type InitSeqInfo; + SEQInfo_Type MeasureSeqInfo; + BoolFlag StopRequired; /* After FIFO is ready, stop the measurement sequence */ + uint32_t FifoDataCount; /* Count how many times impedance have been measured */ +}AppIMPCfg_Type; + +#define IMPCTRL_START 0 +#define IMPCTRL_STOPNOW 1 +#define IMPCTRL_STOPSYNC 2 +#define IMPCTRL_GETFREQ 3 /* Get Current frequency of returned data from ISR */ +#define IMPCTRL_SHUTDOWN 4 /* Note: shutdown here means turn off everything and put AFE to hibernate mode. The word 'SHUT DOWN' is only used here. */ + + +int32_t AppIMPInit(uint32_t *pBuffer, uint32_t BufferSize); +int32_t AppIMPGetCfg(void *pCfg); +int32_t AppIMPISR(void *pBuff, uint32_t *pCount); +int32_t AppIMPCtrl(uint32_t Command, void *pPara); + +#endif diff --git a/examples/AD5940_HSDACCal/AD5940_HSDACCal.c b/examples/AD5940_HSDACCal/AD5940_HSDACCal.c new file mode 100644 index 0000000..130bd7a --- /dev/null +++ b/examples/AD5940_HSDACCal/AD5940_HSDACCal.c @@ -0,0 +1,95 @@ +/*! +***************************************************************************** +@file: AD5940_HSDACCal.c +@author: $Author: nxu2 $ +@brief: HSDAC Offset Calibration Demo calibration demo. +@version: $Revision: 766 $ +@date: $Date: 2017-08-21 14:09:35 +0100 (Mon, 21 Aug 2017) $ +----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*****************************************************************************/ + +#include "ad5940.h" +#include +#include "string.h" + +/* The HSDAC has a number of different gain settings shown in table below. +The HSDAC needs to be calibrated seperately for each gain setting. HSDAC has two powe +modes. There are seperate offset registers for both, DACOFFSET and DACOFFSETHP. The +HSDAC needs to be calibrated for each mode. + +HSDACCON[12] | HSDACCON[0] | Output Range | +0 | 0 | +-607mV | +1 | 0 | +-75mV | +1 | 1 | +-15.14mV | +0 | 1 | +-121.2mV | + +*/ +void AD5940_Main(void){ + HSDACCal_Type hsdac_cal; + ADCPGACal_Type adcpga_cal; + CLKCfg_Type clk_cfg; + /* Use hardware reset */ + AD5940_HWReset(); + AD5940_Initialize(); + + AD5940_AFEPwrBW(AFEPWR_LP, AFEBW_250KHZ); + + clk_cfg.ADCClkDiv = ADCCLKDIV_1; + clk_cfg.ADCCLkSrc = ADCCLKSRC_HFOSC; + clk_cfg.SysClkDiv = SYSCLKDIV_1; + clk_cfg.SysClkSrc = SYSCLKSRC_HFOSC; + clk_cfg.HfOSC32MHzMode = bTRUE; + clk_cfg.HFOSCEn = bTRUE; + clk_cfg.HFXTALEn = bFALSE; + clk_cfg.LFOSCEn = bTRUE; + AD5940_CLKCfg(&clk_cfg); + + + printf("ADC Offset Cal\n"); + adcpga_cal.AdcClkFreq=16000000; + adcpga_cal.ADCPga = ADCPGA_1; + adcpga_cal.ADCSinc2Osr = ADCSINC2OSR_1333; + adcpga_cal.ADCSinc3Osr = ADCSINC3OSR_4; + adcpga_cal.PGACalType = PGACALTYPE_OFFSET; + adcpga_cal.TimeOut10us = 1000; + adcpga_cal.VRef1p11 = 1.11; + adcpga_cal.VRef1p82 = 1.82; + AD5940_ADCPGACal(&adcpga_cal); + + printf("\n 607mV Range Cal\n"); + hsdac_cal.ExcitBufGain = EXCITBUFGAIN_2; /**< Select from EXCITBUFGAIN_2, EXCITBUFGAIN_0P25 */ + hsdac_cal.HsDacGain = HSDACGAIN_1; /**< Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + hsdac_cal.AfePwrMode = AFEPWR_LP; + hsdac_cal.ADCSinc2Osr = ADCSINC2OSR_1333; + hsdac_cal.ADCSinc3Osr = ADCSINC3OSR_4; + AD5940_HSDACCal(&hsdac_cal); + + printf("\nADC GN 4 Offset Cal\n"); + adcpga_cal.ADCPga = ADCPGA_4; + AD5940_ADCPGACal(&adcpga_cal); + + printf("\n 125mV Range Cal\n"); + hsdac_cal.ExcitBufGain = EXCITBUFGAIN_2; /**< Select from EXCITBUFGAIN_2, EXCITBUFGAIN_0P25 */ + hsdac_cal.HsDacGain = HSDACGAIN_0P2; /**< Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + AD5940_HSDACCal(&hsdac_cal); + + printf("\n 75mV Range Cal\n"); + hsdac_cal.ExcitBufGain = EXCITBUFGAIN_0P25; /**< Select from EXCITBUFGAIN_2, EXCITBUFGAIN_0P25 */ + hsdac_cal.HsDacGain = HSDACGAIN_1; /**< Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + AD5940_HSDACCal(&hsdac_cal); + + printf("\n 15mV Range Cal\n"); + hsdac_cal.ExcitBufGain = EXCITBUFGAIN_0P25; /**< Select from EXCITBUFGAIN_2, EXCITBUFGAIN_0P25 */ + hsdac_cal.HsDacGain = HSDACGAIN_0P2; /**< Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + AD5940_HSDACCal(&hsdac_cal); + + printf("HSDAC Cal Complete!\n"); +} + diff --git a/examples/AD5940_Impedance_Adjustable_with_frequency/AD5940Main.c b/examples/AD5940_Impedance_Adjustable_with_frequency/AD5940Main.c new file mode 100644 index 0000000..fa9680e --- /dev/null +++ b/examples/AD5940_Impedance_Adjustable_with_frequency/AD5940Main.c @@ -0,0 +1,142 @@ +/*! + ***************************************************************************** + @file: AD5940Main.c + @author: Neo Xu + @brief: Standard 4-wire or 2-wire impedance measurement example. + ----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*****************************************************************************/ +#include "Impedance.h" + +/** + User could configure following parameters +**/ + +#define APPBUFF_SIZE 512 +uint32_t AppBuff[APPBUFF_SIZE]; + +int32_t ImpedanceShowResult(uint32_t *pData, uint32_t DataCount) +{ + float freq; + + fImpPol_Type *pImp = (fImpPol_Type*)pData; + AppIMPCtrl(IMPCTRL_GETFREQ, &freq); + + printf("Freq:%.2f ", freq); + /*Process data*/ + for(int i=0;iSeqStartAddr = 0; + pImpedanceCfg->MaxSeqLen = 512; /* @todo add checker in function */ + + pImpedanceCfg->RcalVal = 10000.0; + pImpedanceCfg->SinFreq = 60000.0; + pImpedanceCfg->FifoThresh = 4; + + /* Set switch matrix to onboard(EVAL-AD5940ELECZ) dummy sensor. */ + /* Note the RCAL0 resistor is 10kOhm. */ + pImpedanceCfg->DswitchSel = SWD_CE0; + pImpedanceCfg->PswitchSel = SWP_RE0; + pImpedanceCfg->NswitchSel = SWN_SE0; + pImpedanceCfg->TswitchSel = SWT_SE0LOAD; + /* The dummy sensor is as low as 5kOhm. We need to make sure RTIA is small enough that HSTIA won't be saturated. */ + pImpedanceCfg->HstiaRtiaSel = HSTIARTIA_5K; + + /* Configure the sweep function. */ + pImpedanceCfg->SweepCfg.SweepEn = bTRUE; + pImpedanceCfg->SweepCfg.SweepStart = 1.0f; /* Start from 1kHz */ + pImpedanceCfg->SweepCfg.SweepStop = 200e3f; /* Stop at 100kHz */ + pImpedanceCfg->SweepCfg.SweepPoints = 101; /* Points is 101 */ + pImpedanceCfg->SweepCfg.SweepLog = bTRUE; + /* Configure Power Mode. Use HP mode if frequency is higher than 80kHz. */ + pImpedanceCfg->PwrMod = AFEPWR_LP; + /* Configure filters if necessary */ + pImpedanceCfg->ADCSinc3Osr = ADCSINC3OSR_2; /* Sample rate is 800kSPS/2 = 400kSPS */ + pImpedanceCfg->DftNum = DFTNUM_16384; + pImpedanceCfg->DftSrc = DFTSRC_SINC3; +} + +void AD5940_Main(void) +{ + uint32_t temp; + AD5940PlatformCfg(); + AD5940ImpedanceStructInit(); + + AppIMPInit(AppBuff, APPBUFF_SIZE); /* Initialize IMP application. Provide a buffer, which is used to store sequencer commands */ + AppIMPCtrl(IMPCTRL_START, 0); /* Control IMP measurement to start. Second parameter has no meaning with this command. */ + + while(1) + { + if(AD5940_GetMCUIntFlag()) + { + AD5940_ClrMCUIntFlag(); + temp = APPBUFF_SIZE; + AppIMPISR(AppBuff, &temp); + ImpedanceShowResult(AppBuff, temp); + } + } +} + diff --git a/examples/AD5940_Impedance_Adjustable_with_frequency/Impedance.c b/examples/AD5940_Impedance_Adjustable_with_frequency/Impedance.c new file mode 100644 index 0000000..0a0ad3c --- /dev/null +++ b/examples/AD5940_Impedance_Adjustable_with_frequency/Impedance.c @@ -0,0 +1,740 @@ +/*! + ***************************************************************************** + @file: Impedance.c + @author: Neo Xu + @brief: standard 4-wire or 2-wire impedance measurement sequences. + ----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*******************************************************************************/ +#include "ad5940.h" +#include +#include "string.h" +#include "math.h" +#include "Impedance.h" + +/* Default LPDAC resolution(2.5V internal reference). */ +#define DAC12BITVOLT_1LSB (2200.0f/4095) //mV +#define DAC6BITVOLT_1LSB (DAC12BITVOLT_1LSB*64) //mV + +/* + Application configuration structure. Specified by user from template. + The variables are usable in this whole application. + It includes basic configuration for sequencer generator and application related parameters +*/ +AppIMPCfg_Type AppIMPCfg = +{ + .bParaChanged = bFALSE, + .SeqStartAddr = 0, + .MaxSeqLen = 0, + + .SeqStartAddrCal = 0, + .MaxSeqLenCal = 0, + + .ImpODR = 0.0001, /* 20.0 Hz*/ + .NumOfData = -1, + .SysClkFreq = 16000000.0, + .WuptClkFreq = 32000.0, + .AdcClkFreq = 16000000.0, + .RcalVal = 10000.0, + + .DswitchSel = SWD_CE0, + .PswitchSel = SWP_CE0, + .NswitchSel = SWN_AIN1, + .TswitchSel = SWT_AIN1, + + .PwrMod = AFEPWR_HP, + + .HstiaRtiaSel = HSTIARTIA_5K, + .ExtRtia = 0, //set only when HstiaRtiaSel = HSTIARTIA_OPEN + .ExcitBufGain = EXCITBUFGAIN_0P25,//EXCITBUFGAIN_2, + .HsDacGain = HSDACGAIN_0P2,//HSDACGAIN_1, + .HsDacUpdateRate = 7, + .DacVoltPP = 800.0, + .BiasVolt = -0.0f, + + .SinFreq = 100000.0, /* 1000Hz */ + + .DftNum = DFTNUM_16384, + .DftSrc = DFTSRC_SINC3, + .HanWinEn = bTRUE, + + .AdcPgaGain = ADCPGA_4,//ADCPGA_1, + .ADCSinc3Osr = ADCSINC3OSR_2, + .ADCSinc2Osr = ADCSINC2OSR_22, + + .ADCAvgNum = ADCAVGNUM_16, + + .SweepCfg.SweepEn = bTRUE, + .SweepCfg.SweepStart = 1000, + .SweepCfg.SweepStop = 100000.0, + .SweepCfg.SweepPoints = 101, + .SweepCfg.SweepLog = bFALSE, + .SweepCfg.SweepIndex = 0, + + .FifoThresh = 4, + .IMPInited = bFALSE, + .StopRequired = bFALSE, +}; + +/** + This function is provided for upper controllers that want to change + application parameters specially for user defined parameters. +*/ +int32_t AppIMPGetCfg(void *pCfg) +{ + if(pCfg) + { + *(AppIMPCfg_Type**)pCfg = &AppIMPCfg; + return AD5940ERR_OK; + } + return AD5940ERR_PARA; +} + +int32_t AppIMPCtrl(uint32_t Command, void *pPara) +{ + + switch (Command) + { + case IMPCTRL_START: + { + WUPTCfg_Type wupt_cfg; + + if(AD5940_WakeUp(10) > 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + if(AppIMPCfg.IMPInited == bFALSE) + return AD5940ERR_APPERROR; + /* Start it */ + wupt_cfg.WuptEn = bTRUE; + wupt_cfg.WuptEndSeq = WUPTENDSEQ_A; + wupt_cfg.WuptOrder[0] = SEQID_0; + wupt_cfg.SeqxSleepTime[SEQID_0] = 4; + wupt_cfg.SeqxWakeupTime[SEQID_0] = (uint32_t)(AppIMPCfg.WuptClkFreq/AppIMPCfg.ImpODR)-4; + AD5940_WUPTCfg(&wupt_cfg); + + AppIMPCfg.FifoDataCount = 0; /* restart */ + break; + } + case IMPCTRL_STOPNOW: + { + if(AD5940_WakeUp(10) > 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + /* Start Wupt right now */ + AD5940_WUPTCtrl(bFALSE); + /* There is chance this operation will fail because sequencer could put AFE back + to hibernate mode just after waking up. Use STOPSYNC is better. */ + AD5940_WUPTCtrl(bFALSE); + break; + } + case IMPCTRL_STOPSYNC: + { + AppIMPCfg.StopRequired = bTRUE; + break; + } + case IMPCTRL_GETFREQ: + { + if(pPara == 0) + return AD5940ERR_PARA; + if(AppIMPCfg.SweepCfg.SweepEn == bTRUE) + *(float*)pPara = AppIMPCfg.FreqofData; + else + *(float*)pPara = AppIMPCfg.SinFreq; + } + break; + case IMPCTRL_SHUTDOWN: + { + AppIMPCtrl(IMPCTRL_STOPNOW, 0); /* Stop the measurement if it's running. */ + /* Turn off LPloop related blocks which are not controlled automatically by hibernate operation */ + AFERefCfg_Type aferef_cfg; + LPLoopCfg_Type lp_loop; + memset(&aferef_cfg, 0, sizeof(aferef_cfg)); + AD5940_REFCfgS(&aferef_cfg); + memset(&lp_loop, 0, sizeof(lp_loop)); + AD5940_LPLoopCfgS(&lp_loop); + AD5940_EnterSleepS(); /* Enter Hibernate */ + } + break; + default: + break; + } + return AD5940ERR_OK; +} + +/* generated code snnipet */ +float AppIMPGetCurrFreq(void) +{ + if(AppIMPCfg.SweepCfg.SweepEn == bTRUE) + return AppIMPCfg.FreqofData; + else + return AppIMPCfg.SinFreq; +} + +/* Application initialization */ +static AD5940Err AppIMPSeqCfgGen(void) +{ + AD5940Err error = AD5940ERR_OK; + const uint32_t *pSeqCmd; + uint32_t SeqLen; + AFERefCfg_Type aferef_cfg; + HSLoopCfg_Type HsLoopCfg; + DSPCfg_Type dsp_cfg; + float sin_freq; + + /* Start sequence generator here */ + AD5940_SEQGenCtrl(bTRUE); + + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Init all to disable state */ + + aferef_cfg.HpBandgapEn = bTRUE; + aferef_cfg.Hp1V1BuffEn = bTRUE; + aferef_cfg.Hp1V8BuffEn = bTRUE; + aferef_cfg.Disc1V1Cap = bFALSE; + aferef_cfg.Disc1V8Cap = bFALSE; + aferef_cfg.Hp1V8ThemBuff = bFALSE; + aferef_cfg.Hp1V8Ilimit = bFALSE; + aferef_cfg.Lp1V1BuffEn = bFALSE; + aferef_cfg.Lp1V8BuffEn = bFALSE; + /* LP reference control - turn off them to save power*/ + if(AppIMPCfg.BiasVolt != 0.0f) /* With bias voltage */ + { + aferef_cfg.LpBandgapEn = bTRUE; + aferef_cfg.LpRefBufEn = bTRUE; + } + else + { + aferef_cfg.LpBandgapEn = bFALSE; + aferef_cfg.LpRefBufEn = bFALSE; + } + aferef_cfg.LpRefBoostEn = bFALSE; + AD5940_REFCfgS(&aferef_cfg); + HsLoopCfg.HsDacCfg.ExcitBufGain = AppIMPCfg.ExcitBufGain; + HsLoopCfg.HsDacCfg.HsDacGain = AppIMPCfg.HsDacGain; + HsLoopCfg.HsDacCfg.HsDacUpdateRate = AppIMPCfg.HsDacUpdateRate; + + HsLoopCfg.HsTiaCfg.DiodeClose = bFALSE; + if(AppIMPCfg.BiasVolt != 0.0f) /* With bias voltage */ + HsLoopCfg.HsTiaCfg.HstiaBias = HSTIABIAS_VZERO0; + else + HsLoopCfg.HsTiaCfg.HstiaBias = HSTIABIAS_1P1; + HsLoopCfg.HsTiaCfg.HstiaCtia = 31; /* 31pF + 2pF */ + HsLoopCfg.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_OPEN; + HsLoopCfg.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_OPEN; + HsLoopCfg.HsTiaCfg.HstiaRtiaSel = AppIMPCfg.HstiaRtiaSel; + + HsLoopCfg.SWMatCfg.Dswitch = AppIMPCfg.DswitchSel; + HsLoopCfg.SWMatCfg.Pswitch = AppIMPCfg.PswitchSel; + HsLoopCfg.SWMatCfg.Nswitch = AppIMPCfg.NswitchSel; + HsLoopCfg.SWMatCfg.Tswitch = SWT_TRTIA|AppIMPCfg.TswitchSel; + + HsLoopCfg.WgCfg.WgType = WGTYPE_SIN; + HsLoopCfg.WgCfg.GainCalEn = bTRUE; + HsLoopCfg.WgCfg.OffsetCalEn = bTRUE; + if(AppIMPCfg.SweepCfg.SweepEn == bTRUE) + { + AppIMPCfg.FreqofData = AppIMPCfg.SweepCfg.SweepStart; + AppIMPCfg.SweepCurrFreq = AppIMPCfg.SweepCfg.SweepStart; + AD5940_SweepNext(&AppIMPCfg.SweepCfg, &AppIMPCfg.SweepNextFreq); + sin_freq = AppIMPCfg.SweepCurrFreq; + } + else + { + sin_freq = AppIMPCfg.SinFreq; + AppIMPCfg.FreqofData = sin_freq; + } + HsLoopCfg.WgCfg.SinCfg.SinFreqWord = AD5940_WGFreqWordCal(sin_freq, AppIMPCfg.SysClkFreq); + HsLoopCfg.WgCfg.SinCfg.SinAmplitudeWord = (uint32_t)(AppIMPCfg.DacVoltPP/800.0f*2047 + 0.5f); + HsLoopCfg.WgCfg.SinCfg.SinOffsetWord = 0; + HsLoopCfg.WgCfg.SinCfg.SinPhaseWord = 0; + AD5940_HSLoopCfgS(&HsLoopCfg); + if(AppIMPCfg.BiasVolt != 0.0f) /* With bias voltage */ + { + LPDACCfg_Type lpdac_cfg; + + lpdac_cfg.LpdacSel = LPDAC0; + lpdac_cfg.LpDacVbiasMux = LPDACVBIAS_12BIT; /* Use Vbias to tuning BiasVolt. */ + lpdac_cfg.LpDacVzeroMux = LPDACVZERO_6BIT; /* Vbias-Vzero = BiasVolt */ + lpdac_cfg.DacData6Bit = 0x40>>1; /* Set Vzero to middle scale. */ + if(AppIMPCfg.BiasVolt<-1100.0f) AppIMPCfg.BiasVolt = -1100.0f + DAC12BITVOLT_1LSB; + if(AppIMPCfg.BiasVolt> 1100.0f) AppIMPCfg.BiasVolt = 1100.0f - DAC12BITVOLT_1LSB; + lpdac_cfg.DacData12Bit = (uint32_t)((AppIMPCfg.BiasVolt + 1100.0f)/DAC12BITVOLT_1LSB); + lpdac_cfg.DataRst = bFALSE; /* Do not reset data register */ + lpdac_cfg.LpDacSW = LPDACSW_VBIAS2LPPA|LPDACSW_VBIAS2PIN|LPDACSW_VZERO2LPTIA|LPDACSW_VZERO2PIN|LPDACSW_VZERO2HSTIA; + lpdac_cfg.LpDacRef = LPDACREF_2P5; + lpdac_cfg.LpDacSrc = LPDACSRC_MMR; /* Use MMR data, we use LPDAC to generate bias voltage for LPTIA - the Vzero */ + lpdac_cfg.PowerEn = bTRUE; /* Power up LPDAC */ + AD5940_LPDACCfgS(&lpdac_cfg); + } + dsp_cfg.ADCBaseCfg.ADCMuxN = ADCMUXN_HSTIA_N; + dsp_cfg.ADCBaseCfg.ADCMuxP = ADCMUXP_HSTIA_P; + dsp_cfg.ADCBaseCfg.ADCPga = AppIMPCfg.AdcPgaGain; + + memset(&dsp_cfg.ADCDigCompCfg, 0, sizeof(dsp_cfg.ADCDigCompCfg)); + + dsp_cfg.ADCFilterCfg.ADCAvgNum = AppIMPCfg.ADCAvgNum; + dsp_cfg.ADCFilterCfg.ADCRate = ADCRATE_800KHZ; /* Tell filter block clock rate of ADC*/ + dsp_cfg.ADCFilterCfg.ADCSinc2Osr = AppIMPCfg.ADCSinc2Osr; + dsp_cfg.ADCFilterCfg.ADCSinc3Osr = AppIMPCfg.ADCSinc3Osr; + dsp_cfg.ADCFilterCfg.BpNotch = bTRUE; + dsp_cfg.ADCFilterCfg.BpSinc3 = bFALSE; + dsp_cfg.ADCFilterCfg.Sinc2NotchEnable = bTRUE; + dsp_cfg.DftCfg.DftNum = AppIMPCfg.DftNum; + dsp_cfg.DftCfg.DftSrc = AppIMPCfg.DftSrc; + dsp_cfg.DftCfg.HanWinEn = AppIMPCfg.HanWinEn; + + memset(&dsp_cfg.StatCfg, 0, sizeof(dsp_cfg.StatCfg)); + AD5940_DSPCfgS(&dsp_cfg); + + /* Enable all of them. They are automatically turned off during hibernate mode to save power */ + if(AppIMPCfg.BiasVolt == 0.0f) + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\ + AFECTRL_WG|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|\ + AFECTRL_SINC2NOTCH, bTRUE); + else + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\ + AFECTRL_WG|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|\ + AFECTRL_SINC2NOTCH|AFECTRL_DCBUFPWR, bTRUE); + /* Sequence end. */ + AD5940_SEQGenInsert(SEQ_STOP()); /* Add one extra command to disable sequencer for initialization sequence because we only want it to run one time. */ + + /* Stop here */ + error = AD5940_SEQGenFetchSeq(&pSeqCmd, &SeqLen); + AD5940_SEQGenCtrl(bFALSE); /* Stop sequencer generator */ + if(error == AD5940ERR_OK) + { + AppIMPCfg.InitSeqInfo.SeqId = SEQID_1; + AppIMPCfg.InitSeqInfo.SeqRamAddr = AppIMPCfg.SeqStartAddr; + AppIMPCfg.InitSeqInfo.pSeqCmd = pSeqCmd; + AppIMPCfg.InitSeqInfo.SeqLen = SeqLen; + /* Write command to SRAM */ + AD5940_SEQCmdWrite(AppIMPCfg.InitSeqInfo.SeqRamAddr, pSeqCmd, SeqLen); + } + else + return error; /* Error */ + return AD5940ERR_OK; +} + + +static AD5940Err AppIMPSeqMeasureGen(void) +{ + AD5940Err error = AD5940ERR_OK; + const uint32_t *pSeqCmd; + uint32_t SeqLen; + + uint32_t WaitClks; + SWMatrixCfg_Type sw_cfg; + ClksCalInfo_Type clks_cal; + + clks_cal.DataType = DATATYPE_DFT; + clks_cal.DftSrc = AppIMPCfg.DftSrc; + clks_cal.DataCount = 1L<<(AppIMPCfg.DftNum+2); /* 2^(DFTNUMBER+2) */ + clks_cal.ADCSinc2Osr = AppIMPCfg.ADCSinc2Osr; + clks_cal.ADCSinc3Osr = AppIMPCfg.ADCSinc3Osr; + clks_cal.ADCAvgNum = AppIMPCfg.ADCAvgNum; + clks_cal.RatioSys2AdcClk = AppIMPCfg.SysClkFreq/AppIMPCfg.AdcClkFreq; + AD5940_ClksCalculate(&clks_cal, &WaitClks); + + AD5940_SEQGenCtrl(bTRUE); + AD5940_SEQGpioCtrlS(AGPIO_Pin2); /* Set GPIO1, clear others that under control */ + AD5940_SEQGenInsert(SEQ_WAIT(16*250)); /* @todo wait 250us? */ + sw_cfg.Dswitch = SWD_RCAL0; + sw_cfg.Pswitch = SWP_RCAL0; + sw_cfg.Nswitch = SWN_RCAL1; + sw_cfg.Tswitch = SWT_RCAL1|SWT_TRTIA; + AD5940_SWMatrixCfgS(&sw_cfg); + + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\ + AFECTRL_WG|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|\ + AFECTRL_SINC2NOTCH, bTRUE); + AD5940_AFECtrlS(AFECTRL_WG|AFECTRL_ADCPWR, bTRUE); /* Enable Waveform generator */ + //delay for signal settling DFT_WAIT + AD5940_SEQGenInsert(SEQ_WAIT(16*10)); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT, bTRUE); /* Start ADC convert and DFT */ + + AD5940_SEQGenFetchSeq(NULL, &AppIMPCfg.SeqWaitAddr[0]); /* Record the start address of the next command. */ + + AD5940_SEQGenInsert(SEQ_WAIT(WaitClks/2)); + AD5940_SEQGenInsert(SEQ_WAIT(WaitClks/2)); + + //wait for first data ready + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_ADCCNV|AFECTRL_DFT|AFECTRL_WG, bFALSE); /* Stop ADC convert and DFT */ + + /* Configure matrix for external Rz */ + sw_cfg.Dswitch = AppIMPCfg.DswitchSel; + sw_cfg.Pswitch = AppIMPCfg.PswitchSel; + sw_cfg.Nswitch = AppIMPCfg.NswitchSel; + sw_cfg.Tswitch = SWT_TRTIA|AppIMPCfg.TswitchSel; + AD5940_SWMatrixCfgS(&sw_cfg); + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_WG, bTRUE); /* Enable Waveform generator */ + AD5940_SEQGenInsert(SEQ_WAIT(16*10)); //delay for signal settling DFT_WAIT + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT, bTRUE); /* Start ADC convert and DFT */ + + AD5940_SEQGenFetchSeq(NULL, &AppIMPCfg.SeqWaitAddr[1]); /* Record the start address of next command */ + + AD5940_SEQGenInsert(SEQ_WAIT(WaitClks/2)); + AD5940_SEQGenInsert(SEQ_WAIT(WaitClks/2)); + + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT|AFECTRL_WG|AFECTRL_ADCPWR, bFALSE); /* Stop ADC convert and DFT */ + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\ + AFECTRL_WG|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|\ + AFECTRL_SINC2NOTCH, bFALSE); + AD5940_SEQGpioCtrlS(0); /* Clr GPIO1 */ + + AD5940_EnterSleepS();/* Goto hibernate */ + + /* Sequence end. */ + error = AD5940_SEQGenFetchSeq(&pSeqCmd, &SeqLen); + AD5940_SEQGenCtrl(bFALSE); /* Stop sequencer generator */ + + if(error == AD5940ERR_OK) + { + AppIMPCfg.MeasureSeqInfo.SeqId = SEQID_0; + AppIMPCfg.MeasureSeqInfo.SeqRamAddr = AppIMPCfg.InitSeqInfo.SeqRamAddr + AppIMPCfg.InitSeqInfo.SeqLen ; + AppIMPCfg.MeasureSeqInfo.pSeqCmd = pSeqCmd; + AppIMPCfg.MeasureSeqInfo.SeqLen = SeqLen; + /* Write command to SRAM */ + AD5940_SEQCmdWrite(AppIMPCfg.MeasureSeqInfo.SeqRamAddr, pSeqCmd, SeqLen); + } + else + return error; /* Error */ + return AD5940ERR_OK; +} + +/* Depending on frequency of Sin wave set optimum filter settings */ +AD5940Err AppIMPCheckFreq(float freq) +{ + ADCFilterCfg_Type filter_cfg; + DFTCfg_Type dft_cfg; + HSDACCfg_Type hsdac_cfg; + uint32_t WaitClks; + ClksCalInfo_Type clks_cal; + FreqParams_Type freq_params; + uint32_t SeqCmdBuff[32]; + uint32_t SRAMAddr = 0;; + /* Step 1: Check Frequency */ + freq_params = AD5940_GetFreqParameters(freq); + + if(freq < 0.51) + { + /* Update HSDAC update rate */ + hsdac_cfg.ExcitBufGain =EXCITBUFGAIN_2;// AppIMPCfg.ExcitBufGain; + hsdac_cfg.HsDacGain = HSDACGAIN_1;//AppIMPCfg.HsDacGain; + hsdac_cfg.HsDacUpdateRate = 0x1B; + AD5940_HSDacCfgS(&hsdac_cfg); + AD5940_HSRTIACfgS(HSTIARTIA_40K); //set as per load current range + + /*Update ADC rate */ + filter_cfg.ADCRate = ADCRATE_800KHZ; + AppIMPCfg.AdcClkFreq = 16e6; + + /* Change clock to 16MHz oscillator */ + AD5940_HPModeEn(bFALSE); + } + else if(freq < 5 ) + { + /* Update HSDAC update rate */ + hsdac_cfg.ExcitBufGain =EXCITBUFGAIN_2;// AppIMPCfg.ExcitBufGain; + hsdac_cfg.HsDacGain = HSDACGAIN_1;//AppIMPCfg.HsDacGain; + hsdac_cfg.HsDacUpdateRate = 0x1B; + AD5940_HSDacCfgS(&hsdac_cfg); + AD5940_HSRTIACfgS(HSTIARTIA_40K); //set as per load current range + + /*Update ADC rate */ + filter_cfg.ADCRate = ADCRATE_800KHZ; + AppIMPCfg.AdcClkFreq = 16e6; + + /* Change clock to 16MHz oscillator */ + AD5940_HPModeEn(bFALSE); + + }else if(freq < 450) + { + /* Update HSDAC update rate */ + hsdac_cfg.ExcitBufGain =AppIMPCfg.ExcitBufGain; + hsdac_cfg.HsDacGain = AppIMPCfg.HsDacGain; + + hsdac_cfg.HsDacUpdateRate = 0x1B; + AD5940_HSDacCfgS(&hsdac_cfg); + AD5940_HSRTIACfgS(HSTIARTIA_5K); //set as per load current range + + /*Update ADC rate */ + filter_cfg.ADCRate = ADCRATE_800KHZ; + AppIMPCfg.AdcClkFreq = 16e6; + + /* Change clock to 16MHz oscillator */ + AD5940_HPModeEn(bFALSE); + } + else if(freq<80000) + { + /* Update HSDAC update rate */ + hsdac_cfg.ExcitBufGain =AppIMPCfg.ExcitBufGain; + hsdac_cfg.HsDacGain = AppIMPCfg.HsDacGain; + hsdac_cfg.HsDacUpdateRate = 0x1B; + AD5940_HSDacCfgS(&hsdac_cfg); + AD5940_HSRTIACfgS(HSTIARTIA_5K); //set as per load current range + + /*Update ADC rate */ + filter_cfg.ADCRate = ADCRATE_800KHZ; + AppIMPCfg.AdcClkFreq = 16e6; + + /* Change clock to 16MHz oscillator */ + AD5940_HPModeEn(bFALSE); + } + /* High power mode */ + if(freq >= 80000) + { + /* Update HSDAC update rate */ + hsdac_cfg.ExcitBufGain =AppIMPCfg.ExcitBufGain; + hsdac_cfg.HsDacGain = AppIMPCfg.HsDacGain; + hsdac_cfg.HsDacUpdateRate = 0x07; + AD5940_HSDacCfgS(&hsdac_cfg); + AD5940_HSRTIACfgS(HSTIARTIA_5K); //set as per load current range + + /*Update ADC rate */ + filter_cfg.ADCRate = ADCRATE_1P6MHZ; + AppIMPCfg.AdcClkFreq = 32e6; + + /* Change clock to 32MHz oscillator */ + AD5940_HPModeEn(bTRUE); + } + + /* Step 2: Adjust ADCFILTERCON and DFTCON to set optimumn SINC3, SINC2 and DFTNUM settings */ + filter_cfg.ADCAvgNum = ADCAVGNUM_16; /* Don't care because it's disabled */ + filter_cfg.ADCSinc2Osr = freq_params.ADCSinc2Osr; + filter_cfg.ADCSinc3Osr = freq_params.ADCSinc3Osr; + filter_cfg.BpSinc3 = bFALSE; + filter_cfg.BpNotch = bTRUE; + filter_cfg.Sinc2NotchEnable = bTRUE; + dft_cfg.DftNum = freq_params.DftNum; + dft_cfg.DftSrc = freq_params.DftSrc; + dft_cfg.HanWinEn = AppIMPCfg.HanWinEn; + AD5940_ADCFilterCfgS(&filter_cfg); + AD5940_DFTCfgS(&dft_cfg); + + /* Step 3: Calculate clocks needed to get result to FIFO and update sequencer wait command */ + clks_cal.DataType = DATATYPE_DFT; + clks_cal.DftSrc = freq_params.DftSrc; + clks_cal.DataCount = 1L<<(freq_params.DftNum+2); /* 2^(DFTNUMBER+2) */ + clks_cal.ADCSinc2Osr = freq_params.ADCSinc2Osr; + clks_cal.ADCSinc3Osr = freq_params.ADCSinc3Osr; + clks_cal.ADCAvgNum = 0; + clks_cal.RatioSys2AdcClk = AppIMPCfg.SysClkFreq/AppIMPCfg.AdcClkFreq; + AD5940_ClksCalculate(&clks_cal, &WaitClks); + + + SRAMAddr = AppIMPCfg.MeasureSeqInfo.SeqRamAddr + AppIMPCfg.SeqWaitAddr[0]; + + SeqCmdBuff[0] =SEQ_WAIT(WaitClks/2); + SeqCmdBuff[1] =SEQ_WAIT(WaitClks/2); + + AD5940_SEQCmdWrite(SRAMAddr, SeqCmdBuff, 2); + + SRAMAddr = AppIMPCfg.MeasureSeqInfo.SeqRamAddr + AppIMPCfg.SeqWaitAddr[1]; + + SeqCmdBuff[0] =SEQ_WAIT(WaitClks/2); + SeqCmdBuff[1] =SEQ_WAIT(WaitClks/2); + + AD5940_SEQCmdWrite(SRAMAddr, SeqCmdBuff, 2); + + + return AD5940ERR_OK; +} + + +/* This function provide application initialize. It can also enable Wupt that will automatically trigger sequence. Or it can configure */ +int32_t AppIMPInit(uint32_t *pBuffer, uint32_t BufferSize) +{ + AD5940Err error = AD5940ERR_OK; + SEQCfg_Type seq_cfg; + FIFOCfg_Type fifo_cfg; + + if(AD5940_WakeUp(10) > 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + + /* Configure sequencer and stop it */ + seq_cfg.SeqMemSize = SEQMEMSIZE_2KB; /* 2kB SRAM is used for sequencer, others for data FIFO */ + seq_cfg.SeqBreakEn = bFALSE; + seq_cfg.SeqIgnoreEn = bTRUE; + seq_cfg.SeqCntCRCClr = bTRUE; + seq_cfg.SeqEnable = bFALSE; + seq_cfg.SeqWrTimer = 0; + AD5940_SEQCfg(&seq_cfg); + + + /* Reconfigure FIFO */ + AD5940_FIFOCtrlS(FIFOSRC_DFT, bFALSE); /* Disable FIFO firstly */ + fifo_cfg.FIFOEn = bTRUE; + fifo_cfg.FIFOMode = FIFOMODE_FIFO; + fifo_cfg.FIFOSize = FIFOSIZE_4KB; /* 4kB for FIFO, The reset 2kB for sequencer */ + fifo_cfg.FIFOSrc = FIFOSRC_DFT; + fifo_cfg.FIFOThresh = AppIMPCfg.FifoThresh; /* DFT result. One pair for RCAL, another for Rz. One DFT result have real part and imaginary part */ + AD5940_FIFOCfg(&fifo_cfg); + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + + /* Start sequence generator */ + /* Initialize sequencer generator */ + if((AppIMPCfg.IMPInited == bFALSE)||\ + (AppIMPCfg.bParaChanged == bTRUE)) + { + if(pBuffer == 0) return AD5940ERR_PARA; + if(BufferSize == 0) return AD5940ERR_PARA; + AD5940_SEQGenInit(pBuffer, BufferSize); + + /* Generate initialize sequence */ + error = AppIMPSeqCfgGen(); /* Application initialization sequence using either MCU or sequencer */ + if(error != AD5940ERR_OK) return error; + + /* Generate measurement sequence */ + error = AppIMPSeqMeasureGen(); + if(error != AD5940ERR_OK) return error; + + AppIMPCfg.bParaChanged = bFALSE; /* Clear this flag as we already implemented the new configuration */ + } + + /* Initialization sequencer */ + AppIMPCfg.InitSeqInfo.WriteSRAM = bFALSE; + AD5940_SEQInfoCfg(&AppIMPCfg.InitSeqInfo); + seq_cfg.SeqEnable = bTRUE; + AD5940_SEQCfg(&seq_cfg); /* Enable sequencer */ + AD5940_SEQMmrTrig(AppIMPCfg.InitSeqInfo.SeqId); + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_ENDSEQ) == bFALSE); + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + /* Measurement sequence */ + AppIMPCfg.MeasureSeqInfo.WriteSRAM = bFALSE; + AD5940_SEQInfoCfg(&AppIMPCfg.MeasureSeqInfo); + + AppIMPCheckFreq(AppIMPCfg.FreqofData); + + seq_cfg.SeqEnable = bTRUE; + AD5940_SEQCfg(&seq_cfg); /* Enable sequencer, and wait for trigger */ + AD5940_ClrMCUIntFlag(); /* Clear interrupt flag generated before */ + + //AD5940_AFEPwrBW(AppIMPCfg.PwrMod, AFEBW_250KHZ); + + AppIMPCfg.IMPInited = bTRUE; /* IMP application has been initialized. */ + return AD5940ERR_OK; +} + +/* Modify registers when AFE wakeup */ +int32_t AppIMPRegModify(int32_t * const pData, uint32_t *pDataCount) +{ + if(AppIMPCfg.NumOfData > 0) + { + AppIMPCfg.FifoDataCount += *pDataCount/4; + if(AppIMPCfg.FifoDataCount >= AppIMPCfg.NumOfData) + { + AD5940_WUPTCtrl(bFALSE); + return AD5940ERR_OK; + } + } + if(AppIMPCfg.StopRequired == bTRUE) + { + AD5940_WUPTCtrl(bFALSE); + return AD5940ERR_OK; + } + if(AppIMPCfg.SweepCfg.SweepEn) /* Need to set new frequency and set power mode */ + { + AD5940_WGFreqCtrlS(AppIMPCfg.SweepNextFreq, AppIMPCfg.SysClkFreq); + AppIMPCheckFreq(AppIMPCfg.SweepNextFreq); + } + return AD5940ERR_OK; +} + +/* Depending on the data type, do appropriate data pre-process before return back to controller */ +int32_t AppIMPDataProcess(int32_t * const pData, uint32_t *pDataCount) +{ + uint32_t DataCount = *pDataCount; + uint32_t ImpResCount = DataCount/4; + + fImpPol_Type * const pOut = (fImpPol_Type*)pData; + iImpCar_Type * pSrcData = (iImpCar_Type*)pData; + + *pDataCount = 0; + + DataCount = (DataCount/4)*4;/* We expect RCAL data together with Rz data. One DFT result has two data in FIFO, real part and imaginary part. */ + + /* Convert DFT result to int32_t type */ + for(uint32_t i=0; iReal*pDftRcal->Real+(float)pDftRcal->Image*pDftRcal->Image); + RcalPhase = atan2(-pDftRcal->Image,pDftRcal->Real); + RzMag = sqrt((float)pDftRz->Real*pDftRz->Real+(float)pDftRz->Image*pDftRz->Image); + RzPhase = atan2(-pDftRz->Image,pDftRz->Real); + + RzMag = RcalMag/RzMag*AppIMPCfg.RcalVal; + RzPhase = RcalPhase - RzPhase; + //printf("V:%d,%d,I:%d,%d ",pDftRcal->Real,pDftRcal->Image, pDftRz->Real, pDftRz->Image); + + pOut[i].Magnitude = RzMag; + pOut[i].Phase = RzPhase; + } + *pDataCount = ImpResCount; + AppIMPCfg.FreqofData = AppIMPCfg.SweepCurrFreq; + /* Calculate next frequency point */ + if(AppIMPCfg.SweepCfg.SweepEn == bTRUE) + { + AppIMPCfg.FreqofData = AppIMPCfg.SweepCurrFreq; + AppIMPCfg.SweepCurrFreq = AppIMPCfg.SweepNextFreq; + AD5940_SweepNext(&AppIMPCfg.SweepCfg, &AppIMPCfg.SweepNextFreq); + } + + return 0; +} + +/** + +*/ +int32_t AppIMPISR(void *pBuff, uint32_t *pCount) +{ + uint32_t BuffCount; + uint32_t FifoCnt; + BuffCount = *pCount; + + *pCount = 0; + + if(AD5940_WakeUp(10) > 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + AD5940_SleepKeyCtrlS(SLPKEY_LOCK); /* Prohibit AFE to enter sleep mode. */ + + if(AD5940_INTCTestFlag(AFEINTC_0, AFEINTSRC_DATAFIFOTHRESH) == bTRUE) + { + /* Now there should be 4 data in FIFO */ + FifoCnt = (AD5940_FIFOGetCnt()/4)*4; + + if(FifoCnt > BuffCount) + { + ///@todo buffer is limited. + } + AD5940_FIFORd((uint32_t *)pBuff, FifoCnt); + AD5940_INTCClrFlag(AFEINTSRC_DATAFIFOTHRESH); + AppIMPRegModify(pBuff, &FifoCnt); /* If there is need to do AFE re-configure, do it here when AFE is in active state */ + //AD5940_EnterSleepS(); /* Manually put AFE back to hibernate mode. This operation only takes effect when register value is ACTIVE previously */ + AD5940_SleepKeyCtrlS(SLPKEY_UNLOCK); /* Allow AFE to enter sleep mode. */ + /* Process data */ + AppIMPDataProcess((int32_t*)pBuff,&FifoCnt); + *pCount = FifoCnt; + return 0; + } + + return 0; +} + + diff --git a/examples/AD5940_Impedance_Adjustable_with_frequency/Impedance.h b/examples/AD5940_Impedance_Adjustable_with_frequency/Impedance.h new file mode 100644 index 0000000..c24cdf5 --- /dev/null +++ b/examples/AD5940_Impedance_Adjustable_with_frequency/Impedance.h @@ -0,0 +1,85 @@ +/*! + ***************************************************************************** + @file: Impedance.h + @author: Neo XU + @brief: 4-wire/2-wire impedance measurement header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*****************************************************************************/ +#ifndef _IMPEDANCESEQUENCES_H_ +#define _IMPEDANCESEQUENCES_H_ +#include "ad5940.h" +#include +#include "string.h" +#include "math.h" + +typedef struct +{ +/* Common configurations for all kinds of Application. */ + BoolFlag bParaChanged; /* Indicate to generate sequence again. It's auto cleared by AppBIAInit */ + uint32_t SeqStartAddr; /* Initialaztion sequence start address in SRAM of AD5940 */ + uint32_t MaxSeqLen; /* Limit the maximum sequence. */ + uint32_t SeqStartAddrCal; /* Measurement sequence start address in SRAM of AD5940 */ + uint32_t SeqWaitAddr[2]; + uint32_t MaxSeqLenCal; +/* Application related parameters */ + float ImpODR; /* */ + int32_t NumOfData; /* By default it's '-1'. If you want the engine stops after get NumofData, then set the value here. Otherwise, set it to '-1' which means never stop. */ + float WuptClkFreq; /* The clock frequency of Wakeup Timer in Hz. Typically it's 32kHz. Leave it here in case we calibrate clock in software method */ + float SysClkFreq; /* The real frequency of system clock */ + float AdcClkFreq; /* The real frequency of ADC clock */ + float RcalVal; /* Rcal value in Ohm */ + /* Switch Configuration */ + uint32_t DswitchSel; + uint32_t PswitchSel; + uint32_t NswitchSel; + uint32_t TswitchSel; + uint32_t PwrMod; /* Control Chip power mode(LP/HP) */ + uint32_t HstiaRtiaSel; /* Use internal RTIA, select from RTIA_INT_200, RTIA_INT_1K, RTIA_INT_5K, RTIA_INT_10K, RTIA_INT_20K, RTIA_INT_40K, RTIA_INT_80K, RTIA_INT_160K */ + uint32_t ExcitBufGain; /* Select from EXCTBUFGAIN_2, EXCTBUFGAIN_0P25 */ + uint32_t HsDacGain; /* Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + uint32_t HsDacUpdateRate; + float DacVoltPP; /* DAC output voltage in mV peak to peak. Maximum value is 800mVpp. Peak to peak voltage */ + float BiasVolt; /* The excitation signal is DC+AC. This parameter decides the DC value in mV unit. 0.0mV means no DC bias.*/ + float SinFreq; /* Frequency of excitation signal */ + uint32_t DftNum; /* DFT number */ + uint32_t DftSrc; /* DFT Source */ + BoolFlag HanWinEn; /* Enable Hanning window */ + uint32_t AdcPgaGain; /* PGA Gain select from GNPGA_1, GNPGA_1_5, GNPGA_2, GNPGA_4, GNPGA_9 !!! We must ensure signal is in range of +-1.5V which is limited by ADC input stage */ + uint8_t ADCSinc3Osr; + uint8_t ADCSinc2Osr; + uint8_t ADCAvgNum; + /* Sweep Function Control */ + SoftSweepCfg_Type SweepCfg; + uint32_t FifoThresh; /* FIFO threshold. Should be N*4 */ +/* Private variables for internal usage */ +/* Private variables for internal usage */ + float SweepCurrFreq; + float SweepNextFreq; + float FreqofData; /* The frequency of latest data sampled */ + BoolFlag IMPInited; /* If the program run firstly, generated sequence commands */ + SEQInfo_Type InitSeqInfo; + SEQInfo_Type MeasureSeqInfo; + BoolFlag StopRequired; /* After FIFO is ready, stop the measurement sequence */ + uint32_t FifoDataCount; /* Count how many times impedance have been measured */ +}AppIMPCfg_Type; + +#define IMPCTRL_START 0 +#define IMPCTRL_STOPNOW 1 +#define IMPCTRL_STOPSYNC 2 +#define IMPCTRL_GETFREQ 3 /* Get Current frequency of returned data from ISR */ +#define IMPCTRL_SHUTDOWN 4 /* Note: shutdown here means turn off everything and put AFE to hibernate mode. The word 'SHUT DOWN' is only used here. */ + + +int32_t AppIMPInit(uint32_t *pBuffer, uint32_t BufferSize); +int32_t AppIMPGetCfg(void *pCfg); +int32_t AppIMPISR(void *pBuff, uint32_t *pCount); +int32_t AppIMPCtrl(uint32_t Command, void *pPara); + +#endif diff --git a/examples/sequencer/AD5940_Sequencer.c b/examples/sequencer/AD5940_Sequencer.c new file mode 100644 index 0000000..539a6b3 --- /dev/null +++ b/examples/sequencer/AD5940_Sequencer.c @@ -0,0 +1,320 @@ +/*! + ***************************************************************************** + @file: AD5940_Sequencer.c + @author: Neo Xu + @brief: Basic usage of sequencer. + ----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*****************************************************************************/ + +/** + * Sequencer is used to control the AFE automatically. It can execute commands that + * is pre-loaded to SRAM. There are 6kB SRAM available while you can choose to use + * 2kB or 4kB of it and use reset of SRAM for data FIFO. + * There are 3 commands available. We mainly use only two commands: + * - Write register + * - Wait + * We control the AFE by registers, so with sequencer, we can do almost everything. + * + * Once sequencer is enabled, it starts to wait valid trigger signal. Sequencer can + * manage 4sequences at same time. You can choose which sequence you want to trigger. + * To make the AFE can manage measurement automatically, there are three method to + * trigger sequence. + * - MMR. You can trigger any sequence by register write. Or call function @ref AD5940_SEQMmrTrig + * - GPIO. You can trigger any sequence by GPIO. To use this, you must firstly set + * GPIO function to GPx_TRIG. Where x is the GPIO number. GPIO0 is used to trigger + * Sequence0 and GPIO3 is used to trigger Sequence3. Check the macro definition to + * Check the details (or below table). + * |GPIO|WhichSequence| + * |GP0|SEQUENCE0| + * |GP1|SEQUENCE1| + * |GP2|SEQUENCE2| + * |GP3|SEQUENCE3| + * |GP4|SEQUENCE0| + * |GP5|SEQUENCE1| + * |GP6|SEQUENCE2| + * |GP7|SEQUENCE3| + * - WakeupTimer. Wakeuptimer can automatically wakeup AFE from hibernate state and trigger selected + * sequence in register SEQORDER. This register defines the order of sequence that + * Wakeuptimer will trigger. There are 8 slots in this register. You can fill in any + * of the four sequences. Also, you can choose not to use all these 8 slots, just simply + * specify the end slot. We call the 8 slots are A/B/C/D/E/F/G/H. For example you can + * choose the end slot as C. So wakeup timer will trigger the sequence in below order: + * A->B->C->A->B->C->A->B->C->... until you stop Wakeuptimer. + * If you fill in slot A with sequence0, B with Sequence3, C with sequence1, the sequence + * will be executed in the order defined above(A-B-C-A-B-C...) + * SEQ0->SEQ3->SEQ1->SEQ0->SEQ3->SEQ1->... + * For each sequence, there is a sleep timer and a wakeup timer. The timer will automatically + * load corresponding value. + * The structure @ref WUPTCfg_Type can be used to initialize all above settings. + * + * In this example, we use both three kinds of trigger source. + * We firstly use Wakeup Timer to trigger sequence 0/1/2. The sequence is used to write registers and + * generate a custom-interrupt. We detect the interrupt to identify which sequence is running. + * Finally, we use GPIO to trigger sequence3. + * + * When there is conflict between trigger signals, for example, GPIO triggered one sequence that is running, + * current strategy is ignore this trigger. + * Use @reg SEQCfg_Type to configure sequencer. + * + * @note: connect GP2 and GP1 together. This demo show how to use GPIO to trigger sequencer. GP2 is the trigger input. + * We use GP1 to generate the trigger signal, while in real case, it should be the MCU's GPIO. +*/ +#include "ad5940.h" +#include +#include "string.h" + +int32_t SeqISR(void); +BoolFlag bSeqEnd = bFALSE; +static const uint32_t Seq0Commands[]= +{ + SEQ_WR(REG_AFE_SWCON, 0x0000), + SEQ_INT0(), /* generate custom-interrupt 0. We can generate any custom interrupt(SEQ_INT0/1/2/3()) by sequencer. */ +}; + +static const uint32_t Seq1Commands[]= +{ + SEQ_WR(REG_AFE_SWCON, 0x1111), + SEQ_INT1(), /* generate custom-interrupt 0 */ + SEQ_STOP(), /* Disable sequencer */ +}; + +static const uint32_t Seq2Commands[]= +{ + SEQ_WR(REG_AFE_SWCON, 0x2222), + SEQ_INT2(), /* generate custom-interrupt 1 */ +}; + +static const uint32_t Seq3Commands[]= +{ + SEQ_WR(REG_AFE_SWCON, 0x3333), + SEQ_INT3(), /* generate custom-interrupt 1 */ +}; + +static int32_t AD5940PlatformCfg(void) +{ + CLKCfg_Type clk_cfg; + FIFOCfg_Type fifo_cfg; + AGPIOCfg_Type gpio_cfg; + + /* Use hardware reset */ + AD5940_HWReset(); + AD5940_Initialize(); /* Call this right after AFE reset */ + /* Platform configuration */ + /* Step1. Configure clock */ + clk_cfg.ADCClkDiv = ADCCLKDIV_1; + clk_cfg.ADCCLkSrc = ADCCLKSRC_HFOSC; + clk_cfg.SysClkDiv = SYSCLKDIV_1; + clk_cfg.SysClkSrc = SYSCLKSRC_HFOSC; + clk_cfg.HfOSC32MHzMode = bFALSE; + clk_cfg.HFOSCEn = bTRUE; + clk_cfg.HFXTALEn = bFALSE; + clk_cfg.LFOSCEn = bTRUE; + AD5940_CLKCfg(&clk_cfg); + /* Step2. Configure FIFO and Sequencer*/ + fifo_cfg.FIFOEn = bFALSE; + fifo_cfg.FIFOMode = FIFOMODE_FIFO; + fifo_cfg.FIFOSize = FIFOSIZE_4KB; /* 4kB for FIFO, The reset 2kB for sequencer */ + fifo_cfg.FIFOSrc = FIFOSRC_DFT; + fifo_cfg.FIFOThresh = 4;//AppIMPCfg.FifoThresh; /* DFT result. One pair for RCAL, another for Rz. One DFT result have real part and imaginary part */ + AD5940_FIFOCfg(&fifo_cfg); + fifo_cfg.FIFOEn = bTRUE; + AD5940_FIFOCfg(&fifo_cfg); + + /* Step3. Interrupt controller */ + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_ALLINT, bTRUE); /* Enable all interrupt in INTC1, so we can check INTC flags */ + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + AD5940_INTCCfg(AFEINTC_0, AFEINTSRC_ENDSEQ|AFEINTSRC_CUSTOMINT0|AFEINTSRC_CUSTOMINT1|AFEINTSRC_CUSTOMINT2|AFEINTSRC_CUSTOMINT3, bTRUE); + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + /* Step4: Reconfigure GPIO */ + /* GP0: the interrupt output. + GP1: normal GPIO + GP2: used as trigger to sequence2. If valid trigger signal detected, sequencer will try to run sequence2. + GP3: not used. + GP4: controlled by sequencer. + Others: not used. The default function is mode0. + */ + gpio_cfg.FuncSet = GP0_INT|GP1_GPIO|GP2_TRIG|GP4_SYNC; + gpio_cfg.InputEnSet = AGPIO_Pin2; + gpio_cfg.OutputEnSet = AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin2|AGPIO_Pin4; + gpio_cfg.OutVal = 0; + gpio_cfg.PullEnSet = 0; + AD5940_AGPIOCfg(&gpio_cfg); + return 0; +} + +#define SEQ0ADDR 0 +#define SEQ1ADDR 16 +#define SEQ2ADDR 32 +#define SEQ3ADDR 48 + +void AD5940_Main(void) +{ + SEQCfg_Type seq_cfg; + FIFOCfg_Type fifo_cfg; + WUPTCfg_Type wupt_cfg; + SEQInfo_Type seqinfo0, seqinfo1, seqinfo2, seqinfo3; + SeqGpioTrig_Cfg seqgpiotrig_cfg; + AD5940PlatformCfg(); + + /* Configure sequencer and stop it */ + seq_cfg.SeqMemSize = SEQMEMSIZE_2KB; /* 2kB SRAM is used for sequencer, others for data FIFO */ + seq_cfg.SeqBreakEn = bFALSE; + seq_cfg.SeqIgnoreEn = bTRUE; + seq_cfg.SeqCntCRCClr = bTRUE; + seq_cfg.SeqEnable = bTRUE; + seq_cfg.SeqWrTimer = 0; + AD5940_SEQCfg(&seq_cfg); + + /* Reconfigure FIFO */ + AD5940_FIFOCtrlS(FIFOSRC_DFT, bFALSE); /* Disable FIFO firstly */ + fifo_cfg.FIFOEn = bTRUE; + fifo_cfg.FIFOMode = FIFOMODE_FIFO; + fifo_cfg.FIFOSize = FIFOSIZE_4KB; /* 4kB for FIFO, The reset 2kB for sequencer */ + fifo_cfg.FIFOSrc = FIFOSRC_SINC3; + fifo_cfg.FIFOThresh = 4; + AD5940_FIFOCfg(&fifo_cfg); + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + + seqinfo0.pSeqCmd = Seq0Commands; + seqinfo0.SeqId = SEQID_0; + seqinfo0.SeqLen = SEQ_LEN(Seq0Commands); + seqinfo0.SeqRamAddr = SEQ0ADDR; + seqinfo0.WriteSRAM = bTRUE; + AD5940_SEQInfoCfg(&seqinfo0); /* Configure sequence0 info and write commands to SRAM */ + + seqinfo1.pSeqCmd = Seq1Commands; + seqinfo1.SeqId = SEQID_1; + seqinfo1.SeqLen = SEQ_LEN(Seq1Commands); + seqinfo1.SeqRamAddr = SEQ1ADDR; + seqinfo1.WriteSRAM = bTRUE; + AD5940_SEQInfoCfg(&seqinfo1); + + seqinfo2.pSeqCmd = Seq2Commands; + seqinfo2.SeqId = SEQID_2; + seqinfo2.SeqLen = SEQ_LEN(Seq2Commands); + seqinfo2.SeqRamAddr = SEQ2ADDR; + seqinfo2.WriteSRAM = bTRUE; + AD5940_SEQInfoCfg(&seqinfo2); + + seqinfo3.pSeqCmd = Seq3Commands; + seqinfo3.SeqId = SEQID_3; + seqinfo3.SeqLen = SEQ_LEN(Seq3Commands); + seqinfo3.SeqRamAddr = SEQ3ADDR; + seqinfo3.WriteSRAM = bTRUE; + AD5940_SEQInfoCfg(&seqinfo3); + + /* Configure wakeup timer */ + wupt_cfg.WuptEn = bFALSE; /* Don't start it right now. */ + wupt_cfg.WuptEndSeq = WUPTENDSEQ_C; /* A->B->C->A->B-C */ + wupt_cfg.WuptOrder[0] = SEQID_0; /* Put SEQ0 to slotA */ + wupt_cfg.WuptOrder[1] = SEQID_3; /* Put SEQ3 to slotB */ + wupt_cfg.WuptOrder[2] = SEQID_1; /* Put SEQ1 to slotC */ + /* There is no need to init slot DEFGH, that's WuptOrder[3] to WuptOrder[7], becaue we don't use it. EndofSeq is C.*/ + wupt_cfg.SeqxSleepTime[SEQID_0] = 10; + wupt_cfg.SeqxWakeupTime[SEQID_0] = (uint32_t)(32000.0f*500/1000.0f) - 10 - 2; /* 500ms after, wakeup and trigger seq0 */ + wupt_cfg.SeqxSleepTime[SEQID_3] = 10; + wupt_cfg.SeqxWakeupTime[SEQID_3] = (uint32_t)(32000.0f*1000/1000.0f)- 10 -2; /* 1000ms after, trigger seq2 */ + wupt_cfg.SeqxSleepTime[SEQID_1] = 10; + wupt_cfg.SeqxWakeupTime[SEQID_1] = (uint32_t)(32000.0f*2000/1000.0f)- 10 -2; /* 2000ms after, trigger seq2 */ + AD5940_WUPTCfg(&wupt_cfg); + + printf("Test0: trigger sequencer by wakeup timer.\n"); + AD5940_WUPTCtrl(bTRUE); /* Enable wakeup timer. */ + while(1) + { + if(AD5940_GetMCUIntFlag()) + { + AD5940_ClrMCUIntFlag(); + SeqISR(); + if(bSeqEnd) + break; + } + } + AD5940_WUPTCtrl(bFALSE); /* Wakeup timer is still running and triggering. Trigger is not accepted because sequencer + is disabled in last sequence(SEQ1) command. */ + AD5940_SEQCtrlS(bTRUE); /* Enable sequencer again, because we disabled it in seq3 last command. */ + + /* Test MMR trigger */ + printf("\nTest1: trigger sequence2 manually by register write.\n"); + AD5940_SEQMmrTrig(SEQID_2); /* Trigger sequence2 manually. */ + /* Wait until CUSTMINT2 is set. We generate this interrupt in SEQ2 */ + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_CUSTOMINT2) == bFALSE); /* Test INTC1, we enabled all interrupts in INTC1. */ + AD5940_INTCClrFlag(AFEINTSRC_CUSTOMINT2); + printf("sequence2 has been executed\n"); + printf("SWCON:0x%08x\n", AD5940_ReadReg(REG_AFE_SWCON)); + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + + /* Toggle GPIO to trigger sequencer2 */ + printf("\nTest2: trigger sequence2 manually by GPIO\n"); + printf("Please connect GP2 and GP1 together. We will set GP2 function to TRIG.\n" + "GP1 is set to GPIO function and is in output state. We use GP1 to toggle GP2.\n"); + AD5940_Delay10us(100*1000*2); + printf("Toggle GPIO now\n"); + + /* Allow GP2 falling edge to trigger sequence2 */ + seqgpiotrig_cfg.bEnable = bTRUE; + seqgpiotrig_cfg.PinSel = AGPIO_Pin2; + seqgpiotrig_cfg.SeqPinTrigMode = SEQPINTRIGMODE_FALLING; + AD5940_SEQGpioTrigCfg(&seqgpiotrig_cfg); + /* GP2 is connected to GP1 by user. + We generate falling edge on GP1(gpio, output) to control GP2(trigger, input). + */ + AD5940_AGPIOSet(AGPIO_Pin1); + AD5940_AGPIOClr(AGPIO_Pin1); + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_CUSTOMINT2) == bFALSE); /* Test INTC1, we enabled all interrupts in INTC1. */ + + printf("Trigger received and sequence2 has been executed\n\n"); + printf("Sequencer test done!\n"); + while(1); +} + +int32_t SeqISR(void) +{ + uint32_t IntFlag, temp; + + IntFlag = AD5940_INTCGetFlag(AFEINTC_0); + + if(IntFlag & AFEINTSRC_CUSTOMINT0) + { + AD5940_INTCClrFlag(AFEINTSRC_CUSTOMINT0); + printf("Custom INT0!\n"); + temp = AD5940_ReadReg(REG_AFE_SWCON); + printf("SWCON:0x%08x\n", temp); + } + if(IntFlag & AFEINTSRC_CUSTOMINT1) + { + AD5940_INTCClrFlag(AFEINTSRC_CUSTOMINT1); + printf("Custom INT1!\n"); + temp = AD5940_ReadReg(REG_AFE_SWCON); + printf("SWCON:0x%08x\n", temp); + } + if(IntFlag & AFEINTSRC_CUSTOMINT2) + { + AD5940_INTCClrFlag(AFEINTSRC_CUSTOMINT2); + printf("Custom INT2!\n"); + temp = AD5940_ReadReg(REG_AFE_SWCON); + printf("SWCON:0x%08x\n", temp); + } + if(IntFlag & AFEINTSRC_CUSTOMINT3) + { + AD5940_INTCClrFlag(AFEINTSRC_CUSTOMINT3); + printf("Custom INT3!\n"); + temp = AD5940_ReadReg(REG_AFE_SWCON); + printf("SWCON:0x%08x\n", temp); + } + if(IntFlag & AFEINTSRC_ENDSEQ) /* This interrupt is generated when Sequencer is disabled. */ + { + AD5940_INTCClrFlag(AFEINTSRC_ENDSEQ); + printf("End of Sequence\n"); + bSeqEnd = bTRUE; + } + return AD5940ERR_OK; +} + diff --git a/examples/sequencer/NUCLEOF411Port.c b/examples/sequencer/NUCLEOF411Port.c new file mode 100644 index 0000000..c78dd97 --- /dev/null +++ b/examples/sequencer/NUCLEOF411Port.c @@ -0,0 +1,190 @@ +/** + * @file NUCLEOF411Port.c + * @brief ST NUCLEOF411 board port file. + * @version V0.2.0 + * @author ADI + * @date March 2019 + * @par Revision History: + * + * Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + * + * This software is proprietary to Analog Devices, Inc. and its licensors. + * By using this software you agree to the terms of the associated + * Analog Devices Software License Agreement. +**/ +#include "ad5940.h" +#include "stdio.h" +#include "stm32f4xx_hal.h" + +/* Definition for STM32 SPI clock resources */ +#define AD5940SPI SPI1 +#define AD5940_CLK_ENABLE() __HAL_RCC_SPI1_CLK_ENABLE() +#define AD5940_SCK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define AD5940_MISO_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define AD5940_MOSI_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define AD5940_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define AD5940_RST_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define AD5940_GP0INT_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() + +#define AD5940SPI_FORCE_RESET() __HAL_RCC_SPI1_FORCE_RESET() +#define AD5940SPI_RELEASE_RESET() __HAL_RCC_SPI1_RELEASE_RESET() + +/* Definition for AD5940 Pins */ +#define AD5940_SCK_PIN GPIO_PIN_5 +#define AD5940_SCK_GPIO_PORT GPIOA +#define AD5940_SCK_AF GPIO_AF5_SPI1 +#define AD5940_MISO_PIN GPIO_PIN_6 +#define AD5940_MISO_GPIO_PORT GPIOA +#define AD5940_MISO_AF GPIO_AF5_SPI1 +#define AD5940_MOSI_PIN GPIO_PIN_7 +#define AD5940_MOSI_GPIO_PORT GPIOA +#define AD5940_MOSI_AF GPIO_AF5_SPI1 + +#define AD5940_CS_PIN GPIO_PIN_6 +#define AD5940_CS_GPIO_PORT GPIOB + +#define AD5940_RST_PIN GPIO_PIN_0 //A3 +#define AD5940_RST_GPIO_PORT GPIOB + +#define AD5940_GP0INT_PIN GPIO_PIN_10 //A3 +#define AD5940_GP0INT_GPIO_PORT GPIOA +#define AD5940_GP0INT_IRQn EXTI15_10_IRQn + +SPI_HandleTypeDef SpiHandle; + +#define SYSTICK_MAXCOUNT ((1L<<24)-1) /* we use Systick to complete function Delay10uS(). This value only applies to NUCLEOF411 board. */ +#define SYSTICK_CLKFREQ 100000000L /* Systick clock frequency in Hz. This only appies to NUCLEOF411 board */ +volatile static uint8_t ucInterrupted = 0; /* Flag to indicate interrupt occurred */ + +/** + @brief Using SPI to transmit N bytes and return the received bytes. This function targets to + provide a more efficent way to transmit/receive data. + @param pSendBuffer :{0 - 0xFFFFFFFF} + - Pointer to the data to be sent. + @param pRecvBuff :{0 - 0xFFFFFFFF} + - Pointer to the buffer used to store received data. + @param length :{0 - 0xFFFFFFFF} + - Data length in SendBuffer. + @return None. +**/ +void AD5940_ReadWriteNBytes(unsigned char *pSendBuffer,unsigned char *pRecvBuff,unsigned long length) +{ + HAL_SPI_TransmitReceive(&SpiHandle, pSendBuffer, pRecvBuff, length, (uint32_t)-1); +} + +void AD5940_CsClr(void) +{ + HAL_GPIO_WritePin(AD5940_CS_GPIO_PORT, AD5940_CS_PIN, GPIO_PIN_RESET); +} + +void AD5940_CsSet(void) +{ + HAL_GPIO_WritePin(AD5940_CS_GPIO_PORT, AD5940_CS_PIN, GPIO_PIN_SET); +} + +void AD5940_RstSet(void) +{ + HAL_GPIO_WritePin(AD5940_RST_GPIO_PORT, AD5940_RST_PIN, GPIO_PIN_SET); +} + +void AD5940_RstClr(void) +{ + HAL_GPIO_WritePin(AD5940_RST_GPIO_PORT, AD5940_RST_PIN, GPIO_PIN_RESET); +} + +void AD5940_Delay10us(uint32_t time) +{ + time/=100; + if(time == 0) time =1; + HAL_Delay(time); +} + +uint32_t AD5940_GetMCUIntFlag(void) +{ + return ucInterrupted; +} + +uint32_t AD5940_ClrMCUIntFlag(void) +{ + ucInterrupted = 0; + return 1; +} + +uint32_t AD5940_MCUResourceInit(void *pCfg) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* Step1, initialize SPI peripheral and its GPIOs for CS/RST */ + AD5940_SCK_GPIO_CLK_ENABLE(); + AD5940_MISO_GPIO_CLK_ENABLE(); + AD5940_MOSI_GPIO_CLK_ENABLE(); + AD5940_CS_GPIO_CLK_ENABLE(); + AD5940_RST_GPIO_CLK_ENABLE(); + /* Enable SPI clock */ + AD5940_CLK_ENABLE(); + + GPIO_InitStruct.Pin = AD5940_SCK_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = AD5940_SCK_AF; + HAL_GPIO_Init(AD5940_SCK_GPIO_PORT, &GPIO_InitStruct); + + /* SPI MISO GPIO pin configuration */ + GPIO_InitStruct.Pin = AD5940_MISO_PIN; + GPIO_InitStruct.Alternate = AD5940_MISO_AF; + HAL_GPIO_Init(AD5940_MISO_GPIO_PORT, &GPIO_InitStruct); + + /* SPI MOSI GPIO pin configuration */ + GPIO_InitStruct.Pin = AD5940_MOSI_PIN; + GPIO_InitStruct.Alternate = AD5940_MOSI_AF; + HAL_GPIO_Init(AD5940_MOSI_GPIO_PORT, &GPIO_InitStruct); + /* SPI CS GPIO pin configuration */ + GPIO_InitStruct.Pin = AD5940_CS_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + HAL_GPIO_Init(AD5940_CS_GPIO_PORT, &GPIO_InitStruct); + + /* SPI RST GPIO pin configuration */ + GPIO_InitStruct.Pin = AD5940_RST_PIN; + HAL_GPIO_Init(AD5940_RST_GPIO_PORT, &GPIO_InitStruct); + + AD5940_CsSet(); + AD5940_RstSet(); + + /* Set the SPI parameters */ + SpiHandle.Instance = AD5940SPI; + SpiHandle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8; //SPI clock should be < AD5940_SystemClock + SpiHandle.Init.Direction = SPI_DIRECTION_2LINES; + SpiHandle.Init.CLKPhase = SPI_PHASE_1EDGE; + SpiHandle.Init.CLKPolarity = SPI_POLARITY_LOW; + SpiHandle.Init.DataSize = SPI_DATASIZE_8BIT; + SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; + SpiHandle.Init.TIMode = SPI_TIMODE_DISABLE; + SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + SpiHandle.Init.CRCPolynomial = 7; + SpiHandle.Init.NSS = SPI_NSS_SOFT; + SpiHandle.Init.Mode = SPI_MODE_MASTER; + HAL_SPI_Init(&SpiHandle); + + /* Step 2: Configure external interrupot line */ + AD5940_GP0INT_GPIO_CLK_ENABLE(); + GPIO_InitStruct.Pin = AD5940_GP0INT_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = 0; + HAL_GPIO_Init(AD5940_GP0INT_GPIO_PORT, &GPIO_InitStruct); + + /* Enable and set EXTI Line0 Interrupt to the lowest priority */ + HAL_NVIC_EnableIRQ(AD5940_GP0INT_IRQn); +// HAL_NVIC_SetPriority(AD5940_GP0INT_IRQn, 0, 0); + return 0; +} + +/* MCU related external line interrupt service routine */ +void EXTI15_10_IRQHandler() +{ + ucInterrupted = 1; + __HAL_GPIO_EXTI_CLEAR_IT(AD5940_GP0INT_PIN); +} + diff --git a/examples/sequencer/main.c b/examples/sequencer/main.c new file mode 100644 index 0000000..049abeb --- /dev/null +++ b/examples/sequencer/main.c @@ -0,0 +1,143 @@ +/* + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*/ + +#include "stdio.h" +#include "ADuCM3029.h" +#include "AD5940.h" + +/* Functions that used to initialize MCU platform */ +uint32_t MCUPlatformInit(void *pCfg); + +int main(void) +{ + void AD5940_Main(void); + MCUPlatformInit(0); + AD5940_MCUResourceInit(0); + printf("Hello AD5940-Build Time:%s\n",__TIME__); + AD5940_Main(); +} + +/* Below functions are used to initialize MCU Platform */ +uint32_t MCUPlatformInit(void *pCfg) +{ + int UrtCfg(int iBaud); + + /*Stop watch dog timer(ADuCM3029)*/ + pADI_WDT0->CTL = 0xC9; + /* Clock Configure */ + pADI_CLKG0_OSC->KEY = 0xCB14; // Select HFOSC as system clock. + pADI_CLKG0_OSC->CTL = // Int 32khz LFOSC selected in LFMUX + BITM_CLKG_OSC_CTL_HFOSCEN|BITM_CLKG_OSC_CTL_HFXTALEN; + + while((pADI_CLKG0_OSC->CTL&BITM_CLKG_OSC_CTL_HFXTALOK) == 0); + + pADI_CLKG0_OSC->KEY = 0xCB14; + pADI_CLKG0_CLK->CTL0 = 0x201; /* Select XTAL as system clock */ + pADI_CLKG0_CLK->CTL1 = 0; // ACLK,PCLK,HCLK divided by 1 + pADI_CLKG0_CLK->CTL5 = 0x00; // Enable clock to all peripherals - no clock gating + + UrtCfg(230400);/*Baud rate: 230400*/ + return 1; +} + +/** + @brief int UrtCfg(int iBaud, int iBits, int iFormat) + ==========Configure the UART. + @param iBaud :{B1200,B2200,B2400,B4800,B9600,B19200,B38400,B57600,B115200,B230400,B430800} \n + Set iBaud to the baudrate required: + Values usually: 1200, 2200 (for HART), 2400, 4800, 9600, + 19200, 38400, 57600, 115200, 230400, 430800, or type in baud-rate directly + @note + - Powers up UART if not powered up. + - Standard baudrates are accurate to better than 0.1% plus clock error.\n + - Non standard baudrates are accurate to better than 1% plus clock error. + @warning - If an external clock is used for the system the ullRtClk must be modified with \n + the speed of the clock used. +**/ + +int UrtCfg(int iBaud) +{ + int iBits = 3;//8bits, + int iFormat = 0;//, int iBits, int iFormat + int i1; + int iDiv; + int iRtC; + int iOSR; + int iPllMulValue; + unsigned long long ullRtClk = 16000000; // The root clock speed + + + /*Setup P0[11:10] as UART pins*/ + pADI_GPIO0->CFG = (1<<22)|(1<<20)|(pADI_GPIO0->CFG&(~((3<<22)|(3<<20)))); + + iDiv = (pADI_CLKG0_CLK->CTL1& BITM_CLKG_CLK_CTL1_PCLKDIVCNT); // Read UART clock as set by CLKCON1[10:8] + iDiv = iDiv>>8; + if (iDiv == 0) + iDiv = 1; + iRtC = (pADI_CLKG0_CLK->CTL0& BITM_CLKG_CLK_CTL0_CLKMUX); // Check what is the root clock + + switch (iRtC) + { + case 0: // HFOSC selected + ullRtClk = 26000000; + break; + + case 1: // HFXTAL selected + if ((pADI_CLKG0_CLK->CTL0 & 0x200)==0x200) // 26Mhz XTAL used + ullRtClk = 26000000; + else + ullRtClk = 16000000; // Assume 16MHz XTAL + break; + + case 2: // SPLL output + iPllMulValue = (pADI_CLKG0_CLK->CTL3 & // Check muliplication factor in PLL settings + BITM_CLKG_CLK_CTL3_SPLLNSEL); // bits[4:0]. Assume div value of 0xD in bits [14:11] + ullRtClk = (iPllMulValue *1000000); // Assume straight multiplication by pADI_CLKG0_CLK->CTL3[4:0] + break; + + case 3: + ullRtClk = 26000000; //External clock is assumed to be 26MhZ, if different + break; //clock speed is used, this should be changed + + default: + break; + } + // iOSR = (pADI_UART0->COMLCR2 & 0x3); + // iOSR = 2^(2+iOSR); + pADI_UART0->COMLCR2 = 0x3; + iOSR = 32; + //i1 = (ullRtClk/(iOSR*iDiv))/iBaud; // UART baud rate clock source is PCLK divided by OSR + i1 = (ullRtClk/(iOSR*iDiv))/iBaud-1; //for bigger M and N value + pADI_UART0->COMDIV = i1; + + pADI_UART0->COMFBR = 0x8800|(((((2048/(iOSR*iDiv))*ullRtClk)/i1)/iBaud)-2048); + pADI_UART0->COMIEN = 0; + pADI_UART0->COMLCR = (iFormat&0x3c)|(iBits&3); + + + pADI_UART0->COMFCR = (BITM_UART_COMFCR_RFTRIG & 0/*RX_FIFO_1BYTE*/ ) |BITM_UART_COMFCR_FIFOEN; + pADI_UART0->COMFCR |= BITM_UART_COMFCR_RFCLR|BITM_UART_COMFCR_TFCLR; // Clear the UART FIFOs + pADI_UART0->COMFCR &= ~(BITM_UART_COMFCR_RFCLR|BITM_UART_COMFCR_TFCLR); // Disable clearing mechanism + + NVIC_EnableIRQ(UART_EVT_IRQn); // Enable UART interrupt source in NVIC + pADI_UART0->COMIEN = BITM_UART_COMIEN_ERBFI|BITM_UART_COMIEN_ELSI; /* Rx Interrupt */ + return pADI_UART0->COMLSR; +} +#include "stdio.h" +#ifdef __ICCARM__ +int putchar(int c) +#else +int fputc(int c, FILE *f) +#endif +{ + pADI_UART0->COMTX = c; + while((pADI_UART0->COMLSR&0x20) == 0);// tx fifo empty + return c; +} diff --git a/host/CMakeLists.txt b/host/CMakeLists.txt index 4c63d28..0964061 100644 --- a/host/CMakeLists.txt +++ b/host/CMakeLists.txt @@ -1,5 +1,3 @@ -# File: host/CMakeLists.txt - cmake_minimum_required(VERSION 3.18) project(EISConfigurator VERSION 1.0 LANGUAGES CXX C) @@ -83,7 +81,8 @@ set(PROJECT_HEADERS if(ANDROID) add_library(EISConfigurator SHARED ${PROJECT_SOURCES} ${PROJECT_HEADERS}) else() - add_executable(EISConfigurator MANUAL_FINALIZATION ${PROJECT_SOURCES} ${PROJECT_HEADERS}) + # Removed MANUAL_FINALIZATION keyword as add_executable does not support it + add_executable(EISConfigurator ${PROJECT_SOURCES} ${PROJECT_HEADERS}) endif() if(EXISTS "${ICON_SOURCE}" AND MAGICK_EXECUTABLE) diff --git a/host/src/GraphWidget.cpp b/host/src/GraphWidget.cpp index 7040914..b060aac 100644 --- a/host/src/GraphWidget.cpp +++ b/host/src/GraphWidget.cpp @@ -1,89 +1,148 @@ #include "GraphWidget.h" -#include +#include +#include -GraphWidget::GraphWidget(QWidget *parent) : QWidget(parent) -{ - QVBoxLayout *layout = new QVBoxLayout(this); - layout->setContentsMargins(0, 0, 0, 0); - - plot = new JKQTPlotter(this); +GraphWidget::GraphWidget(QWidget *parent) : QWidget(parent) { + layout = new QVBoxLayout(this); + plot = new QCustomPlot(this); + + // Setup Layout layout->addWidget(plot); + layout->setContentsMargins(0, 0, 0, 0); + + // Setup Graphs + graph1 = plot->addGraph(); + graph2 = plot->addGraph(plot->xAxis, plot->yAxis2); - // Initialize Graphs - graphY1 = new JKQTPXYLineGraph(plot); - graphY2 = new JKQTPXYLineGraph(plot); + // Style Graph 1 (Primary - Left Axis) + QPen pen1(Qt::blue); + pen1.setWidth(2); + graph1->setPen(pen1); + graph1->setLineStyle(QCPGraph::lsLine); + graph1->setScatterStyle(QCPScatterStyle(QCPScatterStyle::ssCircle, 3)); + graph1->setName("Primary"); - // Styling Y1 (e.g., Blue) - graphY1->setColor(QColor("blue")); - graphY1->setSymbolColor(QColor("blue")); - graphY1->setSymbol(JKQTPCircle); - graphY1->setSymbolSize(7); - graphY1->setLineWidth(2); + // Style Graph 2 (Secondary - Right Axis) + QPen pen2(Qt::red); + pen2.setWidth(2); + graph2->setPen(pen2); + graph2->setLineStyle(QCPGraph::lsLine); + graph2->setScatterStyle(QCPScatterStyle(QCPScatterStyle::ssTriangle, 3)); + graph2->setName("Secondary"); - // Styling Y2 (e.g., Red) - graphY2->setColor(QColor("red")); - graphY2->setSymbolColor(QColor("red")); - graphY2->setSymbol(JKQTPTriangle); - graphY2->setSymbolSize(7); - graphY2->setLineWidth(2); + // Enable Right Axis + plot->yAxis2->setVisible(true); + plot->yAxis2->setTickLabels(true); - plot->addGraph(graphY1); - plot->addGraph(graphY2); + // Interactions + plot->setInteractions(QCP::iRangeDrag | QCP::iRangeZoom); + + // Legend + plot->legend->setVisible(true); + QFont legendFont = font(); + legendFont.setPointSize(9); + plot->legend->setFont(legendFont); + plot->legend->setBrush(QBrush(QColor(255, 255, 255, 230))); + + // Default Mode + configureBodePlot(); } -void GraphWidget::setupPlot(QString title, QString xLabel, QString y1Label, QString y2Label) -{ - // Basic Settings - plot->getPlotter()->setPlotLabel(title); - plot->getXAxis()->setAxisLabel(xLabel); +void GraphWidget::configureBodePlot() { + clear(); - // Y-Axis setup - plot->getYAxis()->setAxisLabel(y1Label); // Left Axis + // X Axis: Frequency (Log) + plot->xAxis->setLabel("Frequency (Hz)"); + plot->xAxis->setScaleType(QCPAxis::stLogarithmic); + QSharedPointer logTicker(new QCPAxisTickerLog); + plot->xAxis->setTicker(logTicker); + plot->xAxis->setNumberFormat("eb"); - // If we want a secondary axis for Y2, JKQTPlotter supports it, - // but for simplicity here we might plot on the same if scales are similar, - // or rely on user interpretation. - // For Bode (Ohm vs Degree), scales are vastly different. - // Ideally, Y2 should be on the right axis. + // Y Axis 1: Impedance (Log) + plot->yAxis->setLabel("Impedance (Ohms)"); + plot->yAxis->setScaleType(QCPAxis::stLogarithmic); + plot->yAxis->setTicker(logTicker); + plot->yAxis->setNumberFormat("eb"); + + // Y Axis 2: Phase (Linear) + plot->yAxis2->setLabel("Phase (Degrees)"); + plot->yAxis2->setScaleType(QCPAxis::stLinear); + QSharedPointer linTicker(new QCPAxisTicker); + plot->yAxis2->setTicker(linTicker); + plot->yAxis2->setNumberFormat("f"); + plot->yAxis2->setRange(-180, 180); + + graph1->setName("Impedance"); + graph2->setName("Phase"); - // Assign Y1 to Left Axis - graphY1->setTitle(y1Label); - - // Assign Y2 to Right Axis (if supported by specific JKQT config, otherwise same axis) - // Assuming simple usage for now: - graphY2->setTitle(y2Label); - - // Enable Legend - plot->getPlotter()->setShowKey(true); + plot->replot(); } -void GraphWidget::setLogAxis(bool logX, bool logY) -{ - plot->getXAxis()->setLogAxis(logX); - plot->getYAxis()->setLogAxis(logY); +void GraphWidget::configureRawPlot() { + clear(); + + // X Axis: Frequency (Log) + plot->xAxis->setLabel("Frequency (Hz)"); + plot->xAxis->setScaleType(QCPAxis::stLogarithmic); + QSharedPointer logTicker(new QCPAxisTickerLog); + plot->xAxis->setTicker(logTicker); + + // Y Axis 1: Real (Linear) + plot->yAxis->setLabel("Real (Ohms)"); + plot->yAxis->setScaleType(QCPAxis::stLinear); + QSharedPointer linTicker(new QCPAxisTicker); + plot->yAxis->setTicker(linTicker); + plot->yAxis->setNumberFormat("f"); + + // Y Axis 2: Imaginary (Linear) + plot->yAxis2->setLabel("Imaginary (Ohms)"); + plot->yAxis2->setScaleType(QCPAxis::stLinear); + plot->yAxis2->setTicker(linTicker); + plot->yAxis2->setNumberFormat("f"); + + graph1->setName("Real"); + graph2->setName("Imaginary"); + + plot->replot(); } -void GraphWidget::addData(double x, double y1, double y2) -{ - xData.append(x); - y1Data.append(y1); - y2Data.append(y2); +void GraphWidget::addData(double freq, double val1, double val2) { + // 1. Validate X-Axis (Frequency) + // If Log scale, Frequency must be > 0. + if (plot->xAxis->scaleType() == QCPAxis::stLogarithmic && freq <= 0) { + return; + } - // Update graph data pointers - graphY1->setXColumn(xData); - graphY1->setYColumn(y1Data); + // 2. Validate Y-Axis 1 (Impedance/Real) + // If Log scale (Impedance), value must be > 0. + if (plot->yAxis->scaleType() == QCPAxis::stLogarithmic) { + // If we have a zero/negative impedance in log mode, skip it. + // Clamping to 1e-12 causes massive axis scaling issues (squished plots). + if (val1 <= 1e-7) { + val1 = std::numeric_limits::quiet_NaN(); + } + } - graphY2->setXColumn(xData); - graphY2->setYColumn(y2Data); + // 3. Add Data + // QCustomPlot handles NaN by creating a line gap, which is visually correct for missing/bad data. + if (!std::isnan(val1)) { + graph1->addData(freq, val1); + } + + // Graph 2 (Phase/Imag) is usually Linear. + graph2->addData(freq, val2); - // Redraw - plot->redrawPlot(); + // 4. Auto-scale + // We remove 'true' (onlyEnlarge). We want the axes to shrink + // if we zoom in or if the data range stabilizes. + graph1->rescaleAxes(false); + graph2->rescaleAxes(false); + + plot->replot(); } -void GraphWidget::clear() -{ - xData.clear(); - y1Data.clear(); - y2Data.clear(); - plot->redrawPlot(); +void GraphWidget::clear() { + graph1->data()->clear(); + graph2->data()->clear(); + plot->replot(); } \ No newline at end of file diff --git a/host/src/GraphWidget.h b/host/src/GraphWidget.h index e5332bf..210605e 100644 --- a/host/src/GraphWidget.h +++ b/host/src/GraphWidget.h @@ -1,39 +1,26 @@ -#ifndef GRAPHWIDGET_H -#define GRAPHWIDGET_H +#pragma once #include -#include -#include "jkqtplotter/jkqtplotter.h" -#include "jkqtplotter/graphs/jkqtpigraph.h" -#include "jkqtplotter/graphs/jkqtpimage.h" -#include "jkqtplotter/graphs/jkqtpscatter.h" -#include "jkqtplotter/graphs/jkqtplyines.h" +#include +#include "qcustomplot.h" -class GraphWidget : public QWidget -{ +class GraphWidget : public QWidget { Q_OBJECT + public: explicit GraphWidget(QWidget *parent = nullptr); - - // Configuration - void setupPlot(QString title, QString xLabel, QString y1Label, QString y2Label); - void setLogAxis(bool logX, bool logY); - - // Data Access - void addData(double x, double y1, double y2); + + // Data Handling + void addData(double freq, double val1, double val2); void clear(); + + // View Configurations + void configureBodePlot(); + void configureRawPlot(); private: - JKQTPlotter *plot; - - // Internal Data Storage - QVector xData; - QVector y1Data; - QVector y2Data; - - // Graph Objects - JKQTPXYLineGraph *graphY1; - JKQTPXYLineGraph *graphY2; -}; - -#endif // GRAPHWIDGET_H \ No newline at end of file + QVBoxLayout *layout; + QCustomPlot *plot; + QCPGraph *graph1; + QCPGraph *graph2; +}; \ No newline at end of file diff --git a/host/src/MainWindow.cpp b/host/src/MainWindow.cpp index 1c22e65..3a6a1c6 100644 --- a/host/src/MainWindow.cpp +++ b/host/src/MainWindow.cpp @@ -1,228 +1,288 @@ #include "MainWindow.h" -#include #include -#include -#include #include -#include -#include +#include +#include +#include +#include +#include +#include +#include +#include -MainWindow::MainWindow(QWidget *parent) - : QMainWindow(parent) -{ +MainWindow::MainWindow(QWidget *parent) : QMainWindow(parent), currentSweepIndex(0), isSweeping(false) { serial = new QSerialPort(this); - connect(serial, &QSerialPort::readyRead, this, &MainWindow::onReadData); + connect(serial, &QSerialPort::readyRead, this, &MainWindow::handleSerialData); + connect(serial, &QSerialPort::errorOccurred, this, &MainWindow::onPortError); setupUi(); + // Delayed refresh to allow the window to render before auto-scanning + QTimer::singleShot(1000, this, &MainWindow::refreshPorts); + generateSweepPoints(); + + // Enable Swipe Gestures for Mobile Tab Switching + grabGesture(Qt::SwipeGesture); } -MainWindow::~MainWindow() -{ - if (serial->isOpen()) +MainWindow::~MainWindow() { + if (serial->isOpen()) { serial->close(); + } } -void MainWindow::setupUi() -{ - centralWidget = new QWidget(this); - setCentralWidget(centralWidget); - QVBoxLayout *mainLayout = new QVBoxLayout(centralWidget); +void MainWindow::setupUi() { + // Central Layout: Splitter (Graphs Top, Log Bottom) + QSplitter *splitter = new QSplitter(Qt::Vertical, this); + setCentralWidget(splitter); - // --- Toolbar Area --- - QHBoxLayout *toolLayout = new QHBoxLayout(); - - portSelector = new QComboBox(); - const auto ports = QSerialPortInfo::availablePorts(); - for (const QSerialPortInfo &info : ports) { - portSelector->addItem(info.portName()); - } + // Tab Widget for Graphs + tabWidget = new QTabWidget(this); + finalGraph = new GraphWidget(this); + finalGraph->configureBodePlot(); + rawGraph = new GraphWidget(this); + rawGraph->configureRawPlot(); - btnConnect = new QPushButton("Connect"); - connect(btnConnect, &QPushButton::clicked, [this]() { - onPortToggled(serial->isOpen()); - }); - - btnMeasure = new QPushButton("Measure"); - btnMeasure->setEnabled(false); - connect(btnMeasure, &QPushButton::clicked, this, &MainWindow::onMeasureClicked); - - btnCalibrate = new QPushButton("Calibrate"); - btnCalibrate->setEnabled(false); - connect(btnCalibrate, &QPushButton::clicked, this, &MainWindow::onCalibrateClicked); - - viewSelector = new QComboBox(); - viewSelector->addItem("Tabs (Swipe)"); - viewSelector->addItem("Split (Dual)"); - connect(viewSelector, QOverload::of(&QComboBox::currentIndexChanged), this, &MainWindow::onViewModeChanged); - - toolLayout->addWidget(portSelector); - toolLayout->addWidget(btnConnect); - toolLayout->addWidget(btnMeasure); - toolLayout->addWidget(btnCalibrate); - toolLayout->addWidget(viewSelector); // Add view switcher - - mainLayout->addLayout(toolLayout); - - // --- Graphs Initialization --- - finalGraph = new GraphWidget(); - finalGraph->setupPlot("Bode Plot", "Frequency (Hz)", "Impedance (Ohm)", "Phase (Rad)"); - finalGraph->setLogAxis(true, true); // Log-Log for Bode - - rawGraph = new GraphWidget(); - rawGraph->setupPlot("Raw Data (DFT)", "Frequency (Hz)", "Real", "Imaginary"); - rawGraph->setLogAxis(true, false); // Log X, Linear Y (Raw data can be neg) - - // --- Layout Containers --- - - // 1. Tab Widget (Mobile Style) - tabWidget = new QTabWidget(); - tabWidget->addTab(finalGraph, "Final Data"); + tabWidget->addTab(finalGraph, "Bode Plot"); tabWidget->addTab(rawGraph, "Raw Data"); - // 2. Splitter (Desktop Style) - splitter = new QSplitter(Qt::Horizontal); - // Note: We can't add the same widget to two parents. - // We will reparent them in onViewModeChanged. - - // Default to Tabs (Mobile friendly default) - mainLayout->addWidget(tabWidget); - - // Status Bar - statusLabel = new QLabel("Ready"); - statusBar()->addWidget(statusLabel); + // Log Widget + logWidget = new QTextEdit(this); + logWidget->setReadOnly(true); + logWidget->setFont(QFont("Monospace")); + logWidget->setPlaceholderText("Scanning for 0xCAFE EIS Device..."); + QScroller::grabGesture(logWidget->viewport(), QScroller::TouchGesture); + + splitter->addWidget(tabWidget); + splitter->addWidget(logWidget); + splitter->setStretchFactor(0, 2); + splitter->setStretchFactor(1, 1); + + // Toolbar Construction + toolbar = addToolBar("Connection"); + toolbar->setMovable(false); + + portSelector = new QComboBox(this); + portSelector->setMinimumWidth(150); + connectBtn = new QPushButton("Connect", this); + QPushButton *refreshBtn = new QPushButton("Refresh", this); + + toolbar->addWidget(portSelector); + toolbar->addWidget(connectBtn); + toolbar->addWidget(refreshBtn); + toolbar->addSeparator(); + + checkIdBtn = new QPushButton("Check ID", this); + calibrateBtn = new QPushButton("Calibrate", this); + sweepBtn = new QPushButton("Sweep", this); + + toolbar->addWidget(checkIdBtn); + toolbar->addWidget(calibrateBtn); + toolbar->addWidget(sweepBtn); + toolbar->addSeparator(); + + // Measurement Control + QLabel *lblFreq = new QLabel(" Freq:", this); + QDoubleSpinBox *spinFreq = new QDoubleSpinBox(this); + spinFreq->setRange(10.0, 200000.0); + spinFreq->setValue(1000.0); + spinFreq->setSuffix(" Hz"); + QPushButton *measureBtn = new QPushButton("Measure", this); + + toolbar->addWidget(lblFreq); + toolbar->addWidget(spinFreq); + toolbar->addWidget(measureBtn); + + checkIdBtn->setEnabled(false); + calibrateBtn->setEnabled(false); + sweepBtn->setEnabled(false); + + // Signal Connections + connect(connectBtn, &QPushButton::clicked, this, &MainWindow::connectToPort); + connect(refreshBtn, &QPushButton::clicked, this, &MainWindow::refreshPorts); + connect(checkIdBtn, &QPushButton::clicked, this, &MainWindow::checkDeviceId); + connect(calibrateBtn, &QPushButton::clicked, this, &MainWindow::runCalibration); + connect(sweepBtn, &QPushButton::clicked, this, &MainWindow::startSweep); + + connect(measureBtn, &QPushButton::clicked, [this]() { + if (serial->isOpen()) { + logWidget->append(">> Requesting Measure (m)..."); + serial->write("m"); + } + }); - // Auto-detect Platform for default view #if defined(Q_OS_ANDROID) || defined(Q_OS_IOS) - viewSelector->setCurrentIndex(0); // Tabs - viewSelector->setVisible(false); // Hide selector on mobile, force tabs - #else - viewSelector->setCurrentIndex(1); // Default to Split on Desktop + toolbar->setIconSize(QSize(32, 32)); + QFont font = portSelector->font(); + font.setPointSize(14); + portSelector->setFont(font); + connectBtn->setFont(font); + refreshBtn->setFont(font); + checkIdBtn->setFont(font); + calibrateBtn->setFont(font); + sweepBtn->setFont(font); + measureBtn->setFont(font); + spinFreq->setFont(font); #endif } -void MainWindow::onViewModeChanged(int index) -{ - // 0 = Tabs, 1 = Split - - // Remove graphs from their current parents - finalGraph->setParent(nullptr); - rawGraph->setParent(nullptr); - - QVBoxLayout *layout = qobject_cast(centralWidget->layout()); - - if (index == 0) { // Tabs - if (splitter->isVisible()) { - layout->removeWidget(splitter); - splitter->hide(); - } - - tabWidget->clear(); - tabWidget->addTab(finalGraph, "Final Data"); - tabWidget->addTab(rawGraph, "Raw Data"); - - if (!tabWidget->isVisible()) { - layout->addWidget(tabWidget); - tabWidget->show(); - } - } - else { // Split - if (tabWidget->isVisible()) { - layout->removeWidget(tabWidget); - tabWidget->hide(); - } - - splitter->addWidget(finalGraph); - splitter->addWidget(rawGraph); - - if (!splitter->isVisible()) { - layout->addWidget(splitter); - splitter->show(); +void MainWindow::refreshPorts() { + portSelector->clear(); + const auto infos = QSerialPortInfo::availablePorts(); + for (const QSerialPortInfo &info : infos) { + portSelector->addItem(info.portName()); + // Auto-connect to device with 0xCAFE Vendor ID + if (info.hasVendorIdentifier() && info.vendorIdentifier() == 0xCAFE) { + logWidget->append(">> Found EIS Device (0xCAFE) on " + info.portName()); + portSelector->setCurrentText(info.portName()); + if (!serial->isOpen()) { + connectToPort(); + } } } } -void MainWindow::onPortToggled(bool connected) -{ - if (connected) { +void MainWindow::connectToPort() { + if (serial->isOpen()) { serial->close(); - btnConnect->setText("Connect"); - btnMeasure->setEnabled(false); - btnCalibrate->setEnabled(false); - statusLabel->setText("Disconnected"); + connectBtn->setText("Connect"); + logWidget->append("--- Disconnected ---"); + checkIdBtn->setEnabled(false); + calibrateBtn->setEnabled(false); + sweepBtn->setEnabled(false); + isSweeping = false; + return; + } + + if (portSelector->currentText().isEmpty()) return; + + serial->setPortName(portSelector->currentText()); + serial->setBaudRate(500000); + + if (serial->open(QIODevice::ReadWrite)) { + connectBtn->setText("Disconnect"); + logWidget->append("--- Connected and Synchronized ---"); + checkIdBtn->setEnabled(true); + calibrateBtn->setEnabled(true); + sweepBtn->setEnabled(true); } else { - serial->setPortName(portSelector->currentText()); - serial->setBaudRate(115200); // Or whatever your Pico uses, standard 115200 usually - - if (serial->open(QIODevice::ReadWrite)) { - btnConnect->setText("Disconnect"); - btnMeasure->setEnabled(true); - btnCalibrate->setEnabled(true); - statusLabel->setText("Connected"); - - // Clear old data on connect - finalGraph->clear(); - rawGraph->clear(); - } else { - QMessageBox::critical(this, "Error", "Could not open serial port."); - } + logWidget->append(">> Connection Error: " + serial->errorString()); } } -void MainWindow::onMeasureClicked() -{ +void MainWindow::onPortError(QSerialPort::SerialPortError error) { + if (error == QSerialPort::ResourceError) { + logWidget->append(">> Critical Error: Connection Lost."); + serial->close(); + connectBtn->setText("Connect"); + checkIdBtn->setEnabled(false); + calibrateBtn->setEnabled(false); + sweepBtn->setEnabled(false); + isSweeping = false; + } +} + +void MainWindow::checkDeviceId() { if (serial->isOpen()) { - finalGraph->clear(); - rawGraph->clear(); - // Trigger a sweep or single measurement - // Example command logic - // For single: serial->write("MEAS 10000\n"); - // For sweep logic, the MCU might handle it or we loop here. - // Assuming user triggers 'MEAS 1000' style commands manually or logic exists. - // Let's just send a command if needed, or rely on user knowing what to do. - // For now, let's assume we want to measure 10kHz as a test - serial->write("MEAS 10000\n"); + logWidget->append(">> Checking ID (v)..."); + serial->write("v"); } } -void MainWindow::onCalibrateClicked() -{ +void MainWindow::runCalibration() { if (serial->isOpen()) { - serial->write("CAL\n"); + logWidget->append(">> Running Calibration (c)..."); + serial->write("c"); } } -void MainWindow::onReadData() -{ +void MainWindow::startSweep() { + if (!serial->isOpen()) return; + isSweeping = true; + currentSweepIndex = 0; + finalGraph->clear(); + rawGraph->clear(); + logWidget->append(">> Starting Ratio-metric Sweep..."); + sendNextSweepPoint(); +} + +void MainWindow::sendNextSweepPoint() { + if (!isSweeping || !serial->isOpen()) return; + if (currentSweepIndex >= sweepPoints.size()) { + isSweeping = false; + logWidget->append(">> Sweep Complete."); + return; + } + serial->write("m"); +} + +void MainWindow::handleSerialData() { while (serial->canReadLine()) { - QByteArray line = serial->readLine().trimmed(); - processLine(line); + QByteArray line = serial->readLine(); + QString str = QString::fromUtf8(line).trimmed(); + if (str.isEmpty()) continue; + + QString timestamp = QDateTime::currentDateTime().toString("HH:mm:ss.zzz"); + logWidget->append(QString("[%1] %2").arg(timestamp, str)); + logWidget->moveCursor(QTextCursor::End); + + if (str.startsWith("DATA,")) { + parseData(str); + } } } -void MainWindow::processLine(const QByteArray &line) -{ - if (line.startsWith("DATA")) { - // Format: DATA,freq,impedance,phase,raw_real,raw_imag - float freq, imp, phase; - int raw_real, raw_imag; - - // sscanf is dangerous with comma delimited strings if not careful, but works for fixed format - int count = sscanf(line.constData(), "DATA,%f,%f,%f,%d,%d", &freq, &imp, &phase, &raw_real, &raw_imag); - - if (count >= 3) { - // We have at least the final data - finalGraph->addData(freq, imp, phase); // Y1=Imp, Y2=Phase +void MainWindow::parseData(const QString &data) { + QStringList parts = data.split(','); + if (parts.size() < 6) return; + + bool okF, okM, okP, okR, okI; + double freq = parts[1].toDouble(&okF); + double mag = parts[2].toDouble(&okM); + double phase= parts[3].toDouble(&okP); + double real = parts[4].toDouble(&okR); + double imag = parts[5].toDouble(&okI); + + if (okF && okM && okP) finalGraph->addData(freq, mag, phase); + if (okF && okR && okI) rawGraph->addData(freq, real, imag); + + if (isSweeping) { + currentSweepIndex++; + QTimer::singleShot(50, this, &MainWindow::sendNextSweepPoint); + } +} + +void MainWindow::generateSweepPoints() { + sweepPoints.clear(); + double startFreq = 100.0; + double endFreq = 200000.0; + int steps = 50; + double logStart = std::log10(startFreq); + double logEnd = std::log10(endFreq); + double logStep = (logEnd - logStart) / (steps - 1); + for (int i = 0; i < steps; ++i) { + sweepPoints.append(std::pow(10, logStart + i * logStep)); + } +} + +bool MainWindow::event(QEvent *event) { + if (event->type() == QEvent::Gesture) { + QGestureEvent *ge = static_cast(event); + if (QGesture *swipe = ge->gesture(Qt::SwipeGesture)) { + handleSwipe(static_cast(swipe)); + return true; } - - if (count >= 5) { - // We have raw data too - rawGraph->addData(freq, (double)raw_real, (double)raw_imag); + } + return QMainWindow::event(event); +} + +void MainWindow::handleSwipe(QSwipeGesture *gesture) { + if (gesture->state() == Qt::GestureFinished) { + if (gesture->horizontalDirection() == QSwipeGesture::Left) { + if (tabWidget->currentIndex() < tabWidget->count() - 1) + tabWidget->setCurrentIndex(tabWidget->currentIndex() + 1); + } else if (gesture->horizontalDirection() == QSwipeGesture::Right) { + if (tabWidget->currentIndex() > 0) + tabWidget->setCurrentIndex(tabWidget->currentIndex() - 1); } - - statusLabel->setText(QString("Received: %1 Hz").arg(freq)); - } - else if (line.startsWith("LOG")) { - statusLabel->setText(line); - qDebug() << "Device Log:" << line; } } \ No newline at end of file diff --git a/host/src/MainWindow.h b/host/src/MainWindow.h index ef0d0d9..c60f60f 100644 --- a/host/src/MainWindow.h +++ b/host/src/MainWindow.h @@ -1,53 +1,66 @@ -#ifndef MAINWINDOW_H -#define MAINWINDOW_H +#pragma once #include #include #include -#include +#include +#include #include #include -#include +#include +#include +#include +#include +#include +#include #include "GraphWidget.h" -class MainWindow : public QMainWindow -{ +class MainWindow : public QMainWindow { Q_OBJECT public: - MainWindow(QWidget *parent = nullptr); + explicit MainWindow(QWidget *parent = nullptr); ~MainWindow(); +protected: + bool event(QEvent *event) override; + private slots: - void onPortToggled(bool connected); - void onReadData(); - void onMeasureClicked(); - void onCalibrateClicked(); - void onViewModeChanged(int index); // New slot for desktop view switching + void handleSerialData(); + void connectToPort(); + void refreshPorts(); + void onPortError(QSerialPort::SerialPortError error); + + // Action Slots + void checkDeviceId(); + void runCalibration(); + void startSweep(); + void sendNextSweepPoint(); private: void setupUi(); - void processLine(const QByteArray &line); + void parseData(const QString &data); + void handleSwipe(QSwipeGesture *gesture); + void generateSweepPoints(); - // Hardware QSerialPort *serial; - // UI Elements - QComboBox *portSelector; - QPushButton *btnConnect; - QPushButton *btnMeasure; - QPushButton *btnCalibrate; - QLabel *statusLabel; - - // Graphs + // Views GraphWidget *finalGraph; // Bode Plot - GraphWidget *rawGraph; // Raw Real/Imag Plot + GraphWidget *rawGraph; // Raw Data + QTextEdit *logWidget; // Serial Log - // Layout Containers - QWidget *centralWidget; - QTabWidget *tabWidget; // For Mobile/Tab Mode - QSplitter *splitter; // For Desktop/Split Mode - QComboBox *viewSelector; // For Desktop to toggle modes -}; + // Layout + QTabWidget *tabWidget; + QToolBar *toolbar; + QComboBox *portSelector; + QPushButton *connectBtn; + QPushButton *checkIdBtn; + QPushButton *calibrateBtn; + QPushButton *sweepBtn; -#endif // MAINWINDOW_H \ No newline at end of file + // Sweep Logic + QList sweepPoints; + int currentSweepIndex; + bool isSweeping; +}; \ No newline at end of file diff --git a/main.c b/main.c index dfaa850..784e310 100644 --- a/main.c +++ b/main.c @@ -1,474 +1,258 @@ -// File: EIS/main.c +// File: main.c #include -#include -#include #include #include "pico/stdlib.h" #include "hardware/spi.h" #include "hardware/gpio.h" #include "ad5940.h" -// -------------------------------------------------------------------------- // Pin Definitions -// -------------------------------------------------------------------------- -#define PIN_MISO 0 -#define PIN_CS 1 -#define PIN_SCK 2 -#define PIN_MOSI 3 -#define PIN_RESET 9 -#define PIN_AD_INTERRUPT 29 +#define PIN_MISO 0 +#define PIN_CS 1 +#define PIN_SCK 2 +#define PIN_MOSI 3 +#define PIN_RST 9 +#define PIN_INT 29 -#define SPI_PORT spi0 -#define SPI_BAUDRATE_HIGH 500000 +#define RCAL_VALUE 100.0f -// -------------------------------------------------------------------------- -// Switch Matrix Bit Definitions -// -------------------------------------------------------------------------- -#ifndef SWT_SE0 -#define SWT_SE0 (1 << 6) // T7 -#endif -#ifndef SWT_T9 -#define SWT_T9 (1 << 8) // T9 -#endif -#ifndef SWT_TR1 -#define SWT_TR1 (1 << 11) // TR1 -#endif +// --------------------------------------------------------------------------- +// Platform Interface Implementation (Required by AD5940 Lib) +// --------------------------------------------------------------------------- -// DSWFULLCON -#ifndef SWD_AIN2 -#define SWD_AIN2 (1 << 2) // D3 -#endif -#ifndef SWD_CE0 -#define SWD_CE0 (1 << 4) // D5 -#endif - -// TSWFULLCON -#ifndef SWT_AIN3 -#define SWT_AIN3 (1 << 3) // T4 -#endif - -// -------------------------------------------------------------------------- -// AD5940 Library Interface -// -------------------------------------------------------------------------- - -void AD5940_CsClr(void) { - gpio_put(PIN_CS, 0); - sleep_us(1); +void AD5940_CsClr(void) { + gpio_put(PIN_CS, 0); } -void AD5940_CsSet(void) { - sleep_us(1); - gpio_put(PIN_CS, 1); - sleep_us(1); +void AD5940_CsSet(void) { + gpio_put(PIN_CS, 1); } -void AD5940_RstClr(void) { gpio_put(PIN_RESET, 0); } -void AD5940_RstSet(void) { gpio_put(PIN_RESET, 1); } -void AD5940_Delay10us(uint32_t time) { sleep_us(time * 10); } - -uint32_t AD5940_GetMCUIntFlag(void) { - uint32_t flag = AD5940_ReadReg(REG_INTC_INTCFLAG0); - return (flag != 0); +void AD5940_RstClr(void) { + gpio_put(PIN_RST, 0); } -void AD5940_ReadWriteNBytes(unsigned char *pSendBuffer, unsigned char *pRecvBuffer, unsigned long length) { - if (pRecvBuffer == NULL) { - if (pSendBuffer != NULL) { - spi_write_blocking(SPI_PORT, pSendBuffer, length); - } - } else { - if (pSendBuffer == NULL) { - uint8_t dummy = 0x00; - for (unsigned long i = 0; i < length; i++) { - spi_write_read_blocking(SPI_PORT, &dummy, &pRecvBuffer[i], 1); - } - } else { - spi_write_read_blocking(SPI_PORT, pSendBuffer, pRecvBuffer, length); - } - } +void AD5940_RstSet(void) { + gpio_put(PIN_RST, 1); } -// -------------------------------------------------------------------------- -// Helpers -// -------------------------------------------------------------------------- - -void AD5940_PulseReset(void) { - AD5940_RstClr(); - sleep_ms(10); - AD5940_RstSet(); - sleep_ms(50); // Increased wait for boot stability +void AD5940_Delay10us(uint32_t time) { + sleep_us(time * 10); } -// Helper to map Register Macro to Actual Sample Count for calculations -uint32_t GetDftSamples(uint32_t dft_num_macro) { - if (dft_num_macro == DFTNUM_256) return 256; - if (dft_num_macro == DFTNUM_512) return 512; - if (dft_num_macro == DFTNUM_1024) return 1024; - if (dft_num_macro == DFTNUM_2048) return 2048; - if (dft_num_macro == DFTNUM_4096) return 4096; - if (dft_num_macro == DFTNUM_8192) return 8192; - if (dft_num_macro == DFTNUM_16384) return 16384; - return 2048; // Safe default +void AD5940_ReadWriteNBytes(unsigned char *pSendBuffer, unsigned char *pRecvBuff, unsigned long length) { + spi_write_read_blocking(spi0, pSendBuffer, pRecvBuff, length); } -// Structure to hold calculated configuration -typedef struct { - uint32_t DftNum; - uint32_t DftSrc; - uint32_t Sinc3Osr; - uint32_t Sinc2Osr; - float SampleRate; // Estimated -} FilterConfig_Type; +// --------------------------------------------------------------------------- +// Application Logic +// --------------------------------------------------------------------------- -// Calculates optimal DFT and Filter settings based on frequency -// Optimized for High Speed Loop (HFOSC 16MHz) only -void AD5940_GetFilterCfg(float freq, FilterConfig_Type *pCfg) { - // Strategy: - // For > 50Hz, use SINC3 (Fast, ~200kHz) - // For <= 50Hz, use SINC2 path (Slower, ~9kHz) to capture full waves - - if (freq >= 50.0f) { - pCfg->DftSrc = DFTSRC_SINC3; - pCfg->Sinc3Osr = ADCSINC3OSR_4; - pCfg->Sinc2Osr = ADCSINC2OSR_22; // Don't care for SINC3 src - pCfg->SampleRate = 200000.0f; // 800k / 4 - - // Adjust DFT size for speed vs accuracy at high freq - if (freq > 40000.0f) pCfg->DftNum = DFTNUM_2048; - else if (freq > 1000.0f) pCfg->DftNum = DFTNUM_4096; - else pCfg->DftNum = DFTNUM_8192; - } - else { - // Low Frequency High Speed (e.g. 10Hz) - // Use SINC2 filter to slow down data rate - // Rate = 800k / (4 * 22) = 9090 Hz - pCfg->DftSrc = DFTSRC_SINC2NOTCH; - pCfg->Sinc3Osr = ADCSINC3OSR_4; - pCfg->Sinc2Osr = ADCSINC2OSR_22; - pCfg->SampleRate = 9090.0f; - - // 8192 samples @ 9kHz = ~0.9 seconds - // Covers 9 cycles of 10Hz. Perfect. - pCfg->DftNum = DFTNUM_8192; - } -} - -// -------------------------------------------------------------------------- -// Measurement Functions -// -------------------------------------------------------------------------- - -static uint32_t AppBuff[512]; - -// Internal Helper for Calibration -static AD5940Err RunCalibration(void) -{ - ADCPGACal_Type pga_cal; - - pga_cal.AdcClkFreq = 16000000.0; - pga_cal.SysClkFreq = 16000000.0; - pga_cal.ADCPga = ADCPGA_1; - pga_cal.ADCSinc2Osr = ADCSINC2OSR_1333; - pga_cal.ADCSinc3Osr = ADCSINC3OSR_4; - pga_cal.TimeOut10us = 100000; - pga_cal.VRef1p82 = 1.82; - pga_cal.VRef1p11 = 1.11; - pga_cal.PGACalType = PGACALTYPE_OFFSETGAIN; - - return AD5940_ADCPGACal(&pga_cal); -} - -// Command Handler for "CAL" -static void AppADCPgaCal(void) -{ - printf("LOG,Preparing for Calibration...\n"); - // Ensure clean state before CAL - AD5940_PulseReset(); - AD5940_Initialize(); - AD5940_WriteReg(REG_INTC_INTCSEL0, 0xFFFFFFFF); - AD5940_WriteReg(REG_INTC_INTCCLR, 0xFFFFFFFF); - - AD5940Err err = RunCalibration(); - if(err != AD5940ERR_OK) printf("LOG,ADC Cal Failed: %d\n", err); - else printf("LOG,ADC Cal Passed.\n"); - - // Cleanup: Turn off everything after CAL to leave clean slate - AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); -} - -// High Speed Loop (HSTIA + HSDAC) for ALL Frequencies -void MeasureHighSpeed(float freq) -{ - // 1. HARD RESET & Re-Initialize - AD5940_PulseReset(); - AD5940_Initialize(); - AD5940_WriteReg(REG_INTC_INTCSEL0, 0xFFFFFFFF); - AD5940_WriteReg(REG_INTC_INTCCLR, 0xFFFFFFFF); - - // 2. Calibrate - // Note: Calibration routines are invasive. They might leave the AFE in weird states. - AD5940Err calErr = RunCalibration(); - if(calErr != AD5940ERR_OK) { - printf("LOG,Auto-Calibration Failed: %d\n", calErr); - } - - // CRITICAL: Shut down EVERYTHING after calibration. - AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); - - // CRITICAL: Disable Sequencer - AD5940_SEQCtrlS(bFALSE); - - // 3. Clock Configuration - AD5940_WriteReg(REG_ALLON_OSCKEY, 0xCB14); - AD5940_WriteReg(REG_ALLON_OSCCON, 0x0003); // Enable HFOSC - sleep_ms(2); - - AD5940_WriteReg(REG_AFE_LPMODEKEY, 0xC59D6); - AD5940_WriteReg(REG_AFE_LPMODECLKSEL, 0); // Select HFOSC - - spi_set_baudrate(SPI_PORT, SPI_BAUDRATE_HIGH); - - // 4. Switch Matrix Cleanup - AD5940_WriteReg(REG_AFE_LPTIASW0, 0x0000); - AD5940_WriteReg(REG_AFE_LPDACSW0, 0x0000); - - // 5. Configure Loop - HSLoopCfg_Type hs_loop; - hs_loop.HsDacCfg.ExcitBufGain = EXCITBUFGAIN_2; - hs_loop.HsDacCfg.HsDacGain = HSDACGAIN_1; - hs_loop.HsDacCfg.HsDacUpdateRate = 7; - - if (freq > 1000.0f) { - hs_loop.HsTiaCfg.HstiaRtiaSel = HSTIARTIA_1K; - } else { - hs_loop.HsTiaCfg.HstiaRtiaSel = HSTIARTIA_5K; - } - - hs_loop.HsTiaCfg.HstiaBias = HSTIABIAS_1P1; - hs_loop.HsTiaCfg.HstiaCtia = 16; - hs_loop.HsTiaCfg.DiodeClose = bFALSE; - - AD5940_HSLoopCfgS(&hs_loop); - - // 6. Switch Matrix (S+/S-) - AD5940_WriteReg(REG_AFE_SWCON, BITM_AFE_SWCON_SWSOURCESEL); - AD5940_WriteReg(REG_AFE_DSWFULLCON, SWD_CE0); - AD5940_WriteReg(REG_AFE_PSWFULLCON, 0x0000); - AD5940_WriteReg(REG_AFE_NSWFULLCON, 0x0000); - AD5940_WriteReg(REG_AFE_TSWFULLCON, SWT_SE0 | SWT_T9); - - // 7. Get Dynamic Configuration - FilterConfig_Type cfg; - AD5940_GetFilterCfg(freq, &cfg); - - // 8. ADC Configuration - ADCBaseCfg_Type adc_cfg; - memset(&adc_cfg, 0, sizeof(adc_cfg)); - adc_cfg.ADCMuxP = ADCMUXP_HSTIA_P; - adc_cfg.ADCMuxN = ADCMUXN_HSTIA_N; - adc_cfg.ADCPga = ADCPGA_1; - AD5940_ADCBaseCfgS(&adc_cfg); - - // Initialize and Enable Clocks - ADCFilterCfg_Type filter_cfg; - memset(&filter_cfg, 0, sizeof(filter_cfg)); - - filter_cfg.ADCSinc3Osr = cfg.Sinc3Osr; - filter_cfg.ADCSinc2Osr = cfg.Sinc2Osr; - filter_cfg.ADCAvgNum = ADCAVGNUM_16; - filter_cfg.ADCRate = ADCRATE_800KHZ; - filter_cfg.BpNotch = bTRUE; - filter_cfg.BpSinc3 = bFALSE; - filter_cfg.Sinc2NotchEnable = bTRUE; - - // Explicitly Enable Clocks - filter_cfg.DFTClkEnable = bTRUE; - filter_cfg.WGClkEnable = bTRUE; - filter_cfg.Sinc3ClkEnable = bTRUE; - filter_cfg.Sinc2NotchClkEnable = bTRUE; - - AD5940_ADCFilterCfgS(&filter_cfg); - - // Configure ADC Buffers - AD5940_WriteReg(REG_AFE_ADCBUFCON, 0x005F3D0F); - - // 9. Waveform - AD5940_WriteReg(REG_AFE_WGFCW, AD5940_WGFreqWordCal(freq, 16000000.0)); - AD5940_WriteReg(REG_AFE_WGAMPLITUDE, 2047); - AD5940_WriteReg(REG_AFE_WGOFFSET, 0); - AD5940_WriteReg(REG_AFE_WGPHASE, 0); - AD5940_WriteReg(REG_AFE_WGCON, WGTYPE_SIN); - - // 10. DFT - DFTCfg_Type dft_cfg; - dft_cfg.DftNum = cfg.DftNum; - dft_cfg.DftSrc = cfg.DftSrc; - dft_cfg.HanWinEn = bTRUE; - AD5940_DFTCfgS(&dft_cfg); - - // 11. Configure FIFO for DFT - // Ensure we capture DFT results in FIFO - FIFOCfg_Type fifo_cfg; - fifo_cfg.FIFOEn = bTRUE; - fifo_cfg.FIFOMode = FIFOMODE_FIFO; - fifo_cfg.FIFOSize = FIFOSIZE_4KB; - fifo_cfg.FIFOSrc = FIFOSRC_DFT; - fifo_cfg.FIFOThresh = 4; - AD5940_FIFOCfg(&fifo_cfg); - - // 12. Run - - // Power Up Analog Blocks - AD5940_AFECtrlS(AFECTRL_HSDACPWR|AFECTRL_HSTIAPWR|AFECTRL_ADCPWR|AFECTRL_DACREFPWR|AFECTRL_EXTBUFPWR|AFECTRL_INAMPPWR, bTRUE); - - sleep_ms(20); - - // CRITICAL FIX: Force AFECON Clean - uint32_t current_afecon = AD5940_ReadReg(REG_AFE_AFECON); - current_afecon &= ~(0x00003000); // Clear Temp bits - AD5940_WriteReg(REG_AFE_AFECON, current_afecon); - - // Enable ADC Repeat Mode - AD5940_ADCRepeatCfgS(0xffffffff); - - // Clear and Enable Interrupts - AD5940_WriteReg(REG_INTC_INTCCLR, 0xFFFFFFFF); - AD5940_WriteReg(REG_INTC_INTCSEL0, 0xFFFFFFFF); - - // Start Conversion - AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT|AFECTRL_WG, bTRUE); - - // Calculate Timeout using Helper - uint32_t sample_count = GetDftSamples(cfg.DftNum); - float duration = (float)sample_count / cfg.SampleRate; - uint32_t timeout_us = (uint32_t)(duration * 1000000.0f) + 2000000; - - // Polling Loop with Exit Condition - uint32_t start_time = to_us_since_boot(get_absolute_time()); - bool success = false; - - // Results - int32_t real = 0; - int32_t image = 0; - - while((to_us_since_boot(get_absolute_time()) - start_time) < timeout_us) { - - // Polling Strategy: Check FIFO Count instead of Interrupt Flags - // One DFT result = 2 words (Real + Image). We wait for >= 2 words. - uint32_t fifo_cnt = (AD5940_ReadReg(REG_AFE_FIFOCNTSTA) & 0x07FF0000) >> 16; - - if(fifo_cnt >= 2) { - // Read result from FIFO - uint32_t buffer[2]; - AD5940_FIFORd(buffer, 2); - real = (int32_t)buffer[0]; - image = (int32_t)buffer[1]; - - AD5940_WriteReg(REG_INTC_INTCCLR, 0xFFFFFFFF); - success = true; - break; - } - sleep_us(100); - } - - if (!success) { - uint32_t flags = AD5940_ReadReg(REG_INTC_INTCFLAG0); - uint32_t afecon_read = AD5940_ReadReg(REG_AFE_AFECON); - uint32_t fifo_cnt = (AD5940_ReadReg(REG_AFE_FIFOCNTSTA) & 0x07FF0000) >> 16; - printf("LOG,Error: Measurement Timeout (HS). Exp Duration: %.2fs. Flags: 0x%08X, AFECON: 0x%08X, FIFO: %d\n", duration, flags, afecon_read, fifo_cnt); - } - - // 13. Process Result - // Sign Extend 18-bit to 32-bit - // Store original raw values before processing - int32_t raw_real = real; - int32_t raw_image = image; - - if(real & (1<<17)) real |= 0xFFFC0000; - if(image & (1<<17)) image |= 0xFFFC0000; - - float mag = sqrt((float)real*real + (float)image*image); - float rtia_val = (freq > 1000.0f) ? 1000.0f : 5000.0f; - float impedance = (mag > 0) ? (2047.0f / mag) * rtia_val : 0; - float phase = atan2((float)image, (float)real); - - // Updated Output Format: Freq, Impedance, Phase, RawReal, RawImag - printf("DATA,%.2f,%.4f,%.4f,%d,%d\n", freq, impedance, phase, raw_real, raw_image); - - AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); -} - -// -------------------------------------------------------------------------- -// Main -// -------------------------------------------------------------------------- - -void process_command(char* cmd) { - char* token = strtok(cmd, " "); - if (!token) return; - - if (strcmp(token, "CAL") == 0) { - AppADCPgaCal(); - } - else if (strcmp(token, "MEAS") == 0) { - char* arg1 = strtok(NULL, " "); - if (arg1) { - float freq = strtof(arg1, NULL); - if (freq < 10.0f) { - freq = 10.0f; - } - MeasureHighSpeed(freq); - } - } - else if (strcmp(token, "ID") == 0) { - uint32_t chip_id = AD5940_ReadReg(REG_AFECON_CHIPID); - printf("LOG,Chip ID: 0x%04X\n", chip_id); - } -} - -int main() { - stdio_init_all(); - sleep_ms(1000); - - spi_init(SPI_PORT, SPI_BAUDRATE_HIGH); - spi_set_format(SPI_PORT, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST); - +void setup_pins(void) { + // SPI0 at 1MHz + spi_init(spi0, 1000000); gpio_set_function(PIN_MISO, GPIO_FUNC_SPI); - gpio_set_function(PIN_SCK, GPIO_FUNC_SPI); + gpio_set_function(PIN_SCK, GPIO_FUNC_SPI); gpio_set_function(PIN_MOSI, GPIO_FUNC_SPI); + // CS gpio_init(PIN_CS); gpio_set_dir(PIN_CS, GPIO_OUT); gpio_put(PIN_CS, 1); - gpio_init(PIN_RESET); - gpio_set_dir(PIN_RESET, GPIO_OUT); - gpio_put(PIN_RESET, 1); + // RST + gpio_init(PIN_RST); + gpio_set_dir(PIN_RST, GPIO_OUT); + gpio_put(PIN_RST, 1); - gpio_init(PIN_AD_INTERRUPT); - gpio_set_dir(PIN_AD_INTERRUPT, GPIO_IN); - gpio_pull_up(PIN_AD_INTERRUPT); + // INT + gpio_init(PIN_INT); + gpio_set_dir(PIN_INT, GPIO_IN); + gpio_pull_up(PIN_INT); +} - // Initial Start - AD5940_PulseReset(); - AD5940_Initialize(); - AD5940_WriteReg(REG_INTC_INTCSEL0, 0xFFFFFFFF); - AD5940_WriteReg(REG_INTC_INTCCLR, 0xFFFFFFFF); - AD5940_SEQGenInit(AppBuff, 512); +void configure_afe(void) { + HSDACCfg_Type hsdac_cfg; + HSTIACfg_Type hsrtia_cfg; + HSLoopCfg_Type hsloop_cfg; + + // Reset AFE control + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); + + // Configure High Speed DAC + hsdac_cfg.ExcitBufGain = EXCITBUFGAIN_2; + hsdac_cfg.HsDacGain = HSDACGAIN_1; + hsdac_cfg.HsDacUpdateRate = 0x1B; + AD5940_HSDacCfgS(&hsdac_cfg); + + // Configure High Speed TIA + hsrtia_cfg.HstiaDeRtia = HSTIADERTIA_1K; + hsrtia_cfg.HstiaCtia = 31; // 31pF + hsrtia_cfg.HstiaRtiaSel = HSTIARTIA_1K; + hsrtia_cfg.HstiaBias = HSTIABIAS_1P1; + hsrtia_cfg.DiodeClose = bFALSE; + hsrtia_cfg.HstiaDeRload = HSTIADERLOAD_OPEN; + AD5940_HSTIACfgS(&hsrtia_cfg); + + // Configure High Speed Loop + hsloop_cfg.HsDacCfg = hsdac_cfg; + hsloop_cfg.HsTiaCfg = hsrtia_cfg; - char buffer[64]; - int pos = 0; + hsloop_cfg.SWMatCfg.Dswitch = SWD_OPEN; + hsloop_cfg.SWMatCfg.Pswitch = SWP_OPEN; + hsloop_cfg.SWMatCfg.Nswitch = SWN_OPEN; + hsloop_cfg.SWMatCfg.Tswitch = SWT_OPEN; + + hsloop_cfg.WgCfg.WgType = WGTYPE_SIN; + hsloop_cfg.WgCfg.GainCalEn = bFALSE; + hsloop_cfg.WgCfg.OffsetCalEn = bFALSE; + hsloop_cfg.WgCfg.SinCfg.SinFreqWord = AD5940_WGFreqWordCal(1000.0, 16000000.0); + hsloop_cfg.WgCfg.SinCfg.SinAmplitudeWord = 2047; + hsloop_cfg.WgCfg.SinCfg.SinOffsetWord = 0; + hsloop_cfg.WgCfg.SinCfg.SinPhaseWord = 0; + + AD5940_HSLoopCfgS(&hsloop_cfg); + + // Enable Power + AD5940_AFECtrlS(AFECTRL_ADCPWR | AFECTRL_HSTIAPWR | AFECTRL_HSDACPWR | AFECTRL_HPREFPWR, bTRUE); + + // Enable Interrupts + AD5940_WriteReg(REG_INTC_INTCSEL0, BITM_INTC_INTCSEL0_INTSEL14); +} + +float perform_dft(void) { + iImpCar_Type dft_res; + fImpCar_Type f_res; + + AD5940_AFECtrlS(AFECTRL_ADCCNV | AFECTRL_DFT, bTRUE); + + // Wait for interrupt or timeout + uint32_t timeout = 50000; + while(gpio_get(PIN_INT) && timeout--) { + sleep_us(10); + } + + dft_res.Real = (int32_t)AD5940_ReadReg(REG_AFE_DFTREAL); + dft_res.Image = (int32_t)AD5940_ReadReg(REG_AFE_DFTIMAG); + + AD5940_AFECtrlS(AFECTRL_ADCCNV | AFECTRL_DFT, bFALSE); + AD5940_WriteReg(REG_INTC_INTCFLAG0, BITM_INTC_INTCFLAG0_FLAG14); + + f_res.Real = (float)dft_res.Real; + f_res.Image = (float)dft_res.Image; + + return AD5940_ComplexMag(&f_res); +} + +void set_sw_matrix(uint32_t lp_sw, uint32_t hs_sw) { + AD5940_WriteReg(REG_AFE_LPTIASW0, lp_sw); + AD5940_WriteReg(REG_AFE_HSTIACON, hs_sw); +} + +void measure_at_freq(float freq) { + FreqParams_Type freq_params = AD5940_GetFreqParameters(freq); + + // 1. Update HSDAC Update Rate based on frequency + uint32_t hsdac_rate = 0x1B; + if(freq >= 80000.0f) { + hsdac_rate = 0x07; + } + + uint32_t hsdaccon = AD5940_ReadReg(REG_AFE_HSDACCON); + hsdaccon &= ~BITM_AFE_HSDACCON_RATE; + hsdaccon |= (hsdac_rate << BITP_AFE_HSDACCON_RATE); + AD5940_WriteReg(REG_AFE_HSDACCON, hsdaccon); + + // 2. Update Waveform Generator Frequency + uint32_t freq_word = AD5940_WGFreqWordCal(freq, 16000000.0f); + AD5940_WriteReg(REG_AFE_WGFCW, freq_word); + + // 3. Update Filter Settings + ADCFilterCfg_Type filter_cfg; + // Initialize struct to 0 to avoid garbage + filter_cfg.ADCSinc3Osr = freq_params.ADCSinc3Osr; + filter_cfg.ADCSinc2Osr = freq_params.ADCSinc2Osr; + filter_cfg.ADCAvgNum = ADCAVGNUM_16; + filter_cfg.ADCRate = ADCRATE_800KHZ; + filter_cfg.BpNotch = bTRUE; + filter_cfg.BpSinc3 = bFALSE; + filter_cfg.Sinc2NotchEnable = bTRUE; + filter_cfg.DFTClkEnable = bTRUE; + filter_cfg.WGClkEnable = bTRUE; + filter_cfg.Sinc3ClkEnable = bTRUE; + filter_cfg.Sinc2NotchClkEnable = bTRUE; + AD5940_ADCFilterCfgS(&filter_cfg); + + DFTCfg_Type dft_cfg; + dft_cfg.DftNum = freq_params.DftNum; + dft_cfg.DftSrc = freq_params.DftSrc; + dft_cfg.HanWinEn = bTRUE; + AD5940_DFTCfgS(&dft_cfg); + + // 4. Perform Measurement + // RCAL + set_sw_matrix(0, SWP_RCAL0 | SWN_RCAL1); + sleep_ms(5); + float mag_cal = perform_dft(); + + // Z + set_sw_matrix(0, SWP_CE0 | SWP_RE0 | SWN_SE0 | SWT_DE0); + sleep_ms(5); + float mag_z = perform_dft(); + + if (mag_z > 0.01f && mag_cal > 0.01f) { + float impedance = (mag_cal / mag_z) * RCAL_VALUE; + printf("DATA,%.2f,%.2f,0,0,0\n", freq, impedance); + } else { + printf("DATA,%.2f,0,0,0,0\n", freq); + } +} + +void run_sweep(float start_freq, float end_freq, int steps) { + float log_start = log10f(start_freq); + float log_end = log10f(end_freq); + float step_size = (steps > 1) ? (log_end - log_start) / (steps - 1) : 0; + + printf("START_SWEEP\n"); + + for (int i = 0; i < steps; ++i) { + float freq = powf(10.0f, log_start + (i * step_size)); + measure_at_freq(freq); + } + + printf("END_SWEEP\n"); +} + +void system_init(void) { + setup_pins(); + + // Hardware Reset AD5940 + AD5940_RstClr(); + sleep_ms(10); + AD5940_RstSet(); + sleep_ms(10); + + AD5940_Initialize(); + configure_afe(); +} + +int main() { + stdio_init_all(); + sleep_ms(2000); + + system_init(); + + printf("SYSTEM_READY\n"); while (true) { - int c = getchar_timeout_us(1000); - if (c != PICO_ERROR_TIMEOUT) { - if (c == '\n' || c == '\r') { - if (pos > 0) { - buffer[pos] = 0; - process_command(buffer); - pos = 0; - } - } else if (pos < 63) { - buffer[pos++] = (char)c; - } + int c = getchar_timeout_us(100); + if (c == 'm') { + run_sweep(100.0f, 100000.0f, 50); + } + if (c == 'z') { + system_init(); + printf("RESET_DONE\n"); } } + return 0; } \ No newline at end of file