184 lines
8.5 KiB
Plaintext
184 lines
8.5 KiB
Plaintext
/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
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/*-Sizes-*/
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define symbol __ICFEDIT_size_cstack__ = 0x400;
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define symbol __ICFEDIT_size_heap__ = 0x200;
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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// symbols
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define symbol USE_PARITY = 1;
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define symbol FLASH = 0x00000000; // flash address
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define symbol FLASH_SIZE = 256K; // 128k flash size
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define symbol FLASH_PAGE_SIZE = 2K; // 2k flash page size
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define symbol PAGE0_ROM_START = 0x1A0;
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define symbol SIZE_OF_INTVEC = 384;
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define symbol START_OF_READ_PROTECT_KEY_HASH = FLASH+SIZE_OF_INTVEC;
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define symbol SIZE_OF_READ_PROTECT_KEY_HASH = 16;
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define symbol START_OF_CRC_READ_PROTECT_KEY_HASH = FLASH+SIZE_OF_INTVEC+SIZE_OF_READ_PROTECT_KEY_HASH;
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define symbol SIZE_OF_CRC_READ_PROTECT_KEY_HASH = 4;
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define symbol START_OF_NUM_CRC_PAGES = FLASH+SIZE_OF_INTVEC+SIZE_OF_READ_PROTECT_KEY_HASH+SIZE_OF_CRC_READ_PROTECT_KEY_HASH;
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define symbol NUM_OF_CRC_PAGES = 4;
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// user-selectable SRAM mode
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// SRAM Banks 1 & 2 are dynamically configurable for hibernation retention at runtime
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// referred to here as "xRAM_bank#_retained_region", where x = i (instruction) or d (data) and # = 1 or 2
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define symbol USER_SRAM_MODE = 2;
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// RAM bank sizes sizes are invariant... locations vary by RAM Mode#
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define symbol RAM_BANK0_SIZE = 8K;
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define symbol RAM_BANK1_SIZE = 8K;
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define symbol RAM_BANK2_SIZE = 16K;
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define symbol RAM_BANK3_SIZE = 16K;
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define symbol RAM_BANK4_SIZE = 12K;
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define symbol RAM_BANK5_SIZE = 4K;
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//MODE0 0kB CACHE 32kB ISRAM 32kB DSRAM
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if(USER_SRAM_MODE == 0)
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{
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define symbol RAM_BANK0 = 0x20000000; // Always Retained
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define symbol RAM_BANK1 = 0x20002000; // Retained during Hibernate if SRAMRET.BANK1EN=1
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define symbol RAM_BANK2 = 0x10000000; // Retained during Hibernate if SRAMRET.BANK2EN=1
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define symbol RAM_BANK3 = 0x20040000; // Not retained
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define symbol RAM_BANK4 = 0x10004000; // Not retained
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define region iRAM_bank2_retained_region = mem:[from RAM_BANK2 size RAM_BANK2_SIZE];
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define region iRAM_never_retained_region = mem:[from RAM_BANK4 size (RAM_BANK4_SIZE + RAM_BANK5_SIZE)];
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define region dRAM_always_retained_region = mem:[from RAM_BANK0 size RAM_BANK0_SIZE];
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define region dRAM_bank1_retained_region = mem:[from RAM_BANK1 size RAM_BANK1_SIZE];
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define region dRAM_never_retained_region = mem:[from RAM_BANK3 size RAM_BANK3_SIZE];
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}
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//MODE1 4kB CACHE 28kB ISRAM 32kB DSRAM
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else if(USER_SRAM_MODE == 1)
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{
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define symbol RAM_BANK0 = 0x20000000; // Always Retained
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define symbol RAM_BANK1 = 0x20002000; // Retained during Hibernate if SRAMRET.BANK1EN=1
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define symbol RAM_BANK2 = 0x10000000; // Retained during Hibernate if SRAMRET.BANK2EN=1
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define symbol RAM_BANK3 = 0x20040000; // Not retained
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define region iRAM_bank2_retained_region = mem:[from RAM_BANK2 size RAM_BANK2_SIZE];
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define region iRAM_never_retained_region = mem:[from RAM_BANK4 size RAM_BANK4_SIZE];
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define region dRAM_always_retained_region = mem:[from RAM_BANK0 size RAM_BANK0_SIZE];
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define region dRAM_bank1_retained_region = mem:[from RAM_BANK1 size RAM_BANK1_SIZE];
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define region dRAM_never_retained_region = mem:[from RAM_BANK3 size RAM_BANK3_SIZE];
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}
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//MODE2 0kB CACHE 0kB ISRAM 64kB DSRAM
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else if(USER_SRAM_MODE == 2)
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{
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define symbol RAM_BANK0 = 0x20000000; // Always Retained
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define symbol RAM_BANK1 = 0x20002000; // Retained during Hibernate if SRAMRET.BANK1EN=1
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define symbol RAM_BANK2 = 0x20004000; // Retained during Hibernate if SRAMRET.BANK2EN=1
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define symbol RAM_BANK3 = 0x20040000; // Not retained
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define region dRAM_always_retained_region = mem:[from RAM_BANK0 size RAM_BANK0_SIZE];
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define region dRAM_bank1_retained_region = mem:[from RAM_BANK1 size RAM_BANK1_SIZE];
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define region dRAM_bank2_retained_region = mem:[from RAM_BANK2 size RAM_BANK2_SIZE];
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define region dRAM_never_retained_region = mem:[from RAM_BANK3 size (RAM_BANK3_SIZE + RAM_BANK4_SIZE + RAM_BANK5_SIZE)];
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}
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//MODE3 4kB CACHE 0kB ISRAM 60kB DSRAM
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else if(USER_SRAM_MODE == 3)
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{
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define symbol RAM_BANK0 = 0x20000000; // Always Retained
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define symbol RAM_BANK1 = 0x20002000; // Retained during Hibernate if SRAMRET.BANK1EN=1
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define symbol RAM_BANK2 = 0x20004000; // Retained during Hibernate if SRAMRET.BANK2EN=1
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define symbol RAM_BANK3 = 0x20040000; // Not retained
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define region dRAM_always_retained_region = mem:[from RAM_BANK0 size RAM_BANK0_SIZE];
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define region dRAM_bank1_retained_region = mem:[from RAM_BANK1 size RAM_BANK1_SIZE];
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define region dRAM_bank2_retained_region = mem:[from RAM_BANK2 size RAM_BANK2_SIZE];
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define region dRAM_never_retained_region = mem:[from RAM_BANK3 size (RAM_BANK3_SIZE + RAM_BANK4_SIZE)];
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}
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// ROM regions
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define region ROM_PAGE0_INTVEC = mem:[from FLASH size SIZE_OF_INTVEC];
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define region START_OF_PAGE0_REGION = mem:[from (PAGE0_ROM_START) size (FLASH_PAGE_SIZE - PAGE0_ROM_START)];
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define region ROM_REGION = mem:[from (FLASH + FLASH_PAGE_SIZE) size (FLASH_SIZE - FLASH_PAGE_SIZE)];
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define region SRAM_CODE = mem:[from (RAM_BANK2) size (RAM_BANK2_SIZE)];
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place at address mem: START_OF_READ_PROTECT_KEY_HASH { readonly section ReadProtectedKeyHash };
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place at address mem: START_OF_CRC_READ_PROTECT_KEY_HASH { readonly section CRC_ReadProtectedKeyHash };
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place at address mem: START_OF_NUM_CRC_PAGES { readonly section NumCRCPages };
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// C-Runtime blocks
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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// Flash Page0 contains an optional checksum block, as verified by the boot kernel at startup.
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// If generating a checksum ("Checksum" linker dialogue box) during the build, it is also
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// required to add "--keep __checksum" to the linker "Extra Options" dialogue to preserve the
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// linker-generated "__checksum" symbol.
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define block CHECKSUM with alignment = 4, size = 4 { ro section .checksum };
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// force manditory placement of the CHECKSUM block within Page0
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place at address 0x000007FC { block CHECKSUM };
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// KEEP these blocks, avoiding linker elimination...
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keep {
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block CHECKSUM,
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};
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// initializations...
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do not initialize { section .noinit };
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// expand encoded initialized data variables from flash image into RAM during C-Runtime Startup
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initialize by copy { rw };
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//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
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// ROM: place IVT at start of flash, page zero (ahead of the "meta-data")
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place at start of ROM_PAGE0_INTVEC { ro section .intvec };
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place in START_OF_PAGE0_REGION { ro section Page0_region };
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// ROM: place remaining read-only code/data in flash, starting at flash page1
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place in ROM_REGION { ro };
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// Create as large a gap as possible between the stack and the heap to avoid collision...
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// RAM: place stack @ end (high-address) of always-retained dRAM because stack "grows" towards low addresses
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place at end of dRAM_always_retained_region { block CSTACK };
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// RAM: place heap, etc., into low-address, always-retained dRAM
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place in dRAM_always_retained_region { rw, block HEAP };
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// ISRAM section for placing code in SRAM
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place in SRAM_CODE {section ISRAM_REGION};
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initialize by copy {section ISRAM_REGION };
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// NOTE: To direct data to reside in specifically named memory regions
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// (suce as into specific banks or non-hibernation-retained memory),
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// use either of the IAR directives:
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// '#pragma location="named_region"' directive prefix, or the
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// '@ "named_region"' suffix with the data declarations.
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// place data declared as bank1-hibernation-retained
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place in dRAM_bank1_retained_region { rw section bank1_retained_ram };
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// place data declared as bank2-hibernation-retained (RAM modes 2 or 3 only)
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//place in dRAM_bank2_retained_region { rw section bank2_retained_ram };
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// RAM: place volatile RAM data (never retained during hibernation) into select
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// named volatile regions, depending on SRAM Mode# and SRAMRET.BANK#EN bits
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//
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// place unterained sections
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place in dRAM_never_retained_region { rw section never_retained_ram };
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