diff --git a/#AD5940.h reference.md b/#AD5940.h reference.md new file mode 100644 index 0000000..e388ff8 --- /dev/null +++ b/#AD5940.h reference.md @@ -0,0 +1,811 @@ +# # AD594x AFE Controller: A Streamlined Register and Functional Reference +-------------------------------------------------------------------------------- +### 1.0 Introduction +This document serves as a streamlined, developer-focused technical reference for the Analog Devices AD594x Analog Front End (AFE) controller. Its purpose is to provide a clear, structured, and condensed guide to the chip's register map and core functionalities, optimized for clarity and ease of use. +The reference is organized by peripheral module, starting with general-purpose blocks such as I/O and timers. It then proceeds to the central AFE Controller, the watchdog and wakeup timers, and other essential hardware accelerators. The core of the document provides a detailed breakdown of the Analog Front End (AFE) block itself, covering everything from the sequencer and waveform generator to the ADC, TIA, and switch matrix. The document concludes with a practical functional example demonstrating how these registers and features are used to perform a low-frequency oscillator calibration. +### 2.0 General Purpose I/O (AGPIO) +The General Purpose I/O (AGPIO) module is the primary interface for configuring and controlling the AD594x's digital input/output pins. This block allows each pin to be configured for various functions, with direct control over output state, pull-up/pull-down resistors, and input path enabling. This module is crucial for tasks like triggering external events, synchronizing with other ICs, or providing simple status indicators (e.g., LEDs). +**AGPIO_GP0CON** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **GP0CON** | 0x00000000 | 0x00000000 | AGPIO GPIO Port 0 Configuration | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 14-15 | **PIN7CFG** | 0x0000C000 | P0.7 Configuration Bits | +| 12-13 | **PIN6CFG** | 0x00003000 | P0.6 Configuration Bits | +| 10-11 | **PIN5CFG** | 0x00000C00 | P0.5 Configuration Bits | +| 8-9 | **PIN4CFG** | 0x00000300 | P0.4 Configuration Bits | +| 6-7 | **PIN3CFG** | 0x000000C0 | P0.3 Configuration Bits | +| 4-5 | **PIN2CFG** | 0x00000030 | P0.2 Configuration Bits | +| 2-3 | **PIN1CFG** | 0x0000000C | P0.1 Configuration Bits | +| 0-1 | **PIN0CFG** | 0x00000003 | P0.0 Configuration Bits | +**AGPIO_GP0OEN** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **GP0OEN** | 0x00000004 | 0x00000000 | AGPIO GPIO Port 0 Output Enable | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-7 | **OEN** | 0x000000FF | Pin Output Drive Enable | +**AGPIO_GP0PE** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **GP0PE** | 0x00000008 | 0x00000000 | AGPIO GPIO Port 0 Pull-up/Pull-down Enable | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-7 | **PE** | 0x000000FF | Pin Pull Enable | +**AGPIO_GP0IEN** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **GP0IEN** | 0x0000000C | 0x00000000 | AGPIO GPIO Port 0 Input Path Enable | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-7 | **IEN** | 0x000000FF | Input Path Enable | +**AGPIO_GP0IN** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **GP0IN** | 0x00000010 | 0x00000000 | AGPIO GPIO Port 0 Registered Data Input | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-7 | **IN** | 0x000000FF | Registered Data Input | +**AGPIO_GP0OUT** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **GP0OUT** | 0x00000014 | 0x00000000 | AGPIO GPIO Port 0 Data Output | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-7 | **OUT** | 0x000000FF | Data Out | +**AGPIO_GP0SET** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **GP0SET** | 0x00000018 | 0x00000000 | AGPIO GPIO Port 0 Data Out Set | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-7 | **SET** | 0x000000FF | Set the Output HIGH | +**AGPIO_GP0CLR** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **GP0CLR** | 0x0000001C | 0x00000000 | AGPIO GPIO Port 0 Data Out Clear | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-7 | **CLR** | 0x000000FF | Set the Output LOW | +**AGPIO_GP0TGL** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **GP0TGL** | 0x00000020 | 0x00000000 | AGPIO GPIO Port 0 Pin Toggle | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-7 | **TGL** | 0x000000FF | Toggle the Output | +These registers provide a comprehensive interface for managing the digital I/O pins, transitioning next to the core AFE controller block. +### 3.0 AFE Controller (AFECON) +The AFE Controller (AFECON) module is the central control block for the entire AFE. It is responsible for fundamental operations such as chip identification, system and Analog-to-Digital Converter (ADC) clock configuration, software resets, and triggering measurement sequences. +**AFECON_ADIID** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **ADIID** | 0x00000400 | 0x00000000 | ADI Identification | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-15 | **ADIID** | 0x0000FFFF | ADI Identifier. | +**AFECON_CHIPID** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **CHIPID** | 0x00000404 | 0x00000000 | Chip Identification | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 4-15 | **PARTID** | 0x0000FFF0 | Part Identifier | +| 0-3 | **REVISION** | 0x0000000F | Silicon Revision Number | +**AFECON_CLKCON0** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **CLKCON0** | 0x00000408 | 0x00000441 | Clock Divider Configuration | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 10-15 | **SFFTCLKDIVCNT** | 0x0000FC00 | SFFT Clock Divider Configuration | +| 6-9 | **ADCCLKDIV** | 0x000003C0 | ADC Clock Divider Configuration | +| 0-5 | **SYSCLKDIV** | 0x0000003F | System Clock Divider Configuration | +**AFECON_CLKEN1** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **CLKEN1** | 0x00000410 | 0x000002C0 | Clock Gate Enable | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 7 | **GPT1DIS** | 0x00000080 | GPT1 Clock Enable | +| 6 | **GPT0DIS** | 0x00000040 | GPT0 Clock Enable | +| 5 | **ACLKDIS** | 0x00000020 | ACLK Clock Enable | +**AFECON_CLKSEL** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **CLKSEL** | 0x00000414 | 0x00000000 | Clock Select | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 2-3 | **ADCCLKSEL** | 0x0000000C | Select ADC Clock Source | +| 0-1 | **SYSCLKSEL** | 0x00000003 | Select System Clock Source | +**AFECON_CLKCON0KEY** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **CLKCON0KEY** | 0x00000420 | 0x00000000 | Enable Clock Division to 8Mhz, 4Mhz and 2Mhz | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-15 | **DIVSYSCLK_ULP_EN** | 0x0000FFFF | Enable Clock Division to 8Mhz, 4Mhz and 2Mhz | +**AFECON_SWRSTCON** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **SWRSTCON** | 0x00000424 | 0x00000001 | Software Reset | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-15 | **SWRSTL** | 0x0000FFFF | Software Reset | +**AFECON_TRIGSEQ** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **TRIGSEQ** | 0x00000430 | 0x00000000 | Trigger Sequence | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 3 | **TRIG3** | 0x00000008 | Trigger Sequence 3 | +| 2 | **TRIG2** | 0x00000004 | Trigger Sequence 2 | +| 1 | **TRIG1** | 0x00000002 | Trigger Sequence 1 | +| 0 | **TRIG0** | 0x00000001 | Trigger Sequence 0 | +With the central controller defined, the next section covers the system's safety watchdog timer. +### 4.0 AFE Watchdog Timer (AFEWDT) +The AFE Watchdog Timer (AFEWDT) is a critical safety feature designed to monitor system operation. It can be configured to trigger a system reset or generate an interrupt if the application software fails to refresh it within a specified time period, preventing the system from becoming unresponsive. +**AFEWDT_WDTLD** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **WDTLD** | 0x00000900 | Undefined | Watchdog Timer Load Value | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-15 | **LOAD** | 0x0000FFFF | WDT Load Value | +**AFEWDT_WDTVALS** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **WDTVALS** | 0x00000904 | Undefined | Current Count Value | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-15 | **CCOUNT** | 0x0000FFFF | Current WDT Count Value. | +**AFEWDT_WDTCON** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **WDTCON** | 0x00000908 | Undefined | Watchdog Timer Control Register | +| Bit Position(s) | Bitfield Name | Bitmask | Description | Settings/Enumerations | +|---|---|---|---|---| +| 10 | **WDTIRQEN** | 0x00000400 | WDT Interrupt Enable | | +| 9 | **MINLOAD_EN** | 0x00000200 | Timer Window Control | | +| 8 | **CLKDIV2** | 0x00000100 | Clock Source | | +| 6 | **MDE** | 0x00000040 | Timer Mode Select | | +| 5 | **EN** | 0x00000020 | Timer Enable | | +| 2-3 | **PRE** | 0x0000000C | Prescaler. | | +| 1 | **IRQ** | 0x00000002 | WDT Interrupt Enable | 0 **(RESET):** Watchdog timer timeout creates a reset.
1 **(INTERRUPT):** Watchdog timer timeout creates an interrupt. | +| 0 | **PDSTOP** | 0x00000001 | Power Down Stop Enable | 0 **(CONTINUE):** Continue counting in Hibernate mode.
1 **(STOP):** Stop counter in Hibernate mode. | +**AFEWDT_WDTCLRI** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **WDTCLRI** | 0x0000090C | Undefined | Refresh Watchdog Register | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-15 | **CLRWDG** | 0x0000FFFF | Refresh Register | +**AFEWDT_WDTSTA** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **WDTSTA** | 0x00000918 | Undefined | Timer Status | +| Bit Position(s) | Bitfield Name | Bitmask | Description | Settings/Enumerations | +|---|---|---|---|---| +| 6 | **TMINLD** | 0x00000040 | WDTMINLD Write Status | | +| 5 | **OTPWRDONE** | 0x00000020 | Reset Type Status | | +| 4 | **LOCK** | 0x00000010 | Lock Status | 0 **(OPEN):** Timer operation is not locked.
1 **(LOCKED):** Timer is enabled and locked. | +| 3 | **CON** | 0x00000008 | WDTCON Write Status | | +| 2 | **TLD** | 0x00000004 | WDTVAL Write Status | 0 **(SYNC_COMPLETE):** WDTLD values match across clock domains.
1 **(SYNC_IN_PROGRESS):** Synchronize in progress. | +| 1 | **CLRI** | 0x00000002 | WDTCLRI Write Status | | +| 0 | **IRQ** | 0x00000001 | WDT Interrupt | 0 **(CLEARED):** Watchdog timer interrupt is not pending.
1 **(PENDING):** Watchdog timer interrupt is pending. | +**AFEWDT_WDTMINLD** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **WDTMINLD** | 0x0000091C | Undefined | Minimum Load Value | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-15 | **MIN_LOAD** | 0x0000FFFF | WDT Min Load Value | +Complementing the watchdog is the low-power wakeup timer, which enables periodic operation. +### 5.0 Wakeup Timer (WUPTMR) +The Wakeup Timer (WUPTMR) is a strategic peripheral for managing low-power sleep and wake cycles. It enables the AD594x to enter a low-power hibernate state and wake up at precise, user-defined intervals to execute measurement sequences. This functionality is crucial for applications requiring periodic measurements with high precision while minimizing power consumption. +**WUPTMR_CON** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **CON** | 0x00000800 | 0x00000000 | Timer Control | +| Bit Position(s) | Bitfield Name | Bitmask | Description | Settings/Enumerations | +|---|---|---|---|---| +| 6 | **MSKTRG** | 0x00000040 | Mark Sequence Trigger from Sleep Wakeup Timer | | +| 4-5 | **CLKSEL** | 0x00000030 | Clock Selection | 0x0 **(SWT32K0):** Internal 32kHz OSC
0x1 **(SWTEXT0):** External Clock
0x2 **(SWT32K):** Internal 32kHz OSC
0x3 **(SWTEXT):** External Clock | +| 1-3 | **ENDSEQ** | 0x0000000E | End Sequence | 0x0 **(ENDSEQA):** Stop at SeqA, loop to SeqA
0x1 **(ENDSEQB):** Stop at SeqB, loop to SeqA
0x2 **(ENDSEQC):** Stop at SeqC, loop to SeqA
0x3 **(ENDSEQD):** Stop at SeqD, loop to SeqA
0x4 **(ENDSEQE):** Stop at SeqE, loop to SeqA
0x5 **(ENDSEQF):** Stop at SeqF, loop to SeqA
0x6 **(ENDSEQG):** Stop at SeqG, loop to SeqA
0x7 **(ENDSEQH):** Stop at SeqH, loop to SeqA | +| 0 | **EN** | 0x00000001 | Sleep Wake Timer Enable Bit | 0 **(SWTEN):** Enable Sleep Wakeup Timer
1 **(SWTDIS):** Disable Sleep Wakeup Timer | +**WUPTMR_SEQORDER** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **SEQORDER** | 0x00000804 | 0x00000000 | Order Control | +| Bit Position(s) | Bitfield Name | Bitmask | Description | Settings/Enumerations | +|---|---|---|---|---| +| 14-15 | **SEQH** | 0x0000C000 | SEQH Config | 0x0 **(SEQH0):** Fill SEQ0 In
0x1 **(SEQH1):** Fill SEQ1 In
0x2 **(SEQH2):** Fill SEQ2 In
0x3 **(SEQH3):** Fill SEQ3 In | +| 12-13 | **SEQG** | 0x00003000 | SEQG Config | 0x0 **(SEQG0):** Fill SEQ0 In
0x1 **(SEQG1):** Fill SEQ1 In
0x2 **(SEQG2):** Fill SEQ2 In
0x3 **(SEQG3):** Fill SEQ3 In | +| 10-11 | **SEQF** | 0x00000C00 | SEQF Config | 0x0 **(SEQF0):** Fill SEQ0 In
0x1 **(SEQF1):** Fill SEQ1 In
0x2 **(SEQF2):** Fill SEQ2 In
0x3 **(SEQF3):** Fill SEQ3 In | +| 8-9 | **SEQE** | 0x00000300 | SEQE Config | 0x0 **(SEQE0):** Fill SEQ0 In
0x1 **(SEQE1):** Fill SEQ1 In
0x2 **(SEQE2):** Fill SEQ2 In
0x3 **(SEQE3):** Fill SEQ3 In | +| 6-7 | **SEQD** | 0x000000C0 | SEQD Config | 0x0 **(SEQD0):** Fill SEQ0 In
0x1 **(SEQD1):** Fill SEQ1 In
0x2 **(SEQD2):** Fill SEQ2 In
0x3 **(SEQD3):** Fill SEQ3 In | +| 4-5 | **SEQC** | 0x00000030 | SEQC Config | 0x0 **(SEQC0):** Fill SEQ0 In
0x1 **(SEQC1):** Fill SEQ1 In
0x2 **(SEQC2):** Fill SEQ2 In
0x3 **(SEQC3):** Fill SEQ3 In | +| 2-3 | **SEQB** | 0x0000000C | SEQB Config | 0x0 **(SEQB0):** Fill SEQ0 In
0x1 **(SEQB1):** Fill SEQ1 In
0x2 **(SEQB2):** Fill SEQ2 In
0x3 **(SEQB3):** Fill SEQ3 In | +| 0-1 | **SEQA** | 0x00000003 | SEQA Config | 0x0 **(SEQA0):** Fill SEQ0 In
0x1 **(SEQA1):** Fill SEQ1 In
0x2 **(SEQA2):** Fill SEQ2 In
0x3 **(SEQA3):** Fill SEQ3 In | +**WUPTMR_SEQxWUP / SEQxSLEEP Registers** +The timer provides four sets of registers for defining sleep and active periods for different sequences. These register pairs define the 20-bit sleep and active (wakeup) periods for each of the four sequences (0-3). +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **SEQ0WUPL** | 0x00000808 | 0x0000FFFF | SEQ0 Wakeup Time (LSB) | +| **SEQ0WUPH** | 0x0000080C | 0x0000000F | SEQ0 Wakeup Time (MSB) | +| **SEQ0SLEEPL** | 0x00000810 | 0x0000FFFF | SEQ0 Sleep Time (LSB) | +| **SEQ0SLEEPH** | 0x00000814 | 0x0000000F | SEQ0 Sleep Time (MSB) | +| **SEQ1WUPL** | 0x00000818 | 0x0000FFFF | SEQ1 Wakeup Time (LSB) | +| **SEQ1WUPH** | 0x0000081C | 0x0000000F | SEQ1 Wakeup Time (MSB) | +| **SEQ1SLEEPL** | 0x00000820 | 0x0000FFFF | SEQ1 Sleep Time (LSB) | +| **SEQ1SLEEPH** | 0x00000824 | 0x0000000F | SEQ1 Sleep Time (MSB) | +| **SEQ2WUPL** | 0x00000828 | 0x0000FFFF | SEQ2 Wakeup Time (LSB) | +| **SEQ2WUPH** | 0x0000082C | 0x0000000F | SEQ2 Wakeup Time (MSB) | +| **SEQ2SLEEPL** | 0x00000830 | 0x0000FFFF | SEQ2 Sleep Time (LSB) | +| **SEQ2SLEEPH** | 0x00000834 | 0x0000000F | SEQ2 Sleep Time (MSB) | +| **SEQ3WUPL** | 0x00000838 | 0x0000FFFF | SEQ3 Wakeup Time (LSB) | +| **SEQ3WUPH** | 0x0000083C | 0x0000000F | SEQ3 Wakeup Time (MSB) | +| **SEQ3SLEEPL** | 0x00000840 | 0x0000FFFF | SEQ3 Sleep Time (LSB) | +| **SEQ3SLEEPH** | 0x00000844 | 0x0000000F | SEQ3 Sleep Time (MSB) | +The wakeup timer relies on the fundamental clock sources and power modes managed by the Always-On register block. +### 6.0 Always-On Registers (ALLON) +The Always-On (ALLON) register block controls the most fundamental aspects of the chip's operation. These registers manage power modes, core oscillators, and reset status, and their settings persist even when the chip is in its lowest power states. +**ALLON_PWRMOD** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **PWRMOD** | 0x00000A00 | 0x00000001 | Power Modes | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 15 | **RAMRETEN** | 0x00008000 | Retention for RAM | +| 14 | **ADCRETEN** | 0x00004000 | Keep ADC Power Switch on in Hibernate | +| 3 | **SEQSLPEN** | 0x00000008 | Auto Sleep by Sequencer Command | +| 2 | **TMRSLPEN** | 0x00000004 | Auto Sleep by Sleep Wakeup Timer | +| 0-1 | **PWRMOD** | 0x00000003 | Power Mode Control Bits | +**ALLON_OSCCON** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **OSCCON** | 0x00000A10 | 0x00000003 | Oscillator Control | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 10 | **HFXTALOK** | 0x00000400 | Status of HFXTAL Oscillator | +| 9 | **HFOSCOK** | 0x00000200 | Status of HFOSC Oscillator | +| 8 | **LFOSCOK** | 0x00000100 | Status of LFOSC Oscillator | +| 2 | **HFXTALEN** | 0x00000004 | High Frequency Crystal Oscillator Enable | +| 1 | **HFOSCEN** | 0x00000002 | High Frequency Internal Oscillator Enable | +| 0 | **LFOSCEN** | 0x00000001 | Low Frequency Internal Oscillator Enable | +**ALLON_RSTSTA** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **RSTSTA** | 0x00000A40 | 0x00000000 | Reset Status | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 4 | **PINSWRST** | 0x00000010 | Software Reset Pin | +| 3 | **MMRSWRST** | 0x00000008 | MMR Software Reset | +| 2 | **WDRST** | 0x00000004 | Watchdog Timeout | +| 1 | **EXTRST** | 0x00000002 | External Reset | +| 0 | **POR** | 0x00000001 | Power-on Reset | +**ALLON_CLKEN0** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **CLKEN0** | 0x00000A70 | 0x00000004 | 32KHz Peripheral Clock Enable | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 2 | **TIACHPDIS** | 0x00000004 | TIA Chop Clock Disable | +| 1 | **SLPWUTDIS** | 0x00000002 | Sleep/Wakeup Timer Clock Disable | +| 0 | **WDTDIS** | 0x00000001 | Watch Dog Timer Clock Disable | +These core settings provide the foundation for higher-level peripherals, such as the general-purpose timers. +### 7.0 General Purpose Timers (AGPT0 & AGPT1) +The AD594x includes two 16-bit general-purpose timers, AGPT0 and AGPT1. These timers are highly configurable and can be used for a variety of tasks, including event timing, generating interrupts, signal capture, and Pulse Width Modulation (PWM) generation. +**7.1 Timer 0 (AGPT0)** +**AGPT0_LD0** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **LD0** | 0x00000D00 | Undefined | 16-bit Load Value Register. | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-15 | **LOAD** | 0x0000FFFF | Load Value | +**AGPT0_VAL0** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **VAL0** | 0x00000D04 | Undefined | 16-Bit Timer Value Register. | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-15 | **VAL** | 0x0000FFFF | Current Count | +**AGPT0_CON0** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **CON0** | 0x00000D08 | Undefined | Control Register. | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 15 | **SYNCBYP** | 0x00008000 | Synchronization Bypass | +| 14 | **RSTEN** | 0x00004000 | Counter and Prescale Reset Enable | +| 13 | **EVTEN** | 0x00002000 | Event Select | +| 8-12 | **EVENT** | 0x00001F00 | Event Select Range | +| 7 | **RLD** | 0x00000080 | Reload Control | +| 5-6 | **CLK** | 0x00000060 | Clock Select | +| 4 | **ENABLE** | 0x00000010 | Timer Enable | +| 3 | **MOD** | 0x00000008 | Timer Mode | +| 2 | **UP** | 0x00000004 | Count up | +| 0-1 | **PRE** | 0x00000003 | Prescaler | +**AGPT0_PWMCON0** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **PWMCON0** | 0x00000D20 | Undefined | PWM Control Register. | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 1 | **IDLE** | 0x00000002 | PWM Idle State | +| 0 | **MATCHEN** | 0x00000001 | PWM Match Enabled | +**AGPT0_PWMMAT0** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **PWMMAT0** | 0x00000D24 | Undefined | PWM Match Value Register. | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-15 | **MATCHVAL** | 0x0000FFFF | PWM Match Value | +**7.2 Timer 1 (AGPT1)** +**AGPT1_LD1** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **LD1** | 0x00000E00 | Undefined | 16-bit Load Value Register | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-15 | **LOAD** | 0x0000FFFF | Load Value | +**AGPT1_VAL1** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **VAL1** | 0x00000E04 | Undefined | 16-bit Timer Value Register | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-15 | **VAL** | 0x0000FFFF | Current Count | +**AGPT1_CON1** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **CON1** | 0x00000E08 | Undefined | Control Register | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 15 | **SYNCBYP** | 0x00008000 | Synchronization Bypass | +| 14 | **RSTEN** | 0x00004000 | Counter and Prescale Reset Enable | +| 13 | **EVENTEN** | 0x00002000 | Event Select | +| 8-12 | **EVENT** | 0x00001F00 | Event Select Range | +| 7 | **RLD** | 0x00000080 | Reload Control | +| 5-6 | **CLK** | 0x00000060 | Clock Select | +| 4 | **ENABLE** | 0x00000010 | Timer Enable | +| 3 | **MOD** | 0x00000008 | Timer Mode | +| 2 | **UP** | 0x00000004 | Count up | +| 0-1 | **PRE** | 0x00000003 | Prescaler | +**AGPT1_PWMCON1** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **PWMCON1** | 0x00000E20 | Undefined | PWM Control Register | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 1 | **IDLE** | 0x00000002 | PWM Idle State. | +| 0 | **MATCHEN** | 0x00000001 | PWM Match Enabled. | +**AGPT1_PWMMAT1** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **PWMMAT1** | 0x00000E24 | Undefined | PWM Match Value Register | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-15 | **MATCHVAL** | 0x0000FFFF | PWM Match Value | +For data integrity tasks, the device includes a dedicated hardware accelerator. + +## 8.0 Switch Matrix & Electrode Connections (SWMAT) +The AD5940 features a highly flexible switch matrix that routes external electrode signals (SE0, RE0, CE0, AINx) to internal blocks like the High-Speed DAC (Excitation), the ADC, and the TIA. The matrix is divided into four main blocks: **D** (DAC/Excitation), **P** (Positive Input), **N** (Negative Input), and **T** (TIA/Transimpedance). +**8.1 Core Switch Registers** +These registers provide direct control over every switch in the matrix. +**AFE_SWCON** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **SWCON** | 0x0000200C | 0x0000FFFF | Master Switch Matrix Configuration | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 12-15 | **TMUXCON** | 0x0000F000 | Control of T Switch MUX | +| 8-11 | **NMUXCON** | 0x00000F00 | Control of N Switch MUX | +| 4-7 | **PMUXCON** | 0x000000F0 | Control of P Switch MUX | +| 0-3 | **DMUXCON** | 0x0000000F | Control of D Switch MUX | +**AFE_DSWFULLCON (Excitation/DAC Path)** +Controls switches connecting pins to the Excitation Loop (High-Speed DAC output). +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **DSWFULLCON** | 0x00002150 | 0x00000000 | D-Block Switch Configuration | +| Bit Position(s) | Bitfield Name | Bitmask | Connection/Description | +|---|---|---|---| +| 7 | **D8** | 0x00000080 | Connects **SE0** to D-Node | +| 6 | **D7** | 0x00000040 | Connects **CE0** to D-Node | +| 5 | **D6** | 0x00000020 | Connects **RE0** to D-Node | +| 4 | **D5** | 0x00000010 | Connects **AIN3** to D-Node | +| 3 | **D4** | 0x00000008 | Connects **AIN2** to D-Node | +| 2 | **D3** | 0x00000004 | Connects **AIN1** to D-Node | +| 1 | **D2** | 0x00000002 | Connects **AIN0** to D-Node | +| 0 | **DR0** | 0x00000001 | Connects **RCAL0** to D-Node | +**AFE_PSWFULLCON (Positive Input Path)** +Controls switches connecting pins to the Positive Input bus (ADC P-Input, etc.). +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **PSWFULLCON** | 0x00002154 | 0x00000000 | P-Block Switch Configuration | +| Bit Position(s) | Bitfield Name | Bitmask | Connection/Description | +|---|---|---|---| +| 14 | **PL2** | 0x00004000 | Connects **CE0** to P-Node | +| 13 | **PL** | 0x00002000 | Connects **SE0** to P-Node | +| 11 | **P12** | 0x00000800 | Connects **DE0** to P-Node | +| 10 | **P11** | 0x00000400 | Connects **RE0** to P-Node | +| 4 | **P5** | 0x00000010 | Connects **AIN3** to P-Node | +| 3 | **P4** | 0x00000008 | Connects **AIN2** to P-Node | +| 2 | **P3** | 0x00000004 | Connects **AIN1** to P-Node | +| 1 | **P2** | 0x00000002 | Connects **AIN0** to P-Node | +| 0 | **PR0** | 0x00000001 | Connects **RCAL0** to P-Node | +**AFE_NSWFULLCON (Negative Input Path)** +Controls switches connecting pins to the Negative Input bus (ADC N-Input, TIA Input). +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **NSWFULLCON** | 0x00002158 | 0x00000000 | N-Block Switch Configuration | +| Bit Position(s) | Bitfield Name | Bitmask | Connection/Description | +|---|---|---|---| +| 11 | **NL2** | 0x00000800 | Connects **CE0** to N-Node | +| 10 | **NL** | 0x00000400 | Connects **SE0** to N-Node | +| 8 | **N9** | 0x00000100 | Connects **DE0** to N-Node | +| 7 | **N8** | 0x00000080 | Connects **RE0** to N-Node | +| 4 | **N5** | 0x00000010 | Connects **AIN3** to N-Node | +| 3 | **N4** | 0x00000008 | Connects **AIN2** to N-Node | +| 2 | **N3** | 0x00000004 | Connects **AIN1** to N-Node | +| 1 | **N2** | 0x00000002 | Connects **AIN0** to N-Node | +| 0 | **NR1** | 0x00000200 | Connects **RCAL0** to N-Node | +**AFE_TSWFULLCON (TIA Feedback Path)** +Controls switches connecting pins primarily for TIA feedback loops. +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **TSWFULLCON** | 0x0000215C | 0x00000000 | T-Block Switch Configuration | +| Bit Position(s) | Bitfield Name | Bitmask | Connection/Description | +|---|---|---|---| +| 10 | **T11** | 0x00000400 | **SE0** T-Switch (Often used for SE0-RE0 Short) | +| 9 | **T10** | 0x00000200 | **DE0** T-Switch | +| 8 | **T9** | 0x00000100 | **RE0** T-Switch | +| 6 | **T7** | 0x00000040 | **AIN3** T-Switch | +| 4 | **T5** | 0x00000010 | **AIN2** T-Switch | +| 3 | **T4** | 0x00000008 | **AIN1** T-Switch | +| 2 | **T3** | 0x00000004 | **AIN0** T-Switch | +| 1 | **T2** | 0x00000002 | **RCAL0** T-Switch | +**8.2 Shorting SE0 to RE0 (LPTIA Switch)** +While the TSWFULLCON register contains bit **T11** (associated with SE0), the specific functionality to short **SE0** to **RE0** is explicitly defined as a macro configuration in the Low Power TIA Switch register. This closes internal switch **SW11**. +**AFE_LPTIASW0** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **LPTIASW0** | 0x000020E4 | 0x00000000 | LPTIA Channel 0 Switch Config | +**Key Configuration for SE0-RE0 Short:** +* **Bitmask**: 0x00000800 +* **Enum Name**: ENUM_AFE_LPTIASWO_SESHORTRE +* **Description**: Closes **SW11**. This physically shorts the Sense Electrode 0 (SE0) to the Reference Electrode 0 (RE0). This is commonly used in 2-wire measurement modes or specific sensor biasing configurations. + +⠀**8.3 Electrode Pin Capability Summary** +| **Pin Name** | **Can Source (DAC)?** | **Can Sink (TIA)?** | **Can Sense (ADC P/N)?** | **Relevant Switches** | +|---|---|---|---|---| +| **CE0** | Yes (via D7) | Yes (via NL2) | Yes (via PL2/NL2) | D7, PL2, NL2 | +| **RE0** | Yes (via D6) | Yes (via N8) | Yes (via P11/N8) | D6, P11, N8, T9 | +| **SE0** | Yes (via D8) | Yes (via NL) | Yes (via PL/NL) | D8, PL, NL, T11 | +| **AIN0-3** | Yes (via D2-D5) | Yes (via N2-N5) | Yes (via P2-P5) | D2-D5, P2-P5, N2-N5 | +| **RCAL0** | Yes (via DR0) | Yes (via NR1) | Yes (via PR0) | DR0, PR0, NR1 | + + +### 9.0 CRC Accelerator (AFECRC) +The AFECRC module is a dedicated hardware accelerator for calculating Cyclic Redundancy Checks (CRC). This feature is essential for ensuring data integrity, allowing for fast and efficient error-checking of memory contents (like the sequencer command SRAM) or communication data without burdening the host processor. +**AFECRC_CTL** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **CTL** | 0x00001000 | Undefined | CRC Control Register | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 4 | **W16SWP** | 0x00000010 | Word16 Swap Enabled. | +| 3 | **BYTMIRR** | 0x00000008 | Byte Mirroring. | +| 2 | **BITMIRR** | 0x00000004 | Bit Mirroring. | +| 1 | **LSBFIRST** | 0x00000002 | LSB First Calculation Order | +| 0 | **EN** | 0x00000001 | CRC Peripheral Enable | +**AFECRC_IPDATA** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **IPDATA** | 0x00001004 | Undefined | Data Input. | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-31 | **VALUE** | 0xFFFFFFFF | Data Input. | +**AFECRC_RESULT** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **RESULT** | 0x00001008 | Undefined | CRC Residue | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-31 | **VALUE** | 0xFFFFFFFF | CRC Residue | +**AFECRC_POLY** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **POLY** | 0x0000100C | Undefined | CRC Reduction Polynomial | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-31 | **VALUE** | 0xFFFFFFFF | CRC Reduction Polynomial | +**AFECRC_IPBITS** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **IPBITS** | 0x00001010 | Undefined | Input Data Bits | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-7 | **DATA_BITS** | 0x000000FF | Input Data Bits. | +**AFECRC_IPBYTE** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **IPBYTE** | 0x00001014 | Undefined | Input Data Byte | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-7 | **DATA_BYTE** | 0x000000FF | Input Data Byte. | +**AFECRC_CRC_SIG_COMP** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **CRC_SIG_COMP** | 0x00001020 | Undefined | CRC Signature Compare Data Input | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-31 | **CRC_SIG** | 0xFFFFFFFF | CRC Signature Compare Data Input. | +**AFECRC_CRCINTEN** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **CRCINTEN** | 0x00001024 | Undefined | CRC Error Interrupt Enable | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0 | **CRC_ERR_EN** | 0x00000001 | CRC Error Interrupt Enable Bit | +**AFECRC_INTSTA** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **INTSTA** | 0x00001028 | Undefined | CRC Error Interrupt Status | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0 | **CRC_ERR_ST** | 0x00000001 | CRC Error Interrupt Status Bit | +The next section details the main Analog Front End, which integrates all measurement capabilities. +### 10.0 Analog Front End Core (AFE) +The AFE block is the heart of the AD594x, integrating all the high-performance analog and digital components required for advanced electrochemical and bioimpedance measurements. This comprehensive module contains the high-speed and low-power Digital-to-Analog Converters (DACs) and Transimpedance Amplifiers (TIAs), the ADC and its associated digital filters, the powerful command sequencer with its data and command FIFOs, and the flexible switch matrix that routes signals between the analog blocks and external pins. +**10.1 Core and Sequencer Configuration** +**AFE_AFECON** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **AFECON** | 0x00002000 | 0x00080000 | AFE Configuration | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 21 | **DACBUFEN** | 0x00200000 | Enable DC DAC Buffer | +| 20 | **DACREFEN** | 0x00100000 | High Speed DAC Reference Enable | +| 19 | **ALDOILIMITEN** | 0x00080000 | Analog LDO Current Limiting Enable | +| 16 | **SINC2EN** | 0x00010000 | ADC Output 50/60Hz Filter Enable | +| 15 | **DFTEN** | 0x00008000 | DFT Hardware Accelerator Enable | +| 14 | **WAVEGENEN** | 0x00004000 | Waveform Generator Enable | +| 13 | **TEMPCONVEN** | 0x00002000 | ADC Temp Sensor Convert Enable | +| 12 | **TEMPSENSEN** | 0x00001000 | ADC Temperature Sensor Channel Enable | +| 11 | **TIAEN** | 0x00000800 | High Power TIA Enable | +| 10 | **INAMPEN** | 0x00000400 | Enable Excitation Amplifier | +| 9 | **EXBUFEN** | 0x00000200 | Enable Excitation Buffer | +| 8 | **ADCCONVEN** | 0x00000100 | ADC Conversion Start Enable | +| 7 | **ADCEN** | 0x00000080 | ADC Power Enable | +| 6 | **DACEN** | 0x00000040 | High Power DAC Enable | +| 5 | **HPREFDIS** | 0x00000020 | Disable High Power Reference | +**AFE_SEQCON** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **SEQCON** | 0x00002004 | 0x00000002 | Sequencer Configuration | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 8-15 | **SEQWRTMR** | 0x0000FF00 | Timer for Sequencer Write Commands | +| 4 | **SEQHALT** | 0x00000010 | Halt Seq | +| 1 | **SEQHALTFIFOEMPTY** | 0x00000002 | Halt Sequencer If Empty | +| 0 | **SEQEN** | 0x00000001 | Enable Sequencer | +**AFE_FIFOCON** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **FIFOCON** | 0x00002008 | 0x00001010 | FIFOs Configuration | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 13-15 | **DATAFIFOSRCSEL** | 0x0000E000 | Selects the Source for the Data FIFO. | +| 11 | **DATAFIFOEN** | 0x00000800 | Data FIFO Enable. | +**AFE_SEQCRC** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **SEQCRC** | 0x00002060 | 0x00000001 | Sequencer CRC Value | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-7 | **CRC** | 0x000000FF | Sequencer Command CRC Value. | +**AFE_SEQCNT** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **SEQCNT** | 0x00002064 | 0x00000000 | Sequencer Command Count | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-15 | **COUNT** | 0x0000FFFF | Sequencer Command Count | +**AFE_SEQTIMEOUT** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **SEQTIMEOUT** | 0x00002068 | 0x00000000 | Sequencer Timeout Counter | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-29 | **TIMEOUT** | 0x3FFFFFFF | Current Value of the Sequencer Timeout Counter. | +**10.2 Waveform Generator** +**AFE_WGCON** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **WGCON** | 0x00002014 | 0x00000030 | Waveform Generator Configuration | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 5 | **DACGAINCAL** | 0x00000020 | Bypass DAC Gain | +| 4 | **DACOFFSETCAL** | 0x00000010 | Bypass DAC Offset | +| 1-2 | **TYPESEL** | 0x00000006 | Selects the Type of Waveform | +| 0 | **TRAPRSTEN** | 0x00000001 | Resets the Trapezoid Waveform Generator | +**AFE_WGFCW** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **WGFCW** | 0x00002030 | 0x00000000 | Waveform Generator - Sinusoid Frequency Control Word | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-23 | **SINEFCW** | 0x00FFFFFF | Sinusoid Generator Frequency Control Word | +**AFE_WGPHASE** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **WGPHASE** | 0x00002034 | 0x00000000 | Waveform Generator - Sinusoid Phase Offset | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-19 | **SINEOFFSET** | 0x000FFFFF | Sinusoid Phase Offset | +**AFE_WGOFFSET** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **WGOFFSET** | 0x00002038 | 0x00000000 | Waveform Generator - Sinusoid Offset | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-11 | **SINEOFFSET** | 0x00000FFF | Sinusoid Offset | +**AFE_WGAMPLITUDE** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **WGAMPLITUDE** | 0x0000203C | 0x00000000 | Waveform Generator - Sinusoid Amplitude | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 0-10 | **SINEAMPLITUDE** | 0x000007FF | Sinusoid Amplitude | +**Trapezoid Waveform Registers** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **WGDCLEVEL1** | 0x00002018 | 0x00000000 | Waveform Generator - Trapezoid DC Level 1 | +| **WGDCLEVEL2** | 0x0000201C | 0x00000000 | Waveform Generator - Trapezoid DC Level 2 | +| **WGDELAY1** | 0x00002020 | 0x00000000 | Waveform Generator - Trapezoid Delay 1 Time | +| **WGSLOPE1** | 0x00002024 | 0x00000000 | Waveform Generator - Trapezoid Slope 1 Time | +| **WGDELAY2** | 0x00002028 | 0x00000000 | Waveform Generator - Trapezoid Delay 2 Time | +| **WGSLOPE2** | 0x0000202C | 0x00000000 | Waveform Generator - Trapezoid Slope 2 Time | +**10.3 ADC, Filters, and Data Path** +**AFE_ADCFILTERCON** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **ADCFILTERCON** | 0x00002044 | 0x00000301 | ADC Output Filters Configuration | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 14-15 | **AVRGNUM** | 0x0000C000 | Number of Samples Averaged | +| 12-13 | **SINC3OSR** | 0x00003000 | SINC3 OSR | +| 8-11 | **SINC2OSR** | 0x00000F00 | SINC2 OSR | +| 7 | **AVRGEN** | 0x00000080 | Average Function Enable | +| 6 | **SINC3BYP** | 0x00000040 | SINC3 Filter Bypass | +| 0 | **ADCCLK** | 0x00000001 | ADC Data Rate | +**AFE_ADCCON** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **ADCCON** | 0x000021A8 | 0x00000000 | ADC Configuration | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 16-18 | **GNPGA** | 0x00070000 | PGA Gain Setup | +| 15 | **GNOFSELPGA** | 0x00008000 | Internal Offset/Gain Cancellation | +| 8-12 | **MUXSELN** | 0x00001F00 | Select Negative Input | +| 0-5 | **MUXSELP** | 0x0000003F | Select Positive Input | +**AFE_DFTCON** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **DFTCON** | 0x000020D0 | 0x00000090 | AFE DSP Configuration | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 20-21 | **DFTINSEL** | 0x00300000 | DFT Input Select | +| 4-7 | **DFTNUM** | 0x000000F0 | ADC Samples Used | +| 0 | **HANNINGEN** | 0x00000001 | Hanning Window Enable | +**Data and FIFO Registers** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **ADCDAT** | 0x00002074 | 0x00000000 | ADC Raw Result | +| **DFTREAL** | 0x00002078 | 0x00000000 | DFT Result, Real Part | +| **DFTIMAG** | 0x0000207C | 0x00000000 | DFT Result, Imaginary Part | +| **SINC2DAT** | 0x00002080 | 0x00000000 | Supply Rejection Filter Result | +| **TEMPSENSDAT** | 0x00002084 | 0x00000000 | Temperature Sensor Result | +| **DATAFIFORD** | 0x0000206C | 0x00000000 | Data FIFO Read | +| **CMDFIFOWRITE** | 0x00002070 | 0x00000000 | Command FIFO Write | +**10.4 TIA and DAC Configuration** +**High-Speed DAC and TIA** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **HSDACCON** | 0x00002010 | 0x0000001E | High Speed DAC Configuration | +| **HSDACDAT** | 0x00002048 | 0x00000800 | HS DAC Code | +| **HSRTIACON** | 0x000020F0 | 0x0000000F | High Power RTIA Configuration | +| **DE0RESCON** | 0x000020F8 | 0x000000FF | DE0 HSTIA Resistors Configuration | +| **DE1RESCON** | 0x000020F4 | Undefined | DE1 HSTIA Resistors Configuration | +| **HSTIACON** | 0x000020FC | 0x00000000 | HSTIA Amplifier Configuration | +**Low-Power TIA and DAC** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **LPTIACON0** | 0x000020EC | 0x00000003 | ULPTIA Control Bits Channel 0 | +| **LPTIACON1** | 0x000020E8 | Undefined | ULPTIA Control Bits Channel 1 | +| **LPTIASW0** | 0x000020E4 | 0x00000000 | ULPTIA Switch Configuration for Channel 0 | +| **LPTIASW1** | 0x000020E0 | Undefined | ULPTIA Switch Configuration for Channel 1 | +| **LPDACDAT0** | 0x00002120 | 0x00000000 | LPDAC Data-out | +| **LPDACCON0** | 0x00002128 | 0x00000002 | LPDAC Control Bits | +| **LPDACDAT1** | 0x0000212C | Undefined | Low Power DAC1 data register | +| **LPDACCON1** | 0x00002134 | Undefined | ULP_DACCON1 | +**LPTIACON0/LPTIACON1 Bitfield Breakdown** +| Bit Position(s) | Bitfield Name | Bitmask | Description | Settings/Enumerations | +|---|---|---|---|---| +| 5-10 | **TIAGAIN** | 0x000003E0 | Set RTIA Gain Resistor | 0x00000000 (DISCONTIA): Disconnect
0x00000020 (TIAGAIN200): 200 Ω
0x00000040 (TIAGAIN1K): 1 kΩ
0x00000060 (TIAGAIN2K): 2 kΩ
0x00000080 (TIAGAIN3K): 3 kΩ
0x000000A0 (TIAGAIN4K): 4 kΩ
0x000000C0 (TIAGAIN6K): 6 kΩ
0x000000E0 (TIAGAIN8K): 8 kΩ
0x00000100 (TIAGAIN10K): 10 kΩ
0x00000120 (TIAGAIN12K): 12 kΩ
0x00000140 (TIAGAIN16K): 16 kΩ
0x00000160 (TIAGAIN20K): 20 kΩ
0x00000180 (TIAGAIN24K): 24 kΩ
0x000001A0 (TIAGAIN30K): 30 kΩ
0x000001C0 (TIAGAIN32K): 32 kΩ
0x000001E0 (TIAGAIN40K): 40 kΩ
0x00000200 (TIAGAIN48K): 48 kΩ
0x00000220 (TIAGAIN64K): 64 kΩ
0x00000240 (TIAGAIN85K): 85 kΩ
0x00000260 (TIAGAIN96K): 96 kΩ
0x00000280 (TIAGAIN100K): 100 kΩ
0x000002A0 (TIAGAIN120K): 120 kΩ
0x000002C0 (TIAGAIN128K): 128 kΩ
0x000002E0 (TIAGAIN160K): 160 kΩ
0x00000300 (TIAGAIN196K): 196 kΩ
0x00000320 (TIAGAIN256K): 256 kΩ
0x00000340 (TIAGAIN512K): 512 kΩ | +| 10-12 | **TIARL** | 0x00001C00 | Set RLOAD | 0x00000000 (RL0): 0 Ω
0x00000400 (RL10): 10 Ω
0x00000800 (RL30): 30 Ω
0x00000C00 (RL50): 50 Ω
0x00001000 (RL100): 100 Ω
0x00001400 (RL1P6K): 1.6 kΩ
0x00001800 (RL3P1K): 3.1 kΩ
0x00001C00 (RL3P5K): 3.6 kΩ | +| 13-15 | **TIARF** | 0x0000E000 | Set LPF Resistor | 0x00000000 (DISCONRF): Disconnect
0x00002000 (BYPRF): Bypass
0x00004000 (RF20K): 20 kΩ
0x00006000 (RF100K): 100 kΩ
0x00008000 (RF200K): 200 kΩ
0x0000A000 (RF400K): 400 kΩ
0x0000C000 (RF600K): 600 kΩ
0x0000E000 (RF1MOHM): 1 MΩ | +| 1 | **PAPDEN** | 0x00000002 | PA Power Down | | +| 0 | **TIAPDEN** | 0x00000001 | TIA Power Down | | +**10.5 Switch Matrix** +**AFE_SWCON** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **SWCON** | 0x0000200C | 0x0000FFFF | Switch Matrix Configuration | +| Bit Position(s) | Bitfield Name | Bitmask | Description | +|---|---|---|---| +| 16 | **SWSOURCESEL** | 0x00010000 | Switch Control Select | +| 12-15 | **TMUXCON** | 0x0000F000 | Control of T Switch MUX. | +| 8-11 | **NMUXCON** | 0x00000F00 | Control of N Switch MUX | +| 4-7 | **PMUXCON** | 0x000000F0 | Control of P Switch MUX | +| 0-3 | **DMUXCON** | 0x0000000F | Control of D Switch MUX | +**Switch Matrix Full Configuration and Status** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **DSWFULLCON** | 0x00002150 | 0x00000000 | Switch Matrix Full Configuration (D) | +| **NSWFULLCON** | 0x00002154 | 0x00000000 | Switch Matrix Full Configuration (N) | +| **PSWFULLCON** | 0x00002158 | 0x00000000 | Switch Matrix Full Configuration (P) | +| **TSWFULLCON** | 0x0000215C | 0x00000000 | Switch Matrix Full Configuration (T) | +| **DSWSTA** | 0x000021B0 | 0x00000000 | Switch Matrix Status (D) | +| **PSWSTA** | 0x000021B4 | 0x00006000 | Switch Matrix Status (P) | +| **NSWSTA** | 0x000021B8 | 0x00000C00 | Switch Matrix Status (N) | +| **TSWSTA** | 0x000021BC | 0x00000000 | Switch Matrix Status (T) | +**10.6 Power Management and Calibration** +| Register Name | Address | Reset Value | Description | +|---|---|---|---| +| **PMBW** | 0x000022F0 | 0x00088800 | Power Mode Configuration | +| **LPMODECON** | 0x00002114 | 0x00000102 | LPMODECON | +| **LPREFBUFCON** | 0x00002050 | 0x00000000 | LPREF_BUF_CON | +| **BUFSENCON** | 0x00002180 | 0x00000037 | HP and LP Buffer Control | +| **ADCOFFSETHSTIA** | 0x00002234 | 0x00000000 | ADC Offset Calibration High Speed TIA Channel | +| **ADCGNHSTIA** | 0x00002284 | 0x00004000 | ADC Gain Calibration for HS TIA Channel | +| **DACOFFSET** | 0x00002268 | 0x00000000 | DAC Offset with Attenuator Disabled (LP Mode) | +| **DACGAIN** | 0x00002260 | 0x00000800 | DACGAIN | +This comprehensive set of registers enables fine-grained control over the AD594x's powerful analog capabilities. To illustrate how these are used in practice, the following section provides a functional example. +### 11.0 Functional Example: Low Frequency Oscillator (LFOSC) Calibration +This section provides a practical, high-level example of how the AD594x's features, particularly the sequencer and timers, are used to perform a critical task: calibrating the internal low-frequency oscillator (LFOSC). +**11.1 Overview** +The LFOSC is the clock source for the sleep/wakeup timer, which controls the measurement frequency of the AD5940 (i.e., how often it wakes up to run a measurement sequence). For applications that require a highly accurate and repeatable measurement sample rate, the LFOSC must be calibrated against a more precise, high-frequency clock source, such as an external 16 MHz crystal. The calibration process uses two measurement sequences to accurately measure the LFOSC period. +**11.2 Calibration Steps** +The calibration process involves the following sequence of operations: +**1** **Configure Sequence A:** A sequence is created containing a single command, SEQ_TOUT(0x3fffffff), which starts the high-resolution sequencer timeout counter. This sequence is written to a specific location in the AFE's command SRAM (e.g., Sequence ID 0). +**2** **Configure Sequence B:** A second sequence is created with a single SEQ_STOP() command. This command halts the sequencer and generates an END_SEQ interrupt, signaling the host microcontroller that a measurement period is complete. This sequence is written to another SRAM location (e.g., Sequence ID 1). +**3** **Write Sequences to SRAM:** Both sequences are loaded into the AFE's onboard SRAM. +**4** **Configure the Wakeup Timer:** The wakeup timer is configured to execute Sequence A first, then Sequence B, with a specific time duration (CalDuration) between them. +**5** **Run First Measurement:** The wakeup timer is enabled. It triggers Sequence A, which starts the timeout counter. After the specified CalDuration (e.g., 1000 ms), the timer triggers Sequence B. The END_SEQ interrupt from Sequence B prompts the host MCU to read the final count from the **SEQTIMEOUT** register. This value (TimerCount) represents the wakeup period plus the time required for the MCU to read the register. +**6** **Measure Read Latency:** Sequence B is reconfigured to reset the timeout counter before generating the END_SEQ interrupt. It is then run again. This time, the value read back by the host (TimerCount2) represents only the time it takes to read the register. +**7** **Calculate Frequency:** The final LFOSC frequency is calculated using the difference between TimerCount and TimerCount2, along with the known system clock frequency. + +⠀**11.3 Frequency Calculation** +***Editor's Note:*** *The formula presented in the original source documentation for this calculation appears to be erroneous, simplifying to a physically impossible result. The formula below has been corrected to reflect the logical intent of the calibration procedure.* +The frequency of the low-frequency oscillator is calculated by determining how many system clock cycles occur during a known number of LFOSC cycles (CalDuration_in_ticks). The corrected formula is: +### Frequency = (CalDuration_in_ticks * SystemClkFreq) / (TimerCount - TimerCount2) +Where: +* **Frequency**: The calculated Low Frequency Oscillator frequency in Hz. +* **CalDuration_in_ticks**: The length of the calibration period, specified in LFOSC clock ticks. +* **SystemClkFreq**: The frequency of the AD5940 system clock in Hz (ideally 16 MHz from an external crystal for highest accuracy). +* **TimerCount**: The value read from the **SEQTIMEOUT** register after the first measurement. +* **TimerCount2**: The value read from the **SEQTIMEOUT** register after the second (latency) measurement. +* **(TimerCount - TimerCount2)**: This difference represents the total number of system clock cycles that elapsed during the CalDuration period. + +⠀**11.4 SDK Implementation Note** +The AD5940 Software Development Kit (SDK) provides a ready-to-use function, AD5940_LFOSCMeasure(), which encapsulates this entire calibration logic. This function simplifies the process for the developer and takes key input parameters to control the measurement: +* **CalDuration**: Sets the length of the calibration routine (a value of 1000 ms is advisable for accuracy). +* **SystemClkFreq**: Sets the system clock frequency, which should be 16 MHz for best results. + +⠀By performing this calibration, applications can achieve a high level of accuracy in their measurement sampling frequency, which is critical for time-sensitive electrochemical analysis. + + diff --git a/CMakeLists.txt b/CMakeLists.txt index f09e630..7f25ce6 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,6 +1,4 @@ -# The following five lines of boilerplate have to be in your project's -# CMakeLists in this exact order for cmake to work correctly -cmake_minimum_required(VERSION 3.16) +cmake_minimum_required(VERSION 3.5) include($ENV{IDF_PATH}/tools/cmake/project.cmake) -project(AutoSpa) +project(ad5940_webserver) diff --git a/components/ad5940/CMakeLists.txt b/components/ad5940/CMakeLists.txt new file mode 100644 index 0000000..3ff5aff --- /dev/null +++ b/components/ad5940/CMakeLists.txt @@ -0,0 +1,4 @@ +idf_component_register(SRCS "ad5940.c" + INCLUDE_DIRS ".") + +target_compile_options(${COMPONENT_LIB} PRIVATE -w) diff --git a/components/ad5940/ad5940.c b/components/ad5940/ad5940.c new file mode 100644 index 0000000..e4165d3 --- /dev/null +++ b/components/ad5940/ad5940.c @@ -0,0 +1,4422 @@ +/** + * @file ad5940.c + * @brief AD5940 library. This file contains all AD5940 library functions. + * @author ADI + * @date March 2019 + * @par Revision History: + * + * Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + * + * This software is proprietary to Analog Devices, Inc. and its licensors. + * By using this software you agree to the terms of the associated + * Analog Devices Software License Agreement. +**/ +#include "ad5940.h" + +/*! \mainpage AD5940 Library Introduction + * + * ![AD5940 EVAL Board](https://www.analog.com/-/media/analog/en/evaluation-board-images/images/eval-ad5940elcztop-web.gif?h=500&thn=1&hash=1F38F7CC1002894616F74D316365C0A2631C432B "ADI logo") + * + * # Introduction + * + * The documentation is for AD594x library and examples. + * + * # Manual Structure + * + * @ref AD5940_Library + * - @ref AD5940_Functions + * - @ref TypeDefinitions + * @ref AD5940_Standard_Examples + * @ref AD5940_System_Examples + * + * # How to Use It + * We provide examples that can directly run out of box. + * The files can generally be separated to three parts: + * - AD5940 Library files. ad5940.c and ad5940.h specifically. These two files are shared among all examples. + * - AD5940 System Examples. The system examples mean system level application like measuring impedance. + * - Standard examples. These include basic block level examples like ADC. It shows how to setup and use one specific block. + * + * ## Requirements to run these examples + * ### Hardware + * - Use EVAL_AD5940 or EVAL_AD5941. The default MCU board we used is ADICUP3029. We also provide project for ST NUCLEO board. + * - Or use EVAL_ADuCM355 + * ### Software + * - Pull all the source file from [GitHub](https://github.com/analogdevicesinc/ad5940-examples.git) + * - CMSIS pack that related to specific MCU. This normally is done by IDE you use. + * + * ## Materials + * Please use this library together with following materials. + * - [AD5940 Data Sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5940.pdf) + * - [AD5940 Eval Board](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD5940.html) + * + */ + +/* Remove below variables after AD594x is released. */ +static BoolFlag bIsS2silicon = bFALSE; + +/* Declare of SPI functions used to read/write registers */ +#ifndef CHIPSEL_M355 +static uint32_t AD5940_SPIReadReg(uint16_t RegAddr); +static void AD5940_SPIWriteReg(uint16_t RegAddr, uint32_t RegData); +#else +static uint32_t AD5940_D2DReadReg(uint16_t RegAddr); +static void AD5940_D2DWriteReg(uint16_t RegAddr, uint32_t RegData); +#endif + +/** + * @addtogroup AD5940_Library + * The library functions, structures and constants. + * @{ + * @defgroup AD5940_Functions + * @{ + * @defgroup Function_Helpers + * @brief The functions with no hardware access. They are helpers. + * @{ + * @defgroup Sequencer_Generator_Functions + * @brief The set of function used to track all register read and write once it's enabled. It can translate register write operation to sequencer commands. + * @{ +*/ + +#define SEQUENCE_GENERATOR /*!< Build sequence generator part in to lib. Comment this line to remove this feature */ + +#ifdef SEQUENCE_GENERATOR +/** + * Structure used to store register information(address and its data) + * */ +typedef struct +{ + uint32_t RegAddr :8; /**< 8bit address is enough for sequencer */ + uint32_t RegValue :24; /**< Reg data is limited to 24bit by sequencer */ +}SEQGenRegInfo_Type; + +/** + * Sequencer generator data base. +*/ +struct +{ + BoolFlag EngineStart; /**< Flag to mark start of the generator */ + uint32_t BufferSize; /**< Total buffer size */ + + uint32_t *pSeqBuff; /**< The buffer for sequence generator(both sequences and RegInfo) */ + uint32_t SeqLen; /**< Generated sequence length till now */ + SEQGenRegInfo_Type *pRegInfo; /**< Pointer to buffer where stores register info */ + uint32_t RegCount; /**< The count of register info available in buffer *pRegInfo. */ + AD5940Err LastError; /**< The last error message. */ +}SeqGenDB; /* Data base of Seq Generator */ + +/** + * @brief Manually input a command to sequencer generator. + * @param CmdWord: The 32-bit width sequencer command word. @ref Sequencer_Helper can be used to generate commands. + * @return None; +*/ +void AD5940_SEQGenInsert(uint32_t CmdWord) +{ + uint32_t temp; + temp = SeqGenDB.RegCount + SeqGenDB.SeqLen; + /* Generate Sequence command */ + if(temp < SeqGenDB.BufferSize) + { + SeqGenDB.pSeqBuff[SeqGenDB.SeqLen] = CmdWord; + SeqGenDB.SeqLen ++; + } + else /* There is no buffer */ + SeqGenDB.LastError = AD5940ERR_BUFF; +} + +/** + * @brief Search data-base to get current register value. + * @param RegAddr: The register address. + * @param pIndex: Pointer to a variable that used to store index of found register-info. + * @return Return AD5940ERR_OK if register found in data-base. Otherwise return AD5940ERR_SEQREG. +*/ +static AD5940Err AD5940_SEQGenSearchReg(uint32_t RegAddr, uint32_t *pIndex) +{ + uint32_t i; + + RegAddr = (RegAddr>>2)&0xff; + for(i=0;i>2)&0xff; + SeqGenDB.pRegInfo[0].RegValue = RegData&0x00ffffff; + SeqGenDB.RegCount ++; + } + else /* There is no more buffer */ + { + SeqGenDB.LastError = AD5940ERR_BUFF; + } +} + +/** + * @brief Get current register value. If we have record in data-base, read it. Otherwise, return the register default value. + * @param RegAddr: The register address. + * @return Return register value. +*/ +static uint32_t AD5940_SEQReadReg(uint16_t RegAddr) +{ + uint32_t RegIndex, RegData; + + if(AD5940_SEQGenSearchReg(RegAddr, &RegIndex) != AD5940ERR_OK) + { + /* There is no record in data-base, read the default value. */ + AD5940_SEQGenGetRegDefault(RegAddr, &RegData); + AD5940_SEQRegInfoInsert(RegAddr, RegData); + } + else + { + /* return the current register value stored in data-base */ + RegData = SeqGenDB.pRegInfo[RegIndex].RegValue; + } + + return RegData; +} + +/** + * @brief Generate a sequencer command to write register. If the register address is out of range, it won't generate a command. + * This function will also update the register-info in data-base to record current register value. + * @param RegAddr: The register address. + * @param RegData: The register value. + * @return Return None. +*/ +static void AD5940_SEQWriteReg(uint16_t RegAddr, uint32_t RegData) +{ + uint32_t RegIndex; + + if(RegAddr > 0x21ff) + { + SeqGenDB.LastError = AD5940ERR_ADDROR; /* address out of range */ + return; + } + + if(AD5940_SEQGenSearchReg(RegAddr, &RegIndex) == AD5940ERR_OK) + { + /* Store register value */ + SeqGenDB.pRegInfo[RegIndex].RegValue = RegData; + /* Generate Sequence command */ + AD5940_SEQGenInsert(SEQ_WR(RegAddr, RegData)); + } + else + { + AD5940_SEQRegInfoInsert(RegAddr, RegData); + /* Generate Sequence command */ + AD5940_SEQGenInsert(SEQ_WR(RegAddr, RegData)); + } +} + +/** + * @brief Initialize sequencer generator with specified buffer. + * The buffer is used to store sequencer generated and record register value changes. + * The command is stored from start address of buffer while register value is stored from end of buffer. + * Buffer[0] : First sequencer command; + * Buffer[1] : Second Sequencer command; + * ... + * Buffer[Last-1]: The second register value record. + * Buffer[Last]: The first register value record. + * @param pBuffer: Pointer to the buffer. + * @param BufferSize: The buffer length. + * @return Return None. +*/ +void AD5940_SEQGenInit(uint32_t *pBuffer, uint32_t BufferSize) +{ + if(BufferSize < 2) return; + SeqGenDB.BufferSize = BufferSize; + SeqGenDB.pSeqBuff = pBuffer; + SeqGenDB.pRegInfo = (SEQGenRegInfo_Type*)pBuffer + BufferSize - 1; /* Point to the last element in buffer */ + SeqGenDB.SeqLen = 0; + + SeqGenDB.RegCount = 0; + SeqGenDB.LastError = AD5940ERR_OK; + SeqGenDB.EngineStart = bFALSE; +} + +/** + * @brief Get sequencer command generated. + * @param ppSeqCmd: Pointer to a variable(pointer) used to store the pointer to generated sequencer command. + * @param pSeqLen: Pointer to a variable that used to store how many commands available in buffer. + * @return Return lasterror. +*/ +AD5940Err AD5940_SEQGenFetchSeq(const uint32_t **ppSeqCmd, uint32_t *pSeqLen) +{ + AD5940Err lasterror; + + if(ppSeqCmd) + *ppSeqCmd = SeqGenDB.pSeqBuff; + if(pSeqLen) + *pSeqLen = SeqGenDB.SeqLen; + + //SeqGenDB.SeqLen = 0; /* Start a new sequence */ + lasterror = SeqGenDB.LastError; + //SeqGenDB.LastError = AD5940ERR_OK; /* Clear error message */ + return lasterror; +} + +/** + * @brief Start or stop the sequencer generator. Once started, the register write will be recorded to sequencer generator. + * Once it's disabled, the register write is written to AD5940 directly by SPI bus. + * @param bFlag: Enable or disable sequencer generator. + * @return Return None. +*/ +void AD5940_SEQGenCtrl(BoolFlag bFlag) +{ + if(bFlag == bFALSE) /* Disable sequence generator */ + { + SeqGenDB.EngineStart = bFALSE; + } + else + { + SeqGenDB.SeqLen = 0; + SeqGenDB.LastError = AD5940ERR_OK; /* Clear error message */ + SeqGenDB.EngineStart = bTRUE; + } +} + +/** + * @brief Calculate the number of cycles in the sequence + * @return Return Number of ACLK Cycles that a generated sequence will take. +*/ +uint32_t AD5940_SEQCycleTime(void) +{ + uint32_t i, Cycles, Cmd; + Cycles = 0; + for(i=0;i> 30) & 0x3; + if (Cmd & 0x2) + { + /* A write command */ + Cycles += 1; + } + else + { + if (Cmd & 0x1) + { + /* Timeout Command */ + Cycles += 1; + } + else + { + /* Wait command */ + Cycles += SeqGenDB.pSeqBuff[i] & 0x3FFFFFFF; + } + } + } + return Cycles; +} +#endif +/** + * @} Sequencer_Generator_Functions +*/ + +/** + * Check if an uint8_t value exist in table. +*/ +static int32_t _is_value_in_table(uint8_t value, const uint8_t *table, uint8_t len, uint8_t *index) +{ + for(int i=0; iADCRate == ADCRATE_800KHZ && pFilterInfo->ADCSinc3Osr == ADCSINC3OSR_2)||\ + (pFilterInfo->ADCRate == ADCRATE_1P6MHZ && pFilterInfo->ADCSinc3Osr != ADCSINC3OSR_2)) + { + //this combination suits for filter: + //SINC3 OSR2, for 800kSPS + //and SINC3 OSR4 and OSR5 for 1.6MSPS, + const uint8_t available_sinc2_osr[] = {ADCSINC2OSR_533, ADCSINC2OSR_667,ADCSINC2OSR_800, ADCSINC2OSR_889, ADCSINC2OSR_1333}; + const uint8_t dl_50Hz[] = {15,12,10,9,6}; + uint8_t index; + if(_is_value_in_table(pFilterInfo->ADCSinc2Osr, available_sinc2_osr, sizeof(available_sinc2_osr), &index)) + { + *dl = dl_50Hz[index]; + return bTRUE; + } + } + else if(pFilterInfo->ADCRate == ADCRATE_1P6MHZ && pFilterInfo->ADCSinc3Osr == ADCSINC3OSR_2) + { + //this combination suits for filter: + //SINC3 OSR2 for 1.6MSPS + const uint8_t available_sinc2_osr[] = {ADCSINC2OSR_889, ADCSINC2OSR_1067, ADCSINC2OSR_1333}; + const uint8_t dl_50Hz[] = {18,15,12}; + uint8_t index; + if(_is_value_in_table(pFilterInfo->ADCSinc2Osr, available_sinc2_osr, sizeof(available_sinc2_osr), &index)) + { + *dl = dl_50Hz[index]; + return bTRUE; + } + } + else if(pFilterInfo->ADCRate == ADCRATE_800KHZ && pFilterInfo->ADCSinc3Osr != ADCSINC3OSR_2) + { + //this combination suits for filter: + //SINC3 OSR4 and OSR5 for 800kSPS, + const uint8_t available_sinc2_osr[] = {ADCSINC2OSR_178, ADCSINC2OSR_267, ADCSINC2OSR_533, ADCSINC2OSR_640,\ + ADCSINC2OSR_800, ADCSINC2OSR_1067}; + const uint8_t dl_50Hz[] = {18,12,6,5,4,3}; + uint8_t index; + if(_is_value_in_table(pFilterInfo->ADCSinc2Osr, available_sinc2_osr, sizeof(available_sinc2_osr), &index)) + { + *dl = dl_50Hz[index]; + return bTRUE; + } + } + *dl = 0; + return bFALSE; +} + +/** + * @brief return if the SINC3/SINC2 combination is available for notch 60Hz filter. + * If it's not availabe, hardware automatically bypass Notch even if it's enabled. + * @param pFilterInfo the filter configuration, need sinc2/sinc3 osr and adc data rate information. + * @return return bTRUE if notch 60Hz filter is available. +*/ +BoolFlag AD5940_Notch60HzAvailable(ADCFilterCfg_Type *pFilterInfo, uint8_t *dl) +{ + if((pFilterInfo->ADCRate == ADCRATE_800KHZ && pFilterInfo->ADCSinc3Osr == ADCSINC3OSR_2)||\ + (pFilterInfo->ADCRate == ADCRATE_1P6MHZ && pFilterInfo->ADCSinc3Osr != ADCSINC3OSR_2)) + { + //this combination suits for filter: + //SINC3 OSR2, for 800kSPS + //and SINC3 OSR4 and OSR5 for 1.6MSPS, + const uint8_t available_sinc2_osr[] = {ADCSINC2OSR_667, ADCSINC2OSR_1333}; + const uint8_t dl_60Hz[] = {10,5}; + uint8_t index; + if(_is_value_in_table(pFilterInfo->ADCSinc2Osr, available_sinc2_osr, sizeof(available_sinc2_osr), &index)) + { + *dl = dl_60Hz[index]; + return bTRUE; + } + } + else if(pFilterInfo->ADCRate == ADCRATE_1P6MHZ && pFilterInfo->ADCSinc3Osr == ADCSINC3OSR_2) + { + //this combination suits for filter: + //SINC3 OSR2 for 1.6MSPS + const uint8_t available_sinc2_osr[] = {ADCSINC2OSR_889, ADCSINC2OSR_1333}; + const uint8_t dl_60Hz[] = {15,10}; + uint8_t index; + if(_is_value_in_table(pFilterInfo->ADCSinc2Osr, available_sinc2_osr, sizeof(available_sinc2_osr), &index)) + { + *dl = dl_60Hz[index]; + return bTRUE; + } + } + else if(pFilterInfo->ADCRate == ADCRATE_800KHZ && pFilterInfo->ADCSinc3Osr != ADCSINC3OSR_2) + { + //this combination suits for filter: + //SINC3 OSR4 and OSR5 for 800kSPS, + const uint8_t available_sinc2_osr[] = {ADCSINC2OSR_178, ADCSINC2OSR_267, ADCSINC2OSR_533, ADCSINC2OSR_667,\ + ADCSINC2OSR_889, ADCSINC2OSR_1333}; + const uint8_t dl_60Hz[] = {15,10,5,4,3,2}; + uint8_t index; + if(_is_value_in_table(pFilterInfo->ADCSinc2Osr, available_sinc2_osr, sizeof(available_sinc2_osr), &index)) + { + *dl = dl_60Hz[index]; + return bTRUE; + } + } + *dl = 0; + return bFALSE; +} + +/** + * @brief Calculate how many clocks are needed in sequencer wait command to generate required number of data from filter output. + * @note When measurement is done, it's recommend to disable blocks like ADCPWR, ADCCNV, SINC2, DFT etc. If blocks remain powered up, + * they may need less clocks to generate required number of output. Use function @ref AD5940_AFECtrlS to control these blocks. + * @param pFilterInfo: Pointer to configuration structure. + * @param pClocks: pointer used to store results. + * @return return none. +*/ +void AD5940_ClksCalculate(ClksCalInfo_Type *pFilterInfo, uint32_t *pClocks) +{ + uint32_t temp = 0; + const uint32_t sinc2osr_table[] = {22,44,89,178,267,533,640,667,800,889,1067,1333,0}; + const uint32_t sinc3osr_table[] = {5,4,2,0}; + + *pClocks = 0; + if(pFilterInfo == NULL) return; + if(pClocks == NULL) return; + if(pFilterInfo->ADCSinc2Osr > ADCSINC2OSR_1333) return; + if(pFilterInfo->ADCSinc3Osr > 2) return; /* 0: OSR5, 1:OSR4, 2:OSR2 */ + if(pFilterInfo->ADCAvgNum > ADCAVGNUM_16) return; /* Average number index:0,1,2,3 */ + switch(pFilterInfo->DataType) + { + case DATATYPE_ADCRAW: + temp = (uint32_t)(20*pFilterInfo->DataCount*pFilterInfo->RatioSys2AdcClk); + break; + case DATATYPE_SINC3: + temp = (uint32_t)(((pFilterInfo->DataCount+2)*sinc3osr_table[pFilterInfo->ADCSinc3Osr]+1)*20*pFilterInfo->RatioSys2AdcClk + 0.5f); + break; + case DATATYPE_SINC2: + temp = (pFilterInfo->DataCount+1)*sinc2osr_table[pFilterInfo->ADCSinc2Osr] + 1; + pFilterInfo->DataType = DATATYPE_SINC3; + pFilterInfo->DataCount = temp; + AD5940_ClksCalculate(pFilterInfo, &temp); + pFilterInfo->DataType = DATATYPE_SINC2; + temp += 15; /* Need extra 15 clocks for FIFO etc. Just to be safe. */ + break; + case DATATYPE_NOTCH: + { + ADCFilterCfg_Type filter; + filter.ADCRate = pFilterInfo->ADCRate; + filter.ADCSinc3Osr = pFilterInfo->ADCSinc3Osr; + filter.ADCSinc2Osr = pFilterInfo->ADCSinc2Osr; + uint8_t dl=0, dl_50, dl_60; + if(AD5940_Notch50HzAvailable(&filter, &dl_50)){ + dl += dl_50 - 1; + } + if(AD5940_Notch60HzAvailable(&filter, &dl_60)){ + dl += dl_60 - 1; + } + pFilterInfo->DataType = DATATYPE_SINC2; + pFilterInfo->DataCount += dl; //DL is the extra data input needed for filter to output first data. + AD5940_ClksCalculate(pFilterInfo,&temp); + //restore the filter info. + pFilterInfo->DataType = DATATYPE_NOTCH; + pFilterInfo->DataCount -= dl; + break; + } + case DATATYPE_DFT: + switch(pFilterInfo->DftSrc) + { + case DFTSRC_ADCRAW: + pFilterInfo->DataType = DATATYPE_ADCRAW; + AD5940_ClksCalculate(pFilterInfo, &temp); + break; + case DFTSRC_SINC3: + pFilterInfo->DataType = DATATYPE_SINC3; + AD5940_ClksCalculate(pFilterInfo, &temp); + break; + case DFTSRC_SINC2NOTCH: + if(pFilterInfo->BpNotch) + pFilterInfo->DataType = DATATYPE_SINC2; + else + pFilterInfo->DataType = DATATYPE_NOTCH; + AD5940_ClksCalculate(pFilterInfo, &temp); + break; + case DFTSRC_AVG: + pFilterInfo->DataType = DATATYPE_SINC3; + pFilterInfo->DataCount *= 1L<<(pFilterInfo->ADCAvgNum+1); /* 0: average2, 1: average4, 2: average8, 3: average16 */ + AD5940_ClksCalculate(pFilterInfo, &temp); + break; + default: + break; + } + pFilterInfo->DataType = DATATYPE_DFT; + temp += 25; /* add margin */ + break; + default: + break; + } + *pClocks = temp; +} + +/** + @brief void AD5940_SweepNext(SoftSweepCfg_Type *pSweepCfg, float *pNextFreq) + For sweep function, calculate next frequency point according to pSweepCfg info. + @return Return next frequency point in Hz. +*/ +void AD5940_SweepNext(SoftSweepCfg_Type *pSweepCfg, float *pNextFreq) +{ + float frequency; + + if(pSweepCfg->SweepLog)/* Log step */ + { + if(pSweepCfg->SweepStartSweepStop) /* Normal */ + { + if(++pSweepCfg->SweepIndex == pSweepCfg->SweepPoints) + pSweepCfg->SweepIndex = 0; + frequency = pSweepCfg->SweepStart*pow(10,pSweepCfg->SweepIndex*log10(pSweepCfg->SweepStop/pSweepCfg->SweepStart)/(pSweepCfg->SweepPoints-1)); + } + else + { + pSweepCfg->SweepIndex --; + if(pSweepCfg->SweepIndex >= pSweepCfg->SweepPoints) + pSweepCfg->SweepIndex = pSweepCfg->SweepPoints-1; + frequency = pSweepCfg->SweepStop*pow(10,pSweepCfg->SweepIndex* + (log10(pSweepCfg->SweepStart/pSweepCfg->SweepStop)/(pSweepCfg->SweepPoints-1))); + } + } + else/* Linear step */ + { + if(pSweepCfg->SweepStartSweepStop) /* Normal */ + { + if(++pSweepCfg->SweepIndex == pSweepCfg->SweepPoints) + pSweepCfg->SweepIndex = 0; + frequency = pSweepCfg->SweepStart + pSweepCfg->SweepIndex*(double)(pSweepCfg->SweepStop-pSweepCfg->SweepStart)/(pSweepCfg->SweepPoints-1); + } + else + { + pSweepCfg->SweepIndex --; + if(pSweepCfg->SweepIndex >= pSweepCfg->SweepPoints) + pSweepCfg->SweepIndex = pSweepCfg->SweepPoints-1; + frequency = pSweepCfg->SweepStop + pSweepCfg->SweepIndex*(double)(pSweepCfg->SweepStart - pSweepCfg->SweepStop)/(pSweepCfg->SweepPoints-1); + } + } + + *pNextFreq = frequency; +} + +/** + @brief Initialize Structure members to zero + @param pStruct: Pointer to the structure. + @param StructSize: The structure size in Byte. + @return Return None. +**/ +void AD5940_StructInit(void *pStruct, uint32_t StructSize) +{ + memset(pStruct, 0, StructSize); +} + +/** + @brief Convert ADC Code to voltage. + @param ADCPga: The ADC PGA used for this result. + @param code: ADC code. + @param VRef1p82: the actual 1.82V reference voltage. + @return Voltage in volt. +**/ +float AD5940_ADCCode2Volt(uint32_t code, uint32_t ADCPga, float VRef1p82) +{ + float kFactor = 1.835/1.82; + float fVolt = 0.0; + float tmp = 0; + tmp = (int32_t)code - 32768; + switch(ADCPga) + { + case ADCPGA_1: + break; + case ADCPGA_1P5: + tmp /= 1.5f; + break; + case ADCPGA_2: + tmp /= 2.0f; + break; + case ADCPGA_4: + tmp /= 4.0f; + break; + case ADCPGA_9: + tmp /= 9.0f; + break; + default:break; + } + fVolt = tmp*VRef1p82/32768*kFactor; + return fVolt; +} + +/** + * @brief Do complex number division. + * @param a: The dividend. + * @param b: The divisor. + * @return Return result. +**/ +fImpCar_Type AD5940_ComplexDivFloat(fImpCar_Type *a, fImpCar_Type *b) +{ + fImpCar_Type res; + float temp; + temp = b->Real*b->Real + b->Image*b->Image; + res.Real = a->Real*b->Real + a->Image*b->Image; + res.Real /= temp; + res.Image = a->Image*b->Real - a->Real*b->Image; + res.Image /= temp; + return res; +} + +/** + * @brief Do complex number multiplication. + * @param a: The multiplicand. + * @param b: The multiplier . + * @return Return result. +**/ +fImpCar_Type AD5940_ComplexMulFloat(fImpCar_Type *a, fImpCar_Type *b) +{ + fImpCar_Type res; + + res.Real = a->Real*b->Real - a->Image*b->Image; + res.Image = a->Image*b->Real + a->Real*b->Image; + + return res; +} +/** + * @brief Do complex number addition. + * @param a: The addend. + * @param b: The addend . + * @return Return result. +**/ +fImpCar_Type AD5940_ComplexAddFloat(fImpCar_Type *a, fImpCar_Type *b) +{ + fImpCar_Type res; + + res.Real = a->Real + b->Real; + res.Image = a->Image + b->Image; + + return res; +} + +/** + * @brief Do complex number subtraction. + * @param a: The minuend. + * @param b: The subtrahend . + * @return Return result. +**/ +fImpCar_Type AD5940_ComplexSubFloat(fImpCar_Type *a, fImpCar_Type *b) +{ + fImpCar_Type res; + + res.Real = a->Real - b->Real; + res.Image = a->Image - b->Image; + + return res; +} + +/** + * @brief Do complex number division. + * @param a: The dividend. + * @param b: The divisor. + * @return Return result. +**/ +fImpCar_Type AD5940_ComplexDivInt(iImpCar_Type *a, iImpCar_Type *b) +{ + fImpCar_Type res; + float temp; + temp = (float)b->Real*b->Real + (float)b->Image*b->Image; + res.Real = (float)a->Real*b->Real + (float)a->Image*b->Image; + res.Real /= temp; + res.Image = (float)a->Image*b->Real - (float)a->Real*b->Image; + res.Image /= temp; + return res; +} + +/** + * @brief Do complex number multiplication. + * @param a: The multiplicand. + * @param b: The multiplier . + * @return Return result. +**/ +fImpCar_Type AD5940_ComplexMulInt(iImpCar_Type *a, iImpCar_Type *b) +{ + fImpCar_Type res; + + res.Real = (float)a->Real*b->Real - (float)a->Image*b->Image; + res.Image = (float)a->Image*b->Real + (float)a->Real*b->Image; + + return res; +} + +/** + * @brief Calculate the complex number magnitude. + * @param a: The complex number. + * @return Return magnitude. +**/ +float AD5940_ComplexMag(fImpCar_Type *a) +{ + return sqrt(a->Real*a->Real + a->Image*a->Image); +} + +/** + * @brief Calculate the complex number phase. + * @param a: The complex number. + * @return Return phase. +**/ +float AD5940_ComplexPhase(fImpCar_Type *a) +{ + return atan2(a->Image, a->Real); +} + +/** + * @brief Calculate the optimum filter settings based on signal frequency. + * @param freq: Frequency of signalr. + * @return Return FreqParams. +**/ +FreqParams_Type AD5940_GetFreqParameters(float freq) +{ + const uint32_t dft_table[] = {4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384}; + const uint32_t sinc2osr_table[] = {1, 22,44,89,178,267,533,640,667,800,889,1067,1333}; + const uint32_t sinc3osr_table[] = {2, 4, 5}; + float AdcRate = 800000; + uint32_t n1 = 0; // Sample rate after ADC filters + uint32_t n2 = 0; // Sample rate after DFT block + uint32_t iCycle = 0; + FreqParams_Type freq_params; + /* High power mode */ + if(freq >= 20000) + { + freq_params. DftSrc = DFTSRC_SINC3; + freq_params.ADCSinc2Osr = 0; + freq_params.ADCSinc3Osr = 2; + freq_params.DftNum = DFTNUM_8192; + freq_params.NumClks = 0; + freq_params.HighPwrMode = bTRUE; + return freq_params; + } + + if(freq < 0.51) + { + freq_params. DftSrc = DFTSRC_SINC2NOTCH; + freq_params.ADCSinc2Osr = 6; + freq_params.ADCSinc3Osr = 1; + freq_params.DftNum = DFTNUM_8192; + freq_params.NumClks = 0; + freq_params.HighPwrMode = bTRUE; + return freq_params; + } + + /* Start with SINC2 setting */ + for(uint8_t i = 0; i=0x1000)&&(RegAddr<=0x3014))) /* 32bit register */ + *(volatile uint32_t *)(RegAddr+0x400c0000) = RegData; + else /* 16bit register */ + *(volatile uint16_t *)(RegAddr+0x400c0000) = RegData; +} + +static uint32_t AD5940_D2DReadReg(uint16_t RegAddr) +{ + if(((RegAddr>=0x1000)&&(RegAddr<=0x3014))) /* 32bit register */ + return *(volatile uint32_t *)(RegAddr+0x400c0000); + else /* 16bit register */ + return *(volatile uint16_t *)(RegAddr+0x400c0000); +} + +void AD5940_FIFORd(uint32_t *pBuffer, uint32_t uiReadCount) +{ + while(uiReadCount--) + *pBuffer++ = *(volatile uint32_t *)(0x400c206C); +} +#else +/** + * @defgroup SPI_Block + * @brief Functions to communicate with AD5940 registers following AD5940 SPI protocols + * @{ + * + * @defgroup SPI_Block_Functions + * @brief The basic SPI protocols. All functions are basic on AD5940_ReadWriteNBytes which + * provided by user. + * + * ##SPI basic protocol + * All SPI protocol starts with one-byte command word. Following are data(16B or 32B) + * There are four SPI commands available @ref SPI_Block_Const. + * @{ +*/ + +/** + @brief Using SPI to transmit one byte and return the received byte. + @param data: The 8-bit data SPI will transmit. + @return received data. +**/ +static unsigned char AD5940_ReadWrite8B(unsigned char data) +{ + uint8_t tx[1], rx[1]; + tx[0] = data; + AD5940_ReadWriteNBytes(tx,rx,1); + return rx[0]; +} + +/** + @brief Using SPI to transmit two bytes and return the received bytes. + @param data: The 16-bit data SPI will transmit. + @return received data. +**/ +static uint16_t AD5940_ReadWrite16B(uint16_t data) +{ + uint8_t SendBuffer[2]; + uint8_t RecvBuffer[2]; + SendBuffer[0] = data>>8; + SendBuffer[1] = data&0xff; + AD5940_ReadWriteNBytes(SendBuffer,RecvBuffer,2); + return (((uint16_t)RecvBuffer[0])<<8)|RecvBuffer[1]; +} + +/** + * @brief Using SPI to transmit four bytes and return the received bytes. + * @param data: The 32-bit data SPI will transmit. + * @return received data. +**/ +static uint32_t AD5940_ReadWrite32B(uint32_t data) +{ + uint8_t SendBuffer[4]; + uint8_t RecvBuffer[4]; + + SendBuffer[0] = (data>>24)&0xff; + SendBuffer[1] = (data>>16)&0xff; + SendBuffer[2] = (data>> 8)&0xff; + SendBuffer[3] = (data )&0xff; + AD5940_ReadWriteNBytes(SendBuffer,RecvBuffer,4); + return (((uint32_t)RecvBuffer[0])<<24)|(((uint32_t)RecvBuffer[1])<<16)|(((uint32_t)RecvBuffer[2])<<8)|RecvBuffer[3]; +} + +/** + * @brief Write register through SPI. + * @param RegAddr: The register address. + * @param RegData: The register data. + * @return Return None. +**/ +static void AD5940_SPIWriteReg(uint16_t RegAddr, uint32_t RegData) +{ + /* Set register address */ + AD5940_CsClr(); + AD5940_ReadWrite8B(SPICMD_SETADDR); + AD5940_ReadWrite16B(RegAddr); + AD5940_CsSet(); + /* Add delay here to meet the SPI timing. */ + AD5940_CsClr(); + AD5940_ReadWrite8B(SPICMD_WRITEREG); + if(((RegAddr>=0x1000)&&(RegAddr<=0x3014))) + AD5940_ReadWrite32B(RegData); + else + AD5940_ReadWrite16B(RegData); + AD5940_CsSet(); +} + +/** + * @brief Read register through SPI. + * @param RegAddr: The register address. + * @return Return register data. +**/ +static uint32_t AD5940_SPIReadReg(uint16_t RegAddr) +{ + uint32_t Data = 0; + /* Set register address that we want to read */ + AD5940_CsClr(); + AD5940_ReadWrite8B(SPICMD_SETADDR); + AD5940_ReadWrite16B(RegAddr); + AD5940_CsSet(); + /* Read it */ + AD5940_CsClr(); + AD5940_ReadWrite8B(SPICMD_READREG); + AD5940_ReadWrite8B(0); //Dummy read + /* The real data is coming */ + if((RegAddr>=0x1000)&&(RegAddr<=0x3014)) + Data = AD5940_ReadWrite32B(0); + else + Data = AD5940_ReadWrite16B(0); + AD5940_CsSet(); + return Data; +} + +/** + @brief Read specific number of data from FIFO with optimized SPI access. + @param pBuffer: Pointer to a buffer that used to store data read back. + @param uiReadCount: How much data to be read. + @return none. +**/ +void AD5940_FIFORd(uint32_t *pBuffer, uint32_t uiReadCount) +{ + /* Use function AD5940_SPIReadReg to read REG_AFE_DATAFIFORD is also one method. */ + uint32_t i; + + if(uiReadCount < 3) + { + /* This method is more efficient when readcount < 3 */ + uint32_t i; + AD5940_CsClr(); + AD5940_ReadWrite8B(SPICMD_SETADDR); + AD5940_ReadWrite16B(REG_AFE_DATAFIFORD); + AD5940_CsSet(); + for(i=0;iHpBandgapEn == bFALSE) + tempreg |= BITM_AFE_AFECON_HPREFDIS; + AD5940_WriteReg(REG_AFE_AFECON, tempreg); + /* Reference buffer configure */ + tempreg = AD5940_ReadReg(REG_AFE_BUFSENCON); + if(pBufCfg->Hp1V8BuffEn == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P8HPADCEN; + if(pBufCfg->Hp1V1BuffEn == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P1HPADCEN; + if(pBufCfg->Lp1V8BuffEn == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P8LPADCEN; + if(pBufCfg->Lp1V1BuffEn == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P1LPADCEN; + if(pBufCfg->Hp1V8ThemBuff == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P8THERMSTEN; + if(pBufCfg->Hp1V8Ilimit == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P8HPADCILIMITEN; + if(pBufCfg->Disc1V8Cap == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P8HPADCCHGDIS; + if(pBufCfg->Disc1V1Cap == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P1LPADCCHGDIS; + AD5940_WriteReg(REG_AFE_BUFSENCON, tempreg); + + /* LPREFBUFCON */ + tempreg = 0; + if(pBufCfg->LpRefBufEn == bFALSE) + tempreg |= BITM_AFE_LPREFBUFCON_LPBUF2P5DIS; + if(pBufCfg->LpBandgapEn == bFALSE) + tempreg |= BITM_AFE_LPREFBUFCON_LPREFDIS; + if(pBufCfg->LpRefBoostEn == bTRUE) + tempreg |= BITM_AFE_LPREFBUFCON_BOOSTCURRENT; + AD5940_WriteReg(REG_AFE_LPREFBUFCON, tempreg); +} +/** + * @} End of AFE_Control_Functions + * @} End of AFE_Control + * */ + +/** + * @defgroup High_Speed_Loop + * @brief The high speed loop + * @{ + * @defgroup High_Speed_Loop_Functions + * @{ +*/ + +/** + @brief Configure High speed loop(high bandwidth loop or + called excitation loop). This configuration includes HSDAC, HSTIA and Switch matrix. + @param pHsLoopCfg : Pointer to configure structure; + @return return none. +*/ +void AD5940_HSLoopCfgS(HSLoopCfg_Type *pHsLoopCfg) +{ + AD5940_HSDacCfgS(&pHsLoopCfg->HsDacCfg); + AD5940_HSTIACfgS(&pHsLoopCfg->HsTiaCfg); + AD5940_SWMatrixCfgS(&pHsLoopCfg->SWMatCfg); + AD5940_WGCfgS(&pHsLoopCfg->WgCfg); +} + +/** + @brief Initialize switch matrix + @param pSwMatrix: Pointer to configuration structure + @return return none. +*/ +void AD5940_SWMatrixCfgS(SWMatrixCfg_Type *pSwMatrix) +{ + AD5940_WriteReg(REG_AFE_DSWFULLCON, pSwMatrix->Dswitch); + AD5940_WriteReg(REG_AFE_PSWFULLCON, pSwMatrix->Pswitch); + AD5940_WriteReg(REG_AFE_NSWFULLCON, pSwMatrix->Nswitch); + AD5940_WriteReg(REG_AFE_TSWFULLCON, pSwMatrix->Tswitch); + AD5940_WriteReg(REG_AFE_SWCON, BITM_AFE_SWCON_SWSOURCESEL); /* Update switch configuration */ +} + +/** + @brief Initialize HSDAC + @param pHsDacCfg: Pointer to configuration structure + @return return none. +*/ +void AD5940_HSDacCfgS(HSDACCfg_Type *pHsDacCfg) +{ + uint32_t tempreg; + //Check parameters + tempreg = 0; + if(pHsDacCfg->ExcitBufGain == EXCITBUFGAIN_0P25) + tempreg |= BITM_AFE_HSDACCON_INAMPGNMDE; /* Enable attenuator */ + if(pHsDacCfg->HsDacGain == HSDACGAIN_0P2) + tempreg |= BITM_AFE_HSDACCON_ATTENEN; /* Enable attenuator */ + tempreg |= (pHsDacCfg->HsDacUpdateRate&0xff)<= HSTIADERTIA_OPEN) + tempreg = 0x1f << 3; /* bit field HPTIRES03CON[7:3] */ + else if(DeRtia >= HSTIADERTIA_1K) + { + tempreg = (DeRtia - 3 + 11) << 3; + } + else /* DERTIA 50/100/200Ohm */ + { + const uint8_t DeRtiaTable[3][5] = + { +//Rload 0 10 30 50 100 + {0x00, 0x01, 0x02, 0x03, 0x06}, /* RTIA 50Ohm */ + {0x03, 0x04, 0x05, 0x06, 0x07}, /* RTIA 100Ohm */ + {0x07, 0x07, 0x09, 0x09, 0x0a}, /* RTIA 200Ohm */ + }; + if(DeRload < HSTIADERLOAD_OPEN) + tempreg = (uint32_t)(DeRtiaTable[DeRtia][DeRload])<<3; + else + tempreg = (0x1f)<<3; /* Set it to HSTIADERTIA_OPEN. This setting is illegal */ + } + /* deal with HSTIA Rload */ + tempreg |= DeRload; + if(DExPin) //DE1 + AD5940_WriteReg(REG_AFE_DE1RESCON, tempreg); + else //DE0 + AD5940_WriteReg(REG_AFE_DE0RESCON, tempreg); +} + +/** + @brief Initialize High speed TIA amplifier + @param pHsTiaCfg: Pointer to configuration structure + @return return none. +*/ +AD5940Err AD5940_HSTIACfgS(HSTIACfg_Type *pHsTiaCfg) +{ + uint32_t tempreg; + //Check parameters + if(pHsTiaCfg == NULL) return AD5940ERR_NULLP; + /* Available parameter is 1k, 5k,...,160k, short, OPEN */ + if(pHsTiaCfg->HstiaDeRtia < HSTIADERTIA_1K) + return AD5940ERR_PARA; + if(pHsTiaCfg->HstiaDeRtia > HSTIADERTIA_OPEN) + return AD5940ERR_PARA; /* Parameter is invalid */ + + if(pHsTiaCfg->HstiaDeRload > HSTIADERLOAD_OPEN) + return AD5940ERR_PARA; /* Available parameter is OPEN, 0R,..., 100R */ + + tempreg = 0; + tempreg |= pHsTiaCfg->HstiaBias; + AD5940_WriteReg(REG_AFE_HSTIACON, tempreg); + /* HSRTIACON */ + /* Calculate CTIA value */ + tempreg = pHsTiaCfg->HstiaCtia << BITP_AFE_HSRTIACON_CTIACON; + tempreg |= pHsTiaCfg->HstiaRtiaSel; + if(pHsTiaCfg->DiodeClose == bTRUE) + tempreg |= BITM_AFE_HSRTIACON_TIASW6CON; /* Close switch 6 */ + AD5940_WriteReg(REG_AFE_HSRTIACON, tempreg); + /* DExRESCON */ + __AD5940_SetDExRTIA(0, pHsTiaCfg->HstiaDeRtia, pHsTiaCfg->HstiaDeRload); +#ifdef CHIPSEL_M355 + __AD5940_SetDExRTIA(1, pHsTiaCfg->HstiaDe1Rtia, pHsTiaCfg->HstiaDe1Rload); +#endif + + /* Done */ + return AD5940ERR_OK; +} +/** + * @brief Configure HSTIA RTIA resistor and keep other parameters unchanged. + * @param HSTIARtia: The RTIA setting, select it from @ref HSTIARTIA_Const + * @return return none. +*/ +void AD5940_HSRTIACfgS(uint32_t HSTIARtia) +{ + uint32_t tempreg; + tempreg = AD5940_ReadReg(REG_AFE_HSRTIACON); + tempreg &= ~BITM_AFE_HSRTIACON_RTIACON; + HSTIARtia &= BITM_AFE_HSRTIACON_RTIACON; + tempreg |= HSTIARtia<WgType == WGTYPE_SIN) + { + /* Configure Sine wave Generator */ + AD5940_WriteReg(REG_AFE_WGFCW, pWGInit->SinCfg.SinFreqWord); + AD5940_WriteReg(REG_AFE_WGAMPLITUDE, pWGInit->SinCfg.SinAmplitudeWord); + AD5940_WriteReg(REG_AFE_WGOFFSET, pWGInit->SinCfg.SinOffsetWord); + AD5940_WriteReg(REG_AFE_WGPHASE, pWGInit->SinCfg.SinPhaseWord); + } + else if(pWGInit->WgType == WGTYPE_TRAPZ) + { + /* Configure Trapezoid Generator */ + AD5940_WriteReg(REG_AFE_WGDCLEVEL1, pWGInit->TrapzCfg.WGTrapzDCLevel1); + AD5940_WriteReg(REG_AFE_WGDCLEVEL2, pWGInit->TrapzCfg.WGTrapzDCLevel2); + AD5940_WriteReg(REG_AFE_WGDELAY1, pWGInit->TrapzCfg.WGTrapzDelay1); + AD5940_WriteReg(REG_AFE_WGDELAY2, pWGInit->TrapzCfg.WGTrapzDelay2); + AD5940_WriteReg(REG_AFE_WGSLOPE1, pWGInit->TrapzCfg.WGTrapzSlope1); + AD5940_WriteReg(REG_AFE_WGSLOPE2, pWGInit->TrapzCfg.WGTrapzSlope2); + } + else + { + /* Write DAC data. It's only have effect when WgType set to WGTYPE_MMR */ + AD5940_WriteReg(REG_AFE_HSDACDAT, pWGInit->WgCode); + } + tempreg = 0; + + if(pWGInit->GainCalEn == bTRUE) + tempreg |= BITM_AFE_WGCON_DACGAINCAL; + if(pWGInit->OffsetCalEn == bTRUE) + tempreg |= BITM_AFE_WGCON_DACOFFSETCAL; + tempreg |= (pWGInit->WgType) << BITP_AFE_WGCON_TYPESEL; + AD5940_WriteReg(REG_AFE_WGCON, tempreg); +} + +/** + * @brief Write HSDAC code directly when WG configured to MMR type + * @param code: The 12-bit HSDAC code. + * @return return none. +*/ +AD5940Err AD5940_WGDACCodeS(uint32_t code) +{ + code &= 0xfff; + AD5940_WriteReg(REG_AFE_HSDACDAT, code); + return AD5940ERR_OK; +} + +/** + * @brief Update WG SIN wave frequency in Hz. + * @param SinFreqHz: The desired frequency in Hz. + * @param WGClock: The clock for WG. It's same as system clock and the default value is internal 16MHz HSOSC. + * @return return none. +*/ +void AD5940_WGFreqCtrlS(float SinFreqHz, float WGClock) +{ + uint32_t freq_word; + freq_word = AD5940_WGFreqWordCal(SinFreqHz, WGClock); + AD5940_WriteReg(REG_AFE_WGFCW, freq_word); +} + +/** + @brief Calculate sine wave generator frequency word. The maxim frequency is 250kHz-1LSB + @param SinFreqHz : Target frequency in Hz unit. + @param WGClock: Waveform generator clock frequency in Hz unit. The clock is sourced from system clock, default value is 16MHz HFOSC. + @return return none. +*/ +uint32_t AD5940_WGFreqWordCal(float SinFreqHz, float WGClock) +{ + uint32_t temp; + uint32_t __BITWIDTH_WGFCW = 26; + if(bIsS2silicon == bTRUE) + __BITWIDTH_WGFCW = 30; + if(WGClock == 0) return 0; + temp = (uint32_t)(SinFreqHz*(1LL<<__BITWIDTH_WGFCW)/WGClock + 0.5f); + if(temp > ((__BITWIDTH_WGFCW == 26)?0xfffff:0xffffff)) + temp = (__BITWIDTH_WGFCW == 26)?0xfffff:0xffffff; + + return temp; +} + +/** + * @} Waveform_Generator_Functions + * @} High_Speed_Loop_Functions + * @} High_Speed_Loop +*/ + + +/** + * @defgroup Low_Power_Loop + * @brief The low power loop. + * @{ + * @defgroup Low_Power_Loop_Functions + * @{ +*/ + +/** + @brief Configure low power loop include LPDAC LPAmp(PA and TIA) + @param pLpLoopCfg: Pointer to configure structure; + @return return none. +*/ +void AD5940_LPLoopCfgS(LPLoopCfg_Type *pLpLoopCfg) +{ + AD5940_LPDACCfgS(&pLpLoopCfg->LpDacCfg); + AD5940_LPAMPCfgS(&pLpLoopCfg->LpAmpCfg); +} + +/** + @brief Initialize LPDAC + @param pLpDacCfg: Pointer to configuration structure + @return return none. +*/ +void AD5940_LPDACCfgS(LPDACCfg_Type *pLpDacCfg) +{ + uint32_t tempreg; + tempreg = 0; + tempreg = (pLpDacCfg->LpDacSrc)<LpDacVzeroMux)<LpDacVbiasMux)<LpDacRef)<DataRst == bFALSE) + tempreg |= BITM_AFE_LPDACCON0_RSTEN; + if(pLpDacCfg->PowerEn == bFALSE) + tempreg |= BITM_AFE_LPDACCON0_PWDEN; + if(pLpDacCfg->LpdacSel == LPDAC0) + { + AD5940_WriteReg(REG_AFE_LPDACCON0, tempreg); + AD5940_LPDAC0WriteS(pLpDacCfg->DacData12Bit, pLpDacCfg->DacData6Bit); + AD5940_WriteReg(REG_AFE_LPDACSW0, pLpDacCfg->LpDacSW|BITM_AFE_LPDACSW0_LPMODEDIS); /* Overwrite LPDACSW settings. On Si1, this register is not accessible. */ + } + else + { + AD5940_WriteReg(REG_AFE_LPDACCON1, tempreg); + AD5940_LPDAC1WriteS(pLpDacCfg->DacData12Bit, pLpDacCfg->DacData6Bit); + AD5940_WriteReg(REG_AFE_LPDACSW1, pLpDacCfg->LpDacSW|BITM_AFE_LPDACSW0_LPMODEDIS); /* Overwrite LPDACSW settings. On Si1, this register is not accessible. */ + } +} + +/** + @brief Write LPDAC data + @param Data12Bit: 12Bit DAC data + @param Data6Bit: 6Bit DAC data + @return return none. +*/ +void AD5940_LPDACWriteS(uint16_t Data12Bit, uint8_t Data6Bit) +{ + /* Check parameter */ + Data6Bit &= 0x3f; + Data12Bit &= 0xfff; + AD5940_WriteReg(REG_AFE_LPDACDAT0, ((uint32_t)Data6Bit<<12)|Data12Bit); +} + +/** + @brief Write LPDAC0 data + @param Data12Bit: 12Bit DAC data + @param Data6Bit: 6Bit DAC data + @return return none. +*/ +void AD5940_LPDAC0WriteS(uint16_t Data12Bit, uint8_t Data6Bit) +{ + /* Check parameter */ + Data6Bit &= 0x3f; + Data12Bit &= 0xfff; + AD5940_WriteReg(REG_AFE_LPDACDAT0, ((uint32_t)Data6Bit<<12)|Data12Bit); +} + +/** + @brief Write LPDAC1 data + @param Data12Bit: 12Bit DAC data + @param Data6Bit: 6Bit DAC data + @return return none. +*/ +void AD5940_LPDAC1WriteS(uint16_t Data12Bit, uint8_t Data6Bit) +{ + /* Check parameter */ + Data6Bit &= 0x3f; + Data12Bit &= 0xfff; + AD5940_WriteReg(REG_AFE_LPDACDAT1, ((uint32_t)Data6Bit<<12)|Data12Bit); +} + +/** + @brief Initialize LP TIA and PA + @param pLpAmpCfg: Pointer to configuration structure + @return return none. +*/ +void AD5940_LPAMPCfgS(LPAmpCfg_Type *pLpAmpCfg) +{ + //check parameters + uint32_t tempreg; + + tempreg = 0; + if(pLpAmpCfg->LpPaPwrEn == bFALSE) + tempreg |= BITM_AFE_LPTIACON0_PAPDEN; + if(pLpAmpCfg->LpTiaPwrEn == bFALSE) + tempreg |= BITM_AFE_LPTIACON0_TIAPDEN; + if(pLpAmpCfg->LpAmpPwrMod == LPAMPPWR_HALF) + tempreg |= BITM_AFE_LPTIACON0_HALFPWR; + else + { + tempreg |= pLpAmpCfg->LpAmpPwrMod<LpTiaRtia<LpTiaRload<LpTiaRf<LpAmpSel == LPAMP0) + { + AD5940_WriteReg(REG_AFE_LPTIACON0, tempreg); + AD5940_WriteReg(REG_AFE_LPTIASW0, pLpAmpCfg->LpTiaSW); + } + else + { + AD5940_WriteReg(REG_AFE_LPTIACON1, tempreg); + AD5940_WriteReg(REG_AFE_LPTIASW1, pLpAmpCfg->LpTiaSW); + } +} +/** + * @} Low_Power_Loop_Functions + * @} Low_Power_Loop +*/ + + +/** + * @defgroup DSP_Block + * @brief DSP block includes ADC, filters, DFT and statistic functions. + * @{ + * @defgroup DSP_Block_Functions + * @{ + * */ + +/** + @brief Configure low power loop include LPDAC LPAmp(PA and TIA) + @param pDSPCfg: Pointer to configure structure; + @return return none. +*/ +void AD5940_DSPCfgS(DSPCfg_Type *pDSPCfg) +{ + AD5940_ADCBaseCfgS(&pDSPCfg->ADCBaseCfg); + AD5940_ADCFilterCfgS(&pDSPCfg->ADCFilterCfg); + AD5940_ADCDigCompCfgS(&pDSPCfg->ADCDigCompCfg); + AD5940_DFTCfgS(&pDSPCfg->DftCfg); + AD5940_StatisticCfgS(&pDSPCfg->StatCfg); +} + +/** + @brief Read AD5940 generated data like ADC and DFT etc. + @param AfeResultSel: available parameters are @ref AFERESULT_Const + - AFERESULT_SINC3: Read SINC3 filter data result + - AFERESULT_SINC2: Read SINC2+NOTCH filter result, when Notch filter is bypassed, the result is SINC2 + - AFERESULT_STATSVAR: Statistic variance result + @return return data read back. +*/ +uint32_t AD5940_ReadAfeResult(uint32_t AfeResultSel) +{ + uint32_t rd = 0; + //PARA_CHECK((AfeResultSel)); + switch (AfeResultSel) + { + case AFERESULT_SINC3: + rd = AD5940_ReadReg(REG_AFE_ADCDAT); + break; + case AFERESULT_SINC2: + rd = AD5940_ReadReg(REG_AFE_SINC2DAT); + break; + case AFERESULT_TEMPSENSOR: + rd = AD5940_ReadReg(REG_AFE_TEMPSENSDAT); + break; + case AFERESULT_DFTREAL: + rd = AD5940_ReadReg(REG_AFE_DFTREAL); + break; + case AFERESULT_DFTIMAGE: + rd = AD5940_ReadReg(REG_AFE_DFTIMAG); + break; + case AFERESULT_STATSMEAN: + rd = AD5940_ReadReg(REG_AFE_STATSMEAN); + break; + case AFERESULT_STATSVAR: + rd = AD5940_ReadReg(REG_AFE_STATSVAR); + break; + } + + return rd; +} + +/** + * @defgroup ADC_Block_Functions + * @{ +*/ + +/** + @brief Initializes ADC peripheral according to the specified parameters in the pADCInit. + @param pADCInit: Pointer to ADC initialize structure. + @return return none. +*/ +void AD5940_ADCBaseCfgS(ADCBaseCfg_Type *pADCInit) +{ + uint32_t tempreg = 0; + //PARA_CHECK(IS_ADCMUXP(pADCInit->ADCMuxP)); + //PARA_CHECK(IS_ADCMUXN(pADCInit->ADCMuxN)); + PARA_CHECK(IS_ADCPGA(pADCInit->ADCPga)); + PARA_CHECK(IS_ADCAAF(pADCInit->ADCAAF)); + + tempreg = pADCInit->ADCMuxP; + tempreg |= (uint32_t)(pADCInit->ADCMuxN)<OffCancEnable == bTRUE) + // tempreg |= BITM_AFE_ADCCON_GNOFSELPGA; + tempreg |= (uint32_t)(pADCInit->ADCPga)<ADCSinc3Osr)); + PARA_CHECK(IS_ADCSINC2OSR(pFiltCfg->ADCSinc2Osr)); + PARA_CHECK(IS_ADCAVGNUM(pFiltCfg->ADCAvgNum)); + PARA_CHECK(IS_ADCRATE(pFiltCfg->ADCRate)); + + tempreg = AD5940_ReadReg(REG_AFE_ADCFILTERCON); + tempreg &= BITM_AFE_ADCFILTERCON_AVRGEN; /* Keep this bit setting. */ + + tempreg |= pFiltCfg->ADCRate; + if(pFiltCfg->BpNotch == bTRUE) + tempreg |= BITM_AFE_ADCFILTERCON_LPFBYPEN; + if(pFiltCfg->BpSinc3 == bTRUE) + tempreg |= BITM_AFE_ADCFILTERCON_SINC3BYP; + /** + * Average filter is enabled when DFT source is @ref DFTSRC_AVG in function @ref AD5940_DFTCfgS. + * Once average function is enabled, it's automatically set as DFT source, register DFTCON.DFTINSEL is ignored. + */ + //if(pFiltCfg->AverageEnable == bTRUE) + // tempreg |= BITM_AFE_ADCFILTERCON_AVRGEN; + tempreg |= (uint32_t)(pFiltCfg->ADCSinc2Osr)<ADCSinc3Osr)<ADCAvgNum)<Sinc2NotchEnable) + { + AD5940_AFECtrlS(AFECTRL_SINC2NOTCH,bTRUE); + } +} + +/** + @brief Power up or power down ADC block(including ADC PGA and FRONTBUF). + @param State : {bTRUE, bFALSE} + - bTRUE: Power up ADC + - bFALSE: Power down ADC + @return return none. +*/ +void AD5940_ADCPowerCtrlS(BoolFlag State) +{ + uint32_t tempreg; + tempreg = AD5940_ReadReg(REG_AFE_AFECON); + if(State == bTRUE) + { + tempreg |= BITM_AFE_AFECON_ADCEN; + } + else + { + tempreg &= ~BITM_AFE_AFECON_ADCEN; + } + AD5940_WriteReg(REG_AFE_AFECON,tempreg); +} + +/** + @brief Start or stop ADC convert. + @param State : {bTRUE, bFALSE} + - bTRUE: Start ADC convert + - bFALSE: Stop ADC convert + @return return none. +*/ +void AD5940_ADCConvtCtrlS(BoolFlag State) +{ + uint32_t tempreg; + tempreg = AD5940_ReadReg(REG_AFE_AFECON); + if(State == bTRUE) + { + tempreg |= BITM_AFE_AFECON_ADCCONVEN; + } + else + { + tempreg &= ~BITM_AFE_AFECON_ADCCONVEN; + } + AD5940_WriteReg(REG_AFE_AFECON,tempreg); +} + +/** + @brief Configure ADC input MUX + @param ADCMuxP : {ADCMUXP_FLOAT, ADCMUXP_HSTIA_P, ,,, ,ADCMUXP_P_NODE} + - ADCMUXP_FLOAT: float ADC MUX positive input + - ADCMUXP_HSTIA_P: High speed TIA output sense terminal + - ADCMUXP_P_NODE: Excitation loop P node + @param ADCMuxN : {ADCMUXP_FLOAT, ADCMUXP_HSTIA_P, ,,, ,ADCMUXP_P_NODE} + - ADCMUXP_FLOAT: float ADC MUX positive input + - ADCMUXP_HSTIA_P: High speed TIA output sense terminal + - ADCMUXP_P_NODE: Excitation loop P node + + @return return none. +*/ +void AD5940_ADCMuxCfgS(uint32_t ADCMuxP, uint32_t ADCMuxN) +{ + uint32_t tempreg; + //PARA_CHECK(IS_ADCMUXP(ADCMuxP)); + //PARA_CHECK(IS_ADCMUXN(ADCMuxN)); + + tempreg = AD5940_ReadReg(REG_AFE_ADCCON); + tempreg &= ~(BITM_AFE_ADCCON_MUXSELN|BITM_AFE_ADCCON_MUXSELP); + tempreg |= ADCMuxP<ADCMin); + AD5940_WriteReg(REG_AFE_ADCMINSM, pCompCfg->ADCMinHys); + AD5940_WriteReg(REG_AFE_ADCMAX, pCompCfg->ADCMax); + AD5940_WriteReg(REG_AFE_ADCMAXSMEN, pCompCfg->ADCMaxHys); +} +/** @} ADC_Block_Functions */ + +/** + @brief Configure statistic functions + @param pStatCfg: Pointer to configuration structure + @return return none. +*/ +void AD5940_StatisticCfgS(StatCfg_Type *pStatCfg) +{ + uint32_t tempreg; + //check parameters + tempreg = 0; + if(pStatCfg->StatEnable == bTRUE) + tempreg |= BITM_AFE_STATSCON_STATSEN; + tempreg |= (pStatCfg->StatSample) << BITP_AFE_STATSCON_SAMPLENUM; + tempreg |= (pStatCfg->StatDev) << BITP_AFE_STATSCON_STDDEV; + AD5940_WriteReg(REG_AFE_STATSCON, tempreg); +} + +/** + * @brief Set ADC Repeat convert function number. Turn off ADC automatically after Number samples of ADC raw data are ready + * @param Number: Specify after how much ADC raw data need to sample before shutdown ADC + * @return return none. +*/ +void AD5940_ADCRepeatCfgS(uint32_t Number) +{ + //check parameter if(number<255) + AD5940_WriteReg(REG_AFE_REPEATADCCNV, Number<DftSrc == DFTSRC_AVG) + { + reg_adcfilter |= BITM_AFE_ADCFILTERCON_AVRGEN; + AD5940_WriteReg(REG_AFE_ADCFILTERCON, reg_adcfilter); + } + else + { + /* Disable Average function and set correct DFT source */ + reg_adcfilter &= ~BITM_AFE_ADCFILTERCON_AVRGEN; + AD5940_WriteReg(REG_AFE_ADCFILTERCON, reg_adcfilter); + + /* Set new DFT source */ + reg_dftcon |= (pDftCfg->DftSrc) << BITP_AFE_DFTCON_DFTINSEL; + } + /* Set DFT number */ + reg_dftcon |= (pDftCfg->DftNum) << BITP_AFE_DFTCON_DFTNUM; + + if(pDftCfg->HanWinEn == bTRUE) + reg_dftcon |= BITM_AFE_DFTCON_HANNINGEN; + AD5940_WriteReg(REG_AFE_DFTCON, reg_dftcon); +} + +/** + * @} DSP_Block_Functions + * @} DSP_Block +*/ + +/** + * @defgroup Sequencer_FIFO + * @brief Sequencer and FIFO. + * @{ + * @defgroup Sequencer_FIFO_Functions + * @{ +*/ + +/** + @brief Configure AD5940 FIFO + @param pFifoCfg: Pointer to configuration structure. + @return return none. +*/ +void AD5940_FIFOCfg(FIFOCfg_Type *pFifoCfg) +{ + uint32_t tempreg; + //check parameters + AD5940_WriteReg(REG_AFE_FIFOCON, 0); /* Disable FIFO firstly! */ + /* CMDDATACON register. Configure this firstly */ + tempreg = AD5940_ReadReg(REG_AFE_CMDDATACON); + tempreg &= BITM_AFE_CMDDATACON_CMD_MEM_SEL|BITM_AFE_CMDDATACON_CMDMEMMDE; /* Keep sequencer memory settings */ + tempreg |= pFifoCfg->FIFOMode << BITP_AFE_CMDDATACON_DATAMEMMDE; /* Data FIFO mode: stream or FIFO */ + tempreg |= pFifoCfg->FIFOSize << BITP_AFE_CMDDATACON_DATA_MEM_SEL; /* Data FIFO memory size */ + /* The reset memory can be used for sequencer, configure it by function AD5940_SEQCfg() */ + AD5940_WriteReg(REG_AFE_CMDDATACON, tempreg); + + /* FIFO Threshold */ + AD5940_WriteReg(REG_AFE_DATAFIFOTHRES, pFifoCfg->FIFOThresh << BITP_AFE_DATAFIFOTHRES_HIGHTHRES); + /* FIFOCON register. Final step is to enable FIFO */ + tempreg = 0; + if(pFifoCfg->FIFOEn == bTRUE) + tempreg |= BITM_AFE_FIFOCON_DATAFIFOEN; /* Enable FIFO after everything set. */ + tempreg |= pFifoCfg->FIFOSrc << BITP_AFE_FIFOCON_DATAFIFOSRCSEL; + AD5940_WriteReg(REG_AFE_FIFOCON, tempreg); +} + +/** + @brief Read current FIFO configuration. + @param pFifoCfg: Pointer to a buffer that used to store FIFO configuration. + @return return AD5940ERR_OK if succeed. +*/ +AD5940Err AD5940_FIFOGetCfg(FIFOCfg_Type *pFifoCfg) +{ + uint32_t tempreg; + //check parameters + if(pFifoCfg == NULL) return AD5940ERR_NULLP; + /* CMDDATACON register. */ + tempreg = AD5940_ReadReg(REG_AFE_CMDDATACON); + pFifoCfg->FIFOMode = (tempreg&BITM_AFE_CMDDATACON_DATAMEMMDE)>>BITP_AFE_CMDDATACON_DATAMEMMDE; + pFifoCfg->FIFOSize = (tempreg&BITM_AFE_CMDDATACON_DATA_MEM_SEL)>>BITP_AFE_CMDDATACON_DATA_MEM_SEL; + + /* FIFO Threshold */ + tempreg = AD5940_ReadReg(REG_AFE_DATAFIFOTHRES); + pFifoCfg->FIFOThresh = (tempreg&BITM_AFE_DATAFIFOTHRES_HIGHTHRES)>>BITP_AFE_DATAFIFOTHRES_HIGHTHRES; + /* FIFOCON register. */ + tempreg = AD5940_ReadReg(REG_AFE_FIFOCON); + pFifoCfg->FIFOEn = (tempreg&BITM_AFE_FIFOCON_DATAFIFOEN)?bTRUE:bFALSE; + pFifoCfg->FIFOSrc = (tempreg&BITM_AFE_FIFOCON_DATAFIFOSRCSEL)>>BITP_AFE_FIFOCON_DATAFIFOSRCSEL; + + return AD5940ERR_OK; +} + +/** + * @brief Configure AD5940 FIFO Source and enable or disable FIFO. + * @param FifoSrc : available choices are @ref FIFOSRC_Const + * - FIFOSRC_SINC3 SINC3 data + * - FIFOSRC_DFT DFT real and imaginary part + * - FIFOSRC_SINC2NOTCH SINC2+NOTCH block. Notch can be bypassed, so SINC2 data can be feed to FIFO + * - FIFOSRC_VAR Statistic variance output + * - FIFOSRC_MEAN Statistic mean output + * @param FifoEn: enable or disable the FIFO. + * @return return none. +*/ +void AD5940_FIFOCtrlS(uint32_t FifoSrc, BoolFlag FifoEn) +{ + uint32_t tempreg; + + tempreg = 0; + if(FifoEn == bTRUE) + tempreg |= BITM_AFE_FIFOCON_DATAFIFOEN; + tempreg |= FifoSrc << BITP_AFE_FIFOCON_DATAFIFOSRCSEL; + AD5940_WriteReg(REG_AFE_FIFOCON, tempreg); +} + +/** + * @brief Configure AD5940 Data FIFO threshold value + @param FIFOThresh: FIFO threshold value + @return return none. +*/ +void AD5940_FIFOThrshSet(uint32_t FIFOThresh) +{ + /* FIFO Threshold */ + AD5940_WriteReg(REG_AFE_DATAFIFOTHRES, FIFOThresh << BITP_AFE_DATAFIFOTHRES_HIGHTHRES); +} + +/** + * @brief Get Data count in FIFO + * @return return none. +*/ +uint32_t AD5940_FIFOGetCnt(void) +{ + return AD5940_ReadReg(REG_AFE_FIFOCNTSTA) >> BITP_AFE_FIFOCNTSTA_DATAFIFOCNTSTA; +} + + +/* Sequencer */ +/** + * @brief Initialize Sequencer + * @param pSeqCfg: Pointer to configuration structure + @return return none. +*/ +void AD5940_SEQCfg(SEQCfg_Type *pSeqCfg) +{ + /* check parameters */ + uint32_t tempreg, fifocon; + + fifocon = AD5940_ReadReg(REG_AFE_FIFOCON); + AD5940_WriteReg(REG_AFE_FIFOCON, 0); /* Disable FIFO before changing memory configuration */ + /* Configure CMDDATACON register */ + tempreg = AD5940_ReadReg(REG_AFE_CMDDATACON); + tempreg &= ~(BITM_AFE_CMDDATACON_CMDMEMMDE|BITM_AFE_CMDDATACON_CMD_MEM_SEL); /* Clear settings for sequencer memory */ + tempreg |= (1L) << BITP_AFE_CMDDATACON_CMDMEMMDE; /* Sequencer is always in memory mode */ + tempreg |= (pSeqCfg->SeqMemSize) << BITP_AFE_CMDDATACON_CMD_MEM_SEL; + AD5940_WriteReg(REG_AFE_CMDDATACON, tempreg); + + if(pSeqCfg->SeqCntCRCClr) + { + AD5940_WriteReg(REG_AFE_SEQCON, 0); /* Disable sequencer firstly */ + AD5940_WriteReg(REG_AFE_SEQCNT, 0); /* When sequencer is disabled, any write to SEQCNT will clear CNT and CRC register */ + } + tempreg = 0; + if(pSeqCfg->SeqEnable == bTRUE) + tempreg |= BITM_AFE_SEQCON_SEQEN; + tempreg |= (pSeqCfg->SeqWrTimer) << BITP_AFE_SEQCON_SEQWRTMR; + AD5940_WriteReg(REG_AFE_SEQCON, tempreg); + AD5940_WriteReg(REG_AFE_FIFOCON, fifocon); /* restore FIFO configuration */ + + // tempreg = 0; + // if(pSeqCfg->SeqBreakEn) + // tempreg |= 0x01; // add register definition? bitm_afe_ + // if(pSeqCfg->SeqIgnoreEn) + // tempreg |= 0x02; + // AD5940_WriteReg(0x21dc, tempreg); +} +/** + * @brief Read back current sequencer configuration and store it to pSeqCfg + * @param pSeqCfg: Pointer to structure + * @return return AD5940ERR_OK if succeed. +*/ +AD5940Err AD5940_SEQGetCfg(SEQCfg_Type *pSeqCfg) +{ + /* check parameters */ + uint32_t tempreg; + if(pSeqCfg == NULL) + return AD5940ERR_NULLP; + /* Read CMDDATACON register */ + tempreg = AD5940_ReadReg(REG_AFE_CMDDATACON); + pSeqCfg->SeqMemSize = (tempreg&BITM_AFE_CMDDATACON_CMD_MEM_SEL) >> BITP_AFE_CMDDATACON_CMD_MEM_SEL; + pSeqCfg->SeqCntCRCClr = bFALSE; /* Has no meaning */ + /* SEQCON register */ + tempreg = AD5940_ReadReg(REG_AFE_SEQCON); + pSeqCfg->SeqEnable = (tempreg&BITM_AFE_SEQCON_SEQEN)?bTRUE:bFALSE; + pSeqCfg->SeqWrTimer = (tempreg&BITM_AFE_SEQCON_SEQWRTMR) >> BITP_AFE_SEQCON_SEQWRTMR; + return AD5940ERR_OK; +} + +/** + * @brief Enable or Disable sequencer. + * @note Only after valid trigger signal, sequencer can run. + * @return return none. +*/ +void AD5940_SEQCtrlS(BoolFlag SeqEn) +{ + uint32_t tempreg = AD5940_ReadReg(REG_AFE_SEQCON); + if(SeqEn == bTRUE) + tempreg |= BITM_AFE_SEQCON_SEQEN; + else + tempreg &= ~BITM_AFE_SEQCON_SEQEN; + + AD5940_WriteReg(REG_AFE_SEQCON, tempreg); +} + +/** + * @brief Halt sequencer immediately. Use this to debug. In normal application, there is no situation that can use this function. + * @return return none. +*/ +void AD5940_SEQHaltS(void) +{ + AD5940_WriteReg(REG_AFE_SEQCON, BITM_AFE_SEQCON_SEQHALT|BITM_AFE_SEQCON_SEQEN); +} + +/** + * @brief Trigger sequencer by register write. + * @return return none. +**/ +void AD5940_SEQMmrTrig(uint32_t SeqId) +{ + if(SeqId > SEQID_3) + return; + AD5940_WriteReg(REG_AFECON_TRIGSEQ, 1L<SeqId) + { + case SEQID_0: + /* Configure SEQINFO register */ + AD5940_WriteReg(REG_AFE_SEQ0INFO, (pSeq->SeqLen<< 16) | pSeq->SeqRamAddr); + break; + case SEQID_1: + AD5940_WriteReg(REG_AFE_SEQ1INFO, (pSeq->SeqLen<< 16) | pSeq->SeqRamAddr); + break; + case SEQID_2: + AD5940_WriteReg(REG_AFE_SEQ2INFO, (pSeq->SeqLen<< 16) | pSeq->SeqRamAddr); + break; + case SEQID_3: + AD5940_WriteReg(REG_AFE_SEQ3INFO, (pSeq->SeqLen<< 16) | pSeq->SeqRamAddr); + break; + default: + break; + } + if(pSeq->WriteSRAM == bTRUE) + { + AD5940_SEQCmdWrite(pSeq->SeqRamAddr, pSeq->pSeqCmd, pSeq->SeqLen); + } +} + +/** + * @brief Get sequence info: start address and sequence length. + * @param SeqId: Select from {SEQID_0, SEQID_1, SEQID_2, SEQID_3} + - Select which sequence we want to get the information. + @param pSeqInfo: Pointer to sequence info structure. + @return return AD5940ERR_OK when succeed. +*/ +AD5940Err AD5940_SEQInfoGet(uint32_t SeqId, SEQInfo_Type *pSeqInfo) +{ + uint32_t tempreg; + if(pSeqInfo == NULL) return AD5940ERR_NULLP; + switch(SeqId) + { + case SEQID_0: + tempreg = AD5940_ReadReg(REG_AFE_SEQ0INFO); + break; + case SEQID_1: + tempreg = AD5940_ReadReg(REG_AFE_SEQ1INFO); + break; + case SEQID_2: + tempreg = AD5940_ReadReg(REG_AFE_SEQ2INFO); + break; + case SEQID_3: + tempreg = AD5940_ReadReg(REG_AFE_SEQ3INFO); + break; + default: + return AD5940ERR_PARA; + } + pSeqInfo->pSeqCmd = 0; /* We don't know where you store the sequence in MCU SRAM */ + pSeqInfo->SeqId = SeqId; + pSeqInfo->SeqLen = (tempreg>>16)&0x7ff; + pSeqInfo->SeqRamAddr = tempreg&0x7ff; + pSeqInfo->WriteSRAM = bFALSE; /* Don't care */ + + return AD5940ERR_OK; +} + + +/** + @brief Control GPIO with register SYNCEXTDEVICE. Because sequencer have no ability to access register GPIOOUT, + so we use this register for sequencer. + @param Gpio : Select from {AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin2|AGPIO_Pin3|AGPIO_Pin4|AGPIO_Pin5|AGPIO_Pin6|AGPIO_Pin7} + - The combination of GPIO pins. The selected pins will be set to High. Others will be pulled low. + @return return None. + +**/ +void AD5940_SEQGpioCtrlS(uint32_t Gpio) +{ + AD5940_WriteReg(REG_AFE_SYNCEXTDEVICE, Gpio); +} + +/** + * @brief Read back current count down timer value for Sequencer Timer Out command. + * @return return register value of Sequencer Timer out value. +**/ +uint32_t AD5940_SEQTimeOutRd(void) +{ + return AD5940_ReadReg(REG_AFE_SEQTIMEOUT); +} + +/** + * @brief Configure GPIO to allow it to trigger corresponding sequence(SEQ0/1/2/3). + * @details There are four sequences. We can use GPIO to trigger each sequence. For example, + * GP0 or GP4 can be used to trigger sequence0 and GP3 or GP7 to trigger sequence3. + * There are five mode available to detect pin action: Rising edge, falling edge, both rising and falling + * edge, low level or high level. + * Be careful to use level detection. The trigger signal is always available if the pin level is matched. + * Once the sequence is done, it will immediately run again if the pin level is still matched. + * @return return AD5940ERR_OK if succeed. +**/ +AD5940Err AD5940_SEQGpioTrigCfg(SeqGpioTrig_Cfg *pSeqGpioTrigCfg) +{ + uint32_t reg_ei0con, reg_ei1con; + uint32_t pin_count, pin_mask; + uint32_t mode, en; + if(pSeqGpioTrigCfg == NULL) + return AD5940ERR_NULLP; + reg_ei0con = AD5940_ReadReg(REG_ALLON_EI0CON); + reg_ei1con = AD5940_ReadReg(REG_ALLON_EI1CON); + + pin_count = 0; /* Start from pin0 */ + pin_mask = 0x01; /* start from pin0, mask 0x01 */ + pSeqGpioTrigCfg->SeqPinTrigMode &= 0x07; /* 3bit width */ + + mode = pSeqGpioTrigCfg->SeqPinTrigMode; + en = pSeqGpioTrigCfg->bEnable?1:0; + for(;;) + { + uint32_t bit_position; + if(pSeqGpioTrigCfg->PinSel&pin_mask) + { + if(pin_count < 4) /* EI0CON register */ + { + bit_position = pin_count*4; + reg_ei1con &= ~(0xfL<SeqxWakeupTime[0] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ0WUPH, (pWuptCfg->SeqxWakeupTime[0] & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ0SLEEPL, (pWuptCfg->SeqxSleepTime[0] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ0SLEEPH, (pWuptCfg->SeqxSleepTime[0] & 0xF0000)>>16); + + AD5940_WriteReg(REG_WUPTMR_SEQ1WUPL, (pWuptCfg->SeqxWakeupTime[1] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ1WUPH, (pWuptCfg->SeqxWakeupTime[1] & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ1SLEEPL, (pWuptCfg->SeqxSleepTime[1] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ1SLEEPH, (pWuptCfg->SeqxSleepTime[1] & 0xF0000)>>16); + + AD5940_WriteReg(REG_WUPTMR_SEQ2WUPL, (pWuptCfg->SeqxWakeupTime[2] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ2WUPH, (pWuptCfg->SeqxWakeupTime[2] & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ2SLEEPL, (pWuptCfg->SeqxSleepTime[2] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ2SLEEPH, (pWuptCfg->SeqxSleepTime[2] & 0xF0000)>>16); + + AD5940_WriteReg(REG_WUPTMR_SEQ3WUPL, (pWuptCfg->SeqxWakeupTime[3] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ3WUPH, (pWuptCfg->SeqxWakeupTime[3] & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ3SLEEPL, (pWuptCfg->SeqxSleepTime[3] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ3SLEEPH, (pWuptCfg->SeqxSleepTime[3] & 0xF0000)>>16); + + /* TMRCON register */ + //if(pWuptCfg->WakeupEn == bTRUE) /* enable use Wupt to wakeup AFE */ + /* We always allow Wupt to wakeup AFE automatically. */ + AD5940_WriteReg(REG_ALLON_TMRCON, BITM_ALLON_TMRCON_TMRINTEN); + /* Wupt order */ + tempreg = 0; + tempreg |= (pWuptCfg->WuptOrder[0]&0x03) << BITP_WUPTMR_SEQORDER_SEQA; /* position A */ + tempreg |= (pWuptCfg->WuptOrder[1]&0x03) << BITP_WUPTMR_SEQORDER_SEQB; /* position B */ + tempreg |= (pWuptCfg->WuptOrder[2]&0x03) << BITP_WUPTMR_SEQORDER_SEQC; /* position C */ + tempreg |= (pWuptCfg->WuptOrder[3]&0x03) << BITP_WUPTMR_SEQORDER_SEQD; /* position D */ + tempreg |= (pWuptCfg->WuptOrder[4]&0x03) << BITP_WUPTMR_SEQORDER_SEQE; /* position E */ + tempreg |= (pWuptCfg->WuptOrder[5]&0x03) << BITP_WUPTMR_SEQORDER_SEQF; /* position F */ + tempreg |= (pWuptCfg->WuptOrder[6]&0x03) << BITP_WUPTMR_SEQORDER_SEQG; /* position G */ + tempreg |= (pWuptCfg->WuptOrder[7]&0x03) << BITP_WUPTMR_SEQORDER_SEQH; /* position H */ + AD5940_WriteReg(REG_WUPTMR_SEQORDER, tempreg); + + tempreg = 0; + if(pWuptCfg->WuptEn == bTRUE) + tempreg |= BITM_WUPTMR_CON_EN; + /* We always allow Wupt to trigger sequencer */ + tempreg |= pWuptCfg->WuptEndSeq << BITP_WUPTMR_CON_ENDSEQ; + //tempreg |= 1L<<4; + AD5940_WriteReg(REG_WUPTMR_CON, tempreg); +} + +/** + * @brief Enable or disable wakeup timer + * @param Enable : {bTRUE, bFALSE} + * - bTRUE: enable wakeup timer + * - bFALSE: Disable wakeup timer + * @return return none. +*/ +void AD5940_WUPTCtrl(BoolFlag Enable) +{ + uint16_t tempreg; + tempreg = AD5940_ReadReg(REG_WUPTMR_CON); + tempreg &= ~BITM_WUPTMR_CON_EN; + + if(Enable == bTRUE) + tempreg |= BITM_WUPTMR_CON_EN; + + AD5940_WriteReg(REG_WUPTMR_CON, tempreg); +} + +/** + * @brief Configure WakeupTimer. + * @param SeqId: Select from SEQID_0/1/2/3. The wakeup timer will load corresponding value from four sets of registers. + * @param SleepTime: After how much time, AFE will try to enter hibernate. We disabled this feature in AD59840_Initialize. After this timer expired, nothing will happen. + * @param WakeupTime: After how much time, AFE will wakeup and trigger corresponding sequencer. + * @note By SleepTime and WakeupTime, the sequencer is triggered periodically and period is (SleepTime+WakeupTime) + * @return return none. +*/ +AD5940Err AD5940_WUPTTime(uint32_t SeqId, uint32_t SleepTime, uint32_t WakeupTime) +{ + switch (SeqId) + { + case SEQID_0: + { + AD5940_WriteReg(REG_WUPTMR_SEQ0WUPL, (WakeupTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ0WUPH, (WakeupTime & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ0SLEEPL, (SleepTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ0SLEEPH, (SleepTime & 0xF0000)>>16); + break; + } + case SEQID_1: + { + AD5940_WriteReg(REG_WUPTMR_SEQ1WUPL, (WakeupTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ1WUPH, (WakeupTime & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ1SLEEPL, (SleepTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ1SLEEPH, (SleepTime & 0xF0000)>>16); + break; + } + case SEQID_2: + { + AD5940_WriteReg(REG_WUPTMR_SEQ2WUPL, (WakeupTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ2WUPH, (WakeupTime & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ2SLEEPL, (SleepTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ2SLEEPH, (SleepTime & 0xF0000)>>16); + break; + } + case SEQID_3: + { + AD5940_WriteReg(REG_WUPTMR_SEQ3WUPL, (WakeupTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ3WUPH, (WakeupTime & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ3SLEEPL, (SleepTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ3SLEEPH, (SleepTime & 0xF0000)>>16); + break; + } + default: + return AD5940ERR_PARA; + } + return AD5940ERR_OK; +} + +/** + * @} end-of Sequencer_FIFO_Functions + * @} end-of Sequencer_FIFO +*/ + +/** + * @defgroup MISC_Block + * @brief Other functions not included in above blocks. Clock, GPIO, INTC etc. + * @{ + * @defgroup MISC_Block_Functions + * @{ +*/ + +/** + * @brief Configure AD5940 clock + * @param pClkCfg: Pointer to configuration structure. + * @return return none. +*/ +void AD5940_CLKCfg(CLKCfg_Type *pClkCfg) +{ + uint32_t tempreg, reg_osccon; + + reg_osccon = AD5940_ReadReg(REG_ALLON_OSCCON); + /* Enable clocks */ + if(pClkCfg->HFXTALEn == bTRUE) + { + reg_osccon |= BITM_ALLON_OSCCON_HFXTALEN; + AD5940_WriteReg(REG_ALLON_OSCKEY,KEY_OSCCON); /* Write Key */ + AD5940_WriteReg(REG_ALLON_OSCCON, reg_osccon); /* Enable HFXTAL */ + while((AD5940_ReadReg(REG_ALLON_OSCCON)&BITM_ALLON_OSCCON_HFXTALOK) == 0); /* Wait for clock ready */ + } + + if(pClkCfg->HFOSCEn == bTRUE) + { + reg_osccon |= BITM_ALLON_OSCCON_HFOSCEN; + AD5940_WriteReg(REG_ALLON_OSCKEY,KEY_OSCCON); /* Write Key */ + AD5940_WriteReg(REG_ALLON_OSCCON, reg_osccon); /* Enable HFOSC */ + while((AD5940_ReadReg(REG_ALLON_OSCCON)&BITM_ALLON_OSCCON_HFOSCOK) == 0); /* Wait for clock ready */ + /* Configure HFOSC mode if it's enabled. */ + if(pClkCfg->HfOSC32MHzMode == bTRUE) + AD5940_HFOSC32MHzCtrl(bTRUE); + else + AD5940_HFOSC32MHzCtrl(bFALSE); + } + + if(pClkCfg->LFOSCEn == bTRUE) + { + reg_osccon |= BITM_ALLON_OSCCON_LFOSCEN; + AD5940_WriteReg(REG_ALLON_OSCKEY,KEY_OSCCON); /* Write Key */ + AD5940_WriteReg(REG_ALLON_OSCCON, reg_osccon); /* Enable LFOSC */ + while((AD5940_ReadReg(REG_ALLON_OSCCON)&BITM_ALLON_OSCCON_LFOSCOK) == 0); /* Wait for clock ready */ + } + + /* Switch clocks */ + /* step1. Set clock divider */ + tempreg = pClkCfg->SysClkDiv&0x3f; + tempreg |= (pClkCfg->SysClkDiv&0x3f) << BITP_AFECON_CLKCON0_SYSCLKDIV; + tempreg |= (pClkCfg->ADCClkDiv&0xf) << BITP_AFECON_CLKCON0_ADCCLKDIV; + AD5940_WriteReg(REG_AFECON_CLKCON0, tempreg); + AD5940_Delay10us(10); + /* Step2. set clock source */ + tempreg = pClkCfg->SysClkSrc; + tempreg |= pClkCfg->ADCCLkSrc << BITP_AFECON_CLKSEL_ADCCLKSEL; + AD5940_WriteReg(REG_AFECON_CLKSEL, tempreg); + + /* Disable clocks */ + if(pClkCfg->HFXTALEn == bFALSE) + reg_osccon &= ~BITM_ALLON_OSCCON_HFXTALEN; + if(pClkCfg->HFOSCEn == bFALSE) + reg_osccon &= ~BITM_ALLON_OSCCON_HFOSCEN; + if(pClkCfg->LFOSCEn == bFALSE) + reg_osccon &= ~BITM_ALLON_OSCCON_LFOSCEN; + AD5940_WriteReg(REG_ALLON_OSCKEY, KEY_OSCCON); /* Write Key */ + AD5940_WriteReg(REG_ALLON_OSCCON, reg_osccon); +} + +/** + * @brief Configure Internal HFOSC to output 32MHz or 16MHz. + * @param Mode32MHz : {bTRUE, bFALSE} + * - bTRUE: HFOSC 32MHz mode. + * - bFALSE: HFOSC 16MHz mode. + * @return return none. +*/ +void AD5940_HFOSC32MHzCtrl(BoolFlag Mode32MHz) +{ + uint32_t RdCLKEN1; + uint32_t RdHPOSCCON; + + uint32_t bit8,bit9; + + RdCLKEN1 = AD5940_ReadReg(REG_AFECON_CLKEN1); + bit8 = (RdCLKEN1>>9)&0x01; + bit9 = (RdCLKEN1>>8)&0x01; /* Fix bug in silicon, bit8 and bit9 is swapped when read back. */ + RdCLKEN1 = RdCLKEN1&0xff; + RdCLKEN1 |= (bit8<<8)|(bit9<<9); + AD5940_WriteReg(REG_AFECON_CLKEN1,RdCLKEN1|BITM_AFECON_CLKEN1_ACLKDIS); /* Disable ACLK during clock changing */ + + RdHPOSCCON = AD5940_ReadReg(REG_AFE_HPOSCCON); + if(Mode32MHz == bTRUE) + { + AD5940_WriteReg(REG_AFE_HPOSCCON,RdHPOSCCON&(~BITM_AFE_HPOSCCON_CLK32MHZEN)); /* Enable 32MHz output(bit definition-0: 32MHz, 1: 16MHz) */ + while((AD5940_ReadReg(REG_ALLON_OSCCON)&BITM_ALLON_OSCCON_HFOSCOK) == 0); /* Wait for clock ready */ + } + else + { + AD5940_WriteReg(REG_AFE_HPOSCCON,RdHPOSCCON|BITM_AFE_HPOSCCON_CLK32MHZEN); /* Enable 16MHz output(bit definition-0: 32MHz, 1: 16MHz) */ + while((AD5940_ReadReg(REG_ALLON_OSCCON)&BITM_ALLON_OSCCON_HFOSCOK) == 0); /* Wait for clock ready */ + } + + AD5940_WriteReg(REG_AFECON_CLKEN1,RdCLKEN1&(~BITM_AFECON_CLKEN1_ACLKDIS)); /* Enable ACLK */ +} +/** + * @brief Enable high power mode for high frequency EIS + * @param Mode32MHz : {bTRUE, bFALSE} + * - bTRUE: HFOSC 32MHz mode. + * - bFALSE: HFOSC 16MHz mode. + * @return return none. +*/ +void AD5940_HPModeEn(BoolFlag Enable) +{ + CLKCfg_Type clk_cfg; + uint32_t temp_reg = 0; + + /* Check what the system clock is */ + temp_reg = AD5940_ReadReg(REG_AFECON_CLKSEL); + clk_cfg.ADCCLkSrc = (temp_reg>>2)&0x3; + clk_cfg.SysClkSrc = temp_reg & 0x3; + if(Enable == bTRUE) + { + clk_cfg.SysClkDiv = SYSCLKDIV_2; + clk_cfg.HfOSC32MHzMode = bTRUE; + AD5940_AFEPwrBW(AFEPWR_HP, AFEBW_250KHZ); + } + else + { + clk_cfg.SysClkDiv = SYSCLKDIV_1; + clk_cfg.HfOSC32MHzMode = bFALSE; + AD5940_AFEPwrBW(AFEPWR_LP, AFEBW_100KHZ); + } + clk_cfg.ADCClkDiv = ADCCLKDIV_1; + clk_cfg.HFOSCEn = (temp_reg & 0x3) == 0x1? bFALSE : bTRUE;; + clk_cfg.HFXTALEn = (temp_reg & 0x3) == 0x1? bTRUE : bFALSE; + clk_cfg.LFOSCEn = bTRUE; + AD5940_CLKCfg(&clk_cfg); +} + +/** + * @defgroup Interrupt_Controller_Functions + * @{ +*/ +/* AFE Interrupt Controller */ +/** + * @brief Enable or Disable selected interrupt source(s) + * @param AfeIntcSel : {AFEINTC_0, AFEINTC_1} + * - AFEINTC_0: Configure Interrupt Controller 0 + * - AFEINTC_1: Configure Interrupt Controller 1 + * @param AFEIntSrc: select from @ref AFEINTC_SRC_Const + * - AFEINTSRC_ADCRDY : Bit0 ADC Result Ready Status + * - AFEINTSRC_DFTRDY : Bit1 DFT Result Ready Status + * - AFEINTSRC_SUPPLYFILTRDY : Bit2 Low Pass Filter Result Status + * - AFEINTSRC_TEMPRDY : Bit3, Temp Sensor Result Ready + * - AFEINTSRC_ADCMINERR : Bit4, ADC Minimum Value + * - AFEINTSRC_ADCMAXERR : Bit5, ADC Maximum Value + * - AFEINTSRC_ADCDIFFERR : Bit6, ADC Delta Ready + * - AFEINTSRC_MEANRDY : Bit7, Mean Result Ready + * - AFEINTSRC_VARRDY : Bit8, Variance Result Ready + * - AFEINTSRC_DLYCMDDONE : Bit9, User controlled interrupt by writing AFEGENINTSTA. Provides an Early Indication for the End of the Test _Block. + * - AFEINTSRC_HWSETUPDONE : Bit10, User controlled interrupt by writing AFEGENINTSTA. Indicates the MMR Setup for the Measurement Step Finished + * - AFEINTSRC_BRKSEQ : Bit11, User controlled interrupt by writing AFEGENINTSTA. + * - AFEINTSRC_CUSTOMINS : Bit12, User controlled interrupt by writing AFEGENINTSTA. General Purpose Custom Interrupt. + * - AFEINTSRC_BOOTLDDONE : Bit13, OTP Boot Loading Done + * - AFEINTSRC_WAKEUP : Bit14, AFE Woken up + * - AFEINTSRC_ENDSEQ : Bit15, End of Sequence Interrupt. + * - AFEINTSRC_SEQTIMEOUT : Bit16, Sequencer Timeout Command Finished. + * - AFEINTSRC_SEQTIMEOUTERR : Bit17, Sequencer Timeout Command Error. + * - AFEINTSRC_CMDFIFOFULL : Bit18, Command FIFO Full Interrupt. + * - AFEINTSRC_CMDFIFOEMPTY : Bit19, Command FIFO Empty + * - AFEINTSRC_CMDFIFOTHRESH: Bit20, Command FIFO Threshold Interrupt. + * - AFEINTSRC_CMDFIFOOF : Bit21, Command FIFO Overflow Interrupt. + * - AFEINTSRC_CMDFIFOUF : Bit22, Command FIFO Underflow Interrupt. + * - AFEINTSRC_DATAFIFOFULL : Bit23, Data FIFO Full Interrupt. + * - AFEINTSRC_DATAFIFOEMPTY: Bit24, Data FIFO Empty + * - AFEINTSRC_DATAFIFOTHRESH: Bit25, Data FIFO Threshold Interrupt. + * - AFEINTSRC_DATAFIFOOF : Bit26, Data FIFO Overflow Interrupt. + * - AFEINTSRC_DATAFIFOUF : Bit27, Data FIFO Underflow Interrupt. + * - AFEINTSRC_WDTIRQ : Bit28, WDT Timeout Interrupt. + * - AFEINTSRC_CRC_OUTLIER : Bit29, CRC interrupt for M355, Outliers Int for AD5940 + * - AFEINTSRC_GPT0INT_SLPWUT: Bit30, General Purpose Timer0 IRQ for M355. Sleep or Wakeup Timer timeout for AD5940 + * - AFEINTSRC_GPT1INT_TRYBRK: Bit31, General Purpose Timer1 IRQ for M355. Tried to Break IRQ for AD5940 + * - AFE_INTC_ALLINT : All interrupts + * @param State : {bTRUE, bFALSE} + * - bTRUE: Enable these interrupt source(s) + * - bFALSE: Disable interrupt source(s) + * @return return none. +*/ +void AD5940_INTCCfg(uint32_t AfeIntcSel, uint32_t AFEIntSrc, BoolFlag State) +{ + uint32_t tempreg; + uint32_t regaddr = REG_INTC_INTCSEL0; + + if(AfeIntcSel == AFEINTC_1) + regaddr = REG_INTC_INTCSEL1; + + tempreg = AD5940_ReadReg(regaddr); + if(State == bTRUE) + tempreg |= AFEIntSrc; /* Enable this interrupt */ + else + tempreg &= ~(AFEIntSrc); /* Disable this interrupt */ + AD5940_WriteReg(regaddr,tempreg); +} + +/** + * @brief Check if current interrupt configuration. + * @param AfeIntcSel : {AFEINTC_0, AFEINTC_1} + * - AFEINTC_0: Configure Interrupt Controller 0 + * - AFEINTC_1: Configure Interrupt Controller 1 +*/ +uint32_t AD5940_INTCGetCfg(uint32_t AfeIntcSel) +{ + uint32_t tempreg; + if(AfeIntcSel == AFEINTC_0) + tempreg = AD5940_ReadReg(REG_INTC_INTCSEL0); + else + tempreg = AD5940_ReadReg(REG_INTC_INTCSEL1); + return tempreg; +} + +/** + * @brief Clear selected interrupt(s) flag(INTC0Flag and INTC1Flag are both cleared). + * @param AfeIntSrcSel: Select from @ref AFEINTC_SRC_Const + * @return return none. +**/ +void AD5940_INTCClrFlag(uint32_t AfeIntSrcSel) +{ + AD5940_WriteReg(REG_INTC_INTCCLR,AfeIntSrcSel); +} + +/** + * @brief Test if selected interrupt source(s) is(are) bTRUE. + * @param AfeIntcSel : {AFEINTC_0, AFEINTC_1} + * - AFEINTC_0: Read Interrupt Controller 0 flag + * - AFEINTC_1: Read Interrupt Controller 1 flag + * @param AfeIntSrcSel: Select from @ref AFEINTC_SRC_Const + * @return If selected interrupt source(s) are all cleared, return bFALSE. Otherwise return bTRUE. +**/ +BoolFlag AD5940_INTCTestFlag(uint32_t AfeIntcSel, uint32_t AfeIntSrcSel) +{ + uint32_t tempreg; + uint32_t regaddr = (AfeIntcSel == AFEINTC_0)? REG_INTC_INTCFLAG0: REG_INTC_INTCFLAG1; + + tempreg = AD5940_ReadReg(regaddr); + if(tempreg & AfeIntSrcSel) + return bTRUE; + else + return bFALSE; +} + +/** + * @brief return register value of REG_INTC_INTCFLAGx + * @param AfeIntcSel : {AFEINTC_0, AFEINTC_1} + * - AFEINTC_0: Read Interrupt Controller 0 flag + * - AFEINTC_1: Read Interrupt Controller 1 flag + * @return register value of REG_INTC_INTCFLAGx. +**/ +uint32_t AD5940_INTCGetFlag(uint32_t AfeIntcSel) +{ + uint32_t tempreg; + uint32_t regaddr = (AfeIntcSel == AFEINTC_0)? REG_INTC_INTCFLAG0: REG_INTC_INTCFLAG1; + + tempreg = AD5940_ReadReg(regaddr); + return tempreg; +} + +/** + * @} Interrupt_Controller_Functions +*/ + +/** + * @defgroup GPIO_Block_Functions + * @{ +*/ + +/** + * @brief Initialize AFE GPIO + * @param pAgpioCfg: Pointer to configuration structure + * @return return none. +*/ +void AD5940_AGPIOCfg(AGPIOCfg_Type *pAgpioCfg) +{ + AD5940_AGPIOFuncCfg(pAgpioCfg->FuncSet); + AD5940_AGPIOOen(pAgpioCfg->OutputEnSet); + AD5940_AGPIOIen(pAgpioCfg->InputEnSet); + AD5940_AGPIOPen(pAgpioCfg->PullEnSet); + AD5940_WriteReg(REG_AGPIO_GP0OUT, pAgpioCfg->OutVal); +} + +/** + * @brief Configure the function of GP0 to GP7. + * @param uiCfgSet :{GP0_INT,GP0_TRIG,GP0_SYNC,GP0_GPIO| + * GP1_GPIO,GP1_TRIG,GP1_SYNC,GP1_SLEEP| + * GP2_PORB,GP2_TRIG,GP2_SYNC,GP2_EXTCLK| + * GP3_GPIO,GP3_TRIG,GP3_SYNC,GP3_INT0|\ + * GP4_GPIO,GP4_TRIG,GP4_SYNC,GP4_INT1| + * GP5_GPIO,GP5_TRIG,GP5_SYNC,GP5_EXTCLK| + * GP6_GPIO,GP6_TRIG,GP6_SYNC,GP6_INT0| + * GP7_GPIO,GP7_TRIG,GP7_SYNC,GP7_INT} + * @return return none. +**/ +void AD5940_AGPIOFuncCfg(uint32_t uiCfgSet) +{ + AD5940_WriteReg(REG_AGPIO_GP0CON,uiCfgSet); +} + +/** + * @brief Enable GPIO output mode on selected pins. Disable output on non-selected pins. + * @param uiPinSet :Select from {AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin2|AGPIO_Pin3|AGPIO_Pin4|AGPIO_Pin5|AGPIO_Pin6|AGPIO_Pin7} + * @return return none +**/ +void AD5940_AGPIOOen(uint32_t uiPinSet) +{ + AD5940_WriteReg(REG_AGPIO_GP0OEN,uiPinSet); +} + +/** + * @brief Enable input on selected pins while disable others. + * @param uiPinSet: Select from {AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin2|AGPIO_Pin3|AGPIO_Pin4|AGPIO_Pin5|AGPIO_Pin6|AGPIO_Pin7} + * @return return none +**/ +void AD5940_AGPIOIen(uint32_t uiPinSet) +{ + AD5940_WriteReg(REG_AGPIO_GP0IEN,uiPinSet); +} + +/** + * @brief Read the GPIO status. + * @return return GP0IN register which is the GPIO status. +**/ +uint32_t AD5940_AGPIOIn(void) +{ + return AD5940_ReadReg(REG_AGPIO_GP0IN); +} + +/** + * @brief Enable pull-up or down on selected pins while disable other pins. + * @param uiPinSet: Select from: {AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin2|AGPIO_Pin3|AGPIO_Pin4|AGPIO_Pin5|AGPIO_Pin6|AGPIO_Pin7} + * @return return none +**/ +void AD5940_AGPIOPen(uint32_t uiPinSet) +{ + AD5940_WriteReg(REG_AGPIO_GP0PE,uiPinSet); +} + +/** + * @brief Put selected GPIOs to high level. + * @param uiPinSet: Select from: {AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin2|AGPIO_Pin3|AGPIO_Pin4|AGPIO_Pin5|AGPIO_Pin6|AGPIO_Pin7} + * @return return none +**/ +void AD5940_AGPIOSet(uint32_t uiPinSet) +{ + AD5940_WriteReg(REG_AGPIO_GP0SET,uiPinSet); +} + +/** + * @brief Put selected GPIOs to low level. + * @param uiPinSet: Select from: {AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin2|AGPIO_Pin3|AGPIO_Pin4|AGPIO_Pin5|AGPIO_Pin6|AGPIO_Pin7} + * @return return none +**/ +void AD5940_AGPIOClr(uint32_t uiPinSet) +{ + AD5940_WriteReg(REG_AGPIO_GP0CLR,uiPinSet); +} + +/** + * @brief Toggle selected GPIOs. + * @param uiPinSet: Select from: {AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin2|AGPIO_Pin3|AGPIO_Pin4|AGPIO_Pin5|AGPIO_Pin6|AGPIO_Pin7} + * @return return none +**/ +void AD5940_AGPIOToggle(uint32_t uiPinSet) +{ + AD5940_WriteReg(REG_AGPIO_GP0TGL,uiPinSet); +} + +/** + * @} GPIO_Block_Functions +*/ + +/** + * @defgroup LPMode_Block_Functions + * @{ +*/ +/** + * @brief Enter or leave LPMODE. + * @details Once enter this mode, some registers are collected together to a new register so we can + * Control most blocks with in one register. The so called LPMODE has nothing to do with AD5940 power. + * @return return AD5940ERR_OK +**/ +AD5940Err AD5940_LPModeEnS(BoolFlag LPModeEn) +{ + if(LPModeEn == bTRUE) + AD5940_WriteReg(REG_AFE_LPMODEKEY, KEY_LPMODEKEY); /* Enter LP mode by right key. */ + else + AD5940_WriteReg(REG_AFE_LPMODEKEY, 0); /* Write wrong key to exit LP mode */ + return AD5940ERR_OK; +} + +/** + * @brief Select system clock source for LPMODE. + * @note Only in LP Mode, this operation takes effect. Enter LPMODE by function @ref AD5940_LPModeEnS. + * @param LPModeClk: Select from @ref LPMODECLK_Const + * - LPMODECLK_LFOSC: Select LFOSC 32kHz for system clock + * - LPMODECLK_HFOSC: Select HFOSC 16MHz/32MHz for system clock + * @return none. +*/ +void AD5940_LPModeClkS(uint32_t LPModeClk) +{ + AD5940_WriteReg(REG_AFE_LPMODECLKSEL, LPModeClk); +} + +/** + * @} LPMode_Block_Functions +*/ + +/** + * @brief Enter sleep mode key to unlock it or enter incorrect key to lock it. \ + * Once key is unlocked, it will always be effect until manually lock it + * @param SlpKey : {SLPKEY_UNLOCK, SLPKEY_LOCK} + - SLPKEY_UNLOCK Unlock Key so we can enter sleep(or called hibernate) mode. + - SLPKEY_LOCK Lock key so AD5940 is prohibited to enter sleep mode. + @return return none. +*/ +void AD5940_SleepKeyCtrlS(uint32_t SlpKey) +{ + AD5940_WriteReg(REG_AFE_SEQSLPLOCK, SlpKey); +} + +/** + * @brief Put AFE to hibernate. + * @details This will only take effect when SLP_KEY has been unlocked. Use function @ref AD5940_SleepKeyCtrlS to enter correct key. + * @return return none. +*/ +void AD5940_EnterSleepS(void) +{ + AD5940_WriteReg(REG_AFE_SEQTRGSLP, 0); + AD5940_WriteReg(REG_AFE_SEQTRGSLP, 1); +} + +/** + * @brief Turn off LP-Loop and put AFE to hibernate mode; + * @details By function @ref AD5940_EnterSleepS, we can put most blocks to hibernate mode except LP block. + * This function will shut down LP block and then enter sleep mode. + * @return return none. +*/ +void AD5940_ShutDownS(void) +{ + /* Turn off LPloop related blocks which are not controlled automatically by hibernate operation */ + AFERefCfg_Type aferef_cfg; + LPLoopCfg_Type lp_loop; + /* Turn off LP-loop manually because it's not affected by sleep/hibernate mode */ + AD5940_StructInit(&aferef_cfg, sizeof(aferef_cfg)); + AD5940_StructInit(&lp_loop, sizeof(lp_loop)); + AD5940_REFCfgS(&aferef_cfg); + AD5940_LPLoopCfgS(&lp_loop); + AD5940_SleepKeyCtrlS(SLPKEY_UNLOCK); /* Unlock the key */ + AD5940_EnterSleepS(); /* Enter Hibernate */ +} + +/** + * @brief Try to wakeup AD5940 by read register. + * @details Any SPI operation can wakeup AD5940. AD5940_Initialize must be called to enable this function. + * @param TryCount Specify how many times we will read register. Zero or negative number means always waiting here. + * @return How many times register is read. If returned value is bigger than TryCount, it means wakeup failed. +*/ +uint32_t AD5940_WakeUp(int32_t TryCount) +{ + uint32_t count = 0; + while(1) + { + count++; + if(AD5940_ReadReg(REG_AFECON_ADIID) == AD5940_ADIID) + break; /* Succeed */ + if(TryCount<=0) + continue; /* Always try to wakeup AFE */ + + if(count > TryCount) + break; /* Failed */ + } + return count; +} + +/** + * @brief Read ADIID register, the value for current version is @ref AD5940_ADIID + * @return return none. +*/ +uint32_t AD5940_GetADIID(void) +{ + return AD5940_ReadReg(REG_AFECON_ADIID); +} + +/** + * @brief Read CHIPID register, the value for current version is 0x5501. + * @return return none. +*/ +uint32_t AD5940_GetChipID(void) +{ + return AD5940_ReadReg(REG_AFECON_CHIPID); +} +/** + * @brief Reset AD5940 by register. + * @note AD5940 must be in active state so we can access registers. + * If AD5940 system clock is too low, we consider to use hardware reset, or + * we need to make sure register write is successfully. + * @return return none. +*/ +AD5940Err AD5940_SoftRst(void) +{ + AD5940_WriteReg(REG_AFECON_SWRSTCON, AD5940_SWRST); + AD5940_Delay10us(20); /* AD5940 need some time to exit reset status. 200us looks good. */ + /* We can check RSTSTA register to make sure software reset happened. */ + return AD5940ERR_OK; +} + +/** + * @brief Reset AD5940 with RESET pin. + * @note This will call function AD5940_RstClr which locates in file XXXPort.C + * @return return none. +*/ +void AD5940_HWReset(void) +{ +#ifndef CHIPSEL_M355 + AD5940_RstClr(); + AD5940_Delay10us(200); /* Delay some time */ + AD5940_RstSet(); + AD5940_Delay10us(500); /* AD5940 need some time to exit reset status. 200us looks good. */ +#else + //There is no method to reset AFE only for M355. +#endif +} + +/** + * @} MISC_Block_Functions + * @} MISC_Block +*/ + +/** + * @defgroup Calibration_Block + * @brief The non-factory calibration routines. + * @{ + * @defgroup Calibration_Functions + * @{ + * + * + */ +/** + * @brief Turn on High power 1.8V/1.1V reference and 2.5V LP reference. + * @return return none. +*/ +static void __AD5940_ReferenceON(void) +{ + AFERefCfg_Type ref_cfg; + /* Turn ON ADC/DAC and LPDAC reference */ + ref_cfg.Hp1V1BuffEn = bTRUE; + ref_cfg.Hp1V8BuffEn = bTRUE; + ref_cfg.HpBandgapEn = bTRUE; + ref_cfg.HSDACRefEn = bTRUE; + ref_cfg.LpBandgapEn = bTRUE; + ref_cfg.LpRefBufEn = bTRUE; + + ref_cfg.Disc1V1Cap = bFALSE; + ref_cfg.Disc1V8Cap = bFALSE; + ref_cfg.Hp1V8Ilimit = bFALSE; + ref_cfg.Hp1V8ThemBuff = bFALSE; + ref_cfg.Lp1V1BuffEn = bFALSE; + ref_cfg.Lp1V8BuffEn = bFALSE; + ref_cfg.LpRefBoostEn = bFALSE; + AD5940_REFCfgS(&ref_cfg); +} + +/** + * @brief Turn on ADC to sample one SINC2 data. + * @return return ADCCode. +*/ +static uint32_t __AD5940_TakeMeasurement(int32_t *time_out) +{ + uint32_t ADCCode = 0; + AD5940_INTCClrFlag(AFEINTSRC_SINC2RDY); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_SINC2NOTCH, bTRUE);/* Start conversion */ + do + { + AD5940_Delay10us(1); /* Delay 10us */ + if(AD5940_INTCTestFlag(AFEINTC_1,AFEINTSRC_SINC2RDY)) + { + ADCCode = AD5940_ReadAfeResult(AFERESULT_SINC2); + break; + } + if(*time_out != -1) + (*time_out)--; + }while(*time_out != 0); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_SINC2NOTCH, bFALSE);/* Stop conversion */ + return ADCCode; +} + +/** + @brief Calibrate ADC PGA + @param pADCPGACal: PGA calibration parameters include filter setup and PGA gain. + @return AD5940ERR_OK. +**/ +AD5940Err AD5940_ADCPGACal(ADCPGACal_Type *pADCPGACal) +{ + const float kFactor = 1.835f/1.82f; + ADCBaseCfg_Type adc_base; + + int32_t time_out; + uint32_t INTCCfg; + int32_t ADCCode; + BoolFlag bADCClk32MHzMode; + + uint32_t regaddr_gain, regaddr_offset; + + if(pADCPGACal == NULL) return AD5940ERR_NULLP; + if(pADCPGACal->ADCPga > ADCPGA_9) return AD5940ERR_PARA; /* Parameter Error */ + + if(pADCPGACal->AdcClkFreq > (32000000*0.8)) + bADCClk32MHzMode = bTRUE; + + /** + * Determine Gain calibration method according to different gain value... + * and calibration register + * */ + static const struct _cal_registers + { + uint16_t gain_reg; + uint16_t offset_reg; + }cal_registers[] = { + {REG_AFE_ADCGAINGN1,REG_AFE_ADCOFFSETGN1}, + {REG_AFE_ADCGAINGN1P5,REG_AFE_ADCOFFSETGN1P5}, + {REG_AFE_ADCGAINGN2,REG_AFE_ADCOFFSETGN2}, + {REG_AFE_ADCGAINGN4,REG_AFE_ADCOFFSETGN4}, + {REG_AFE_ADCGAINGN9,REG_AFE_ADCOFFSETGN9}, + }; + regaddr_gain = cal_registers[pADCPGACal->ADCPga].gain_reg; + regaddr_offset = cal_registers[pADCPGACal->ADCPga].offset_reg; + + /* Do initialization */ + __AD5940_ReferenceON(); + ADCFilterCfg_Type adc_filter; + /* Initialize ADC filters ADCRawData-->SINC3-->SINC2+NOTCH. Use SIN2 data for calibration-->Lower noise */ + adc_filter.ADCSinc3Osr = pADCPGACal->ADCSinc3Osr; + adc_filter.ADCSinc2Osr = pADCPGACal->ADCSinc2Osr; /* 800KSPS/4/1333 = 150SPS */ + adc_filter.ADCAvgNum = ADCAVGNUM_2; /* Don't care about it. Average function is only used for DFT */ + adc_filter.ADCRate = bADCClk32MHzMode?ADCRATE_1P6MHZ:ADCRATE_800KHZ; /* If ADC clock is 32MHz, then set it to ADCRATE_1P6MHZ. Default is 16MHz, use ADCRATE_800KHZ. */ + adc_filter.BpNotch = bTRUE; /* SINC2+Notch is one block, when bypass notch filter, we can get fresh data from SINC2 filter. */ + adc_filter.BpSinc3 = bFALSE; /* We use SINC3 filter. */ + adc_filter.Sinc2NotchEnable = bTRUE; /* Enable the SINC2+Notch block. You can also use function AD5940_AFECtrlS */ + AD5940_ADCFilterCfgS(&adc_filter); + /* Turn ON reference and ADC power, and DAC reference. We use DAC 1.8V reference to calibrate ADC because of the ADC reference bug. */ + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Disable all */ + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_HPREFPWR|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|AFECTRL_SINC2NOTCH, bTRUE); + AD5940_Delay10us(25); /* Wait 250us for reference power up */ + /* INTC configure and open calibration lock */ + INTCCfg = AD5940_INTCGetCfg(AFEINTC_1); + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bTRUE); /* Enable SINC2 Interrupt in INTC1 */ + AD5940_WriteReg(REG_AFE_CALDATLOCK, KEY_CALDATLOCK); /* Unlock KEY */ + + /* Do offset calibration. */ + if(pADCPGACal->PGACalType != PGACALTYPE_GAIN){ /* Need offset calibration */ + int32_t ExpectedCode = 0x8000; /* Ideal ADC output */ + AD5940_WriteReg(regaddr_offset, 0); /* Reset offset register */ + + adc_base.ADCMuxP = ADCMUXP_VSET1P1; + adc_base.ADCMuxN = ADCMUXN_VSET1P1; /* Short input with common voltage set to 1.11v */ + adc_base.ADCPga = pADCPGACal->ADCPga; /* Set correct Gain value. */ + AD5940_ADCBaseCfgS(&adc_base); + AD5940_Delay10us(5); /* Wait for sometime */ + ADCCode = 0; + for(int i=0; i<8; i++) + { /* ADC offset calibration register has resolution of 0.25LSB. take full use of it. */ + time_out = pADCPGACal->TimeOut10us; /* Reset time out counter */ + ADCCode += __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + if(time_out == 0) goto ADCPGACALERROR_TIMEOUT; /* Time out error. */ + } + /* Calculate and write the result to registers before gain calibration */ + ADCCode = (ExpectedCode<<3) - ADCCode; /* We will shift back 1bit below */ + /** + * AD5940 use formular Output = gain*(input + offset) for calibration. + * So, the measured results should be divided by gain to get value for offset register. + */ + uint32_t gain = AD5940_ReadReg(regaddr_gain); + ADCCode = (ADCCode*0x4000)/gain; + ADCCode = ((ADCCode+1)>>1)&0x7fff; /* Round 0.5 */ + AD5940_WriteReg(regaddr_offset, ADCCode); + } + + /* Do gain calibration */ + if(pADCPGACal->PGACalType != PGACALTYPE_OFFSET) /* Need gain calibration */ + { + int32_t ExpectedGainCode; + static const float ideal_pga_gain[]={1,1.5,2,4,9}; + AD5940_WriteReg(regaddr_gain, 0x4000); /* Reset gain register */ + if(pADCPGACal->ADCPga <= ADCPGA_2) + { + //gain1,1.5,2 could use reference directly + adc_base.ADCMuxP = ADCMUXP_VREF1P8DAC; + adc_base.ADCMuxN = ADCMUXN_VSET1P1; + ExpectedGainCode = (int32_t)((pADCPGACal->VRef1p82 - pADCPGACal->VRef1p11)*ideal_pga_gain[pADCPGACal->ADCPga]/\ + pADCPGACal->VRef1p82*32768/kFactor)\ + + 0x8000; + } + else + { + //gain4,9 use DAC generated voltage + adc_base.ADCMuxP = ADCMUXP_P_NODE; + adc_base.ADCMuxN = ADCMUXN_N_NODE; + /* Setup HSLOOP to generate voltage for GAIN4/9 calibration. */ + AD5940_AFECtrlS(AFECTRL_EXTBUFPWR|AFECTRL_INAMPPWR|AFECTRL_HSTIAPWR|AFECTRL_WG, bTRUE); + HSLoopCfg_Type hsloop_cfg; + hsloop_cfg.HsDacCfg.ExcitBufGain = EXCITBUFGAIN_2; + hsloop_cfg.HsDacCfg.HsDacGain = HSDACGAIN_1; + hsloop_cfg.HsDacCfg.HsDacUpdateRate = 7; + hsloop_cfg.HsTiaCfg.DiodeClose = bFALSE; + hsloop_cfg.HsTiaCfg.HstiaBias = HSTIABIAS_1P1; + hsloop_cfg.HsTiaCfg.HstiaCtia = 31; + hsloop_cfg.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_OPEN; + hsloop_cfg.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_OPEN; + hsloop_cfg.HsTiaCfg.HstiaDe1Rload = HSTIADERLOAD_OPEN; + hsloop_cfg.HsTiaCfg.HstiaDe1Rtia = HSTIADERTIA_OPEN; + hsloop_cfg.HsTiaCfg.HstiaRtiaSel = HSTIARTIA_200; + hsloop_cfg.SWMatCfg.Dswitch = SWD_OPEN; + hsloop_cfg.SWMatCfg.Pswitch = SWP_PL; + hsloop_cfg.SWMatCfg.Nswitch = SWN_NL; + hsloop_cfg.SWMatCfg.Tswitch = SWT_TRTIA; + hsloop_cfg.WgCfg.GainCalEn = bTRUE; + hsloop_cfg.WgCfg.OffsetCalEn = bTRUE; + hsloop_cfg.WgCfg.WgType = WGTYPE_MMR; + uint32_t HSDACCode; + if(pADCPGACal->ADCPga == ADCPGA_4) + HSDACCode = 0x800 + 0x300; /* 0x300--> 0x300/0x1000*0.8*BUFFERGAIN2 = 0.3V. */ + else if(pADCPGACal->ADCPga == ADCPGA_9) + HSDACCode = 0x800 + 0x155; /* 0x155--> 0x155/0x1000*0.8*BUFFERGAIN2 = 0.133V. */ + hsloop_cfg.WgCfg.WgCode = HSDACCode; + AD5940_HSLoopCfgS(&hsloop_cfg); + + //measure expected code + adc_base.ADCPga = ADCPGA_1P5; + AD5940_ADCBaseCfgS(&adc_base); + AD5940_Delay10us(5); + time_out = pADCPGACal->TimeOut10us; /* Reset time out counter */ + ExpectedGainCode = 0x8000 + (int32_t)((__AD5940_TakeMeasurement(&time_out) - 0x8000)/1.5f\ + *ideal_pga_gain[pADCPGACal->ADCPga]); + if(time_out == 0) goto ADCPGACALERROR_TIMEOUT; + } + adc_base.ADCPga = pADCPGACal->ADCPga; /* Set to gain under calibration */ + AD5940_ADCBaseCfgS(&adc_base); + AD5940_Delay10us(5); + time_out = pADCPGACal->TimeOut10us; /* Reset time out counter */ + ADCCode = __AD5940_TakeMeasurement(&time_out); + if(time_out == 0) goto ADCPGACALERROR_TIMEOUT; + /* Calculate and write the result to registers */ + ADCCode = (ExpectedGainCode - 0x8000)*0x4000/(ADCCode-0x8000); + ADCCode &= 0x7fff; + AD5940_WriteReg(regaddr_gain, ADCCode); + } + + /* Restore INTC1 SINC2 configure */ + if(INTCCfg&AFEINTSRC_SINC2RDY); + else + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bFALSE); /* Disable SINC2 Interrupt */ + + AD5940_WriteReg(REG_AFE_CALDATLOCK, 0); /* Lock KEY */ + /* Done */ + return AD5940ERR_OK; + +ADCPGACALERROR_TIMEOUT: + AD5940_ADCConvtCtrlS(bFALSE); /* Stop conversion */ + AD5940_WriteReg(REG_AFE_CALDATLOCK, 0); /* Lock KEY */ + return AD5940ERR_TIMEOUT; +} + +/** + * @brief Calibrate LPTIA offset + * @param pLPTIAOffsetCal Pointer to LPTIA offset calibration settings. + * @return AD5940ERR_OK. +**/ +AD5940Err AD5940_LPTIAOffsetCal(LPTIAOffsetCal_Type *pLPTIAOffsetCal) +{ + AD5940Err error = AD5940ERR_OK; + LPLoopCfg_Type lploop_cfg; + ADCBaseCfg_Type adc_base; + ADCFilterCfg_Type adc_filter; + + int32_t time_out; + uint32_t INTCCfg; + int32_t ADCCode; + BoolFlag bADCClk32MHzMode; + + if(pLPTIAOffsetCal == NULL) return AD5940ERR_NULLP; + if(pLPTIAOffsetCal->AdcClkFreq > (32000000*0.8)) + bADCClk32MHzMode = bTRUE; + + /* Step0: Do initialization */ + /* Turn on AD5940 references in case it's disabled. */ + __AD5940_ReferenceON(); + lploop_cfg.LpAmpCfg.LpAmpSel = pLPTIAOffsetCal->LpAmpSel; + lploop_cfg.LpAmpCfg.LpAmpPwrMod = pLPTIAOffsetCal->LpAmpPwrMod; /* Power mode will affect amp offset. */ + lploop_cfg.LpAmpCfg.LpPaPwrEn = bTRUE; + lploop_cfg.LpAmpCfg.LpTiaPwrEn = bTRUE; + lploop_cfg.LpAmpCfg.LpTiaRf = LPTIARF_OPEN; + lploop_cfg.LpAmpCfg.LpTiaRload = LPTIARLOAD_100R; + lploop_cfg.LpAmpCfg.LpTiaRtia = pLPTIAOffsetCal->LpTiaRtia; + lploop_cfg.LpAmpCfg.LpTiaSW = pLPTIAOffsetCal->LpTiaSW; /* Disconnect capacitors so it settles quickly */ + lploop_cfg.LpDacCfg.LpdacSel = (pLPTIAOffsetCal->LpAmpSel == LPAMP0)?LPDAC0:LPDAC1; + lploop_cfg.LpDacCfg.DacData12Bit = pLPTIAOffsetCal->DacData12Bit; + lploop_cfg.LpDacCfg.DacData6Bit = pLPTIAOffsetCal->DacData6Bit; + lploop_cfg.LpDacCfg.DataRst = bFALSE; + lploop_cfg.LpDacCfg.LpDacRef = LPDACREF_2P5; + lploop_cfg.LpDacCfg.LpDacSrc = LPDACSRC_MMR; + lploop_cfg.LpDacCfg.LpDacVzeroMux = pLPTIAOffsetCal->LpDacVzeroMux; + lploop_cfg.LpDacCfg.LpDacSW = LPDACSW_VZERO2LPTIA; + lploop_cfg.LpDacCfg.LpDacVbiasMux = LPDACVBIAS_12BIT; + lploop_cfg.LpDacCfg.PowerEn = bTRUE; + AD5940_LPLoopCfgS(&lploop_cfg); + + /* Initialize ADC filters ADCRawData-->SINC3-->SINC2+NOTCH. Use SIN2 data for calibration-->Lower noise */ + adc_filter.ADCSinc3Osr = pLPTIAOffsetCal->ADCSinc3Osr; + adc_filter.ADCSinc2Osr = pLPTIAOffsetCal->ADCSinc2Osr; /* 800KSPS/4/1333 = 150SPS */ + adc_filter.ADCAvgNum = ADCAVGNUM_2; /* Don't care about it. Average function is only used for DFT */ + adc_filter.ADCRate = bADCClk32MHzMode?ADCRATE_1P6MHZ:ADCRATE_800KHZ; /* If ADC clock is 32MHz, then set it to ADCRATE_1P6MHZ. Default is 16MHz, use ADCRATE_800KHZ. */ + adc_filter.BpNotch = bTRUE; /* SINC2+Notch is one block, when bypass notch filter, we can get fresh data from SINC2 filter. */ + adc_filter.BpSinc3 = bFALSE; /* We use SINC3 filter. */ + adc_filter.Sinc2NotchEnable = bTRUE; /* Enable the SINC2+Notch block. You can also use function AD5940_AFECtrlS */ + AD5940_ADCFilterCfgS(&adc_filter); + /* Initialize ADC MUx and PGA */ + if(pLPTIAOffsetCal->LpAmpSel == LPAMP0) + { + adc_base.ADCMuxP = ADCMUXP_LPTIA0_P; + adc_base.ADCMuxN = ADCMUXN_LPTIA0_N; + } + else + { + adc_base.ADCMuxP = ADCMUXP_LPTIA1_P; + adc_base.ADCMuxN = ADCMUXN_LPTIA1_N; + } + adc_base.ADCPga = pLPTIAOffsetCal->ADCPga; /* Set correct Gain value. */ + AD5940_ADCBaseCfgS(&adc_base); + /* Turn ON ADC and its reference. And SINC2. */ + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Disable all firstly, we only enable things we use */ + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_HPREFPWR|AFECTRL_SINC2NOTCH, bTRUE); + AD5940_Delay10us(25); /* Wait 250us for reference power up */ + /* INTC configure and open calibration lock */ + INTCCfg = AD5940_INTCGetCfg(AFEINTC_1); + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bTRUE); /* Enable SINC2 Interrupt in INTC1 */ + AD5940_WriteReg(REG_AFE_CALDATLOCK, KEY_CALDATLOCK); /* Unlock KEY */ + + /* Do offset calibration. */ + { + int32_t ExpectedCode = 0x8000; /* Ideal ADC output */ + AD5940_WriteReg(REG_AFE_ADCOFFSETLPTIA0, 0); /* Reset offset register */ + + if(pLPTIAOffsetCal->SettleTime10us > 0) + AD5940_Delay10us(pLPTIAOffsetCal->SettleTime10us); /* Delay 10us */ + time_out = pLPTIAOffsetCal->TimeOut10us; /* Reset time out counter */ + ADCCode = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + if(time_out == 0) + { + error = AD5940ERR_TIMEOUT; + goto LPTIAOFFSETCALERROR; + } /* Time out error. */ + /* Calculate and write the result to registers before gain calibration */ + ADCCode = ((ExpectedCode - ADCCode)<<3); /* We will shift back 1bit below */ + ADCCode = ((ADCCode+1)>>1); /* Round 0.5 */ + if((ADCCode > 0x3fff) || + (ADCCode < -0x4000)) /* The register used for offset calibration is limited to -0x4000 to 0x3fff */ + { + error = AD5940ERR_CALOR; + goto LPTIAOFFSETCALERROR; + } + ADCCode &= 0x7fff; + if(pLPTIAOffsetCal->LpAmpSel == LPAMP0) + AD5940_WriteReg(REG_AFE_ADCOFFSETLPTIA0, ADCCode); + else + AD5940_WriteReg(REG_AFE_ADCOFFSETLPTIA1, ADCCode); + } + /* Restore INTC1 SINC2 configure */ + if(INTCCfg&AFEINTSRC_SINC2RDY); + else + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bFALSE); /* Disable SINC2 Interrupt */ + + AD5940_WriteReg(REG_AFE_CALDATLOCK, 0); /* Lock KEY */ + /* Done */ + return AD5940ERR_OK; + +LPTIAOFFSETCALERROR: + AD5940_ADCConvtCtrlS(bFALSE); /* Stop conversion */ + AD5940_WriteReg(REG_AFE_CALDATLOCK, 0); /* Lock KEY */ + return error; +} + +/** + * @brief Calibrate HSTIA offset-ongoing. + * @param pHSTIAOffsetCal: pointer to configuration. + * @return AD5940ERR_OK. +**/ +AD5940Err AD5940_HSTIAOffsetCal(LPTIAOffsetCal_Type *pHSTIAOffsetCal) +{ + return AD5940ERR_OK; +} + +/** + * @brief Measure HSTIA internal RTIA impedance. + * @param pCalCfg: pointer to calibration structure. + * @param pResult: Pointer to a variable that used to store result. + * If bPolarResult in structure is set, then use type fImpPol_Type otherwise use fImpCar_Type. + * @return AD5940ERR_OK if succeed. +**/ +AD5940Err AD5940_HSRtiaCal(HSRTIACal_Type *pCalCfg, void *pResult) +{ + /***** CALIBRATION METHOD ****** + 1) Measure the complex voltage V_Rcal across the calibration DUT (Rcal). + 2) Measure the complex voltage V_Rtia across Rtia [HSTIA_P (output) - HSTIA_N]. + 3) Note Rtia carries the same current as Rcal; I_Rtia = I_exc = I_Rcal + 4) Implement the equation: Rtia = V_Rtia / I_Rtia + --> Rtia = (V_Rtia / V_Rcal) * Rcal + *******************************/ + + AFERefCfg_Type aferef_cfg; + HSLoopCfg_Type hs_loop; + DSPCfg_Type dsp_cfg; + uint32_t INTCCfg; + + BoolFlag bADCClk32MHzMode = bFALSE; + uint32_t ExcitBuffGain = EXCITBUFGAIN_2; + uint32_t HsDacGain = HSDACGAIN_1; + + float ExcitVolt; /* Excitation voltage, unit is mV */ + uint32_t RtiaVal; + uint32_t const HpRtiaTable[]={200,1000,5000,10000,20000,40000,80000,160000,0}; + uint32_t const HSTIADERLOADTable[]={0,10,30,50,100,999999999999}; + uint32_t const HSTIADERTIATable[] = {50,100,200,1000,5000,10000,20000,40000,80000,160000,0,999999999999999}; + uint32_t WgAmpWord; + + iImpCar_Type DftRcalVolt, DftRtiaVolt; + + if(pCalCfg == NULL) return AD5940ERR_NULLP; + if(pCalCfg->fRcal == 0) + return AD5940ERR_PARA; + //if(pCalCfg->HsTiaCfg.HstiaRtiaSel > HSTIARTIA_160K) + // return AD5940ERR_PARA; + //if(pCalCfg->HsTiaCfg.HstiaRtiaSel == HSTIARTIA_OPEN) + // return AD5940ERR_PARA; /* Do not support calibrating DE0-RTIA */ + if(pResult == NULL) + return AD5940ERR_NULLP; + + if(pCalCfg->AdcClkFreq > (32000000*0.8)) + bADCClk32MHzMode = bTRUE; + + /* Calculate the excitation voltage we should use based on RCAL/Rtia */ + if(pCalCfg->HsTiaCfg.HstiaRtiaSel == HSTIARTIA_OPEN) + { + if(pCalCfg->HsTiaCfg.HstiaDeRtia == HSTIADERTIA_TODE) + { + RtiaVal = pCalCfg->HsTiaCfg.ExtRtia; + } + else + { + RtiaVal = pCalCfg->HsTiaCfg.ExtRtia + HSTIADERLOADTable[pCalCfg->HsTiaCfg.HstiaDeRload] + HSTIADERTIATable[pCalCfg->HsTiaCfg.HstiaDeRtia]; + } + } + else + RtiaVal = HpRtiaTable[pCalCfg->HsTiaCfg.HstiaRtiaSel]; + /* + DAC output voltage calculation + Note: RCAL value should be similar to RTIA so the accuracy is best. + HSTIA output voltage should be limited to 0.2V to AVDD-0.2V, with 1.1V bias. We use 80% of this range for safe. + Because the bias voltage is fixed to 1.1V, so for AC signal maximum amplitude is 1.1V-0.2V = 0.9Vp. That's 1.8Vpp. + Formula is: ExcitVolt(in mVpp) = (1800mVpp*80% / RTIA) * RCAL + ADC input range is +-1.5V which is enough for calibration. + + */ + ExcitVolt = 1800*0.8*pCalCfg->fRcal/RtiaVal; + + if(ExcitVolt <= 800*0.05) /* Voltage is so small that we can enable the attenuator of DAC(1/5) and Excitation buffer(1/4). 800mVpp is the DAC output voltage */ + { + ExcitBuffGain = EXCITBUFGAIN_0P25; + HsDacGain = HSDACGAIN_0P2; + /* Excitation buffer voltage full range is 800mVpp*0.05 = 40mVpp */ + WgAmpWord = ((uint32_t)(ExcitVolt/40*2047*2)+1)>>1; /* Assign value with rounding (0.5 LSB error) */ + } + else if(ExcitVolt <= 800*0.25) /* Enable Excitation buffer attenuator */ + { + ExcitBuffGain = EXCITBUFGAIN_0P25; + HsDacGain = HSDACGAIN_1; + /* Excitation buffer voltage full range is 800mVpp*0.25 = 200mVpp */ + WgAmpWord = ((uint32_t)(ExcitVolt/200*2047*2)+1)>>1; /* Assign value with rounding (0.5 LSB error) */ + } + else if(ExcitVolt <= 800*0.4) /* Enable DAC attenuator */ + { + ExcitBuffGain = EXCITBUFGAIN_2; + HsDacGain = HSDACGAIN_0P2; + /* Excitation buffer voltage full range is 800mVpp*0.4 = 320mV */ + WgAmpWord = ((uint32_t)(ExcitVolt/320*2047*2)+1)>>1; /* Assign value with rounding (0.5 LSB error) */ + } + else /* No attenuator is needed. This is the best condition which means RTIA is close to RCAL */ + { + ExcitBuffGain = EXCITBUFGAIN_2; + HsDacGain = HSDACGAIN_1; + /* Excitation buffer voltage full range is 800mVpp*2=1600mVpp */ + WgAmpWord = ((uint32_t)(ExcitVolt/1600*2047*2)+1)>>1; /* Assign value with rounding (0.5 LSB error) */ + } + + if(WgAmpWord > 0x7ff) + WgAmpWord = 0x7ff; + + /*INTC configuration */ + INTCCfg = AD5940_INTCGetCfg(AFEINTC_1); + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_DFTRDY, bTRUE); /* Enable SINC2 Interrupt in INTC1 */ + + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Init all to disable state */ + /* Configure reference system */ + aferef_cfg.HpBandgapEn = bTRUE; + aferef_cfg.Hp1V1BuffEn = bTRUE; + aferef_cfg.Hp1V8BuffEn = bTRUE; + aferef_cfg.Disc1V1Cap = bFALSE; + aferef_cfg.Disc1V8Cap = bFALSE; + aferef_cfg.Hp1V8ThemBuff = bFALSE; + aferef_cfg.Hp1V8Ilimit = bFALSE; + aferef_cfg.Lp1V1BuffEn = bFALSE; + aferef_cfg.Lp1V8BuffEn = bFALSE; + aferef_cfg.LpBandgapEn = bFALSE; + aferef_cfg.LpRefBufEn = bFALSE; + aferef_cfg.LpRefBoostEn = bFALSE; + AD5940_REFCfgS(&aferef_cfg); + /* Configure HP Loop */ + hs_loop.HsDacCfg.ExcitBufGain = ExcitBuffGain; + hs_loop.HsDacCfg.HsDacGain = HsDacGain; + hs_loop.HsDacCfg.HsDacUpdateRate = 7; /* Set it to highest update rate */ + memcpy(&hs_loop.HsTiaCfg, &pCalCfg->HsTiaCfg, sizeof(pCalCfg->HsTiaCfg)); + hs_loop.SWMatCfg.Dswitch = SWD_RCAL0; + hs_loop.SWMatCfg.Pswitch = SWP_RCAL0; + hs_loop.SWMatCfg.Nswitch = SWN_RCAL1; + hs_loop.SWMatCfg.Tswitch = SWT_RCAL1|SWT_TRTIA|SWT_AIN1; + hs_loop.WgCfg.WgType = WGTYPE_SIN; + hs_loop.WgCfg.GainCalEn = bTRUE; + hs_loop.WgCfg.OffsetCalEn = bTRUE; + hs_loop.WgCfg.SinCfg.SinFreqWord = AD5940_WGFreqWordCal(pCalCfg->fFreq, pCalCfg->SysClkFreq); + hs_loop.WgCfg.SinCfg.SinAmplitudeWord = WgAmpWord; + hs_loop.WgCfg.SinCfg.SinOffsetWord = 0; + hs_loop.WgCfg.SinCfg.SinPhaseWord = 0; + AD5940_HSLoopCfgS(&hs_loop); + /* Configure DSP */ + dsp_cfg.ADCBaseCfg.ADCMuxN = ADCMUXN_N_NODE; + dsp_cfg.ADCBaseCfg.ADCMuxP = ADCMUXP_P_NODE; + dsp_cfg.ADCBaseCfg.ADCPga = ADCPGA_1P5; + AD5940_StructInit(&dsp_cfg.ADCDigCompCfg, sizeof(dsp_cfg.ADCDigCompCfg)); + dsp_cfg.ADCFilterCfg.ADCAvgNum = ADCAVGNUM_16; /* Don't care because it's disabled */ + dsp_cfg.ADCFilterCfg.ADCRate = bADCClk32MHzMode?ADCRATE_1P6MHZ:ADCRATE_800KHZ; + dsp_cfg.ADCFilterCfg.ADCSinc2Osr = pCalCfg->ADCSinc2Osr; + dsp_cfg.ADCFilterCfg.ADCSinc3Osr = pCalCfg->ADCSinc3Osr; + dsp_cfg.ADCFilterCfg.BpNotch = bTRUE; + dsp_cfg.ADCFilterCfg.BpSinc3 = bFALSE; + dsp_cfg.ADCFilterCfg.Sinc2NotchEnable = bTRUE; + + memcpy(&dsp_cfg.DftCfg, &pCalCfg->DftCfg, sizeof(pCalCfg->DftCfg)); + memset(&dsp_cfg.StatCfg, 0, sizeof(dsp_cfg.StatCfg)); + AD5940_DSPCfgS(&dsp_cfg); + + /* Enable all of them. They are automatically turned off during hibernate mode to save power */ + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\ + /*AFECTRL_WG|*/AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|\ + AFECTRL_SINC2NOTCH, bTRUE); + + /***** MEASURE VOLTAGE ACROSS RCAL *****/ + AD5940_AFECtrlS(AFECTRL_WG|AFECTRL_ADCPWR, bTRUE); /* Enable Waveform generator, ADC power */ + //wait for sometime. + AD5940_Delay10us(25); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT, bTRUE); /* Start ADC convert and DFT */ + /* Wait until DFT ready */ + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_DFTRDY) == bFALSE); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT|AFECTRL_WG|AFECTRL_ADCPWR, bFALSE); /* Stop ADC convert and DFT */ + AD5940_INTCClrFlag(AFEINTSRC_DFTRDY); + + DftRcalVolt.Real = AD5940_ReadAfeResult(AFERESULT_DFTREAL); + DftRcalVolt.Image = AD5940_ReadAfeResult(AFERESULT_DFTIMAGE); + + /***** MEASURE VOLTAGE ACROSS RTIA *****/ + AD5940_ADCMuxCfgS(ADCMUXP_HSTIA_P, ADCMUXN_HSTIA_N); + AD5940_AFECtrlS(AFECTRL_WG|AFECTRL_ADCPWR, bTRUE); /* Enable Waveform generator, ADC power */ + //wait for sometime. + AD5940_Delay10us(25); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT, bTRUE); /* Start ADC convert and DFT */ + /* Wait until DFT ready */ + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_DFTRDY) == bFALSE); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT|AFECTRL_WG|AFECTRL_ADCPWR, bFALSE); /* Stop ADC convert and DFT */ + AD5940_INTCClrFlag(AFEINTSRC_DFTRDY); + + DftRtiaVolt.Real = AD5940_ReadAfeResult(AFERESULT_DFTREAL); + DftRtiaVolt.Image = AD5940_ReadAfeResult(AFERESULT_DFTIMAGE); + + if(DftRcalVolt.Real&(1L<<17)) + DftRcalVolt.Real |= 0xfffc0000; + if(DftRcalVolt.Image&(1L<<17)) + DftRcalVolt.Image |= 0xfffc0000; + if(DftRtiaVolt.Real&(1L<<17)) + DftRtiaVolt.Real |= 0xfffc0000; + if(DftRtiaVolt.Image&(1L<<17)) + DftRtiaVolt.Image |= 0xfffc0000; + /* + ADC MUX is set to HSTIA_P and HSTIA_N. + While the current flow through RCAL and then into RTIA, the current direction should be from HSTIA_N to HSTIA_P if we + measure the voltage across RCAL by MUXSELP_P_NODE and MUXSELN_N_NODE. + So here, we add a negative sign to results + */ + DftRtiaVolt.Image = -DftRtiaVolt.Image; + DftRtiaVolt.Real = -DftRtiaVolt.Real; /* Current is measured by MUX HSTIA_P-HSTIA_N. It should be */ + /* + The impedance engine inside of AD594x give us Real part and Imaginary part of DFT. Due to technology used, the Imaginary + part in register is the opposite number. So we add a negative sign on the Imaginary part of results. + */ + DftRtiaVolt.Image = -DftRtiaVolt.Image; + DftRcalVolt.Image = -DftRcalVolt.Image; + + + /***** Implement RTIA = (V_Rtia / V_Rcal) * Rcal ******/ + fImpCar_Type temp; + temp = AD5940_ComplexDivInt(&DftRtiaVolt, &DftRcalVolt); + temp.Real *= pCalCfg->fRcal; + temp.Image *= pCalCfg->fRcal; + if(pCalCfg->bPolarResult == bFALSE) + { + *(fImpCar_Type*)pResult = temp; + } + else + { + ((fImpPol_Type*)pResult)->Magnitude = AD5940_ComplexMag(&temp); + ((fImpPol_Type*)pResult)->Phase = AD5940_ComplexPhase(&temp); + } + + /* Restore INTC1 DFT configure */ + if(INTCCfg&AFEINTSRC_DFTRDY); + else + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_DFTRDY, bFALSE); /* Disable DFT Interrupt */ + + return AD5940ERR_OK; +} + +/** + * @brief Measure LPTIA internal RTIA impedance with HSTIA. This is the recommended method for LPTIA RTIA calibration. + * @param pCalCfg: pointer to calibration structure. + * @param pResult: Pointer to a variable that used to store result. + * If bPolarResult in structure is set, then use type fImpPol_Type otherwise use fImpCar_Type. + * @return AD5940ERR_OK if succeed. +**/ +AD5940Err AD5940_LPRtiaCal(LPRTIACal_Type *pCalCfg, void *pResult) +{ + HSLoopCfg_Type hs_loop; + LPLoopCfg_Type lp_loop; + DSPCfg_Type dsp_cfg; + ADCBaseCfg_Type *pADCBaseCfg; + SWMatrixCfg_Type *pSWCfg; + uint32_t INTCCfg, reg_afecon; + BoolFlag bADCClk32MHzMode = bFALSE; + BoolFlag bDCMode = bFALSE; /* Indicate if frequency is 0, which means we calibrate at DC. */ + + float ExcitVolt; /* Excitation voltage, unit is mV */ + uint32_t RtiaVal; + /* RTIA value table when RLOAD set to 100Ohm */ + uint32_t const LpRtiaTable[]={0,110,1000,2000,3000,4000,6000,8000,10000,12000,16000,20000,24000,30000,32000,40000,48000,64000,85000,96000,100000,120000,128000,160000,196000,256000,512000}; + float const ADCPGAGainTable[] = {1, 1.5, 2, 4, 9}; + uint32_t WgAmpWord; + + uint32_t ADCPgaGainRtia, ADCPgaGainRcal; + float GainRatio; + + iImpCar_Type DftRcal, DftRtia; + + if(pCalCfg == NULL) return AD5940ERR_NULLP; /* Parameters illegal */ + + if(pCalCfg->fRcal == 0) + return AD5940ERR_PARA; + if(pCalCfg->LpTiaRtia > LPTIARTIA_512K) + return AD5940ERR_PARA; + if(pCalCfg->LpTiaRtia == LPTIARTIA_OPEN) + return AD5940ERR_PARA; /* Not supported now. By setting RTIA to open and set corresponding switches can calibrate external RTIA */ + if(pResult == NULL) + return AD5940ERR_NULLP; + + if(pCalCfg->AdcClkFreq > (32000000*0.8)) + bADCClk32MHzMode = bTRUE; /* Clock frequency is high. */ + if(pCalCfg->fFreq == 0.0f) /* Frequency is zero means we calibrate RTIA at DC. */ + bDCMode = bTRUE; + /* Init two pointers */ + pSWCfg = &hs_loop.SWMatCfg; + pADCBaseCfg = &dsp_cfg.ADCBaseCfg; + /* Calculate the excitation voltage we should use based on RCAL/Rtia */ + RtiaVal = LpRtiaTable[pCalCfg->LpTiaRtia]; + /* + * DAC output voltage calculation + * Note: RCAL value should be similar to RTIA so the accuracy is best. + * LPTIA output voltage should be limited to 0.3V to AVDD-0.4V, with 1.3V bias. We use 80% of this range for safe. + * That's 2.0Vpp*80%@2.7V AVDD + * Formula is: ExcitVolt(in mVpp) = (2000mVpp*80% / RTIA) * RCAL + * ADC input range is +-1.5V which is enough for calibration. + * Limitations: + * Note: HSTIA output range is AVDD-0.4V to AGND+0.2V + * HSTIA input common voltage range is 0.3V to AVDD-0.7V; + * When AVDD is 2.7V, the input range is 0.3V to 2.0V; + * If we set Vbias to 1.3V, then maximum AC signal is 0.7Vp*2 = 1.4Vpp. + * Maximum AC signal is further limited by HSTIA RTIA=200Ohm, when RCAL is 200Ohm(for ADuCM355). The maximum output of HSTIA is limited to 2.3V. + * Maximum Vzero voltage is 1.9V when Rcal is 200Ohm and Switch On resistance is 50Ohm*2. Vzero_max = 1.3V + (2.3V-1.3V)/(200+200+50*2)*300. + * Maximum AC signal is (1.9-1.3)*2 = 1.2Vpp(for ADuCM355, RCAl=200Ohm). + */ + /** @cond */ + #define MAXVOLT_P2P 1400 /* Maximum peak to peak voltage 1200mV for ADuCM355. */ + /* Maximum peak2peak voltage for AD5940 10kOhm RCAL is 1400mV */ + #define __MAXVOLT_AMP_CODE (MAXVOLT_P2P*2047L/2200) + /** @endcond */ + ExcitVolt = 2000*0.8*pCalCfg->fRcal/RtiaVal; + WgAmpWord = ((uint32_t)(ExcitVolt/2200*2047*2)+1)>>1; /* Assign value with rounding (0.5 LSB error) */ + if(WgAmpWord > __MAXVOLT_AMP_CODE) + WgAmpWord = __MAXVOLT_AMP_CODE; + /** + * Determine the best ADC PGA gain for both RCAL and RTIA voltage measurement. + */ + { + float RtiaVolt, RcalVolt, temp; + ExcitVolt = WgAmpWord*2000.0f/2047; /* 2000mVpp -->ExcitVolt in Peak to Peak unit */ + RtiaVolt = ExcitVolt/(pCalCfg->fRcal + 100)*RtiaVal; + RcalVolt = RtiaVolt/RtiaVal*pCalCfg->fRcal; + /* The input range of ADC is 1.5Vp, we calculate how much gain we need */ + temp = 3000.0f/RcalVolt; + if(temp >= 9.0f) ADCPgaGainRcal = ADCPGA_9; + else if(temp >= 4.0f) ADCPgaGainRcal = ADCPGA_4; + else if(temp >= 2.0f) ADCPgaGainRcal = ADCPGA_2; + else if(temp >= 1.5f) ADCPgaGainRcal = ADCPGA_1P5; + else ADCPgaGainRcal = ADCPGA_1; + temp = 3000.0f/RtiaVolt; + if(temp >= 9.0f) ADCPgaGainRtia = ADCPGA_9; + else if(temp >= 4.0f) ADCPgaGainRtia = ADCPGA_4; + else if(temp >= 2.0f) ADCPgaGainRtia = ADCPGA_2; + else if(temp >= 1.5f) ADCPgaGainRtia = ADCPGA_1P5; + else ADCPgaGainRtia = ADCPGA_1; + GainRatio = ADCPGAGainTable[ADCPgaGainRtia]/ADCPGAGainTable[ADCPgaGainRcal]; + } + reg_afecon = AD5940_ReadReg(REG_AFE_AFECON); + /* INTC configuration */ + INTCCfg = AD5940_INTCGetCfg(AFEINTC_1); + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_DFTRDY|AFEINTSRC_SINC2RDY, bTRUE); /* Enable SINC2 Interrupt in INTC1 */ + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Init all to disable state */ + /* Configure reference system */ + __AD5940_ReferenceON(); + /* Configure DSP */ + AD5940_StructInit(&dsp_cfg, sizeof(dsp_cfg)); + dsp_cfg.ADCFilterCfg.ADCAvgNum = ADCAVGNUM_16; /* Don't care because it's disabled */ + dsp_cfg.ADCFilterCfg.ADCRate = bADCClk32MHzMode?ADCRATE_1P6MHZ:ADCRATE_800KHZ; + dsp_cfg.ADCFilterCfg.ADCSinc2Osr = pCalCfg->ADCSinc2Osr; + dsp_cfg.ADCFilterCfg.ADCSinc3Osr = pCalCfg->ADCSinc3Osr; + dsp_cfg.ADCFilterCfg.BpNotch = bTRUE; + dsp_cfg.ADCFilterCfg.BpSinc3 = bFALSE; + dsp_cfg.ADCFilterCfg.Sinc2NotchEnable = bTRUE; + memcpy(&dsp_cfg.DftCfg, &pCalCfg->DftCfg, sizeof(pCalCfg->DftCfg)); + AD5940_DSPCfgS(&dsp_cfg); + /* Configure LP Loop */ + AD5940_StructInit(&lp_loop, sizeof(lp_loop)); + /* Configure LP Amplifies(LPPA and LPTIA). We won't use LP-PA */ + lp_loop.LpDacCfg.LpdacSel = (pCalCfg->LpAmpSel == LPAMP0)?LPDAC0:LPDAC1; + lp_loop.LpDacCfg.DacData12Bit = 0x800; /* Controlled by WG */ + lp_loop.LpDacCfg.DacData6Bit = 32; /* middle scale value */ + lp_loop.LpDacCfg.DataRst =bFALSE; /* Do not keep DATA registers at reset status */ + lp_loop.LpDacCfg.LpDacSW = LPDACSW_VBIAS2LPPA|LPDACSW_VZERO2HSTIA; + lp_loop.LpDacCfg.LpDacRef = LPDACREF_2P5; /* Select internal 2.5V reference */ + lp_loop.LpDacCfg.LpDacSrc = LPDACSRC_WG; /* The LPDAC data comes from WG not MMR in this case */ + lp_loop.LpDacCfg.LpDacVbiasMux = LPDACVBIAS_6BIT; /* Connect Vbias signal to 6Bit LPDAC output */ + lp_loop.LpDacCfg.LpDacVzeroMux = LPDACVZERO_12BIT; /* Connect Vzero signal to 12bit LPDAC output */ + lp_loop.LpDacCfg.PowerEn = bTRUE; /* Power up LPDAC */ + + lp_loop.LpAmpCfg.LpAmpSel = pCalCfg->LpAmpSel; + lp_loop.LpAmpCfg.LpAmpPwrMod = pCalCfg->LpAmpPwrMod; /* Set low power amplifiers to normal power mode */ + lp_loop.LpAmpCfg.LpPaPwrEn = bTRUE; /* Enable LP PA(potential-stat amplifier) power */ + lp_loop.LpAmpCfg.LpTiaPwrEn = bTRUE; /* Enable LPTIA*/ + lp_loop.LpAmpCfg.LpTiaRload = LPTIARLOAD_100R; + lp_loop.LpAmpCfg.LpTiaRtia = pCalCfg->LpTiaRtia; + lp_loop.LpAmpCfg.LpTiaRf = LPTIARF_OPEN; + lp_loop.LpAmpCfg.LpTiaSW = LPTIASW(6)|LPTIASW(8)|(pCalCfg->bWithCtia==bTRUE?LPTIASW(5)/*|LPTIASW(9)*/:0); + AD5940_LPLoopCfgS(&lp_loop); + /* Configure HS Loop */ + AD5940_StructInit(&hs_loop, sizeof(hs_loop)); + /* Take care of HSTIA, we need to disconnect internal RTIA because it connects to Tswitch directly. */ + hs_loop.HsTiaCfg.DiodeClose = bFALSE; + hs_loop.HsTiaCfg.HstiaBias = (pCalCfg->LpAmpSel == LPAMP0)?HSTIABIAS_VZERO0:HSTIABIAS_VZERO1; + hs_loop.HsTiaCfg.HstiaCtia = 31; + hs_loop.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_OPEN; + hs_loop.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_OPEN; + hs_loop.HsTiaCfg.HstiaDe1Rload = HSTIADERLOAD_OPEN; + hs_loop.HsTiaCfg.HstiaDe1Rtia = HSTIADERTIA_OPEN; + hs_loop.HsTiaCfg.HstiaRtiaSel = HSTIARTIA_200; + /* Configure HSDAC */ + hs_loop.HsDacCfg.ExcitBufGain = 0; + hs_loop.HsDacCfg.HsDacGain = 0; /* Don't care */ + hs_loop.HsDacCfg.HsDacUpdateRate = 255; /* Lowest for LPDAC */ + + hs_loop.SWMatCfg.Dswitch = SWD_RCAL0|((pCalCfg->LpAmpSel == LPAMP0)?SWD_SE0:SWD_SE1); + hs_loop.SWMatCfg.Pswitch = SWP_RCAL0; + hs_loop.SWMatCfg.Nswitch = SWN_RCAL1; + hs_loop.SWMatCfg.Tswitch = SWT_TRTIA|SWT_RCAL1; + if(bDCMode) + { + int32_t time_out = -1; /* Always wait. */ + int32_t offset_rcal, offset_rtia; + /* Configure WG */ + hs_loop.WgCfg.WgType = WGTYPE_MMR; + hs_loop.WgCfg.WgCode = WgAmpWord; /* Amplitude word is exactly the maximum DC voltage we could use */ + hs_loop.WgCfg.GainCalEn = bFALSE; /* We don't have calibration value for LPDAC, so we don't use it. */ + hs_loop.WgCfg.OffsetCalEn = bFALSE; + AD5940_HSLoopCfgS(&hs_loop); + AD5940_WGDACCodeS(WgAmpWord + 0x800); + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_WG|AFECTRL_ADCPWR, bTRUE); /* Apply voltage to loop and turn on ADC */ + /* Do offset measurement */ + pSWCfg->Dswitch = SWD_RCAL0;//|SWD_SE0; /* Disconnect SE0 for now to measure the offset voltage. */ + pSWCfg->Pswitch = SWP_RCAL0; + pSWCfg->Nswitch = SWN_RCAL1; + pSWCfg->Tswitch = SWT_TRTIA|SWT_RCAL1; + AD5940_SWMatrixCfgS(pSWCfg); + AD5940_Delay10us(1000); /* Wait some time here. */ + /* Measure RCAL channel voltage offset */ + pADCBaseCfg->ADCMuxN = ADCMUXN_N_NODE; + pADCBaseCfg->ADCMuxP = ADCMUXP_P_NODE; + pADCBaseCfg->ADCPga = ADCPgaGainRcal; + AD5940_ADCBaseCfgS(pADCBaseCfg); + AD5940_Delay10us(50); /* Wait some time here. */ + offset_rcal = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + /* Measure RTIA channel voltage offset */ + if(pCalCfg->LpAmpSel == LPAMP0) + { + pADCBaseCfg->ADCMuxN = ADCMUXN_LPTIA0_N; + pADCBaseCfg->ADCMuxP = ADCMUXP_LPTIA0_P; + }else + { + pADCBaseCfg->ADCMuxN = ADCMUXN_LPTIA1_N; + pADCBaseCfg->ADCMuxP = ADCMUXP_LPTIA1_P; + } + pADCBaseCfg->ADCPga = ADCPgaGainRtia; + AD5940_ADCBaseCfgS(pADCBaseCfg); + AD5940_Delay10us(50); /* Wait some time here. */ + offset_rtia = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + /* Connect LPTIA loop, let current flow to RTIA. */ + pSWCfg->Dswitch = SWD_RCAL0|((pCalCfg->LpAmpSel == LPAMP0)?SWD_SE0:SWD_SE1); + pSWCfg->Pswitch = SWP_RCAL0; + pSWCfg->Nswitch = SWN_RCAL1; + pSWCfg->Tswitch = SWT_TRTIA|SWT_RCAL1; + AD5940_SWMatrixCfgS(pSWCfg); + AD5940_Delay10us(1000); /* Wait some time here. */ + /* Measure RCAL */ + pADCBaseCfg = &dsp_cfg.ADCBaseCfg; + pADCBaseCfg->ADCMuxN = ADCMUXN_N_NODE; + pADCBaseCfg->ADCMuxP = ADCMUXP_P_NODE; + pADCBaseCfg->ADCPga = ADCPgaGainRcal; + AD5940_ADCBaseCfgS(pADCBaseCfg); + AD5940_Delay10us(50); /* Wait some time here. */ + DftRcal.Real = (int32_t)__AD5940_TakeMeasurement(&time_out)- offset_rcal; + DftRcal.Image = 0; + /* Measure RTIA */ + if(pCalCfg->LpAmpSel == LPAMP0) + { + pADCBaseCfg->ADCMuxN = ADCMUXN_LPTIA0_N; + pADCBaseCfg->ADCMuxP = ADCMUXP_LPTIA0_P; + }else + { + pADCBaseCfg->ADCMuxN = ADCMUXN_LPTIA1_N; + pADCBaseCfg->ADCMuxP = ADCMUXP_LPTIA1_P; + } + pADCBaseCfg->ADCPga = ADCPgaGainRtia; + AD5940_ADCBaseCfgS(pADCBaseCfg); + AD5940_Delay10us(50); /* Wait some time here. */ + DftRtia.Real = (int32_t)__AD5940_TakeMeasurement(&time_out)- offset_rtia; + DftRtia.Image = 0; + } + else + { + hs_loop.WgCfg.SinCfg.SinAmplitudeWord = WgAmpWord; + hs_loop.WgCfg.SinCfg.SinFreqWord = AD5940_WGFreqWordCal(pCalCfg->fFreq, pCalCfg->SysClkFreq); + hs_loop.WgCfg.SinCfg.SinOffsetWord = 0; + hs_loop.WgCfg.SinCfg.SinPhaseWord = 0; + hs_loop.WgCfg.WgCode = 0; + hs_loop.WgCfg.WgType = WGTYPE_SIN; + hs_loop.WgCfg.GainCalEn = bFALSE; /* disable it */ + hs_loop.WgCfg.OffsetCalEn = bFALSE; + AD5940_HSLoopCfgS(&hs_loop); + AD5940_INTCClrFlag(AFEINTSRC_DFTRDY); + + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR, bTRUE); + AD5940_Delay10us(100); /* Wait for loop stable. */ + pADCBaseCfg = &dsp_cfg.ADCBaseCfg; + /* DFT on RCAL */ + pADCBaseCfg->ADCMuxN = ADCMUXN_N_NODE; + pADCBaseCfg->ADCMuxP = ADCMUXP_P_NODE; + pADCBaseCfg->ADCPga = ADCPgaGainRcal; + AD5940_ADCBaseCfgS(pADCBaseCfg); + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_WG, bTRUE); + AD5940_Delay10us(25); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT, bTRUE); + /* Wait until DFT ready */ + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_DFTRDY) == bFALSE); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT|AFECTRL_WG|AFECTRL_ADCPWR, bFALSE); /* Stop ADC convert and DFT */ + AD5940_INTCClrFlag(AFEINTSRC_DFTRDY); + DftRcal.Real = AD5940_ReadAfeResult(AFERESULT_DFTREAL); + DftRcal.Image = AD5940_ReadAfeResult(AFERESULT_DFTIMAGE); + /* DFT on RTIA */ + if(pCalCfg->LpAmpSel == LPAMP0) + { + pADCBaseCfg->ADCMuxN = ADCMUXN_LPTIA0_N; + pADCBaseCfg->ADCMuxP = ADCMUXP_LPTIA0_P; + }else + { + pADCBaseCfg->ADCMuxN = ADCMUXN_LPTIA1_N; + pADCBaseCfg->ADCMuxP = ADCMUXP_LPTIA1_P; + } + pADCBaseCfg->ADCPga = ADCPgaGainRtia; + AD5940_ADCBaseCfgS(pADCBaseCfg); + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_WG, bTRUE); + AD5940_Delay10us(25); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT, bTRUE); + /* Wait until DFT ready */ + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_DFTRDY) == bFALSE); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT|AFECTRL_WG|AFECTRL_ADCPWR, bFALSE); /* Stop ADC convert and DFT */ + AD5940_INTCClrFlag(AFEINTSRC_DFTRDY); + DftRtia.Real = AD5940_ReadAfeResult(AFERESULT_DFTREAL); + DftRtia.Image = AD5940_ReadAfeResult(AFERESULT_DFTIMAGE); + if(DftRcal.Real&(1L<<17)) + DftRcal.Real |= 0xfffc0000; + if(DftRcal.Image&(1L<<17)) + DftRcal.Image |= 0xfffc0000; + if(DftRtia.Real&(1L<<17)) + DftRtia.Real |= 0xfffc0000; + if(DftRtia.Image&(1L<<17)) + DftRtia.Image |= 0xfffc0000; + } + /* + The impedance engine inside of AD594x give us Real part and Imaginary part of DFT. Due to technology used, the Imaginary + part in register is the opposite number. So we add a negative sign on the Imaginary part of results. + */ + DftRtia.Image = -DftRtia.Image; + DftRcal.Image = -DftRcal.Image; + + fImpCar_Type res; + /* RTIA = (DftRtia.Real, DftRtia.Image)/(DftRcal.Real, DftRcal.Image)*fRcal */ + res = AD5940_ComplexDivInt(&DftRtia, &DftRcal); + res.Real *= pCalCfg->fRcal/GainRatio; + res.Image *= pCalCfg->fRcal/GainRatio; + if(pCalCfg->bPolarResult == bFALSE) + { + ((fImpCar_Type*)pResult)->Real = res.Real; + ((fImpCar_Type*)pResult)->Image = res.Image; + } + else + { + ((fImpPol_Type*)pResult)->Magnitude = AD5940_ComplexMag(&res); + ((fImpPol_Type*)pResult)->Phase = AD5940_ComplexPhase(&res); + } + + /* Restore INTC1 DFT configure */ + if(INTCCfg&AFEINTSRC_DFTRDY); + else + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_DFTRDY, bFALSE); /* Disable DFT Interrupt */ + if(INTCCfg&AFEINTSRC_SINC2RDY); + else + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bFALSE); /* Disable SINC2 Interrupt */ + AD5940_WriteReg(REG_AFE_AFECON, reg_afecon); /* Restore AFECON register */ + /* Open all switches in switch-matrix */ + hs_loop.SWMatCfg.Dswitch = SWD_OPEN; + hs_loop.SWMatCfg.Pswitch = SWP_OPEN; + hs_loop.SWMatCfg.Nswitch = SWN_OPEN; + hs_loop.SWMatCfg.Tswitch = SWT_OPEN; + AD5940_SWMatrixCfgS(&hs_loop.SWMatCfg); + + return AD5940ERR_OK; +} + + +/** + * @brief calibrate HSDAC output voltage using ADC. + * @note It acutally calibrates voltage output of excitation buffer. + * @param pCalCfg: pointer to configuration structure + * @return return AD5940ERR_OK if succeeded. +*/ +AD5940Err AD5940_HSDACCal(HSDACCal_Type *pCalCfg) +{ + ADCBaseCfg_Type adc_base; + ADCFilterCfg_Type adc_filter; + HSLoopCfg_Type hsloop_cfg; + LPLoopCfg_Type lploop_cfg; + + /* LSB_Numerator and LSB_Denometer are used to calculate + the codes to write to calibration registers depending on + which calibration register is used + There are LSB_Numerator ADC LSBs in + LSB_Denominator DAC Calibration LSBs*/ + int32_t LSB_Numerator; + int32_t LEB_Denominator; + int32_t time_out; + int32_t ADCCode; + uint32_t HSDACCode = 0x800; /* Mid scale DAC */ + + uint32_t regaddr_offset; + uint32_t ADCPGA_Sel; + BoolFlag bHPMode; + + if(pCalCfg == NULL) return AD5940ERR_NULLP; + if(pCalCfg->ExcitBufGain > 1) return AD5940ERR_PARA; + if(pCalCfg->HsDacGain > 1) return AD5940ERR_PARA; + + bHPMode = pCalCfg->AfePwrMode == AFEPWR_HP?bTRUE:bFALSE; + + switch(pCalCfg->ExcitBufGain) + { + case EXCITBUFGAIN_2: + regaddr_offset = bHPMode?REG_AFE_DACOFFSETHP:REG_AFE_DACOFFSET; + if(pCalCfg->HsDacGain == HSDACGAIN_0P2) + { + LSB_Numerator = 40; + LEB_Denominator = 14; + ADCPGA_Sel = ADCPGA_4; + } + else + { + LSB_Numerator = 7; + LEB_Denominator = 2; + ADCPGA_Sel = ADCPGA_1; + } + break; + case EXCITBUFGAIN_0P25: + regaddr_offset = bHPMode?REG_AFE_DACOFFSETATTENHP:REG_AFE_DACOFFSETATTEN; + if(pCalCfg->HsDacGain == HSDACGAIN_0P2) + { + LSB_Numerator = 5; + LEB_Denominator = 14; + } + else + { + LSB_Numerator = 25; + LEB_Denominator = 14; + } + ADCPGA_Sel = ADCPGA_4; + break; + default: + return AD5940ERR_PARA; + } + + /* Turn On References*/ + __AD5940_ReferenceON(); + /* Step0.0 Initialize ADC filters ADCRawData-->SINC3-->SINC2+NOTCH. Use SIN2 data for calibration-->Lower noise */ + adc_filter.ADCSinc3Osr = pCalCfg->ADCSinc3Osr; + adc_filter.ADCSinc2Osr = pCalCfg->ADCSinc2Osr; /* 800KSPS/4/1333 = 150SPS */ + adc_filter.ADCAvgNum = ADCAVGNUM_2; /* Don't care about it. Average function is only used for DFT */ + adc_filter.ADCRate = bHPMode?ADCRATE_1P6MHZ:ADCRATE_800KHZ; /* If ADC clock is 32MHz, then set it to ADCRATE_1P6MHZ. Default is 16MHz, use ADCRATE_800KHZ. */ + adc_filter.BpNotch = bTRUE; /* SINC2+Notch is one block, when bypass notch filter, we can get fresh data from SINC2 filter. */ + adc_filter.BpSinc3 = bFALSE; /* We use SINC3 filter. */ + adc_filter.Sinc2NotchEnable = bTRUE; /* Enable the SINC2+Notch block. You can also use function AD5940_AFECtrlS */ + AD5940_ADCFilterCfgS(&adc_filter); + /* Step0.1 Initialize ADC basic function */ + adc_base.ADCMuxP = ADCMUXP_P_NODE; + adc_base.ADCMuxN = ADCMUXN_N_NODE; + adc_base.ADCPga = ADCPGA_Sel; + AD5940_ADCBaseCfgS(&adc_base); + + /* Step0.2 Configure LPDAC to connect VZERO to HSTIA */ + lploop_cfg.LpDacCfg.LpdacSel = LPDAC0; + lploop_cfg.LpDacCfg.DacData12Bit = 0x7C0; + lploop_cfg.LpDacCfg.DacData6Bit = 0x1F; + lploop_cfg.LpDacCfg.DataRst = bFALSE; + lploop_cfg.LpDacCfg.LpDacRef = LPDACREF_2P5; + lploop_cfg.LpDacCfg.LpDacSrc = LPDACSRC_MMR; + lploop_cfg.LpDacCfg.LpDacVzeroMux = LPDACVZERO_6BIT; + lploop_cfg.LpDacCfg.LpDacVbiasMux = LPDACVBIAS_12BIT; + lploop_cfg.LpDacCfg.PowerEn = bTRUE; + lploop_cfg.LpDacCfg.LpDacSW = LPDACSW_VBIAS2LPPA|LPDACSW_VBIAS2PIN|LPDACSW_VZERO2HSTIA; + AD5940_LPLoopCfgS(&lploop_cfg); + + /* Step0.3 Configure HSLOOP */ + hsloop_cfg.HsDacCfg.ExcitBufGain = pCalCfg->ExcitBufGain; + hsloop_cfg.HsDacCfg.HsDacGain = pCalCfg->HsDacGain; + hsloop_cfg.HsDacCfg.HsDacUpdateRate = bHPMode?0x7:0x1B; + hsloop_cfg.HsTiaCfg.DiodeClose = bFALSE; + hsloop_cfg.HsTiaCfg.HstiaBias = HSTIABIAS_VZERO0; + hsloop_cfg.HsTiaCfg.HstiaCtia = 8; + hsloop_cfg.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_OPEN; + hsloop_cfg.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_OPEN; + hsloop_cfg.HsTiaCfg.HstiaDe1Rload = HSTIADERLOAD_OPEN; + hsloop_cfg.HsTiaCfg.HstiaDe1Rtia = HSTIADERTIA_OPEN; + hsloop_cfg.HsTiaCfg.HstiaRtiaSel = HSTIARTIA_200; + hsloop_cfg.SWMatCfg.Dswitch = SWD_RCAL0; + hsloop_cfg.SWMatCfg.Pswitch = SWP_RCAL0; + hsloop_cfg.SWMatCfg.Nswitch = SWN_RCAL1; + hsloop_cfg.SWMatCfg.Tswitch = SWT_TRTIA|SWT_RCAL1; + hsloop_cfg.WgCfg.GainCalEn = bTRUE; + hsloop_cfg.WgCfg.OffsetCalEn = bTRUE; + hsloop_cfg.WgCfg.WgType = WGTYPE_MMR; + hsloop_cfg.WgCfg.WgCode = HSDACCode; + AD5940_HSLoopCfgS(&hsloop_cfg); + /* Step0.4 Turn ON reference and ADC power, and DAC power and DAC reference. We use DAC 1.8V reference to calibrate ADC. */ + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Disable all */ + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_HPREFPWR|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|AFECTRL_SINC2NOTCH|\ + AFECTRL_EXTBUFPWR|AFECTRL_INAMPPWR|AFECTRL_HSTIAPWR|AFECTRL_WG, bTRUE); + AD5940_Delay10us(25); /* Wait 250us for reference power up */ + /* Step0.5 INTC configure and open calibration lock */ + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bTRUE); /* Enable SINC2 Interrupt in INTC1 */ + AD5940_WriteReg(REG_AFE_CALDATLOCK, KEY_CALDATLOCK); /* Unlock KEY */ + /* Reset Offset register before calibration */ + AD5940_WriteReg(regaddr_offset, 0); + /* Update HSDACDAT after resetting calibration register */ + AD5940_WriteReg(REG_AFE_HSDACDAT, 0x800); + /* Step1: Do offset calibration. */ + { + int32_t ExpectedCode = 0x8000; /* Ideal ADC output */ + AD5940_Delay10us(10); + time_out = 1000; /* Reset time out counter */ + ADCCode = __AD5940_TakeMeasurement(&time_out); +#ifdef ADI_DEBUG + ADI_Print("Voltage before cal: %f \n", AD5940_ADCCode2Volt(ADCCode, ADCPGA_Sel, 1.82)); +#endif + + if(time_out == 0) goto DACCALERROR_TIMEOUT; /* Time out error. */ + ADCCode = ADCCode - ExpectedCode; + ADCCode = (((ADCCode)*LEB_Denominator)/LSB_Numerator); + if(ADCCode>0) + ADCCode = 0xFFF - ADCCode; + else + ADCCode = -ADCCode; + AD5940_WriteReg(regaddr_offset, ADCCode); + AD5940_Delay10us(10); + AD5940_WriteReg(REG_AFE_HSDACDAT, 0x800); + AD5940_Delay10us(10); +#ifdef ADI_DEBUG + ADCCode = __AD5940_TakeMeasurement(&time_out); + ADI_Print("Voltage after cal: %f \n", AD5940_ADCCode2Volt(ADCCode, ADCPGA_Sel, 1.82)); +#endif + } + AD5940_WriteReg(REG_AFE_CALDATLOCK, 0); /* Lock KEY */ + return AD5940ERR_OK; +DACCALERROR_TIMEOUT: + AD5940_ADCConvtCtrlS(bFALSE); /* Stop conversion */ + AD5940_WriteReg(REG_AFE_CALDATLOCK, 0); /* Lock KEY */ + return AD5940ERR_TIMEOUT; +} + +/** + * @brief Use ADC to measure LPDAC offset and gain factor. + * @note Assume ADC is accurate enough or accurate than LPDAC at least. + * @param pCalCfg: pointer to structure. + * @param pResult: the pointer to save calibration result. + * @return AD5940ERR_OK if succeed. + *LPDACCal() function is added in ad5940.c only to suggest an optional LPDAC calibration sequence. + *It is not verified by ADI software team and user may use it at own risk. + +**/ +AD5940Err AD5940_LPDACCal(LPDACCal_Type *pCalCfg, LPDACPara_Type *pResult) +{ + AD5940Err error = AD5940ERR_OK; + LPDACCfg_Type LpDacCfg; + ADCBaseCfg_Type adc_base; + ADCFilterCfg_Type adc_filter; + + int32_t time_out; + uint32_t INTCCfg; + int32_t ADCCode, ADCCodeVref1p1; + BoolFlag bADCClk32MHzMode; + + if(pCalCfg == NULL) return AD5940ERR_NULLP; + if(pResult == NULL) return AD5940ERR_NULLP; + if(pCalCfg->AdcClkFreq > (32000000*0.8)) + bADCClk32MHzMode = bTRUE; + + /* Step0: Do initialization */ + /* Turn on AD5940 references in case it's disabled. */ + __AD5940_ReferenceON(); + LpDacCfg.LpdacSel = pCalCfg->LpdacSel; + LpDacCfg.DacData12Bit = 0; + LpDacCfg.DacData6Bit = 0; + LpDacCfg.DataRst = bFALSE; + LpDacCfg.LpDacRef = LPDACREF_2P5; + LpDacCfg.LpDacSrc = LPDACSRC_MMR; + LpDacCfg.LpDacSW = LPDACSW_VBIAS2PIN|LPDACSW_VZERO2PIN; + LpDacCfg.LpDacVbiasMux = LPDACVBIAS_12BIT; + LpDacCfg.LpDacVzeroMux = LPDACVZERO_6BIT; + LpDacCfg.PowerEn = bTRUE; + AD5940_LPDACCfgS(&LpDacCfg); + + /* Initialize ADC filters ADCRawData-->SINC3-->SINC2+NOTCH. Use SIN2 data for calibration-->Lower noise */ + adc_filter.ADCSinc3Osr = pCalCfg->ADCSinc3Osr; + adc_filter.ADCSinc2Osr = pCalCfg->ADCSinc2Osr; /* 800KSPS/4/1333 = 150SPS */ + adc_filter.ADCAvgNum = ADCAVGNUM_2; /* Don't care about it. Average function is only used for DFT */ + adc_filter.ADCRate = bADCClk32MHzMode?ADCRATE_1P6MHZ:ADCRATE_800KHZ; /* If ADC clock is 32MHz, then set it to ADCRATE_1P6MHZ. Default is 16MHz, use ADCRATE_800KHZ. */ + adc_filter.BpNotch = bTRUE; /* SINC2+Notch is one block, when bypass notch filter, we can get fresh data from SINC2 filter. */ + adc_filter.BpSinc3 = bFALSE; /* We use SINC3 filter. */ + adc_filter.Sinc2NotchEnable = bTRUE; /* Enable the SINC2+Notch block. You can also use function AD5940_AFECtrlS */ + AD5940_ADCFilterCfgS(&adc_filter); + /* Initialize ADC MUx and PGA */ + adc_base.ADCMuxP = ADCMUXP_AGND; + adc_base.ADCMuxN = ADCMUXN_VSET1P1; + adc_base.ADCPga = ADCPGA_1; + AD5940_ADCBaseCfgS(&adc_base); + /* Turn ON ADC and its reference. And SINC2. */ + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Disable all firstly, we only enable things we use */ + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_HPREFPWR|AFECTRL_SINC2NOTCH, bTRUE); + AD5940_Delay10us(25); /* Wait 250us for reference power up */ + /* INTC configure and open calibration lock */ + INTCCfg = AD5940_INTCGetCfg(AFEINTC_1); + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bTRUE); /* Enable SINC2 Interrupt in INTC1 */ + /* Step1: Measure internal 1.1V reference. */ + { + //AD5940_ADCMuxCfgS(ADCMUXP_AGND, ADCMUXN_VSET1P1); + time_out = pCalCfg->TimeOut10us; /* Reset time out counter */ + ADCCodeVref1p1 = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + if(time_out == 0) + { + error = AD5940ERR_TIMEOUT; + goto LPDACCALERROR; + } /* Time out error. */ + /* Equation1: ADCCodeVref1p1 = AGND - Vref1p1 */ + } + /* Step2: Do offset measurement. */ + { + /* Equation2': ADCCode = Vbias0/1 - Vref1p1 */ + AD5940_LPDACWriteS(0,0); /* Set LPDAC output voltage to 0.2V(zero code) */ + if(pCalCfg->SettleTime10us > 0) + AD5940_Delay10us(pCalCfg->SettleTime10us); /* Delay nx10us */ + if(pCalCfg->LpdacSel == LPDAC0) + AD5940_ADCMuxCfgS(ADCMUXP_VBIAS0, ADCMUXN_VREF1P1); /* Vbias0 is routed to 12BIT LPDAC */ + else + AD5940_ADCMuxCfgS(ADCMUXP_VBIAS1, ADCMUXN_VREF1P1); /* Vbias1 is routed to 12BIT LPDAC */ + + AD5940_Delay10us(5); /* Delay 50us */ + time_out = pCalCfg->TimeOut10us; /* Reset time out counter */ + ADCCode = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + if(time_out == 0) + { + error = AD5940ERR_TIMEOUT; + goto LPDACCALERROR; + } /* Time out error. */ + /* Calculate the offset voltage using Equation2 - Equation1 */ + ADCCode -= ADCCodeVref1p1; /* Get the code of Vbias0-AGND. Then calculate the offset voltage in mV. */ + pResult->bC2V_DAC12B = ADCCode*pCalCfg->ADCRefVolt*1e3f/32768*1.835f/1.82f; /*mV unit*/ + /* Measure 6BIT DAC output(Vzero0/1) */ + if(pCalCfg->LpdacSel == LPDAC0) + AD5940_ADCMuxCfgS(ADCMUXP_VZERO0, ADCMUXN_VREF1P1); /* Vbias0 is routed to 12BIT LPDAC */ + else + AD5940_ADCMuxCfgS(ADCMUXP_VZERO1, ADCMUXN_VREF1P1); /* Vbias1 is routed to 12BIT LPDAC */ + AD5940_Delay10us(5); /* Delay 50us */ + time_out = pCalCfg->TimeOut10us; /* Reset time out counter */ + ADCCode = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + if(time_out == 0) + { + error = AD5940ERR_TIMEOUT; + goto LPDACCALERROR; + } /* Time out error. */ + /* Calculate the offset voltage */ + ADCCode -= ADCCodeVref1p1; /* Get the code of Vbias0-AGND. Then calculate the offset voltage in mV. */ + pResult->bC2V_DAC6B = ADCCode*pCalCfg->ADCRefVolt*1e3f/32768*1.835f/1.82f; /*mV unit*/ + } + /* Step3: Do gain measurement */ + { + /* Equation2: ADCCode = Vbias0 - Vref1p1 */ + AD5940_LPDACWriteS(0xfff,0x3f); /* Set LPDAC output voltage to 2.4V(zero code) */ + if(pCalCfg->SettleTime10us > 0) + AD5940_Delay10us(pCalCfg->SettleTime10us); /* Delay nx10us */ + if(pCalCfg->LpdacSel == LPDAC0) + AD5940_ADCMuxCfgS(ADCMUXP_VBIAS0, ADCMUXN_VREF1P1); /* Vbias0 is routed to 12BIT LPDAC */ + else + AD5940_ADCMuxCfgS(ADCMUXP_VBIAS1, ADCMUXN_VREF1P1); /* Vbias1 is routed to 12BIT LPDAC */ + AD5940_Delay10us(5); /* Delay 50us */ + time_out = pCalCfg->TimeOut10us; /* Reset time out counter */ + ADCCode = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + if(time_out == 0) + { + error = AD5940ERR_TIMEOUT; + goto LPDACCALERROR; + } /* Time out error. */ + /* Calculate the offset voltage */ + ADCCode -= ADCCodeVref1p1; /* Get the code of Vbias0-AGND. Then calculate the gain factor 'k'. */ + pResult->kC2V_DAC12B = (ADCCode*pCalCfg->ADCRefVolt*1e3f/32768*1.835f/1.82f - pResult->bC2V_DAC12B)/0xfff;/*mV unit*/ + /* Measure 6BIT DAC output(Vzero0) */ + if(pCalCfg->LpdacSel == LPDAC0) + AD5940_ADCMuxCfgS(ADCMUXP_VZERO0, ADCMUXN_VREF1P1); /* Vbias0 is routed to 12BIT LPDAC */ + else + AD5940_ADCMuxCfgS(ADCMUXP_VZERO1, ADCMUXN_VREF1P1); /* Vbias1 is routed to 12BIT LPDAC */ + AD5940_Delay10us(5); /* Delay 50us */ + time_out = pCalCfg->TimeOut10us; /* Reset time out counter */ + ADCCode = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + if(time_out == 0) + { + error = AD5940ERR_TIMEOUT; + goto LPDACCALERROR; + } /* Time out error. */ + /* Calculate the offset voltage */ + ADCCode -= ADCCodeVref1p1; /* Get the code of Vbias0-AGND. Then calculate the offset voltage in mV. */ + pResult->kC2V_DAC6B = (ADCCode*pCalCfg->ADCRefVolt*1e3f/32768*1.835f/1.82f - pResult->bC2V_DAC6B)/0x3f;/*mV unit*/ + } + /* Step4: calculate the parameters for voltage to code calculation. */ + pResult->kV2C_DAC12B = 1/pResult->kC2V_DAC12B; + pResult->bV2C_DAC12B = -pResult->bC2V_DAC12B/pResult->kC2V_DAC12B; + pResult->kV2C_DAC6B = 1/pResult->kC2V_DAC6B; + pResult->bV2C_DAC6B = -pResult->bC2V_DAC6B/pResult->kC2V_DAC6B; + /* Restore INTC1 SINC2 configure */ + if(INTCCfg&AFEINTSRC_SINC2RDY); + else + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bFALSE); /* Disable SINC2 Interrupt */ + /* Done */ + return AD5940ERR_OK; + +LPDACCALERROR: + AD5940_ADCConvtCtrlS(bFALSE); /* Stop conversion */ + return error; +} + +/** + * @brief Use system clock to measure LFOSC frequency. + * @note Set system clock to external crystal to get a better measurement accuracy. + * This function use 3 sequences and the start address is specified by parameter. + * @param pCfg: pointer to structure. + * @param pFreq: Pointer to a variable that used to store frequency in Hz. + * @return AD5940ERR_OK if succeed. +**/ +AD5940Err AD5940_LFOSCMeasure(LFOSCMeasure_Type *pCfg, float *pFreq) /* Measure current LFOSC frequency. */ +{ + /** + * @code + * Sleep wakeup timer running... + * -SLP----WKP----SLP----WKP----SLP----WKP + * --|-----|-------------|-------------|------------Trigger sequencer when Wakeup Timer over. + * --------|SEQA---------|SEQB----------------------Execute SeqA then SeqB + * ---------|InitT--------|StopT--------------------SeqA start timer and SeqB trigger interrupt so MCU read back current count + * ------------------------|INT--------------------- + * -----------------------------------------|Read---We read SEQTIMEOUT register here + * ---------|-----TimerCount----------------|------- + * ---------|--------------|---TimerCount2--|-------We change SeqB to reset timer so we measure how much time needed for MCU to read back SEQTIMEOUT register(TimerCount2) + * @endcode + * **/ + uint32_t TimerCount, TimerCount2; + SEQCfg_Type seq_cfg, seq_cfg_backup; + SEQInfo_Type seqinfo; + WUPTCfg_Type wupt_cfg; + uint32_t INTCCfg; + uint32_t WuptPeriod; + + static const uint32_t SeqA[]= + { + SEQ_TOUT(0x3fffffff), /* Set time-out timer. It will always run until disable Sequencer by SPI interface. */ + }; + static const uint32_t SeqB[]= + { + /** + * Interrupt flag AFEINTSRC_ENDSEQ will be set after this command. So We can inform MCU to read back + * current timer value. MCU will need some additional time to read back time count. + * So we use SeqB to measure how much time needed for MCU to read back + * */ + SEQ_STOP(), + }; + static const uint32_t SeqBB[]= + { + SEQ_TOUT(0x3fffffff), /* Re-Set time-out timer, so we can measure the time needed for MCU to read out Timer Count register. */ + SEQ_STOP(), /* Interrupt flag AFEINTSRC_ENDSEQ will be set here */ + }; + + if(pCfg == NULL) return AD5940ERR_NULLP; + if(pFreq == NULL) return AD5940ERR_NULLP; + if(pCfg->CalDuration < 1.0f) + return AD5940ERR_PARA; + AD5940_SEQGetCfg(&seq_cfg_backup); + INTCCfg = AD5940_INTCGetCfg(AFEINTC_1); + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_ENDSEQ, bTRUE); + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + + seq_cfg.SeqMemSize = SEQMEMSIZE_2KB; /* 2kB SRAM is used for sequencer */ + seq_cfg.SeqBreakEn = bFALSE; + seq_cfg.SeqIgnoreEn = bFALSE; + seq_cfg.SeqCntCRCClr = bFALSE; + seq_cfg.SeqEnable = bTRUE; + seq_cfg.SeqWrTimer = 0; + AD5940_SEQCfg(&seq_cfg); /* Enable sequencer */ + + seqinfo.pSeqCmd = SeqA; + seqinfo.SeqId = SEQID_0; + seqinfo.SeqLen = SEQ_LEN(SeqA); + seqinfo.SeqRamAddr = pCfg->CalSeqAddr; + seqinfo.WriteSRAM = bTRUE; + AD5940_SEQInfoCfg(&seqinfo); + seqinfo.SeqId = SEQID_1; + seqinfo.SeqRamAddr = pCfg->CalSeqAddr + SEQ_LEN(SeqA) ; + seqinfo.SeqLen = SEQ_LEN(SeqB); + seqinfo.pSeqCmd = SeqB; + AD5940_SEQInfoCfg(&seqinfo); /* Configure sequence0 and sequence1 with command SeqA and SeqB */ + + wupt_cfg.WuptEn = bFALSE; + wupt_cfg.WuptOrder[0] = SEQID_0; + wupt_cfg.WuptOrder[1] = SEQID_1; + wupt_cfg.WuptEndSeq = WUPTENDSEQ_B; + wupt_cfg.SeqxWakeupTime[0] = 4; /* Don't care. >4 is acceptable */ + wupt_cfg.SeqxSleepTime[0] = (uint32_t)((pCfg->CalDuration)*32 + 0.5f) - 1 - 4; + wupt_cfg.SeqxWakeupTime[1] = 4-1; + wupt_cfg.SeqxSleepTime[1] = 0xffffffff; /* Don't care */ + WuptPeriod = (wupt_cfg.SeqxSleepTime[0]+1) + (wupt_cfg.SeqxWakeupTime[1]+1); + AD5940_WUPTCfg(&wupt_cfg); + + AD5940_INTCClrFlag(AFEINTSRC_ENDSEQ); + AD5940_WUPTCtrl(bTRUE); + + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_ENDSEQ) == bFALSE); + TimerCount = AD5940_SEQTimeOutRd(); + + AD5940_WUPTCtrl(bFALSE); + AD5940_WUPTTime(SEQID_0, 4, 4); /* Set it to minimum value because we don't care about sequence0 now. We only want to measure how much time MCU will need to read register */ + seqinfo.SeqId = SEQID_1; + seqinfo.SeqRamAddr = pCfg->CalSeqAddr + SEQ_LEN(SeqA) ; + seqinfo.SeqLen = SEQ_LEN(SeqBB); + seqinfo.pSeqCmd = SeqBB; + seqinfo.WriteSRAM = bTRUE; + AD5940_SEQInfoCfg(&seqinfo); + AD5940_SEQCtrlS(bTRUE); /* Enable Sequencer again */ + + AD5940_INTCClrFlag(AFEINTSRC_ENDSEQ); + AD5940_WUPTCtrl(bTRUE); + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_ENDSEQ) == bFALSE); + TimerCount2 = AD5940_SEQTimeOutRd(); + AD5940_INTCTestFlag(AFEINTC_0, AFEINTSRC_ENDSEQ); + + AD5940_WUPTCtrl(bFALSE); + AD5940_SEQCfg(&seq_cfg_backup); /* restore sequencer configuration */ + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_ENDSEQ, (INTCCfg&AFEINTSRC_ENDSEQ)?bTRUE:bFALSE); /* Restore interrupt configuration */ + AD5940_INTCClrFlag(AFEINTSRC_ENDSEQ); + //printf("Time duration:%d ", (TimerCount2 - TimerCount)); + *pFreq = pCfg->SystemClkFreq*WuptPeriod/(TimerCount2 - TimerCount); + return AD5940ERR_OK; +} + +/** + * @} Calibration + * @} Calibration_Block +*/ + +/** + * @} AD5940_Functions + * @} AD5940_Library +*/ diff --git a/components/ad5940/ad5940.h b/components/ad5940/ad5940.h new file mode 100644 index 0000000..00beec9 --- /dev/null +++ b/components/ad5940/ad5940.h @@ -0,0 +1,6175 @@ +/** + * @file ad5940.h + * @brief AD5940 library. This file contains all AD5940 library functions. + * @author ADI + * @date March 2019 + * @par Revision History: + * + * Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + * + * This software is proprietary to Analog Devices, Inc. and its licensors. + * By using this software you agree to the terms of the associated + * Analog Devices Software License Agreement. + **/ +#ifndef _AD5940_H_ +#define _AD5940_H_ +#include "math.h" +#include "stdio.h" +#include "string.h" +/** @addtogroup AD5940_Library + * @{ + */ + +/** + * Select the correct chip. + * Recommend to define this in your compiler. + * */ +// #define CHIPSEL_M355 /**< ADuCM355 */ +// #define CHIPSEL_594X /**< AD5940 or AD5941 */ + +/* library version number */ +#define AD5940LIB_VER_MAJOR 0 /**< Major number */ +#define AD5940LIB_VER_MINOR 2 /**< Minor number */ +#define AD5940LIB_VER_PATCH 1 /**< Path number */ +#define AD5940LIB_VER \ + (AD5940LIB_VER_MAJOR << 16) | (AD5940LIB_VER_MINOR << 8) | \ + (AD5940LIB_VER_PATCH) + +#define CHIPSEL_594X + +// #define ADI_DEBUG /**< Comment this line to remove debug info. */ + +#ifdef ADI_DEBUG +#define ADI_Print printf /**< Select the method to print out debug message */ +#endif + +#if defined(CHIPSEL_M355) && defined(CHIPSEL_594X) +#error Please select the correct chip by define CHIPSEL_M355 or CHIPSEL_594X. +#endif + +#if !defined(CHIPSEL_M355) && !defined(CHIPSEL_594X) +#error Please select the correct chip by define CHIPSEL_M355 or CHIPSEL_594X. +#endif + +/** + * @cond + * @defgroup AD5940RegistersBitfields + * @brief All AD5940 registers and bitfields definition. + * @{ + */ +// #if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +// #endif /* _LANGUAGE_C */ + +#ifndef __ADI_GENERATED_DEF_HEADERS__ +#define __ADI_GENERATED_DEF_HEADERS__ 1 +#endif + +#define __ADI_HAS_AGPIO__ 1 +#define __ADI_HAS_ALLON__ 1 +#define __ADI_HAS_INTC__ 1 +#define __ADI_HAS_AFECON__ 1 +#define __ADI_HAS_WUPTMR__ 1 +#define __ADI_HAS_AFE__ 1 + +/* ============================================================================================================================ + GPIO + ============================================================================================================================ + */ + +/* ============================================================================================================================ + AGPIO + ============================================================================================================================ + */ +#define REG_AGPIO_GP0CON_RESET 0x00000000 /* Reset Value for GP0CON */ +#define REG_AGPIO_GP0CON 0x00000000 /* AGPIO GPIO Port 0 Configuration */ +#define REG_AGPIO_GP0OEN_RESET 0x00000000 /* Reset Value for GP0OEN */ +#define REG_AGPIO_GP0OEN 0x00000004 /* AGPIO GPIO Port 0 Output Enable */ +#define REG_AGPIO_GP0PE_RESET 0x00000000 /* Reset Value for GP0PE */ +#define REG_AGPIO_GP0PE \ + 0x00000008 /* AGPIO GPIO Port 0 Pullup/Pulldown Enable */ +#define REG_AGPIO_GP0IEN_RESET 0x00000000 /* Reset Value for GP0IEN */ +#define REG_AGPIO_GP0IEN 0x0000000C /* AGPIO GPIO Port 0 Input Path Enable */ +#define REG_AGPIO_GP0IN_RESET 0x00000000 /* Reset Value for GP0IN */ +#define REG_AGPIO_GP0IN \ + 0x00000010 /* AGPIO GPIO Port 0 Registered Data Input */ +#define REG_AGPIO_GP0OUT_RESET 0x00000000 /* Reset Value for GP0OUT */ +#define REG_AGPIO_GP0OUT 0x00000014 /* AGPIO GPIO Port 0 Data Output */ +#define REG_AGPIO_GP0SET_RESET 0x00000000 /* Reset Value for GP0SET */ +#define REG_AGPIO_GP0SET 0x00000018 /* AGPIO GPIO Port 0 Data Out Set */ +#define REG_AGPIO_GP0CLR_RESET 0x00000000 /* Reset Value for GP0CLR */ +#define REG_AGPIO_GP0CLR 0x0000001C /* AGPIO GPIO Port 0 Data Out Clear */ +#define REG_AGPIO_GP0TGL_RESET 0x00000000 /* Reset Value for GP0TGL */ +#define REG_AGPIO_GP0TGL 0x00000020 /* AGPIO GPIO Port 0 Pin Toggle */ + +/* ============================================================================================================================ + AGPIO Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0CON_PIN7CFG 14 /* P0.7 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN6CFG 12 /* P0.6 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN5CFG 10 /* P0.5 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN4CFG 8 /* P0.4 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN3CFG 6 /* P0.3 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN2CFG 4 /* P0.2 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN1CFG 2 /* P0.1 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN0CFG 0 /* P0.0 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN7CFG 0x0000C000 /* P0.7 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN6CFG 0x00003000 /* P0.6 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN5CFG 0x00000C00 /* P0.5 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN4CFG 0x00000300 /* P0.4 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN3CFG 0x000000C0 /* P0.3 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN2CFG 0x00000030 /* P0.2 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN1CFG 0x0000000C /* P0.1 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN0CFG 0x00000003 /* P0.0 Configuration Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0OEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0OEN_OEN 0 /* Pin Output Drive Enable */ +#define BITM_AGPIO_GP0OEN_OEN 0x000000FF /* Pin Output Drive Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0PE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0PE_PE 0 /* Pin Pull Enable */ +#define BITM_AGPIO_GP0PE_PE 0x000000FF /* Pin Pull Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0IEN_IEN 0 /* Input Path Enable */ +#define BITM_AGPIO_GP0IEN_IEN 0x000000FF /* Input Path Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0IN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0IN_IN 0 /* Registered Data Input */ +#define BITM_AGPIO_GP0IN_IN 0x000000FF /* Registered Data Input */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0OUT_OUT 0 /* Data Out */ +#define BITM_AGPIO_GP0OUT_OUT 0x000000FF /* Data Out */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0SET_SET 0 /* Set the Output HIGH */ +#define BITM_AGPIO_GP0SET_SET 0x000000FF /* Set the Output HIGH */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0CLR_CLR 0 /* Set the Output LOW */ +#define BITM_AGPIO_GP0CLR_CLR 0x000000FF /* Set the Output LOW */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0TGL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0TGL_TGL 0 /* Toggle the Output */ +#define BITM_AGPIO_GP0TGL_TGL 0x000000FF /* Toggle the Output */ + +/* ============================================================================================================================ + + ============================================================================================================================ + */ + +/* ============================================================================================================================ + AFECON + ============================================================================================================================ + */ +#define REG_AFECON_ADIID_RESET 0x00000000 /* Reset Value for ADIID */ +#define REG_AFECON_ADIID 0x00000400 /* AFECON ADI Identification */ +#define REG_AFECON_CHIPID_RESET 0x00000000 /* Reset Value for CHIPID */ +#define REG_AFECON_CHIPID 0x00000404 /* AFECON Chip Identification */ +#define REG_AFECON_CLKCON0_RESET 0x00000441 /* Reset Value for CLKCON0 */ +#define REG_AFECON_CLKCON0 0x00000408 /* AFECON Clock Divider Configuration \ + */ +#define REG_AFECON_CLKEN1_RESET 0x000002C0 /* Reset Value for CLKEN1 */ +#define REG_AFECON_CLKEN1 0x00000410 /* AFECON Clock Gate Enable */ +#define REG_AFECON_CLKSEL_RESET 0x00000000 /* Reset Value for CLKSEL */ +#define REG_AFECON_CLKSEL 0x00000414 /* AFECON Clock Select */ +#define REG_AFECON_CLKCON0KEY_RESET \ + 0x00000000 /* Reset Value for CLKCON0KEY */ +#define REG_AFECON_CLKCON0KEY \ + 0x00000420 /* AFECON Enable Clock Division to 8Mhz,4Mhz and 2Mhz */ +#define REG_AFECON_SWRSTCON_RESET \ + 0x00000001 /* Reset Value for SWRSTCON */ +#define REG_AFECON_SWRSTCON 0x00000424 /* AFECON Software Reset */ +#define REG_AFECON_TRIGSEQ_RESET 0x00000000 /* Reset Value for TRIGSEQ */ +#define REG_AFECON_TRIGSEQ 0x00000430 /* AFECON Trigger Sequence */ + +/* ============================================================================================================================ + AFECON Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_ADIID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_ADIID_ADIID 0 /* ADI Identifier. */ +#define BITM_AFECON_ADIID_ADIID 0x0000FFFF /* ADI Identifier. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CHIPID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_CHIPID_PARTID 4 /* Part Identifier */ +#define BITP_AFECON_CHIPID_REVISION 0 /* Silicon Revision Number */ +#define BITM_AFECON_CHIPID_PARTID 0x0000FFF0 /* Part Identifier */ +#define BITM_AFECON_CHIPID_REVISION 0x0000000F /* Silicon Revision Number */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKCON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_CLKCON0_SFFTCLKDIVCNT \ + 10 /* SFFT Clock Divider Configuration */ +#define BITP_AFECON_CLKCON0_ADCCLKDIV 6 /* ADC Clock Divider Configuration */ +#define BITP_AFECON_CLKCON0_SYSCLKDIV \ + 0 /* System Clock Divider Configuration */ +#define BITM_AFECON_CLKCON0_SFFTCLKDIVCNT \ + 0x0000FC00 /* SFFT Clock Divider Configuration */ +#define BITM_AFECON_CLKCON0_ADCCLKDIV \ + 0x000003C0 /* ADC Clock Divider Configuration */ +#define BITM_AFECON_CLKCON0_SYSCLKDIV \ + 0x0000003F /* System Clock Divider Configuration */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKEN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_CLKEN1_GPT1DIS 7 /* GPT1 Clock Enable */ +#define BITP_AFECON_CLKEN1_GPT0DIS 6 /* GPT0 Clock Enable */ +#define BITP_AFECON_CLKEN1_ACLKDIS 5 /* ACLK Clock Enable */ +#define BITM_AFECON_CLKEN1_GPT1DIS 0x00000080 /* GPT1 Clock Enable */ +#define BITM_AFECON_CLKEN1_GPT0DIS 0x00000040 /* GPT0 Clock Enable */ +#define BITM_AFECON_CLKEN1_ACLKDIS 0x00000020 /* ACLK Clock Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKSEL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_CLKSEL_ADCCLKSEL 2 /* Select ADC Clock Source */ +#define BITP_AFECON_CLKSEL_SYSCLKSEL 0 /* Select System Clock Source */ +#define BITM_AFECON_CLKSEL_ADCCLKSEL 0x0000000C /* Select ADC Clock Source */ +#define BITM_AFECON_CLKSEL_SYSCLKSEL \ + 0x00000003 /* Select System Clock Source */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKCON0KEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_CLKCON0KEY_DIVSYSCLK_ULP_EN \ + 0 /* Enable Clock Division to 8Mhz,4Mhz and 2Mhz */ +#define BITM_AFECON_CLKCON0KEY_DIVSYSCLK_ULP_EN \ + 0x0000FFFF /* Enable Clock Division to 8Mhz,4Mhz and 2Mhz */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_SWRSTCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_SWRSTCON_SWRSTL 0 /* Software Reset */ +#define BITM_AFECON_SWRSTCON_SWRSTL 0x0000FFFF /* Software Reset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_TRIGSEQ Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_TRIGSEQ_TRIG3 3 /* Trigger Sequence 3 */ +#define BITP_AFECON_TRIGSEQ_TRIG2 2 /* Trigger Sequence 2 */ +#define BITP_AFECON_TRIGSEQ_TRIG1 1 /* Trigger Sequence 1 */ +#define BITP_AFECON_TRIGSEQ_TRIG0 0 /* Trigger Sequence 0 */ +#define BITM_AFECON_TRIGSEQ_TRIG3 0x00000008 /* Trigger Sequence 3 */ +#define BITM_AFECON_TRIGSEQ_TRIG2 0x00000004 /* Trigger Sequence 2 */ +#define BITM_AFECON_TRIGSEQ_TRIG1 0x00000002 /* Trigger Sequence 1 */ +#define BITM_AFECON_TRIGSEQ_TRIG0 0x00000001 /* Trigger Sequence 0 */ + +/* ============================================================================================================================ + AFEWDT + ============================================================================================================================ + */ +#define REG_AFEWDT_WDTLD 0x00000900 /* AFEWDT Watchdog Timer Load Value */ +#define REG_AFEWDT_WDTVALS 0x00000904 /* AFEWDT Current Count Value */ +#define REG_AFEWDT_WDTCON \ + 0x00000908 /* AFEWDT Watchdog Timer Control Register */ +#define REG_AFEWDT_WDTCLRI 0x0000090C /* AFEWDT Refresh Watchdog Register */ +#define REG_AFEWDT_WDTSTA 0x00000918 /* AFEWDT Timer Status */ +#define REG_AFEWDT_WDTMINLD 0x0000091C /* AFEWDT Minimum Load Value */ + +/* ============================================================================================================================ + AFEWDT Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTLD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFEWDT_WDTLD_LOAD 0 /* WDT Load Value */ +#define BITM_AFEWDT_WDTLD_LOAD \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* WDT Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTVALS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFEWDT_WDTVALS_CCOUNT 0 /* Current WDT Count Value. */ +#define BITM_AFEWDT_WDTVALS_CCOUNT \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Current WDT Count Value. \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFEWDT_WDTCON_RESERVED_15_11 11 /* RESERVED */ +#define BITP_AFEWDT_WDTCON_WDTIRQEN 10 /* WDT Interrupt Enable */ +#define BITP_AFEWDT_WDTCON_MINLOAD_EN 9 /* Timer Window Control */ +#define BITP_AFEWDT_WDTCON_CLKDIV2 8 /* Clock Source */ +#define BITP_AFEWDT_WDTCON_RESERVED1_7 7 /* Reserved */ +#define BITP_AFEWDT_WDTCON_MDE 6 /* Timer Mode Select */ +#define BITP_AFEWDT_WDTCON_EN 5 /* Timer Enable */ +#define BITP_AFEWDT_WDTCON_PRE 2 /* Prescaler. */ +#define BITP_AFEWDT_WDTCON_IRQ 1 /* WDT Interrupt Enable */ +#define BITP_AFEWDT_WDTCON_PDSTOP 0 /* Power Down Stop Enable */ +#define BITM_AFEWDT_WDTCON_RESERVED_15_11 \ + (_ADI_MSK_3(0x0000F800, 0x0000F800U, uint16_t)) /* RESERVED */ +#define BITM_AFEWDT_WDTCON_WDTIRQEN \ + (_ADI_MSK_3(0x00000400, 0x00000400U, uint16_t)) /* WDT Interrupt Enable */ +#define BITM_AFEWDT_WDTCON_MINLOAD_EN \ + (_ADI_MSK_3(0x00000200, 0x00000200U, uint16_t)) /* Timer Window Control */ +#define BITM_AFEWDT_WDTCON_CLKDIV2 \ + (_ADI_MSK_3(0x00000100, 0x00000100U, uint16_t)) /* Clock Source */ +#define BITM_AFEWDT_WDTCON_RESERVED1_7 \ + (_ADI_MSK_3(0x00000080, 0x00000080U, uint16_t)) /* Reserved */ +#define BITM_AFEWDT_WDTCON_MDE \ + (_ADI_MSK_3(0x00000040, 0x00000040U, uint16_t)) /* Timer Mode Select */ +#define BITM_AFEWDT_WDTCON_EN \ + (_ADI_MSK_3(0x00000020, 0x00000020U, uint16_t)) /* Timer Enable */ +#define BITM_AFEWDT_WDTCON_PRE \ + (_ADI_MSK_3(0x0000000C, 0x0000000CU, uint16_t)) /* Prescaler. */ +#define BITM_AFEWDT_WDTCON_IRQ \ + (_ADI_MSK_3(0x00000002, 0x00000002U, uint16_t)) /* WDT Interrupt Enable */ +#define BITM_AFEWDT_WDTCON_PDSTOP \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* Power Down Stop Enable \ + */ +#define ENUM_AFEWDT_WDTCON_RESET \ + (_ADI_MSK_3(0x00000000, 0x00000000U, \ + uint16_t)) /* IRQ: Watchdog Timer timeout creates a reset. */ +#define ENUM_AFEWDT_WDTCON_INTERRUPT \ + (_ADI_MSK_3(0x00000002, 0x00000002U, \ + uint16_t)) /* IRQ: Watchdog Timer timeout creates an interrupt \ + instead of reset. */ +#define ENUM_AFEWDT_WDTCON_CONTINUE \ + (_ADI_MSK_3(0x00000000, 0x00000000U, \ + uint16_t)) /* PDSTOP: Continue Counting When In Hibernate */ +#define ENUM_AFEWDT_WDTCON_STOP \ + (_ADI_MSK_3(0x00000001, 0x00000001U, \ + uint16_t)) /* PDSTOP: Stop Counter When In Hibernate. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTCLRI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFEWDT_WDTCLRI_CLRWDG 0 /* Refresh Register */ +#define BITM_AFEWDT_WDTCLRI_CLRWDG \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Refresh Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFEWDT_WDTSTA_RESERVED_15_7 7 /* RESERVED */ +#define BITP_AFEWDT_WDTSTA_TMINLD 6 /* WDTMINLD Write Status */ +#define BITP_AFEWDT_WDTSTA_OTPWRDONE 5 /* Reset Type Status */ +#define BITP_AFEWDT_WDTSTA_LOCK 4 /* Lock Status */ +#define BITP_AFEWDT_WDTSTA_CON 3 /* WDTCON Write Status */ +#define BITP_AFEWDT_WDTSTA_TLD 2 /* WDTVAL Write Status */ +#define BITP_AFEWDT_WDTSTA_CLRI 1 /* WDTCLRI Write Status */ +#define BITP_AFEWDT_WDTSTA_IRQ 0 /* WDT Interrupt */ +#define BITM_AFEWDT_WDTSTA_RESERVED_15_7 \ + (_ADI_MSK_3(0x0000FF80, 0x0000FF80U, uint16_t)) /* RESERVED */ +#define BITM_AFEWDT_WDTSTA_TMINLD \ + (_ADI_MSK_3(0x00000040, 0x00000040U, uint16_t)) /* WDTMINLD Write Status */ +#define BITM_AFEWDT_WDTSTA_OTPWRDONE \ + (_ADI_MSK_3(0x00000020, 0x00000020U, uint16_t)) /* Reset Type Status */ +#define BITM_AFEWDT_WDTSTA_LOCK \ + (_ADI_MSK_3(0x00000010, 0x00000010U, uint16_t)) /* Lock Status */ +#define BITM_AFEWDT_WDTSTA_CON \ + (_ADI_MSK_3(0x00000008, 0x00000008U, uint16_t)) /* WDTCON Write Status */ +#define BITM_AFEWDT_WDTSTA_TLD \ + (_ADI_MSK_3(0x00000004, 0x00000004U, uint16_t)) /* WDTVAL Write Status */ +#define BITM_AFEWDT_WDTSTA_CLRI \ + (_ADI_MSK_3(0x00000002, 0x00000002U, uint16_t)) /* WDTCLRI Write Status */ +#define BITM_AFEWDT_WDTSTA_IRQ \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* WDT Interrupt */ +#define ENUM_AFEWDT_WDTSTA_OPEN \ + (_ADI_MSK_3(0x00000000, 0x00000000U, \ + uint16_t)) /* LOCK: Timer Operation Not Locked */ +#define ENUM_AFEWDT_WDTSTA_LOCKED \ + (_ADI_MSK_3(0x00000010, 0x00000010U, \ + uint16_t)) /* LOCK: Timer Enabled and Locked */ +#define ENUM_AFEWDT_WDTSTA_SYNC_COMPLETE \ + (_ADI_MSK_3(0x00000000, 0x00000000U, \ + uint16_t)) /* TLD: Arm and AFE Watchdog Clock Domains WDTLD \ + values match */ +#define ENUM_AFEWDT_WDTSTA_SYNC_IN_PROGRESS \ + (_ADI_MSK_3(0x00000004, 0x00000004U, \ + uint16_t)) /* TLD: Synchronize In Progress */ +#define ENUM_AFEWDT_WDTSTA_CLEARED \ + (_ADI_MSK_3(0x00000000, 0x00000000U, \ + uint16_t)) /* IRQ: Watchdog Timer Interrupt Not Pending */ +#define ENUM_AFEWDT_WDTSTA_PENDING \ + (_ADI_MSK_3(0x00000001, 0x00000001U, \ + uint16_t)) /* IRQ: Watchdog Timer Interrupt Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTMINLD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFEWDT_WDTMINLD_MIN_LOAD 0 /* WDT Min Load Value */ +#define BITM_AFEWDT_WDTMINLD_MIN_LOAD \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* WDT Min Load Value */ + +/* ============================================================================================================================ + Wakeup Timer + ============================================================================================================================ + */ + +/* ============================================================================================================================ + WUPTMR + ============================================================================================================================ + */ +#define REG_WUPTMR_CON_RESET 0x00000000 /* Reset Value for CON */ +#define REG_WUPTMR_CON 0x00000800 /* WUPTMR Timer Control */ +#define REG_WUPTMR_SEQORDER_RESET \ + 0x00000000 /* Reset Value for SEQORDER */ +#define REG_WUPTMR_SEQORDER 0x00000804 /* WUPTMR Order Control */ +#define REG_WUPTMR_SEQ0WUPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ0WUPL */ +#define REG_WUPTMR_SEQ0WUPL 0x00000808 /* WUPTMR SEQ0 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ0WUPH_RESET \ + 0x0000000F /* Reset Value for SEQ0WUPH */ +#define REG_WUPTMR_SEQ0WUPH 0x0000080C /* WUPTMR SEQ0 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ0SLEEPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ0SLEEPL */ +#define REG_WUPTMR_SEQ0SLEEPL 0x00000810 /* WUPTMR SEQ0 STimeL (LSB) */ +#define REG_WUPTMR_SEQ0SLEEPH_RESET \ + 0x0000000F /* Reset Value for SEQ0SLEEPH */ +#define REG_WUPTMR_SEQ0SLEEPH 0x00000814 /* WUPTMR SEQ0 STimeH (MSB) */ +#define REG_WUPTMR_SEQ1WUPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ1WUPL */ +#define REG_WUPTMR_SEQ1WUPL 0x00000818 /* WUPTMR SEQ1 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ1WUPH_RESET \ + 0x0000000F /* Reset Value for SEQ1WUPH */ +#define REG_WUPTMR_SEQ1WUPH 0x0000081C /* WUPTMR SEQ1 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ1SLEEPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ1SLEEPL */ +#define REG_WUPTMR_SEQ1SLEEPL 0x00000820 /* WUPTMR SEQ1 STimeL (LSB) */ +#define REG_WUPTMR_SEQ1SLEEPH_RESET \ + 0x0000000F /* Reset Value for SEQ1SLEEPH */ +#define REG_WUPTMR_SEQ1SLEEPH 0x00000824 /* WUPTMR SEQ1 STimeH (MSB) */ +#define REG_WUPTMR_SEQ2WUPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ2WUPL */ +#define REG_WUPTMR_SEQ2WUPL 0x00000828 /* WUPTMR SEQ2 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ2WUPH_RESET \ + 0x0000000F /* Reset Value for SEQ2WUPH */ +#define REG_WUPTMR_SEQ2WUPH 0x0000082C /* WUPTMR SEQ2 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ2SLEEPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ2SLEEPL */ +#define REG_WUPTMR_SEQ2SLEEPL 0x00000830 /* WUPTMR SEQ2 STimeL (LSB) */ +#define REG_WUPTMR_SEQ2SLEEPH_RESET \ + 0x0000000F /* Reset Value for SEQ2SLEEPH */ +#define REG_WUPTMR_SEQ2SLEEPH 0x00000834 /* WUPTMR SEQ2 STimeH (MSB) */ +#define REG_WUPTMR_SEQ3WUPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ3WUPL */ +#define REG_WUPTMR_SEQ3WUPL 0x00000838 /* WUPTMR SEQ3 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ3WUPH_RESET \ + 0x0000000F /* Reset Value for SEQ3WUPH */ +#define REG_WUPTMR_SEQ3WUPH 0x0000083C /* WUPTMR SEQ3 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ3SLEEPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ3SLEEPL */ +#define REG_WUPTMR_SEQ3SLEEPL 0x00000840 /* WUPTMR SEQ3 STimeL (LSB) */ +#define REG_WUPTMR_SEQ3SLEEPH_RESET \ + 0x0000000F /* Reset Value for SEQ3SLEEPH */ +#define REG_WUPTMR_SEQ3SLEEPH 0x00000844 /* WUPTMR SEQ3 STimeH (MSB) */ + +/* ============================================================================================================================ + WUPTMR Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_CON_MSKTRG \ + 6 /* Mark Sequence Trigger from Sleep Wakeup Timer */ +#define BITP_WUPTMR_CON_CLKSEL 4 /* Clock Selection */ +#define BITP_WUPTMR_CON_ENDSEQ 1 /* End Sequence */ +#define BITP_WUPTMR_CON_EN 0 /* Sleep Wake Timer Enable Bit */ +#define BITM_WUPTMR_CON_MSKTRG \ + 0x00000040 /* Mark Sequence Trigger from Sleep Wakeup Timer */ +#define BITM_WUPTMR_CON_CLKSEL 0x00000030 /* Clock Selection */ +#define BITM_WUPTMR_CON_ENDSEQ 0x0000000E /* End Sequence */ +#define BITM_WUPTMR_CON_EN 0x00000001 /* Sleep Wake Timer Enable Bit */ +#define ENUM_WUPTMR_CON_SWT32K0 0x00000000 /* CLKSEL: Internal 32kHz OSC */ +#define ENUM_WUPTMR_CON_SWTEXT0 0x00000010 /* CLKSEL: External Clock */ +#define ENUM_WUPTMR_CON_SWT32K 0x00000020 /* CLKSEL: Internal 32kHz OSC */ +#define ENUM_WUPTMR_CON_SWTEXT 0x00000030 /* CLKSEL: External Clock */ +#define ENUM_WUPTMR_CON_ENDSEQA \ + 0x00000000 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqA And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQB \ + 0x00000002 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqB And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQC \ + 0x00000004 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqC And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQD \ + 0x00000006 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqD And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQE \ + 0x00000008 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqE And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQF \ + 0x0000000A /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqF And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQG \ + 0x0000000C /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqG And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQH \ + 0x0000000E /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqH And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_SWTEN 0x00000000 /* EN: Enable Sleep Wakeup Timer */ +#define ENUM_WUPTMR_CON_SWTDIS 0x00000001 /* EN: Disable Sleep Wakeup Timer \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQORDER Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQORDER_SEQH 14 /* SEQH Config */ +#define BITP_WUPTMR_SEQORDER_SEQG 12 /* SEQG Config */ +#define BITP_WUPTMR_SEQORDER_SEQF 10 /* SEQF Config */ +#define BITP_WUPTMR_SEQORDER_SEQE 8 /* SEQE Config */ +#define BITP_WUPTMR_SEQORDER_SEQD 6 /* SEQD Config */ +#define BITP_WUPTMR_SEQORDER_SEQC 4 /* SEQC Config */ +#define BITP_WUPTMR_SEQORDER_SEQB 2 /* SEQB Config */ +#define BITP_WUPTMR_SEQORDER_SEQA 0 /* SEQA Config */ +#define BITM_WUPTMR_SEQORDER_SEQH 0x0000C000 /* SEQH Config */ +#define BITM_WUPTMR_SEQORDER_SEQG 0x00003000 /* SEQG Config */ +#define BITM_WUPTMR_SEQORDER_SEQF 0x00000C00 /* SEQF Config */ +#define BITM_WUPTMR_SEQORDER_SEQE 0x00000300 /* SEQE Config */ +#define BITM_WUPTMR_SEQORDER_SEQD 0x000000C0 /* SEQD Config */ +#define BITM_WUPTMR_SEQORDER_SEQC 0x00000030 /* SEQC Config */ +#define BITM_WUPTMR_SEQORDER_SEQB 0x0000000C /* SEQB Config */ +#define BITM_WUPTMR_SEQORDER_SEQA 0x00000003 /* SEQA Config */ +#define ENUM_WUPTMR_SEQORDER_SEQH0 0x00000000 /* SEQH: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQH1 0x00004000 /* SEQH: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQH2 0x00008000 /* SEQH: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQH3 0x0000C000 /* SEQH: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG0 0x00000000 /* SEQG: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG1 0x00001000 /* SEQG: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG2 0x00002000 /* SEQG: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG3 0x00003000 /* SEQG: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF0 0x00000000 /* SEQF: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF1 0x00000400 /* SEQF: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF2 0x00000800 /* SEQF: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF3 0x00000C00 /* SEQF: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE0 0x00000000 /* SEQE: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE1 0x00000100 /* SEQE: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE2 0x00000200 /* SEQE: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE3 0x00000300 /* SEQE: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD0 0x00000000 /* SEQD: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD1 0x00000040 /* SEQD: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD2 0x00000080 /* SEQD: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD3 0x000000C0 /* SEQD: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC0 0x00000000 /* SEQC: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC1 0x00000010 /* SEQC: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC2 0x00000020 /* SEQC: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC3 0x00000030 /* SEQC: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB0 0x00000000 /* SEQB: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB1 0x00000004 /* SEQB: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB2 0x00000008 /* SEQB: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB3 0x0000000C /* SEQB: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA0 0x00000000 /* SEQA: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA1 0x00000001 /* SEQA: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA2 0x00000002 /* SEQA: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA3 0x00000003 /* SEQA: Fill SEQ3 In */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ0WUPL_WAKEUPTIME0 0 /* Sequence 0 Sleep Period */ +#define BITM_WUPTMR_SEQ0WUPL_WAKEUPTIME0 \ + 0x0000FFFF /* Sequence 0 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ0WUPH_WAKEUPTIME0 0 /* Sequence 0 Sleep Period */ +#define BITM_WUPTMR_SEQ0WUPH_WAKEUPTIME0 \ + 0x0000000F /* Sequence 0 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ0SLEEPL_SLEEPTIME0 0 /* Sequence 0 Active Period */ +#define BITM_WUPTMR_SEQ0SLEEPL_SLEEPTIME0 \ + 0x0000FFFF /* Sequence 0 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ0SLEEPH_SLEEPTIME0 0 /* Sequence 0 Active Period */ +#define BITM_WUPTMR_SEQ0SLEEPH_SLEEPTIME0 \ + 0x0000000F /* Sequence 0 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ1WUPL_WAKEUPTIME 0 /* Sequence 1 Sleep Period */ +#define BITM_WUPTMR_SEQ1WUPL_WAKEUPTIME \ + 0x0000FFFF /* Sequence 1 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ1WUPH_WAKEUPTIME 0 /* Sequence 1 Sleep Period */ +#define BITM_WUPTMR_SEQ1WUPH_WAKEUPTIME \ + 0x0000000F /* Sequence 1 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ1SLEEPL_SLEEPTIME1 0 /* Sequence 1 Active Period */ +#define BITM_WUPTMR_SEQ1SLEEPL_SLEEPTIME1 \ + 0x0000FFFF /* Sequence 1 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ1SLEEPH_SLEEPTIME1 0 /* Sequence 1 Active Period */ +#define BITM_WUPTMR_SEQ1SLEEPH_SLEEPTIME1 \ + 0x0000000F /* Sequence 1 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ2WUPL_WAKEUPTIME2 0 /* Sequence 2 Sleep Period */ +#define BITM_WUPTMR_SEQ2WUPL_WAKEUPTIME2 \ + 0x0000FFFF /* Sequence 2 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ2WUPH_WAKEUPTIME2 0 /* Sequence 2 Sleep Period */ +#define BITM_WUPTMR_SEQ2WUPH_WAKEUPTIME2 \ + 0x0000000F /* Sequence 2 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ2SLEEPL_SLEEPTIME2 0 /* Sequence 2 Active Period */ +#define BITM_WUPTMR_SEQ2SLEEPL_SLEEPTIME2 \ + 0x0000FFFF /* Sequence 2 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ2SLEEPH_SLEEPTIME2 0 /* Sequence 2 Active Period */ +#define BITM_WUPTMR_SEQ2SLEEPH_SLEEPTIME2 \ + 0x0000000F /* Sequence 2 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ3WUPL_WAKEUPTIME3 0 /* Sequence 3 Sleep Period */ +#define BITM_WUPTMR_SEQ3WUPL_WAKEUPTIME3 \ + 0x0000FFFF /* Sequence 3 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ3WUPH_WAKEUPTIME3 0 /* Sequence 3 Sleep Period */ +#define BITM_WUPTMR_SEQ3WUPH_WAKEUPTIME3 \ + 0x0000000F /* Sequence 3 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ3SLEEPL_SLEEPTIME3 0 /* Sequence 3 Active Period */ +#define BITM_WUPTMR_SEQ3SLEEPL_SLEEPTIME3 \ + 0x0000FFFF /* Sequence 3 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ3SLEEPH_SLEEPTIME3 0 /* Sequence 3 Active Period */ +#define BITM_WUPTMR_SEQ3SLEEPH_SLEEPTIME3 \ + 0x0000000F /* Sequence 3 Active Period */ + +/* ============================================================================================================================ + Always On Register + ============================================================================================================================ + */ + +/* ============================================================================================================================ + ALLON + ============================================================================================================================ + */ +#define REG_ALLON_PWRMOD_RESET 0x00000001 /* Reset Value for PWRMOD */ +#define REG_ALLON_PWRMOD 0x00000A00 /* ALLON Power Modes */ +#define REG_ALLON_PWRKEY_RESET 0x00000000 /* Reset Value for PWRKEY */ +#define REG_ALLON_PWRKEY 0x00000A04 /* ALLON Key Protection for PWRMOD */ +#define REG_ALLON_OSCKEY_RESET 0x00000000 /* Reset Value for OSCKEY */ +#define REG_ALLON_OSCKEY 0x00000A0C /* ALLON Key Protection for OSCCON */ +#define REG_ALLON_OSCCON_RESET 0x00000003 /* Reset Value for OSCCON */ +#define REG_ALLON_OSCCON 0x00000A10 /* ALLON Oscillator Control */ +#define REG_ALLON_TMRCON_RESET 0x00000000 /* Reset Value for TMRCON */ +#define REG_ALLON_TMRCON 0x00000A1C /* ALLON Timer Wakeup Configuration */ +#define REG_ALLON_EI0CON_RESET 0x00000000 /* Reset Value for EI0CON */ +#define REG_ALLON_EI0CON \ + 0x00000A20 /* ALLON External Interrupt Configuration 0 */ +#define REG_ALLON_EI1CON_RESET 0x00000000 /* Reset Value for EI1CON */ +#define REG_ALLON_EI1CON \ + 0x00000A24 /* ALLON External Interrupt Configuration 1 */ +#define REG_ALLON_EI2CON_RESET 0x00000000 /* Reset Value for EI2CON */ +#define REG_ALLON_EI2CON \ + 0x00000A28 /* ALLON External Interrupt Configuration 2 */ +#define REG_ALLON_EICLR_RESET 0x0000C000 /* Reset Value for EICLR */ +#define REG_ALLON_EICLR 0x00000A30 /* ALLON External Interrupt Clear */ +#define REG_ALLON_RSTSTA_RESET 0x00000000 /* Reset Value for RSTSTA */ +#define REG_ALLON_RSTSTA 0x00000A40 /* ALLON Reset Status */ +#define REG_ALLON_RSTCONKEY_RESET \ + 0x00000000 /* Reset Value for RSTCONKEY */ +#define REG_ALLON_RSTCONKEY \ + 0x00000A5C /* ALLON Key Protection for RSTCON Register */ +#define REG_ALLON_LOSCTST_RESET 0x0000008F /* Reset Value for LOSCTST */ +#define REG_ALLON_LOSCTST 0x00000A6C /* ALLON Internal LF Oscillator Test */ +#define REG_ALLON_CLKEN0_RESET 0x00000004 /* Reset Value for CLKEN0 */ +#define REG_ALLON_CLKEN0 0x00000A70 /* ALLON 32KHz Peripheral Clock Enable */ + +/* ============================================================================================================================ + ALLON Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_PWRMOD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_PWRMOD_RAMRETEN 15 /* Retention for RAM */ +#define BITP_ALLON_PWRMOD_ADCRETEN \ + 14 /* Keep ADC Power Switch on in Hibernate */ +#define BITP_ALLON_PWRMOD_SEQSLPEN 3 /* Auto Sleep by Sequencer Command */ +#define BITP_ALLON_PWRMOD_TMRSLPEN 2 /* Auto Sleep by Sleep Wakeup Timer */ +#define BITP_ALLON_PWRMOD_PWRMOD 0 /* Power Mode Control Bits */ +#define BITM_ALLON_PWRMOD_RAMRETEN 0x00008000 /* Retention for RAM */ +#define BITM_ALLON_PWRMOD_ADCRETEN \ + 0x00004000 /* Keep ADC Power Switch on in Hibernate */ +#define BITM_ALLON_PWRMOD_SEQSLPEN \ + 0x00000008 /* Auto Sleep by Sequencer Command */ +#define BITM_ALLON_PWRMOD_TMRSLPEN \ + 0x00000004 /* Auto Sleep by Sleep Wakeup Timer */ +#define BITM_ALLON_PWRMOD_PWRMOD 0x00000003 /* Power Mode Control Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_PWRKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_PWRKEY_PWRKEY 0 /* PWRMOD Key Register */ +#define BITM_ALLON_PWRKEY_PWRKEY 0x0000FFFF /* PWRMOD Key Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_OSCKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_OSCKEY_OSCKEY 0 /* Oscillator Control Key Register. */ +#define BITM_ALLON_OSCKEY_OSCKEY \ + 0x0000FFFF /* Oscillator Control Key Register. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_OSCCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_OSCCON_HFXTALOK 10 /* Status of HFXTAL Oscillator */ +#define BITP_ALLON_OSCCON_HFOSCOK 9 /* Status of HFOSC Oscillator */ +#define BITP_ALLON_OSCCON_LFOSCOK 8 /* Status of LFOSC Oscillator */ +#define BITP_ALLON_OSCCON_HFXTALEN \ + 2 /* High Frequency Crystal Oscillator Enable */ +#define BITP_ALLON_OSCCON_HFOSCEN \ + 1 /* High Frequency Internal Oscillator Enable */ +#define BITP_ALLON_OSCCON_LFOSCEN \ + 0 /* Low Frequency Internal Oscillator Enable */ +#define BITM_ALLON_OSCCON_HFXTALOK 0x00000400 /* Status of HFXTAL Oscillator \ + */ +#define BITM_ALLON_OSCCON_HFOSCOK 0x00000200 /* Status of HFOSC Oscillator */ +#define BITM_ALLON_OSCCON_LFOSCOK 0x00000100 /* Status of LFOSC Oscillator */ +#define BITM_ALLON_OSCCON_HFXTALEN \ + 0x00000004 /* High Frequency Crystal Oscillator Enable */ +#define BITM_ALLON_OSCCON_HFOSCEN \ + 0x00000002 /* High Frequency Internal Oscillator Enable */ +#define BITM_ALLON_OSCCON_LFOSCEN \ + 0x00000001 /* Low Frequency Internal Oscillator Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_TMRCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_TMRCON_TMRINTEN 0 /* Enable Wakeup Timer */ +#define BITM_ALLON_TMRCON_TMRINTEN 0x00000001 /* Enable Wakeup Timer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EI0CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_EI0CON_IRQ3EN 15 /* External Interrupt 3 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ3MDE 12 /* External Interrupt 3 Mode Registers \ + */ +#define BITP_ALLON_EI0CON_IRQ2EN 11 /* External Interrupt 2 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ2MDE 8 /* External Interrupt 2 Mode Registers */ +#define BITP_ALLON_EI0CON_IRQ1EN 7 /* External Interrupt 1 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ1MDE 4 /* External Interrupt 1 Mode Registers */ +#define BITP_ALLON_EI0CON_IRQ0EN 3 /* External Interrupt 0 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ0MDE 0 /* External Interrupt 0 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ3EN \ + 0x00008000 /* External Interrupt 3 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ3MDE \ + 0x00007000 /* External Interrupt 3 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ2EN \ + 0x00000800 /* External Interrupt 2 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ2MDE \ + 0x00000700 /* External Interrupt 2 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ1EN \ + 0x00000080 /* External Interrupt 1 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ1MDE \ + 0x00000070 /* External Interrupt 1 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ0EN \ + 0x00000008 /* External Interrupt 0 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ0MDE \ + 0x00000007 /* External Interrupt 0 Mode Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EI1CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_EI1CON_IRQ7EN 15 /* External Interrupt 7 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ7MDE 12 /* External Interrupt 7 Mode Registers \ + */ +#define BITP_ALLON_EI1CON_IRQ6EN 11 /* External Interrupt 6 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ6MDE 8 /* External Interrupt 6 Mode Registers */ +#define BITP_ALLON_EI1CON_IRQ5EN 7 /* External Interrupt 5 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ5MDE 4 /* External Interrupt 5 Mode Registers */ +#define BITP_ALLON_EI1CON_IRQ4EN 3 /* External Interrupt 4 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ4MDE 0 /* External Interrupt 4 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ7EN \ + 0x00008000 /* External Interrupt 7 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ7MDE \ + 0x00007000 /* External Interrupt 7 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ6EN \ + 0x00000800 /* External Interrupt 6 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ6MDE \ + 0x00000700 /* External Interrupt 6 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ5EN \ + 0x00000080 /* External Interrupt 5 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ5MDE \ + 0x00000070 /* External Interrupt 5 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ4EN \ + 0x00000008 /* External Interrupt 4 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ4MDE \ + 0x00000007 /* External Interrupt 4 Mode Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EI2CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_EI2CON_BUSINTEN 3 /* BUS Interrupt Detection Enable Bit */ +#define BITP_ALLON_EI2CON_BUSINTMDE \ + 0 /* BUS Interrupt Detection Mode Registers */ +#define BITM_ALLON_EI2CON_BUSINTEN \ + 0x00000008 /* BUS Interrupt Detection Enable Bit */ +#define BITM_ALLON_EI2CON_BUSINTMDE \ + 0x00000007 /* BUS Interrupt Detection Mode Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EICLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_EICLR_AUTCLRBUSEN \ + 15 /* Enable Auto Clear of Bus Interrupt */ +#define BITP_ALLON_EICLR_BUSINT 8 /* BUS Interrupt */ +#define BITM_ALLON_EICLR_AUTCLRBUSEN \ + 0x00008000 /* Enable Auto Clear of Bus Interrupt */ +#define BITM_ALLON_EICLR_BUSINT 0x00000100 /* BUS Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_RSTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_RSTSTA_PINSWRST 4 /* Software Reset Pin */ +#define BITP_ALLON_RSTSTA_MMRSWRST 3 /* MMR Software Reset */ +#define BITP_ALLON_RSTSTA_WDRST 2 /* Watchdog Timeout */ +#define BITP_ALLON_RSTSTA_EXTRST 1 /* External Reset */ +#define BITP_ALLON_RSTSTA_POR 0 /* Power-on Reset */ +#define BITM_ALLON_RSTSTA_PINSWRST 0x00000010 /* Software Reset Pin */ +#define BITM_ALLON_RSTSTA_MMRSWRST 0x00000008 /* MMR Software Reset */ +#define BITM_ALLON_RSTSTA_WDRST 0x00000004 /* Watchdog Timeout */ +#define BITM_ALLON_RSTSTA_EXTRST 0x00000002 /* External Reset */ +#define BITM_ALLON_RSTSTA_POR 0x00000001 /* Power-on Reset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_RSTCONKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_RSTCONKEY_KEY 0 /* Reset Control Key Register */ +#define BITM_ALLON_RSTCONKEY_KEY 0x0000FFFF /* Reset Control Key Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_LOSCTST Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_LOSCTST_TRIM 0 /* Trim Caps to Adjust Frequency. */ +#define BITM_ALLON_LOSCTST_TRIM 0x0000000F /* Trim Caps to Adjust Frequency. \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_CLKEN0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_CLKEN0_TIACHPDIS 2 /* TIA Chop Clock Disable */ +#define BITP_ALLON_CLKEN0_SLPWUTDIS 1 /* Sleep/Wakeup Timer Clock Disable */ +#define BITP_ALLON_CLKEN0_WDTDIS 0 /* Watch Dog Timer Clock Disable */ +#define BITM_ALLON_CLKEN0_TIACHPDIS 0x00000004 /* TIA Chop Clock Disable */ +#define BITM_ALLON_CLKEN0_SLPWUTDIS \ + 0x00000002 /* Sleep/Wakeup Timer Clock Disable */ +#define BITM_ALLON_CLKEN0_WDTDIS 0x00000001 /* Watch Dog Timer Clock Disable \ + */ + +/* ============================================================================================================================ + General Purpose Timer + ============================================================================================================================ + */ + +/* ============================================================================================================================ + AGPT0 + ============================================================================================================================ + */ +#define REG_AGPT0_LD0 0x00000D00 /* AGPT0 16-bit Load Value Register. */ +#define REG_AGPT0_VAL0 0x00000D04 /* AGPT0 16-Bit Timer Value Register. */ +#define REG_AGPT0_CON0 0x00000D08 /* AGPT0 Control Register. */ +#define REG_AGPT0_CLRI0 0x00000D0C /* AGPT0 Clear Interrupt Register. */ +#define REG_AGPT0_CAP0 0x00000D10 /* AGPT0 Capture Register. */ +#define REG_AGPT0_ALD0 0x00000D14 /* AGPT0 16-Bit Load Value, Asynchronous. \ + */ +#define REG_AGPT0_AVAL0 \ + 0x00000D18 /* AGPT0 16-Bit Timer Value, Asynchronous Register. */ +#define REG_AGPT0_STA0 0x00000D1C /* AGPT0 Status Register. */ +#define REG_AGPT0_PWMCON0 0x00000D20 /* AGPT0 PWM Control Register. */ +#define REG_AGPT0_PWMMAT0 0x00000D24 /* AGPT0 PWM Match Value Register. */ +#define REG_AGPT0_INTEN 0x00000D28 /* AGPT0 Interrupt Enable */ + +/* ============================================================================================================================ + AGPT0 Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_LD0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_LD0_LOAD 0 /* Load Value */ +#define BITM_AGPT0_LD0_LOAD \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_VAL0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_VAL0_VAL 0 /* Current Count */ +#define BITM_AGPT0_VAL0_VAL \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Current Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_CON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_CON0_SYNCBYP 15 /* Synchronization Bypass */ +#define BITP_AGPT0_CON0_RSTEN 14 /* Counter and Prescale Reset Enable */ +#define BITP_AGPT0_CON0_EVTEN 13 /* Event Select */ +#define BITP_AGPT0_CON0_EVENT 8 /* Event Select Range */ +#define BITP_AGPT0_CON0_RLD 7 /* Reload Control */ +#define BITP_AGPT0_CON0_CLK 5 /* Clock Select */ +#define BITP_AGPT0_CON0_ENABLE 4 /* Timer Enable */ +#define BITP_AGPT0_CON0_MOD 3 /* Timer Mode */ +#define BITP_AGPT0_CON0_UP 2 /* Count up */ +#define BITP_AGPT0_CON0_PRE 0 /* Prescaler */ +#define BITM_AGPT0_CON0_SYNCBYP \ + (_ADI_MSK_3(0x00008000, 0x00008000U, uint16_t)) /* Synchronization Bypass \ + */ +#define BITM_AGPT0_CON0_RSTEN \ + (_ADI_MSK_3(0x00004000, 0x00004000U, \ + uint16_t)) /* Counter and Prescale Reset Enable */ +#define BITM_AGPT0_CON0_EVTEN \ + (_ADI_MSK_3(0x00002000, 0x00002000U, uint16_t)) /* Event Select */ +#define BITM_AGPT0_CON0_EVENT \ + (_ADI_MSK_3(0x00001F00, 0x00001F00U, uint16_t)) /* Event Select Range */ +#define BITM_AGPT0_CON0_RLD \ + (_ADI_MSK_3(0x00000080, 0x00000080U, uint16_t)) /* Reload Control */ +#define BITM_AGPT0_CON0_CLK \ + (_ADI_MSK_3(0x00000060, 0x00000060U, uint16_t)) /* Clock Select */ +#define BITM_AGPT0_CON0_ENABLE \ + (_ADI_MSK_3(0x00000010, 0x00000010U, uint16_t)) /* Timer Enable */ +#define BITM_AGPT0_CON0_MOD \ + (_ADI_MSK_3(0x00000008, 0x00000008U, uint16_t)) /* Timer Mode */ +#define BITM_AGPT0_CON0_UP \ + (_ADI_MSK_3(0x00000004, 0x00000004U, uint16_t)) /* Count up */ +#define BITM_AGPT0_CON0_PRE \ + (_ADI_MSK_3(0x00000003, 0x00000003U, uint16_t)) /* Prescaler */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_CLRI0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_CLRI0_CAP 1 /* Clear Captured Event Interrupt */ +#define BITP_AGPT0_CLRI0_TMOUT 0 /* Clear Timeout Interrupt */ +#define BITM_AGPT0_CLRI0_CAP \ + (_ADI_MSK_3(0x00000002, 0x00000002U, \ + uint16_t)) /* Clear Captured Event Interrupt */ +#define BITM_AGPT0_CLRI0_TMOUT \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* Clear Timeout Interrupt \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_CAP0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_CAP0_CAP 0 /* 16-bit Captured Value */ +#define BITM_AGPT0_CAP0_CAP \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* 16-bit Captured Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_ALD0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_ALD0_ALOAD 0 /* Load Value, Asynchronous */ +#define BITM_AGPT0_ALD0_ALOAD \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Load Value, Asynchronous \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_AVAL0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_AVAL0_AVAL 0 /* Counter Value */ +#define BITM_AGPT0_AVAL0_AVAL \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Counter Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_STA0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_STA0_RSTCNT 8 /* Counter Reset Occurring */ +#define BITP_AGPT0_STA0_PDOK 7 /* Clear Interrupt Register Synchronization */ +#define BITP_AGPT0_STA0_BUSY 6 /* Timer Busy */ +#define BITP_AGPT0_STA0_CAP 1 /* Capture Event Pending */ +#define BITP_AGPT0_STA0_TMOUT 0 /* Timeout Event Occurred */ +#define BITM_AGPT0_STA0_RSTCNT \ + (_ADI_MSK_3(0x00000100, 0x00000100U, uint16_t)) /* Counter Reset Occurring \ + */ +#define BITM_AGPT0_STA0_PDOK \ + (_ADI_MSK_3(0x00000080, 0x00000080U, \ + uint16_t)) /* Clear Interrupt Register Synchronization */ +#define BITM_AGPT0_STA0_BUSY \ + (_ADI_MSK_3(0x00000040, 0x00000040U, uint16_t)) /* Timer Busy */ +#define BITM_AGPT0_STA0_CAP \ + (_ADI_MSK_3(0x00000002, 0x00000002U, uint16_t)) /* Capture Event Pending */ +#define BITM_AGPT0_STA0_TMOUT \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* Timeout Event Occurred \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_PWMCON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_PWMCON0_IDLE 1 /* PWM Idle State */ +#define BITP_AGPT0_PWMCON0_MATCHEN 0 /* PWM Match Enabled */ +#define BITM_AGPT0_PWMCON0_IDLE \ + (_ADI_MSK_3(0x00000002, 0x00000002U, uint16_t)) /* PWM Idle State */ +#define BITM_AGPT0_PWMCON0_MATCHEN \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* PWM Match Enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_PWMMAT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_PWMMAT0_MATCHVAL 0 /* PWM Match Value */ +#define BITM_AGPT0_PWMMAT0_MATCHVAL \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* PWM Match Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_INTEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_INTEN_INTEN 0 /* Interrupt Enable */ +#define BITM_AGPT0_INTEN_INTEN \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* Interrupt Enable */ + +/* ============================================================================================================================ + General Purpose Timer + ============================================================================================================================ + */ + +/* ============================================================================================================================ + AGPT1 + ============================================================================================================================ + */ +#define REG_AGPT1_LD1 0x00000E00 /* AGPT1 16-bit Load Value Register */ +#define REG_AGPT1_VAL1 0x00000E04 /* AGPT1 16-bit Timer Value Register */ +#define REG_AGPT1_CON1 0x00000E08 /* AGPT1 Control Register */ +#define REG_AGPT1_CLRI1 0x00000E0C /* AGPT1 Clear Interrupt Register */ +#define REG_AGPT1_CAP1 0x00000E10 /* AGPT1 Capture Register */ +#define REG_AGPT1_ALD1 \ + 0x00000E14 /* AGPT1 16-bit Load Value, Asynchronous Register */ +#define REG_AGPT1_AVAL1 \ + 0x00000E18 /* AGPT1 16-bit Timer Value, Asynchronous Register */ +#define REG_AGPT1_STA1 0x00000E1C /* AGPT1 Status Register */ +#define REG_AGPT1_PWMCON1 0x00000E20 /* AGPT1 PWM Control Register */ +#define REG_AGPT1_PWMMAT1 0x00000E24 /* AGPT1 PWM Match Value Register */ +#define REG_AGPT1_INTEN1 0x00000E28 /* AGPT1 Interrupt Enable */ + +/* ============================================================================================================================ + AGPT1 Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_LD1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_LD1_LOAD 0 /* Load Value */ +#define BITM_AGPT1_LD1_LOAD \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_VAL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_VAL1_VAL 0 /* Current Count */ +#define BITM_AGPT1_VAL1_VAL \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Current Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_CON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_CON1_SYNCBYP 15 /* Synchronization Bypass */ +#define BITP_AGPT1_CON1_RSTEN 14 /* Counter and Prescale Reset Enable */ +#define BITP_AGPT1_CON1_EVENTEN 13 /* Event Select */ +#define BITP_AGPT1_CON1_EVENT 8 /* Event Select Range */ +#define BITP_AGPT1_CON1_RLD 7 /* Reload Control */ +#define BITP_AGPT1_CON1_CLK 5 /* Clock Select */ +#define BITP_AGPT1_CON1_ENABLE 4 /* Timer Enable */ +#define BITP_AGPT1_CON1_MOD 3 /* Timer Mode */ +#define BITP_AGPT1_CON1_UP 2 /* Count up */ +#define BITP_AGPT1_CON1_PRE 0 /* Prescaler */ +#define BITM_AGPT1_CON1_SYNCBYP \ + (_ADI_MSK_3(0x00008000, 0x00008000U, uint16_t)) /* Synchronization Bypass \ + */ +#define BITM_AGPT1_CON1_RSTEN \ + (_ADI_MSK_3(0x00004000, 0x00004000U, \ + uint16_t)) /* Counter and Prescale Reset Enable */ +#define BITM_AGPT1_CON1_EVENTEN \ + (_ADI_MSK_3(0x00002000, 0x00002000U, uint16_t)) /* Event Select */ +#define BITM_AGPT1_CON1_EVENT \ + (_ADI_MSK_3(0x00001F00, 0x00001F00U, uint16_t)) /* Event Select Range */ +#define BITM_AGPT1_CON1_RLD \ + (_ADI_MSK_3(0x00000080, 0x00000080U, uint16_t)) /* Reload Control */ +#define BITM_AGPT1_CON1_CLK \ + (_ADI_MSK_3(0x00000060, 0x00000060U, uint16_t)) /* Clock Select */ +#define BITM_AGPT1_CON1_ENABLE \ + (_ADI_MSK_3(0x00000010, 0x00000010U, uint16_t)) /* Timer Enable */ +#define BITM_AGPT1_CON1_MOD \ + (_ADI_MSK_3(0x00000008, 0x00000008U, uint16_t)) /* Timer Mode */ +#define BITM_AGPT1_CON1_UP \ + (_ADI_MSK_3(0x00000004, 0x00000004U, uint16_t)) /* Count up */ +#define BITM_AGPT1_CON1_PRE \ + (_ADI_MSK_3(0x00000003, 0x00000003U, uint16_t)) /* Prescaler */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_CLRI1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_CLRI1_CAP 1 /* Clear Captured Event Interrupt */ +#define BITP_AGPT1_CLRI1_TMOUT 0 /* Clear Timeout Interrupt */ +#define BITM_AGPT1_CLRI1_CAP \ + (_ADI_MSK_3(0x00000002, 0x00000002U, \ + uint16_t)) /* Clear Captured Event Interrupt */ +#define BITM_AGPT1_CLRI1_TMOUT \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* Clear Timeout Interrupt \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_CAP1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_CAP1_CAP 0 /* 16-bit Captured Value. */ +#define BITM_AGPT1_CAP1_CAP \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* 16-bit Captured Value. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_ALD1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_ALD1_ALOAD 0 /* Load Value, Asynchronous */ +#define BITM_AGPT1_ALD1_ALOAD \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Load Value, Asynchronous \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_AVAL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_AVAL1_AVAL 0 /* Counter Value */ +#define BITM_AGPT1_AVAL1_AVAL \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Counter Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_STA1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_STA1_RSTCNT 8 /* Counter Reset Occurring */ +#define BITP_AGPT1_STA1_PDOK 7 /* Clear Interrupt Register Synchronization */ +#define BITP_AGPT1_STA1_BUSY 6 /* Timer Busy */ +#define BITP_AGPT1_STA1_CAP 1 /* Capture Event Pending */ +#define BITP_AGPT1_STA1_TMOUT 0 /* Timeout Event Occurred */ +#define BITM_AGPT1_STA1_RSTCNT \ + (_ADI_MSK_3(0x00000100, 0x00000100U, uint16_t)) /* Counter Reset Occurring \ + */ +#define BITM_AGPT1_STA1_PDOK \ + (_ADI_MSK_3(0x00000080, 0x00000080U, \ + uint16_t)) /* Clear Interrupt Register Synchronization */ +#define BITM_AGPT1_STA1_BUSY \ + (_ADI_MSK_3(0x00000040, 0x00000040U, uint16_t)) /* Timer Busy */ +#define BITM_AGPT1_STA1_CAP \ + (_ADI_MSK_3(0x00000002, 0x00000002U, uint16_t)) /* Capture Event Pending */ +#define BITM_AGPT1_STA1_TMOUT \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* Timeout Event Occurred \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_PWMCON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_PWMCON1_IDLE 1 /* PWM Idle State. */ +#define BITP_AGPT1_PWMCON1_MATCHEN 0 /* PWM Match Enabled. */ +#define BITM_AGPT1_PWMCON1_IDLE \ + (_ADI_MSK_3(0x00000002, 0x00000002U, uint16_t)) /* PWM Idle State. */ +#define BITM_AGPT1_PWMCON1_MATCHEN \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* PWM Match Enabled. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_PWMMAT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_PWMMAT1_MATCHVAL 0 /* PWM Match Value */ +#define BITM_AGPT1_PWMMAT1_MATCHVAL \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* PWM Match Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_INTEN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_INTEN1_INTEN 0 /* Interrupt Enable */ +#define BITM_AGPT1_INTEN1_INTEN \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* Interrupt Enable */ + +/* ============================================================================================================================ + CRC Accelerator + ============================================================================================================================ + */ + +/* ============================================================================================================================ + AFECRC + ============================================================================================================================ + */ +#define REG_AFECRC_CTL 0x00001000 /* AFECRC CRC Control Register */ +#define REG_AFECRC_IPDATA 0x00001004 /* AFECRC Data Input. */ +#define REG_AFECRC_RESULT 0x00001008 /* AFECRC CRC Residue */ +#define REG_AFECRC_POLY 0x0000100C /* AFECRC CRC Reduction Polynomial */ +#define REG_AFECRC_IPBITS 0x00001010 /* AFECRC Input Data Bits */ +#define REG_AFECRC_IPBYTE 0x00001014 /* AFECRC Input Data Byte */ +#define REG_AFECRC_CRC_SIG_COMP \ + 0x00001020 /* AFECRC CRC Signature Compare Data Input. */ +#define REG_AFECRC_CRCINTEN \ + 0x00001024 /* AFECRC CRC Error Interrupt Enable Bit */ +#define REG_AFECRC_INTSTA \ + 0x00001028 /* AFECRC CRC Error Interrupt Status Bit */ + +/* ============================================================================================================================ + AFECRC Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_CTL_REVID 28 /* Revision ID */ +#define BITP_AFECRC_CTL_MON_EN \ + 9 /* Enable Apb32/Apb16 to Get Address/Data for CRC Calculation */ +#define BITP_AFECRC_CTL_W16SWP 4 /* Word16 Swap Enabled. */ +#define BITP_AFECRC_CTL_BYTMIRR 3 /* Byte Mirroring. */ +#define BITP_AFECRC_CTL_BITMIRR 2 /* Bit Mirroring. */ +#define BITP_AFECRC_CTL_LSBFIRST 1 /* LSB First Calculation Order */ +#define BITP_AFECRC_CTL_EN 0 /* CRC Peripheral Enable */ +#define BITM_AFECRC_CTL_REVID \ + (_ADI_MSK_3(0xF0000000, 0xF0000000UL, uint32_t)) /* Revision ID */ +#define BITM_AFECRC_CTL_MON_EN \ + (_ADI_MSK_3(0x00000200, 0x00000200UL, \ + uint32_t)) /* Enable Apb32/Apb16 to Get Address/Data for CRC \ + Calculation */ +#define BITM_AFECRC_CTL_W16SWP \ + (_ADI_MSK_3(0x00000010, 0x00000010UL, uint32_t)) /* Word16 Swap Enabled. */ +#define BITM_AFECRC_CTL_BYTMIRR \ + (_ADI_MSK_3(0x00000008, 0x00000008UL, uint32_t)) /* Byte Mirroring. */ +#define BITM_AFECRC_CTL_BITMIRR \ + (_ADI_MSK_3(0x00000004, 0x00000004UL, uint32_t)) /* Bit Mirroring. */ +#define BITM_AFECRC_CTL_LSBFIRST \ + (_ADI_MSK_3(0x00000002, 0x00000002UL, \ + uint32_t)) /* LSB First Calculation Order */ +#define BITM_AFECRC_CTL_EN \ + (_ADI_MSK_3(0x00000001, 0x00000001UL, uint32_t)) /* CRC Peripheral Enable \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_IPDATA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_IPDATA_VALUE 0 /* Data Input. */ +#define BITM_AFECRC_IPDATA_VALUE \ + (_ADI_MSK_3(0xFFFFFFFF, 0xFFFFFFFF, int32_t)) /* Data Input. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_RESULT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_RESULT_VALUE 0 /* CRC Residue */ +#define BITM_AFECRC_RESULT_VALUE \ + (_ADI_MSK_3(0xFFFFFFFF, 0xFFFFFFFF, int32_t)) /* CRC Residue */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_POLY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_POLY_VALUE 0 /* CRC Reduction Polynomial */ +#define BITM_AFECRC_POLY_VALUE \ + (_ADI_MSK_3(0xFFFFFFFF, 0xFFFFFFFFUL, \ + uint32_t)) /* CRC Reduction Polynomial */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_IPBITS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_IPBITS_DATA_BITS 0 /* Input Data Bits. */ +#define BITM_AFECRC_IPBITS_DATA_BITS \ + (_ADI_MSK_3(0x000000FF, 0x000000FFU, uint8_t)) /* Input Data Bits. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_IPBYTE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_IPBYTE_DATA_BYTE 0 /* Input Data Byte. */ +#define BITM_AFECRC_IPBYTE_DATA_BYTE \ + (_ADI_MSK_3(0x000000FF, 0x000000FFU, uint8_t)) /* Input Data Byte. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_CRC_SIG_COMP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_CRC_SIG_COMP_CRC_SIG \ + 0 /* CRC Signature Compare Data Input. */ +#define BITM_AFECRC_CRC_SIG_COMP_CRC_SIG \ + (_ADI_MSK_3(0xFFFFFFFF, 0xFFFFFFFFUL, \ + uint32_t)) /* CRC Signature Compare Data Input. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_CRCINTEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_CRCINTEN_RESERVED_31_1 1 /* Reserved */ +#define BITP_AFECRC_CRCINTEN_CRC_ERR_EN 0 /* CRC Error Interrupt Enable Bit \ + */ +#define BITM_AFECRC_CRCINTEN_RESERVED_31_1 \ + (_ADI_MSK_3(0xFFFFFFFE, 0xFFFFFFFEUL, uint32_t)) /* Reserved */ +#define BITM_AFECRC_CRCINTEN_CRC_ERR_EN \ + (_ADI_MSK_3(0x00000001, 0x00000001UL, \ + uint32_t)) /* CRC Error Interrupt Enable Bit */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_INTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_INTSTA_CRC_ERR_ST 0 /* CRC Error Interrupt Status Bit */ +#define BITM_AFECRC_INTSTA_CRC_ERR_ST \ + (_ADI_MSK_3(0x00000001, 0x00000001UL, \ + uint32_t)) /* CRC Error Interrupt Status Bit */ + +/* ============================================================================================================================ + + ============================================================================================================================ + */ + +/* ============================================================================================================================ + AFE + ============================================================================================================================ + */ +#define REG_AFE_AFECON_RESET 0x00080000 /* Reset Value for AFECON */ +#define REG_AFE_AFECON 0x00002000 /* AFE AFE Configuration */ +#define REG_AFE_SEQCON_RESET 0x00000002 /* Reset Value for SEQCON */ +#define REG_AFE_SEQCON 0x00002004 /* AFE Sequencer Configuration */ +#define REG_AFE_FIFOCON_RESET 0x00001010 /* Reset Value for FIFOCON */ +#define REG_AFE_FIFOCON 0x00002008 /* AFE FIFOs Configuration */ +#define REG_AFE_SWCON_RESET 0x0000FFFF /* Reset Value for SWCON */ +#define REG_AFE_SWCON 0x0000200C /* AFE Switch Matrix Configuration */ +#define REG_AFE_HSDACCON_RESET 0x0000001E /* Reset Value for HSDACCON */ +#define REG_AFE_HSDACCON 0x00002010 /* AFE High Speed DAC Configuration */ +#define REG_AFE_WGCON_RESET 0x00000030 /* Reset Value for WGCON */ +#define REG_AFE_WGCON 0x00002014 /* AFE Waveform Generator Configuration */ +#define REG_AFE_WGDCLEVEL1_RESET \ + 0x00000000 /* Reset Value for WGDCLEVEL1 */ +#define REG_AFE_WGDCLEVEL1 \ + 0x00002018 /* AFE Waveform Generator - Trapezoid DC Level 1 */ +#define REG_AFE_WGDCLEVEL2_RESET \ + 0x00000000 /* Reset Value for WGDCLEVEL2 */ +#define REG_AFE_WGDCLEVEL2 \ + 0x0000201C /* AFE Waveform Generator - Trapezoid DC Level 2 */ +#define REG_AFE_WGDELAY1_RESET 0x00000000 /* Reset Value for WGDELAY1 */ +#define REG_AFE_WGDELAY1 \ + 0x00002020 /* AFE Waveform Generator - Trapezoid Delay 1 Time */ +#define REG_AFE_WGSLOPE1_RESET 0x00000000 /* Reset Value for WGSLOPE1 */ +#define REG_AFE_WGSLOPE1 \ + 0x00002024 /* AFE Waveform Generator - Trapezoid Slope 1 Time */ +#define REG_AFE_WGDELAY2_RESET 0x00000000 /* Reset Value for WGDELAY2 */ +#define REG_AFE_WGDELAY2 \ + 0x00002028 /* AFE Waveform Generator - Trapezoid Delay 2 Time */ +#define REG_AFE_WGSLOPE2_RESET 0x00000000 /* Reset Value for WGSLOPE2 */ +#define REG_AFE_WGSLOPE2 \ + 0x0000202C /* AFE Waveform Generator - Trapezoid Slope 2 Time */ +#define REG_AFE_WGFCW_RESET 0x00000000 /* Reset Value for WGFCW */ +#define REG_AFE_WGFCW \ + 0x00002030 /* AFE Waveform Generator - Sinusoid Frequency Control Word */ +#define REG_AFE_WGPHASE_RESET 0x00000000 /* Reset Value for WGPHASE */ +#define REG_AFE_WGPHASE \ + 0x00002034 /* AFE Waveform Generator - Sinusoid Phase Offset */ +#define REG_AFE_WGOFFSET_RESET 0x00000000 /* Reset Value for WGOFFSET */ +#define REG_AFE_WGOFFSET \ + 0x00002038 /* AFE Waveform Generator - Sinusoid Offset */ +#define REG_AFE_WGAMPLITUDE_RESET \ + 0x00000000 /* Reset Value for WGAMPLITUDE */ +#define REG_AFE_WGAMPLITUDE \ + 0x0000203C /* AFE Waveform Generator - Sinusoid Amplitude */ +#define REG_AFE_ADCFILTERCON_RESET \ + 0x00000301 /* Reset Value for ADCFILTERCON */ +#define REG_AFE_ADCFILTERCON \ + 0x00002044 /* AFE ADC Output Filters Configuration */ +#define REG_AFE_HSDACDAT_RESET 0x00000800 /* Reset Value for HSDACDAT */ +#define REG_AFE_HSDACDAT 0x00002048 /* AFE HS DAC Code */ +#define REG_AFE_LPREFBUFCON_RESET \ + 0x00000000 /* Reset Value for LPREFBUFCON */ +#define REG_AFE_LPREFBUFCON 0x00002050 /* AFE LPREF_BUF_CON */ +#define REG_AFE_SYNCEXTDEVICE_RESET \ + 0x00000000 /* Reset Value for SYNCEXTDEVICE */ +#define REG_AFE_SYNCEXTDEVICE 0x00002054 /* AFE SYNC External Devices */ +#define REG_AFE_SEQCRC_RESET 0x00000001 /* Reset Value for SEQCRC */ +#define REG_AFE_SEQCRC 0x00002060 /* AFE Sequencer CRC Value */ +#define REG_AFE_SEQCNT_RESET 0x00000000 /* Reset Value for SEQCNT */ +#define REG_AFE_SEQCNT 0x00002064 /* AFE Sequencer Command Count */ +#define REG_AFE_SEQTIMEOUT_RESET \ + 0x00000000 /* Reset Value for SEQTIMEOUT */ +#define REG_AFE_SEQTIMEOUT 0x00002068 /* AFE Sequencer Timeout Counter */ +#define REG_AFE_DATAFIFORD_RESET \ + 0x00000000 /* Reset Value for DATAFIFORD */ +#define REG_AFE_DATAFIFORD 0x0000206C /* AFE Data FIFO Read */ +#define REG_AFE_CMDFIFOWRITE_RESET \ + 0x00000000 /* Reset Value for CMDFIFOWRITE */ +#define REG_AFE_CMDFIFOWRITE 0x00002070 /* AFE Command FIFO Write */ +#define REG_AFE_ADCDAT_RESET 0x00000000 /* Reset Value for ADCDAT */ +#define REG_AFE_ADCDAT 0x00002074 /* AFE ADC Raw Result */ +#define REG_AFE_DFTREAL_RESET 0x00000000 /* Reset Value for DFTREAL */ +#define REG_AFE_DFTREAL 0x00002078 /* AFE DFT Result, Real Part */ +#define REG_AFE_DFTIMAG_RESET 0x00000000 /* Reset Value for DFTIMAG */ +#define REG_AFE_DFTIMAG 0x0000207C /* AFE DFT Result, Imaginary Part */ +#define REG_AFE_SINC2DAT_RESET 0x00000000 /* Reset Value for SINC2DAT */ +#define REG_AFE_SINC2DAT 0x00002080 /* AFE Supply Rejection Filter Result */ +#define REG_AFE_TEMPSENSDAT_RESET \ + 0x00000000 /* Reset Value for TEMPSENSDAT */ +#define REG_AFE_TEMPSENSDAT 0x00002084 /* AFE Temperature Sensor Result */ +#define REG_AFE_AFEGENINTSTA_RESET \ + 0x00000000 /* Reset Value for AFEGENINTSTA */ +#define REG_AFE_AFEGENINTSTA 0x0000209C /* AFE Analog Generation Interrupt */ +#define REG_AFE_ADCMIN_RESET 0x00000000 /* Reset Value for ADCMIN */ +#define REG_AFE_ADCMIN 0x000020A8 /* AFE ADC Minimum Value Check */ +#define REG_AFE_ADCMINSM_RESET 0x00000000 /* Reset Value for ADCMINSM */ +#define REG_AFE_ADCMINSM 0x000020AC /* AFE ADCMIN Hysteresis Value */ +#define REG_AFE_ADCMAX_RESET 0x00000000 /* Reset Value for ADCMAX */ +#define REG_AFE_ADCMAX 0x000020B0 /* AFE ADC Maximum Value Check */ +#define REG_AFE_ADCMAXSMEN_RESET \ + 0x00000000 /* Reset Value for ADCMAXSMEN */ +#define REG_AFE_ADCMAXSMEN 0x000020B4 /* AFE ADCMAX Hysteresis Value */ +#define REG_AFE_ADCDELTA_RESET 0x00000000 /* Reset Value for ADCDELTA */ +#define REG_AFE_ADCDELTA 0x000020B8 /* AFE ADC Delta Value */ +#define REG_AFE_HPOSCCON_RESET 0x00000024 /* Reset Value for HPOSCCON */ +#define REG_AFE_HPOSCCON 0x000020BC /* AFE HPOSC Configuration */ +#define REG_AFE_DFTCON_RESET 0x00000090 /* Reset Value for DFTCON */ +#define REG_AFE_DFTCON 0x000020D0 /* AFE AFE DSP Configuration */ +#define REG_AFE_LPTIASW1 \ + 0x000020E0 /* AFE ULPTIA Switch Configuration for Channel 1 */ +#define REG_AFE_LPTIASW0_RESET 0x00000000 /* Reset Value for LPTIASW0 */ +#define REG_AFE_LPTIACON1 0x000020E8 /* AFE ULPTIA Control Bits Channel 1 */ +#define REG_AFE_LPTIASW0 \ + 0x000020E4 /* AFE ULPTIA Switch Configuration for Channel 0 */ +#define REG_AFE_LPTIACON0_RESET 0x00000003 /* Reset Value for LPTIACON0 \ + */ +#define REG_AFE_LPTIACON0 0x000020EC /* AFE ULPTIA Control Bits Channel 0 */ +#define REG_AFE_HSRTIACON_RESET 0x0000000F /* Reset Value for HSRTIACON \ + */ +#define REG_AFE_HSRTIACON 0x000020F0 /* AFE High Power RTIA Configuration */ +#define REG_AFE_DE1RESCON \ + 0x000020F4 /* AFE DE1 HSTIA Resistors Configuration */ +#define REG_AFE_DE0RESCON_RESET 0x000000FF /* Reset Value for DE0RESCON \ + */ +#define REG_AFE_DE0RESCON \ + 0x000020F8 /* AFE DE0 HSTIA Resistors Configuration */ +#define REG_AFE_HSTIACON_RESET 0x00000000 /* Reset Value for HSTIACON */ +#define REG_AFE_HSTIACON 0x000020FC /* AFE HSTIA Amplifier Configuration */ +#define REG_AFE_LPMODEKEY_RESET 0x00000000 /* Reset Value for LPMODEKEY \ + */ +#define REG_AFE_LPMODEKEY 0x0000210C /* AFE LP Mode AFE Control Lock */ +#define REG_AFE_LPMODECLKSEL_RESET \ + 0x00000000 /* Reset Value for LPMODECLKSEL */ +#define REG_AFE_LPMODECLKSEL 0x00002110 /* AFE LFSYSCLKEN */ +#define REG_AFE_LPMODECON_RESET 0x00000102 /* Reset Value for LPMODECON \ + */ +#define REG_AFE_LPMODECON 0x00002114 /* AFE LPMODECON */ +#define REG_AFE_SEQSLPLOCK_RESET \ + 0x00000000 /* Reset Value for SEQSLPLOCK */ +#define REG_AFE_SEQSLPLOCK 0x00002118 /* AFE Sequencer Sleep Control Lock */ +#define REG_AFE_SEQTRGSLP_RESET 0x00000000 /* Reset Value for SEQTRGSLP \ + */ +#define REG_AFE_SEQTRGSLP 0x0000211C /* AFE Sequencer Trigger Sleep */ +#define REG_AFE_LPDACDAT0_RESET 0x00000000 /* Reset Value for LPDACDAT0 \ + */ +#define REG_AFE_LPDACDAT0 0x00002120 /* AFE LPDAC Data-out */ +#define REG_AFE_LPDACSW0_RESET 0x00000000 /* Reset Value for LPDACSW0 */ +#define REG_AFE_LPDACSW0 0x00002124 /* AFE LPDAC0 Switch Control */ +#define REG_AFE_LPDACCON0_RESET 0x00000002 /* Reset Value for LPDACCON0 \ + */ +#define REG_AFE_LPDACCON0 0x00002128 /* AFE LPDAC Control Bits */ +#define REG_AFE_LPDACDAT1 0x0000212C /* AFE Low Power DAC1 data register */ +#define REG_AFE_LPDACSW1 \ + 0x00002130 /* AFE Control register for switches to LPDAC1 */ +#define REG_AFE_LPDACCON1 0x00002134 /* AFE ULP_DACCON1 */ +#define REG_AFE_DSWFULLCON_RESET \ + 0x00000000 /* Reset Value for DSWFULLCON */ +#define REG_AFE_DSWFULLCON \ + 0x00002150 /* AFE Switch Matrix Full Configuration (D) */ +#define REG_AFE_NSWFULLCON_RESET \ + 0x00000000 /* Reset Value for NSWFULLCON */ +#define REG_AFE_NSWFULLCON \ + 0x00002154 /* AFE Switch Matrix Full Configuration (N) */ +#define REG_AFE_PSWFULLCON_RESET \ + 0x00000000 /* Reset Value for PSWFULLCON */ +#define REG_AFE_PSWFULLCON \ + 0x00002158 /* AFE Switch Matrix Full Configuration (P) */ +#define REG_AFE_TSWFULLCON_RESET \ + 0x00000000 /* Reset Value for TSWFULLCON */ +#define REG_AFE_TSWFULLCON \ + 0x0000215C /* AFE Switch Matrix Full Configuration (T) */ +#define REG_AFE_TEMPSENS_RESET 0x00000000 /* Reset Value for TEMPSENS */ +#define REG_AFE_TEMPSENS 0x00002174 /* AFE Temp Sensor Configuration */ +#define REG_AFE_BUFSENCON_RESET 0x00000037 /* Reset Value for BUFSENCON \ + */ +#define REG_AFE_BUFSENCON 0x00002180 /* AFE HP and LP Buffer Control */ +#define REG_AFE_ADCCON_RESET 0x00000000 /* Reset Value for ADCCON */ +#define REG_AFE_ADCCON 0x000021A8 /* AFE ADC Configuration */ +#define REG_AFE_DSWSTA_RESET 0x00000000 /* Reset Value for DSWSTA */ +#define REG_AFE_DSWSTA 0x000021B0 /* AFE Switch Matrix Status (D) */ +#define REG_AFE_PSWSTA_RESET 0x00006000 /* Reset Value for PSWSTA */ +#define REG_AFE_PSWSTA 0x000021B4 /* AFE Switch Matrix Status (P) */ +#define REG_AFE_NSWSTA_RESET 0x00000C00 /* Reset Value for NSWSTA */ +#define REG_AFE_NSWSTA 0x000021B8 /* AFE Switch Matrix Status (N) */ +#define REG_AFE_TSWSTA_RESET 0x00000000 /* Reset Value for TSWSTA */ +#define REG_AFE_TSWSTA 0x000021BC /* AFE Switch Matrix Status (T) */ +#define REG_AFE_STATSVAR_RESET 0x00000000 /* Reset Value for STATSVAR */ +#define REG_AFE_STATSVAR 0x000021C0 /* AFE Variance Output */ +#define REG_AFE_STATSCON_RESET 0x00000000 /* Reset Value for STATSCON */ +#define REG_AFE_STATSCON 0x000021C4 /* AFE Statistics Control */ +#define REG_AFE_STATSMEAN_RESET 0x00000000 /* Reset Value for STATSMEAN \ + */ +#define REG_AFE_STATSMEAN 0x000021C8 /* AFE Statistics Mean Output */ +#define REG_AFE_SEQ0INFO_RESET 0x00000000 /* Reset Value for SEQ0INFO */ +#define REG_AFE_SEQ0INFO 0x000021CC /* AFE Sequence 0 Info */ +#define REG_AFE_SEQ2INFO_RESET 0x00000000 /* Reset Value for SEQ2INFO */ +#define REG_AFE_SEQ2INFO 0x000021D0 /* AFE Sequence 2 Info */ +#define REG_AFE_CMDFIFOWADDR_RESET \ + 0x00000000 /* Reset Value for CMDFIFOWADDR */ +#define REG_AFE_CMDFIFOWADDR 0x000021D4 /* AFE Command FIFO Write Address */ +#define REG_AFE_CMDDATACON_RESET \ + 0x00000410 /* Reset Value for CMDDATACON */ +#define REG_AFE_CMDDATACON 0x000021D8 /* AFE Command Data Control */ +#define REG_AFE_DATAFIFOTHRES_RESET \ + 0x00000000 /* Reset Value for DATAFIFOTHRES */ +#define REG_AFE_DATAFIFOTHRES 0x000021E0 /* AFE Data FIFO Threshold */ +#define REG_AFE_SEQ3INFO_RESET 0x00000000 /* Reset Value for SEQ3INFO */ +#define REG_AFE_SEQ3INFO 0x000021E4 /* AFE Sequence 3 Info */ +#define REG_AFE_SEQ1INFO_RESET 0x00000000 /* Reset Value for SEQ1INFO */ +#define REG_AFE_SEQ1INFO 0x000021E8 /* AFE Sequence 1 Info */ +#define REG_AFE_REPEATADCCNV_RESET \ + 0x00000160 /* Reset Value for REPEATADCCNV */ +#define REG_AFE_REPEATADCCNV 0x000021F0 /* AFE REPEAT ADC Conversions */ +#define REG_AFE_FIFOCNTSTA_RESET \ + 0x00000000 /* Reset Value for FIFOCNTSTA */ +#define REG_AFE_FIFOCNTSTA \ + 0x00002200 /* AFE CMD and DATA FIFO INTERNAL DATA COUNT */ +#define REG_AFE_CALDATLOCK_RESET \ + 0x00000000 /* Reset Value for CALDATLOCK */ +#define REG_AFE_CALDATLOCK 0x00002230 /* AFE Calibration Data Lock */ +#define REG_AFE_ADCOFFSETHSTIA_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETHSTIA */ +#define REG_AFE_ADCOFFSETHSTIA \ + 0x00002234 /* AFE ADC Offset Calibration High Speed TIA Channel */ +#define REG_AFE_ADCGAINTEMPSENS0_RESET \ + 0x00004000 /* Reset Value for ADCGAINTEMPSENS0 */ +#define REG_AFE_ADCGAINTEMPSENS0 \ + 0x00002238 /* AFE ADC Gain Calibration Temp Sensor Channel */ +#define REG_AFE_ADCOFFSETTEMPSENS0_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETTEMPSENS0 */ +#define REG_AFE_ADCOFFSETTEMPSENS0 \ + 0x0000223C /* AFE ADC Offset Calibration Temp Sensor Channel 0 */ +#define REG_AFE_ADCGAINGN1_RESET \ + 0x00004000 /* Reset Value for ADCGAINGN1 */ +#define REG_AFE_ADCGAINGN1 \ + 0x00002240 /* AFE ADCPGAGN1: ADC Gain Calibration Auxiliary Input Channel \ + */ +#define REG_AFE_ADCOFFSETGN1_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETGN1 */ +#define REG_AFE_ADCOFFSETGN1 \ + 0x00002244 /* AFE ADC Offset Calibration Auxiliary Channel (PGA Gain=1) */ +#define REG_AFE_DACGAIN_RESET 0x00000800 /* Reset Value for DACGAIN */ +#define REG_AFE_DACGAIN 0x00002260 /* AFE DACGAIN */ +#define REG_AFE_DACOFFSETATTEN_RESET \ + 0x00000000 /* Reset Value for DACOFFSETATTEN */ +#define REG_AFE_DACOFFSETATTEN \ + 0x00002264 /* AFE DAC Offset with Attenuator Enabled (LP Mode) */ +#define REG_AFE_DACOFFSET_RESET 0x00000000 /* Reset Value for DACOFFSET \ + */ +#define REG_AFE_DACOFFSET \ + 0x00002268 /* AFE DAC Offset with Attenuator Disabled (LP Mode) */ +#define REG_AFE_ADCGAINGN1P5_RESET \ + 0x00004000 /* Reset Value for ADCGAINGN1P5 */ +#define REG_AFE_ADCGAINGN1P5 \ + 0x00002270 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA \ + Gain=1.5) */ +#define REG_AFE_ADCGAINGN2_RESET \ + 0x00004000 /* Reset Value for ADCGAINGN2 */ +#define REG_AFE_ADCGAINGN2 \ + 0x00002274 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=2) \ + */ +#define REG_AFE_ADCGAINGN4_RESET \ + 0x00004000 /* Reset Value for ADCGAINGN4 */ +#define REG_AFE_ADCGAINGN4 \ + 0x00002278 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=4) \ + */ +#define REG_AFE_ADCPGAOFFSETCANCEL_RESET \ + 0x00000000 /* Reset Value for ADCPGAOFFSETCANCEL */ +#define REG_AFE_ADCPGAOFFSETCANCEL \ + 0x00002280 /* AFE ADC Offset Cancellation (Optional) */ +#define REG_AFE_ADCGNHSTIA_RESET \ + 0x00004000 /* Reset Value for ADCGNHSTIA */ +#define REG_AFE_ADCGNHSTIA \ + 0x00002284 /* AFE ADC Gain Calibration for HS TIA Channel */ +#define REG_AFE_ADCOFFSETLPTIA0_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETLPTIA0 */ +#define REG_AFE_ADCOFFSETLPTIA0 \ + 0x00002288 /* AFE ADC Offset Calibration ULP-TIA0 Channel */ +#define REG_AFE_ADCGNLPTIA0_RESET \ + 0x00004000 /* Reset Value for ADCGNLPTIA0 */ +#define REG_AFE_ADCGNLPTIA0 \ + 0x0000228C /* AFE ADC GAIN Calibration for LP TIA0 Channel */ +#define REG_AFE_ADCPGAGN4OFCAL_RESET \ + 0x00004000 /* Reset Value for ADCPGAGN4OFCAL */ +#define REG_AFE_ADCPGAGN4OFCAL \ + 0x00002294 /* AFE ADC Gain Calibration with DC Cancellation(PGA G=4) */ +#define REG_AFE_ADCGAINGN9_RESET \ + 0x00004000 /* Reset Value for ADCGAINGN9 */ +#define REG_AFE_ADCGAINGN9 \ + 0x00002298 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=9) \ + */ +#define REG_AFE_ADCOFFSETEMPSENS1_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETEMPSENS1 */ +#define REG_AFE_ADCOFFSETEMPSENS1 \ + 0x000022A8 /* AFE ADC Offset Calibration Temp Sensor Channel 1 */ +#define REG_AFE_ADCGAINDIOTEMPSENS_RESET \ + 0x00004000 /* Reset Value for ADCGAINDIOTEMPSENS */ +#define REG_AFE_ADCGAINDIOTEMPSENS \ + 0x000022AC /* AFE ADC Gain Calibration Diode Temperature Sensor Channel */ +#define REG_AFE_DACOFFSETATTENHP_RESET \ + 0x00000000 /* Reset Value for DACOFFSETATTENHP */ +#define REG_AFE_DACOFFSETATTENHP \ + 0x000022B8 /* AFE DAC Offset with Attenuator Enabled (HP Mode) */ +#define REG_AFE_DACOFFSETHP_RESET \ + 0x00000000 /* Reset Value for DACOFFSETHP */ +#define REG_AFE_DACOFFSETHP \ + 0x000022BC /* AFE DAC Offset with Attenuator Disabled (HP Mode) */ +#define REG_AFE_ADCGNLPTIA1_RESET \ + 0x00004000 /* Reset Value for ADCGNLPTIA1 */ +#define REG_AFE_ADCOFFSETLPTIA1 \ + 0x000022C0 /* AFE ADC Offset Calibration ULP-TIA0 Channel */ +#define REG_AFE_ADCGNLPTIA1 \ + 0x000022C4 /* AFE ADC GAIN Calibration for LP TIA1 Channel */ +#define REG_AFE_ADCOFFSETGN2_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETGN2 */ +#define REG_AFE_ADCOFFSETGN2 \ + 0x000022C8 /* AFE Offset Calibration Auxiliary Channel (PGA Gain =2) */ +#define REG_AFE_ADCOFFSETGN1P5_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETGN1P5 */ +#define REG_AFE_ADCOFFSETGN1P5 \ + 0x000022CC /* AFE Offset Calibration Auxiliary Channel (PGA Gain =1.5) */ +#define REG_AFE_ADCOFFSETGN9_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETGN9 */ +#define REG_AFE_ADCOFFSETGN9 \ + 0x000022D0 /* AFE Offset Calibration Auxiliary Channel (PGA Gain =9) */ +#define REG_AFE_ADCOFFSETGN4_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETGN4 */ +#define REG_AFE_ADCOFFSETGN4 \ + 0x000022D4 /* AFE Offset Calibration Auxiliary Channel (PGA Gain =4) */ +#define REG_AFE_PMBW_RESET 0x00088800 /* Reset Value for PMBW */ +#define REG_AFE_PMBW 0x000022F0 /* AFE Power Mode Configuration */ +#define REG_AFE_SWMUX_RESET 0x00000000 /* Reset Value for SWMUX */ +#define REG_AFE_SWMUX 0x0000235C /* AFE Switch Mux for ECG */ +#define REG_AFE_AFE_TEMPSEN_DIO_RESET \ + 0x00020000 /* Reset Value for AFE_TEMPSEN_DIO */ +#define REG_AFE_AFE_TEMPSEN_DIO 0x00002374 /* AFE AFE_TEMPSEN_DIO */ +#define REG_AFE_ADCBUFCON_RESET 0x005F3D00 /* Reset Value for ADCBUFCON \ + */ +#define REG_AFE_ADCBUFCON 0x0000238C /* AFE Configure ADC Input Buffer */ + +/* ============================================================================================================================ + AFE Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_AFECON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_AFECON_DACBUFEN 21 /* Enable DC DAC Buffer */ +#define BITP_AFE_AFECON_DACREFEN 20 /* High Speed DAC Reference Enable */ +#define BITP_AFE_AFECON_ALDOILIMITEN \ + 19 /* Analog LDO Current Limiting Enable */ +#define BITP_AFE_AFECON_SINC2EN 16 /* ADC Output 50/60Hz Filter Enable */ +#define BITP_AFE_AFECON_DFTEN 15 /* DFT Hardware Accelerator Enable */ +#define BITP_AFE_AFECON_WAVEGENEN 14 /* Waveform Generator Enable */ +#define BITP_AFE_AFECON_TEMPCONVEN 13 /* ADC Temp Sensor Convert Enable */ +#define BITP_AFE_AFECON_TEMPSENSEN \ + 12 /* ADC Temperature Sensor Channel Enable */ +#define BITP_AFE_AFECON_TIAEN 11 /* High Power TIA Enable */ +#define BITP_AFE_AFECON_INAMPEN 10 /* Enable Excitation Amplifier */ +#define BITP_AFE_AFECON_EXBUFEN 9 /* Enable Excitation Buffer */ +#define BITP_AFE_AFECON_ADCCONVEN 8 /* ADC Conversion Start Enable */ +#define BITP_AFE_AFECON_ADCEN 7 /* ADC Power Enable */ +#define BITP_AFE_AFECON_DACEN 6 /* High Power DAC Enable */ +#define BITP_AFE_AFECON_HPREFDIS 5 /* Disable High Power Reference */ +#define BITM_AFE_AFECON_DACBUFEN 0x00200000 /* Enable DC DAC Buffer */ +#define BITM_AFE_AFECON_DACREFEN \ + 0x00100000 /* High Speed DAC Reference Enable */ +#define BITM_AFE_AFECON_ALDOILIMITEN \ + 0x00080000 /* Analog LDO Current Limiting Enable */ +#define BITM_AFE_AFECON_SINC2EN \ + 0x00010000 /* ADC Output 50/60Hz Filter Enable */ +#define BITM_AFE_AFECON_DFTEN 0x00008000 /* DFT Hardware Accelerator Enable \ + */ +#define BITM_AFE_AFECON_WAVEGENEN 0x00004000 /* Waveform Generator Enable */ +#define BITM_AFE_AFECON_TEMPCONVEN \ + 0x00002000 /* ADC Temp Sensor Convert Enable */ +#define BITM_AFE_AFECON_TEMPSENSEN \ + 0x00001000 /* ADC Temperature Sensor Channel Enable */ +#define BITM_AFE_AFECON_TIAEN 0x00000800 /* High Power TIA Enable */ +#define BITM_AFE_AFECON_INAMPEN 0x00000400 /* Enable Excitation Amplifier */ +#define BITM_AFE_AFECON_EXBUFEN 0x00000200 /* Enable Excitation Buffer */ +#define BITM_AFE_AFECON_ADCCONVEN 0x00000100 /* ADC Conversion Start Enable \ + */ +#define BITM_AFE_AFECON_ADCEN 0x00000080 /* ADC Power Enable */ +#define BITM_AFE_AFECON_DACEN 0x00000040 /* High Power DAC Enable */ +#define BITM_AFE_AFECON_HPREFDIS 0x00000020 /* Disable High Power Reference \ + */ +#define ENUM_AFE_AFECON_OFF 0x00000000 /* DACEN: High Power DAC Disabled */ +#define ENUM_AFE_AFECON_ON 0x00000040 /* DACEN: High Power DAC Enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQCON_SEQWRTMR 8 /* Timer for Sequencer Write Commands */ +#define BITP_AFE_SEQCON_SEQHALT 4 /* Halt Seq */ +#define BITP_AFE_SEQCON_SEQHALTFIFOEMPTY 1 /* Halt Sequencer If Empty */ +#define BITP_AFE_SEQCON_SEQEN 0 /* Enable Sequencer */ +#define BITM_AFE_SEQCON_SEQWRTMR \ + 0x0000FF00 /* Timer for Sequencer Write Commands */ +#define BITM_AFE_SEQCON_SEQHALT 0x00000010 /* Halt Seq */ +#define BITM_AFE_SEQCON_SEQHALTFIFOEMPTY \ + 0x00000002 /* Halt Sequencer If Empty */ +#define BITM_AFE_SEQCON_SEQEN 0x00000001 /* Enable Sequencer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_FIFOCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_FIFOCON_DATAFIFOSRCSEL \ + 13 /* Selects the Source for the Data FIFO. */ +#define BITP_AFE_FIFOCON_DATAFIFOEN 11 /* Data FIFO Enable. */ +#define BITM_AFE_FIFOCON_DATAFIFOSRCSEL \ + 0x0000E000 /* Selects the Source for the Data FIFO. */ +#define BITM_AFE_FIFOCON_DATAFIFOEN 0x00000800 /* Data FIFO Enable. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SWCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SWCON_T11CON 19 /* Control of T[11] */ +#define BITP_AFE_SWCON_T10CON 18 /* Control of T[10] */ +#define BITP_AFE_SWCON_T9CON 17 /* Control of T[9] */ +#define BITP_AFE_SWCON_SWSOURCESEL 16 /* Switch Control Select */ +#define BITP_AFE_SWCON_TMUXCON 12 /* Control of T Switch MUX. */ +#define BITP_AFE_SWCON_NMUXCON 8 /* Control of N Switch MUX */ +#define BITP_AFE_SWCON_PMUXCON 4 /* Control of P Switch MUX */ +#define BITP_AFE_SWCON_DMUXCON 0 /* Control of D Switch MUX */ +#define BITM_AFE_SWCON_T11CON 0x00080000 /* Control of T[11] */ +#define BITM_AFE_SWCON_T10CON 0x00040000 /* Control of T[10] */ +#define BITM_AFE_SWCON_T9CON 0x00020000 /* Control of T[9] */ +#define BITM_AFE_SWCON_SWSOURCESEL 0x00010000 /* Switch Control Select */ +#define BITM_AFE_SWCON_TMUXCON 0x0000F000 /* Control of T Switch MUX. */ +#define BITM_AFE_SWCON_NMUXCON 0x00000F00 /* Control of N Switch MUX */ +#define BITM_AFE_SWCON_PMUXCON 0x000000F0 /* Control of P Switch MUX */ +#define BITM_AFE_SWCON_DMUXCON 0x0000000F /* Control of D Switch MUX */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSDACCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_HSDACCON_INAMPGNMDE 12 /* Excitation Amplifier Gain Control \ + */ +#define BITP_AFE_HSDACCON_RATE 1 /* DAC Update Rate */ +#define BITP_AFE_HSDACCON_ATTENEN 0 /* PGA Stage Gain Attenuation */ +#define BITM_AFE_HSDACCON_INAMPGNMDE \ + 0x00001000 /* Excitation Amplifier Gain Control */ +#define BITM_AFE_HSDACCON_RATE 0x000001FE /* DAC Update Rate */ +#define BITM_AFE_HSDACCON_ATTENEN 0x00000001 /* PGA Stage Gain Attenuation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGCON_DACGAINCAL 5 /* Bypass DAC Gain */ +#define BITP_AFE_WGCON_DACOFFSETCAL 4 /* Bypass DAC Offset */ +#define BITP_AFE_WGCON_TYPESEL 1 /* Selects the Type of Waveform */ +#define BITP_AFE_WGCON_TRAPRSTEN \ + 0 /* Resets the Trapezoid Waveform Generator */ +#define BITM_AFE_WGCON_DACGAINCAL 0x00000020 /* Bypass DAC Gain */ +#define BITM_AFE_WGCON_DACOFFSETCAL 0x00000010 /* Bypass DAC Offset */ +#define BITM_AFE_WGCON_TYPESEL 0x00000006 /* Selects the Type of Waveform */ +#define BITM_AFE_WGCON_TRAPRSTEN \ + 0x00000001 /* Resets the Trapezoid Waveform Generator */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDCLEVEL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGDCLEVEL1_TRAPDCLEVEL1 \ + 0 /* DC Level 1 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDCLEVEL1_TRAPDCLEVEL1 \ + 0x00000FFF /* DC Level 1 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDCLEVEL2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGDCLEVEL2_TRAPDCLEVEL2 \ + 0 /* DC Level 2 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDCLEVEL2_TRAPDCLEVEL2 \ + 0x00000FFF /* DC Level 2 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDELAY1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGDELAY1_DELAY1 \ + 0 /* Delay 1 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDELAY1_DELAY1 \ + 0x000FFFFF /* Delay 1 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGSLOPE1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGSLOPE1_SLOPE1 \ + 0 /* Slope 1 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGSLOPE1_SLOPE1 \ + 0x000FFFFF /* Slope 1 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDELAY2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGDELAY2_DELAY2 \ + 0 /* Delay 2 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDELAY2_DELAY2 \ + 0x000FFFFF /* Delay 2 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGSLOPE2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGSLOPE2_SLOPE2 \ + 0 /* Slope 2 Value for Trapezoid Waveform Generation. */ +#define BITM_AFE_WGSLOPE2_SLOPE2 \ + 0x000FFFFF /* Slope 2 Value for Trapezoid Waveform Generation. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGFCW Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGFCW_SINEFCW \ + 0 /* Sinusoid Generator Frequency Control Word */ +#define BITM_AFE_WGFCW_SINEFCW \ + 0x00FFFFFF /* Sinusoid Generator Frequency Control Word */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGPHASE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGPHASE_SINEOFFSET 0 /* Sinusoid Phase Offset */ +#define BITM_AFE_WGPHASE_SINEOFFSET 0x000FFFFF /* Sinusoid Phase Offset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGOFFSET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGOFFSET_SINEOFFSET 0 /* Sinusoid Offset */ +#define BITM_AFE_WGOFFSET_SINEOFFSET 0x00000FFF /* Sinusoid Offset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGAMPLITUDE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGAMPLITUDE_SINEAMPLITUDE 0 /* Sinusoid Amplitude */ +#define BITM_AFE_WGAMPLITUDE_SINEAMPLITUDE 0x000007FF /* Sinusoid Amplitude \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCFILTERCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCFILTERCON_AVRGNUM 14 /* Number of Samples Averaged */ +#define BITP_AFE_ADCFILTERCON_SINC3OSR 12 /* SINC3 OSR */ +#define BITP_AFE_ADCFILTERCON_SINC2OSR 8 /* SINC2 OSR */ +#define BITP_AFE_ADCFILTERCON_AVRGEN 7 /* Average Function Enable */ +#define BITP_AFE_ADCFILTERCON_SINC3BYP 6 /* SINC3 Filter Bypass */ +#define BITP_AFE_ADCFILTERCON_LPFBYPEN 4 /* 50/60Hz Low Pass Filter */ +#define BITP_AFE_ADCFILTERCON_ADCCLK 0 /* ADC Data Rate */ +#define BITM_AFE_ADCFILTERCON_AVRGNUM \ + 0x0000C000 /* Number of Samples Averaged */ +#define BITM_AFE_ADCFILTERCON_SINC3OSR 0x00003000 /* SINC3 OSR */ +#define BITM_AFE_ADCFILTERCON_SINC2OSR 0x00000F00 /* SINC2 OSR */ +#define BITM_AFE_ADCFILTERCON_AVRGEN 0x00000080 /* Average Function Enable */ +#define BITM_AFE_ADCFILTERCON_SINC3BYP 0x00000040 /* SINC3 Filter Bypass */ +#define BITM_AFE_ADCFILTERCON_LPFBYPEN 0x00000010 /* 50/60Hz Low Pass Filter \ + */ +#define BITM_AFE_ADCFILTERCON_ADCCLK 0x00000001 /* ADC Data Rate */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSDACDAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_HSDACDAT_DACDAT 0 /* DAC Code */ +#define BITM_AFE_HSDACDAT_DACDAT 0x00000FFF /* DAC Code */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPREFBUFCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPREFBUFCON_BOOSTCURRENT \ + 2 /* Set: Drive 2 Dac ;Unset Drive 1 Dac, and Save Power */ +#define BITP_AFE_LPREFBUFCON_LPBUF2P5DIS \ + 1 /* Low Power Bandgap's Output Buffer */ +#define BITP_AFE_LPREFBUFCON_LPREFDIS \ + 0 /* Set This Bit Will Power Down Low Power Bandgap */ +#define BITM_AFE_LPREFBUFCON_BOOSTCURRENT \ + 0x00000004 /* Set: Drive 2 Dac ;Unset Drive 1 Dac, and Save Power */ +#define BITM_AFE_LPREFBUFCON_LPBUF2P5DIS \ + 0x00000002 /* Low Power Bandgap's Output Buffer */ +#define BITM_AFE_LPREFBUFCON_LPREFDIS \ + 0x00000001 /* Set This Bit Will Power Down Low Power Bandgap */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SYNCEXTDEVICE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SYNCEXTDEVICE_SYNC 0 /* As Output Data of GPIO */ +#define BITM_AFE_SYNCEXTDEVICE_SYNC 0x000000FF /* As Output Data of GPIO */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQCRC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQCRC_CRC 0 /* Sequencer Command CRC Value. */ +#define BITM_AFE_SEQCRC_CRC 0x000000FF /* Sequencer Command CRC Value. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQCNT_COUNT 0 /* Sequencer Command Count */ +#define BITM_AFE_SEQCNT_COUNT 0x0000FFFF /* Sequencer Command Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQTIMEOUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQTIMEOUT_TIMEOUT \ + 0 /* Current Value of the Sequencer Timeout Counter. */ +#define BITM_AFE_SEQTIMEOUT_TIMEOUT \ + 0x3FFFFFFF /* Current Value of the Sequencer Timeout Counter. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DATAFIFORD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DATAFIFORD_DATAFIFOOUT 0 /* Data FIFO Read */ +#define BITM_AFE_DATAFIFORD_DATAFIFOOUT 0x0000FFFF /* Data FIFO Read */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CMDFIFOWRITE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_CMDFIFOWRITE_CMDFIFOIN 0 /* Command FIFO Write. */ +#define BITM_AFE_CMDFIFOWRITE_CMDFIFOIN 0xFFFFFFFF /* Command FIFO Write. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCDAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCDAT_DATA 0 /* ADC Result */ +#define BITM_AFE_ADCDAT_DATA 0x0000FFFF /* ADC Result */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DFTREAL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DFTREAL_DATA 0 /* DFT Real */ +#define BITM_AFE_DFTREAL_DATA 0x0003FFFF /* DFT Real */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DFTIMAG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DFTIMAG_DATA 0 /* DFT Imaginary */ +#define BITM_AFE_DFTIMAG_DATA 0x0003FFFF /* DFT Imaginary */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SINC2DAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SINC2DAT_DATA 0 /* LPF Result */ +#define BITM_AFE_SINC2DAT_DATA 0x0000FFFF /* LPF Result */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TEMPSENSDAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_TEMPSENSDAT_DATA 0 /* Temp Sensor */ +#define BITM_AFE_TEMPSENSDAT_DATA 0x0000FFFF /* Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_AFEGENINTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ3 3 /* Custom IRQ 3. */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ2 2 /* Custom IRQ 2 */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ1 1 /* Custom IRQ 1. */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ0 0 /* Custom IRQ 0 */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ3 0x00000008 /* Custom IRQ 3. */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ2 0x00000004 /* Custom IRQ 2 */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ1 0x00000002 /* Custom IRQ 1. */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ0 0x00000001 /* Custom IRQ 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMIN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCMIN_MINVAL 0 /* ADC Minimum Value Threshold */ +#define BITM_AFE_ADCMIN_MINVAL 0x0000FFFF /* ADC Minimum Value Threshold */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMINSM Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCMINSM_MINCLRVAL 0 /* ADCMIN Hysteresis Value */ +#define BITM_AFE_ADCMINSM_MINCLRVAL 0x0000FFFF /* ADCMIN Hysteresis Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMAX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCMAX_MAXVAL 0 /* ADC Max Threshold */ +#define BITM_AFE_ADCMAX_MAXVAL 0x0000FFFF /* ADC Max Threshold */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMAXSMEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCMAXSMEN_MAXSWEN 0 /* ADCMAX Hysteresis Value */ +#define BITM_AFE_ADCMAXSMEN_MAXSWEN 0x0000FFFF /* ADCMAX Hysteresis Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCDELTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCDELTA_DELTAVAL 0 /* ADCDAT Code Differences Limit Option \ + */ +#define BITM_AFE_ADCDELTA_DELTAVAL \ + 0x0000FFFF /* ADCDAT Code Differences Limit Option */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HPOSCCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_HPOSCCON_CLK32MHZEN 2 /* 16M/32M Output Selector Signal. */ +#define BITM_AFE_HPOSCCON_CLK32MHZEN \ + 0x00000004 /* 16M/32M Output Selector Signal. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DFTCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DFTCON_DFTINSEL 20 /* DFT Input Select */ +#define BITP_AFE_DFTCON_DFTNUM 4 /* ADC Samples Used */ +#define BITP_AFE_DFTCON_HANNINGEN 0 /* Hanning Window Enable */ +#define BITM_AFE_DFTCON_DFTINSEL 0x00300000 /* DFT Input Select */ +#define BITM_AFE_DFTCON_DFTNUM 0x000000F0 /* ADC Samples Used */ +#define BITM_AFE_DFTCON_HANNINGEN 0x00000001 /* Hanning Window Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIASW1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPTIASW1_TIABIASSEL 13 /* TIA SW13 Control. Active High */ +#define BITP_AFE_LPTIASW1_PABIASSEL 12 /* TIA SW12 Control. Active High */ +#define BITP_AFE_LPTIASW1_TIASWCON 0 /* TIA SW[11:0] Control */ +#define BITM_AFE_LPTIASW1_TIABIASSEL \ + (_ADI_MSK_3(0x00002000, 0x00002000UL, \ + uint32_t)) /* TIA SW13 Control. Active High */ +#define BITM_AFE_LPTIASW1_PABIASSEL \ + (_ADI_MSK_3(0x00001000, 0x00001000UL, \ + uint32_t)) /* TIA SW12 Control. Active High */ +#define BITM_AFE_LPTIASW1_TIASWCON \ + (_ADI_MSK_3(0x00000FFF, 0x00000FFFUL, uint32_t)) /* TIA SW[11:0] Control */ +#define ENUM_AFE_LPTIASW1_CAPA_LP \ + (_ADI_MSK_3(0x00000014, 0x00000014UL, \ + uint32_t)) /* TIASWCON: CAPA test with LP TIA */ +#define ENUM_AFE_LPTIASW1_NORM \ + (_ADI_MSK_3(0x0000002C, 0x0000002CUL, \ + uint32_t)) /* TIASWCON: Normal work mode */ +#define ENUM_AFE_LPTIASW1_DIO \ + (_ADI_MSK_3(0x0000002D, 0x0000002DUL, \ + uint32_t)) /* TIASWCON: Normal work mode with back-back diode \ + enabled. */ +#define ENUM_AFE_LPTIASW1_SHORTSW \ + (_ADI_MSK_3( \ + 0x0000002E, 0x0000002EUL, \ + uint32_t)) /* TIASWCON: Work mode with short switch protection */ +#define ENUM_AFE_LPTIASW1_LOWNOISE \ + (_ADI_MSK_3(0x0000006C, 0x0000006CUL, \ + uint32_t)) /* TIASWCON: Work mode, vzero-vbias=0. */ +#define ENUM_AFE_LPTIASW1_CAPA_RAMP_H \ + (_ADI_MSK_3(0x00000094, 0x00000094UL, \ + uint32_t)) /* TIASWCON: CAPA test or Ramp test with HP TIA */ +#define ENUM_AFE_LPTIASW1_BUFDIS \ + (_ADI_MSK_3(0x00000180, 0x00000180UL, \ + uint32_t)) /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW1_BUFEN \ + (_ADI_MSK_3(0x000001A4, 0x000001A4UL, \ + uint32_t)) /* TIASWCON: Set PA/TIA as unity gain buffer. \ + Connect amp's output to CE1 & RC11. */ +#define ENUM_AFE_LPTIASW1_TWOLEAD \ + (_ADI_MSK_3(0x0000042C, 0x0000042CUL, \ + uint32_t)) /* TIASWCON: Two lead sensor, set PA as unity gain \ + buffer. */ +#define ENUM_AFE_LPTIASW1_BUFEN2 \ + (_ADI_MSK_3(0x000004A4, 0x000004A4UL, \ + uint32_t)) /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW1_SESHORTRE \ + (_ADI_MSK_3(0x00000800, 0x00000800UL, \ + uint32_t)) /* TIASWCON: Close SW11 - Short SE1 to RE1, */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIASW0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPTIASW0_RECAL 15 /* TIA SW15 Control. Active High */ +#define BITP_AFE_LPTIASW0_VZEROSHARE 14 /* TIA SW14 Control. Active High */ +#define BITP_AFE_LPTIASW0_TIABIASSEL 13 /* TIA SW13 Control. Active High */ +#define BITP_AFE_LPTIASW0_PABIASSEL 12 /* TIA SW12 Control. Active High */ +#define BITP_AFE_LPTIASW0_TIASWCON 0 /* TIA SW[11:0] Control */ +#define BITM_AFE_LPTIASW0_RECAL 0x00008000 /* TIA SW15 Control. Active High \ + */ +#define BITM_AFE_LPTIASW0_VZEROSHARE \ + 0x00004000 /* TIA SW14 Control. Active High */ +#define BITM_AFE_LPTIASW0_TIABIASSEL \ + 0x00002000 /* TIA SW13 Control. Active High */ +#define BITM_AFE_LPTIASW0_PABIASSEL \ + 0x00001000 /* TIA SW12 Control. Active High */ +#define BITM_AFE_LPTIASW0_TIASWCON 0x00000FFF /* TIA SW[11:0] Control */ +#define ENUM_AFE_LPTIASW0_11 0x00000014 /* TIASWCON: CAPA test with LP TIA */ +#define ENUM_AFE_LPTIASW0_NORM 0x0000002C /* TIASWCON: Normal work mode */ +#define ENUM_AFE_LPTIASW0_DIO \ + 0x0000002D /* TIASWCON: Normal work mode with back-back diode enabled. */ +#define ENUM_AFE_LPTIASW0_SHORTSW \ + 0x0000002E /* TIASWCON: Work mode with short switch protection */ +#define ENUM_AFE_LPTIASW0_LOWNOISE \ + 0x0000006C /* TIASWCON: Work mode, vzero-vbias=0. */ +#define ENUM_AFE_LPTIASW0_1 \ + 0x00000094 /* TIASWCON: CAPA test or Ramp test with HP TIA */ +#define ENUM_AFE_LPTIASW0_BUFDIS \ + 0x00000180 /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW0_BUFEN \ + 0x000001A4 /* TIASWCON: Set PA/TIA as unity gain buffer. Connect amp's \ + output to CE0 & RC01. */ +#define ENUM_AFE_LPTIASW0_TWOLEAD \ + 0x0000042C /* TIASWCON: Two lead sensor, set PA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW0_BUFEN2 \ + 0x000004A4 /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW0_SESHORTRE \ + 0x00000800 /* TIASWCON: Close SW11 - Short SE0 to RE0. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIACON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPTIACON1_CHOPEN 16 /* Chopping Enable */ +#define BITP_AFE_LPTIACON1_TIARF 13 /* Set LPF Resistor */ +#define BITP_AFE_LPTIACON1_TIARL 10 /* Set RLOAD */ +#define BITP_AFE_LPTIACON1_TIAGAIN 5 /* Set RTIA Gain Resistor */ +#define BITP_AFE_LPTIACON1_IBOOST 3 /* Current Boost Control */ +#define BITP_AFE_LPTIACON1_HALFPWR 2 /* Half Power Mode Select */ +#define BITP_AFE_LPTIACON1_PAPDEN 1 /* PA Power Down */ +#define BITP_AFE_LPTIACON1_TIAPDEN 0 /* TIA Power Down */ +#define BITM_AFE_LPTIACON1_CHOPEN \ + (_ADI_MSK_3(0x00030000, 0x00030000UL, uint32_t)) /* Chopping Enable */ +#define BITM_AFE_LPTIACON1_TIARF \ + (_ADI_MSK_3(0x0000E000, 0x0000E000UL, uint32_t)) /* Set LPF Resistor */ +#define BITM_AFE_LPTIACON1_TIARL \ + (_ADI_MSK_3(0x00001C00, 0x00001C00UL, uint32_t)) /* Set RLOAD */ +#define BITM_AFE_LPTIACON1_TIAGAIN \ + (_ADI_MSK_3(0x000003E0, 0x000003E0UL, uint32_t)) /* Set RTIA Gain Resistor \ + */ +#define BITM_AFE_LPTIACON1_IBOOST \ + (_ADI_MSK_3(0x00000018, 0x00000018UL, uint32_t)) /* Current Boost Control \ + */ +#define BITM_AFE_LPTIACON1_HALFPWR \ + (_ADI_MSK_3(0x00000004, 0x00000004UL, uint32_t)) /* Half Power Mode Select \ + */ +#define BITM_AFE_LPTIACON1_PAPDEN \ + (_ADI_MSK_3(0x00000002, 0x00000002UL, uint32_t)) /* PA Power Down */ +#define BITM_AFE_LPTIACON1_TIAPDEN \ + (_ADI_MSK_3(0x00000001, 0x00000001UL, uint32_t)) /* TIA Power Down */ +#define ENUM_AFE_LPTIACON1_DISCONRF \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, \ + uint32_t)) /* TIARF: Disconnect TIA output from LPF pin */ +#define ENUM_AFE_LPTIACON1_BYPRF \ + (_ADI_MSK_3(0x00002000, 0x00002000UL, uint32_t)) /* TIARF: Bypass resistor \ + */ +#define ENUM_AFE_LPTIACON1_RF20K \ + (_ADI_MSK_3(0x00004000, 0x00004000UL, uint32_t)) /* TIARF: 20k Ohm */ +#define ENUM_AFE_LPTIACON1_RF100K \ + (_ADI_MSK_3(0x00006000, 0x00006000UL, uint32_t)) /* TIARF: 100k Ohm */ +#define ENUM_AFE_LPTIACON1_RF200K \ + (_ADI_MSK_3(0x00008000, 0x00008000UL, uint32_t)) /* TIARF: 200k Ohm */ +#define ENUM_AFE_LPTIACON1_RF400K \ + (_ADI_MSK_3(0x0000A000, 0x0000A000UL, uint32_t)) /* TIARF: 400k Ohm */ +#define ENUM_AFE_LPTIACON1_RF600K \ + (_ADI_MSK_3(0x0000C000, 0x0000C000UL, uint32_t)) /* TIARF: 600k Ohm */ +#define ENUM_AFE_LPTIACON1_RF1MOHM \ + (_ADI_MSK_3(0x0000E000, 0x0000E000UL, uint32_t)) /* TIARF: 1Meg Ohm */ +#define ENUM_AFE_LPTIACON1_RL0 \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, uint32_t)) /* TIARL: 0 ohm */ +#define ENUM_AFE_LPTIACON1_RL10 \ + (_ADI_MSK_3(0x00000400, 0x00000400UL, uint32_t)) /* TIARL: 10 ohm */ +#define ENUM_AFE_LPTIACON1_RL30 \ + (_ADI_MSK_3(0x00000800, 0x00000800UL, uint32_t)) /* TIARL: 30 ohm */ +#define ENUM_AFE_LPTIACON1_RL50 \ + (_ADI_MSK_3(0x00000C00, 0x00000C00UL, uint32_t)) /* TIARL: 50 ohm */ +#define ENUM_AFE_LPTIACON1_RL100 \ + (_ADI_MSK_3(0x00001000, 0x00001000UL, uint32_t)) /* TIARL: 100 ohm */ +#define ENUM_AFE_LPTIACON1_RL1P6K \ + (_ADI_MSK_3(0x00001400, 0x00001400UL, uint32_t)) /* TIARL: 1.6kohm */ +#define ENUM_AFE_LPTIACON1_RL3P1K \ + (_ADI_MSK_3(0x00001800, 0x00001800UL, uint32_t)) /* TIARL: 3.1kohm */ +#define ENUM_AFE_LPTIACON1_RL3P5K \ + (_ADI_MSK_3(0x00001C00, 0x00001C00UL, uint32_t)) /* TIARL: 3.6kohm */ +#define ENUM_AFE_LPTIACON1_DISCONTIA \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, \ + uint32_t)) /* TIAGAIN: Disconnect TIA Gain resistor */ +#define ENUM_AFE_LPTIACON1_TIAGAIN200 \ + (_ADI_MSK_3(0x00000020, 0x00000020UL, uint32_t)) /* TIAGAIN: 200 Ohm */ +#define ENUM_AFE_LPTIACON1_TIAGAIN1K \ + (_ADI_MSK_3(0x00000040, 0x00000040UL, uint32_t)) /* TIAGAIN: 1k ohm */ +#define ENUM_AFE_LPTIACON1_TIAGAIN2K \ + (_ADI_MSK_3(0x00000060, 0x00000060UL, uint32_t)) /* TIAGAIN: 2k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN3K \ + (_ADI_MSK_3(0x00000080, 0x00000080UL, uint32_t)) /* TIAGAIN: 3k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN4K \ + (_ADI_MSK_3(0x000000A0, 0x000000A0UL, uint32_t)) /* TIAGAIN: 4k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN6K \ + (_ADI_MSK_3(0x000000C0, 0x000000C0UL, uint32_t)) /* TIAGAIN: 6k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN8K \ + (_ADI_MSK_3(0x000000E0, 0x000000E0UL, uint32_t)) /* TIAGAIN: 8k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN10K \ + (_ADI_MSK_3(0x00000100, 0x00000100UL, uint32_t)) /* TIAGAIN: 10k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN12K \ + (_ADI_MSK_3(0x00000120, 0x00000120UL, uint32_t)) /* TIAGAIN: 12k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN16K \ + (_ADI_MSK_3(0x00000140, 0x00000140UL, uint32_t)) /* TIAGAIN: 16k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN20K \ + (_ADI_MSK_3(0x00000160, 0x00000160UL, uint32_t)) /* TIAGAIN: 20k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN24K \ + (_ADI_MSK_3(0x00000180, 0x00000180UL, uint32_t)) /* TIAGAIN: 24k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN30K \ + (_ADI_MSK_3(0x000001A0, 0x000001A0UL, uint32_t)) /* TIAGAIN: 30k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN32K \ + (_ADI_MSK_3(0x000001C0, 0x000001C0UL, uint32_t)) /* TIAGAIN: 32k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN40K \ + (_ADI_MSK_3(0x000001E0, 0x000001E0UL, uint32_t)) /* TIAGAIN: 40k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN48K \ + (_ADI_MSK_3(0x00000200, 0x00000200UL, uint32_t)) /* TIAGAIN: 48k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN64K \ + (_ADI_MSK_3(0x00000220, 0x00000220UL, uint32_t)) /* TIAGAIN: 64k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN85K \ + (_ADI_MSK_3(0x00000240, 0x00000240UL, uint32_t)) /* TIAGAIN: 85k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN96K \ + (_ADI_MSK_3(0x00000260, 0x00000260UL, uint32_t)) /* TIAGAIN: 96k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN100K \ + (_ADI_MSK_3(0x00000280, 0x00000280UL, uint32_t)) /* TIAGAIN: 100k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN120K \ + (_ADI_MSK_3(0x000002A0, 0x000002A0UL, uint32_t)) /* TIAGAIN: 120k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN128K \ + (_ADI_MSK_3(0x000002C0, 0x000002C0UL, uint32_t)) /* TIAGAIN: 128k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN160K \ + (_ADI_MSK_3(0x000002E0, 0x000002E0UL, uint32_t)) /* TIAGAIN: 160k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN196K \ + (_ADI_MSK_3(0x00000300, 0x00000300UL, uint32_t)) /* TIAGAIN: 196k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN256K \ + (_ADI_MSK_3(0x00000320, 0x00000320UL, uint32_t)) /* TIAGAIN: 256k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN512K \ + (_ADI_MSK_3(0x00000340, 0x00000340UL, uint32_t)) /* TIAGAIN: 512k */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIACON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPTIACON0_CHOPEN 16 /* Chopping Enable */ +#define BITP_AFE_LPTIACON0_TIARF 13 /* Set LPF Resistor */ +#define BITP_AFE_LPTIACON0_TIARL 10 /* Set RLOAD */ +#define BITP_AFE_LPTIACON0_TIAGAIN 5 /* Set RTIA */ +#define BITP_AFE_LPTIACON0_IBOOST 3 /* Current Boost Control */ +#define BITP_AFE_LPTIACON0_HALFPWR 2 /* Half Power Mode Select */ +#define BITP_AFE_LPTIACON0_PAPDEN 1 /* PA Power Down */ +#define BITP_AFE_LPTIACON0_TIAPDEN 0 /* TIA Power Down */ +#define BITM_AFE_LPTIACON0_CHOPEN 0x00030000 /* Chopping Enable */ +#define BITM_AFE_LPTIACON0_TIARF 0x0000E000 /* Set LPF Resistor */ +#define BITM_AFE_LPTIACON0_TIARL 0x00001C00 /* Set RLOAD */ +#define BITM_AFE_LPTIACON0_TIAGAIN 0x000003E0 /* Set RTIA */ +#define BITM_AFE_LPTIACON0_IBOOST 0x00000018 /* Current Boost Control */ +#define BITM_AFE_LPTIACON0_HALFPWR 0x00000004 /* Half Power Mode Select */ +#define BITM_AFE_LPTIACON0_PAPDEN 0x00000002 /* PA Power Down */ +#define BITM_AFE_LPTIACON0_TIAPDEN 0x00000001 /* TIA Power Down */ +#define ENUM_AFE_LPTIACON0_DISCONRF \ + 0x00000000 /* TIARF: Disconnect TIA output from LPF pin */ +#define ENUM_AFE_LPTIACON0_BYPRF 0x00002000 /* TIARF: Bypass resistor */ +#define ENUM_AFE_LPTIACON0_RF20K 0x00004000 /* TIARF: 20k Ohm */ +#define ENUM_AFE_LPTIACON0_RF100K 0x00006000 /* TIARF: 100k Ohm */ +#define ENUM_AFE_LPTIACON0_RF200K 0x00008000 /* TIARF: 200k Ohm */ +#define ENUM_AFE_LPTIACON0_RF400K 0x0000A000 /* TIARF: 400k Ohm */ +#define ENUM_AFE_LPTIACON0_RF600K 0x0000C000 /* TIARF: 600k Ohm */ +#define ENUM_AFE_LPTIACON0_RF1MOHM 0x0000E000 /* TIARF: 1Meg Ohm */ +#define ENUM_AFE_LPTIACON0_RL0 0x00000000 /* TIARL: 0 ohm */ +#define ENUM_AFE_LPTIACON0_RL10 0x00000400 /* TIARL: 10 ohm */ +#define ENUM_AFE_LPTIACON0_RL30 0x00000800 /* TIARL: 30 ohm */ +#define ENUM_AFE_LPTIACON0_RL50 0x00000C00 /* TIARL: 50 ohm */ +#define ENUM_AFE_LPTIACON0_RL100 0x00001000 /* TIARL: 100 ohm */ +#define ENUM_AFE_LPTIACON0_RL1P6K 0x00001400 /* TIARL: 1.6kohm */ +#define ENUM_AFE_LPTIACON0_RL3P1K 0x00001800 /* TIARL: 3.1kohm */ +#define ENUM_AFE_LPTIACON0_RL3P5K 0x00001C00 /* TIARL: 3.6kohm */ +#define ENUM_AFE_LPTIACON0_DISCONTIA \ + 0x00000000 /* TIAGAIN: Disconnect TIA Gain resistor */ +#define ENUM_AFE_LPTIACON0_TIAGAIN200 0x00000020 /* TIAGAIN: 200 Ohm */ +#define ENUM_AFE_LPTIACON0_TIAGAIN1K 0x00000040 /* TIAGAIN: 1k ohm */ +#define ENUM_AFE_LPTIACON0_TIAGAIN2K 0x00000060 /* TIAGAIN: 2k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN3K 0x00000080 /* TIAGAIN: 3k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN4K 0x000000A0 /* TIAGAIN: 4k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN6K 0x000000C0 /* TIAGAIN: 6k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN8K 0x000000E0 /* TIAGAIN: 8k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN10K 0x00000100 /* TIAGAIN: 10k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN12K 0x00000120 /* TIAGAIN: 12k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN16K 0x00000140 /* TIAGAIN: 16k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN20K 0x00000160 /* TIAGAIN: 20k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN24K 0x00000180 /* TIAGAIN: 24k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN30K 0x000001A0 /* TIAGAIN: 30k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN32K 0x000001C0 /* TIAGAIN: 32k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN40K 0x000001E0 /* TIAGAIN: 40k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN48K 0x00000200 /* TIAGAIN: 48k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN64K 0x00000220 /* TIAGAIN: 64k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN85K 0x00000240 /* TIAGAIN: 85k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN96K 0x00000260 /* TIAGAIN: 96k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN100K 0x00000280 /* TIAGAIN: 100k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN120K 0x000002A0 /* TIAGAIN: 120k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN128K 0x000002C0 /* TIAGAIN: 128k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN160K 0x000002E0 /* TIAGAIN: 160k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN196K 0x00000300 /* TIAGAIN: 196k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN256K 0x00000320 /* TIAGAIN: 256k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN512K 0x00000340 /* TIAGAIN: 512k */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSRTIACON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_HSRTIACON_CTIACON \ + 5 /* Configure Capacitor in Parallel with RTIA */ +#define BITP_AFE_HSRTIACON_TIASW6CON 4 /* SW6 Control */ +#define BITP_AFE_HSRTIACON_RTIACON 0 /* Configure General RTIA Value */ +#define BITM_AFE_HSRTIACON_CTIACON \ + 0x00001FE0 /* Configure Capacitor in Parallel with RTIA */ +#define BITM_AFE_HSRTIACON_TIASW6CON 0x00000010 /* SW6 Control */ +#define BITM_AFE_HSRTIACON_RTIACON \ + 0x0000000F /* Configure General RTIA Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DE1RESCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DE1RESCON_DE1RCON 0 /* DE1 RLOAD RTIA Setting */ +#define BITM_AFE_DE1RESCON_DE1RCON \ + (_ADI_MSK_3(0x000000FF, 0x000000FFUL, uint32_t)) /* DE1 RLOAD RTIA Setting \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DE0RESCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DE0RESCON_DE0RCON 0 /* DE0 RLOAD RTIA Setting */ +#define BITM_AFE_DE0RESCON_DE0RCON 0x000000FF /* DE0 RLOAD RTIA Setting */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSTIACON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_HSTIACON_VBIASSEL 0 /* Select HSTIA Positive Input */ +#define BITM_AFE_HSTIACON_VBIASSEL 0x00000003 /* Select HSTIA Positive Input \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACDCBUFCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DACDCBUFCON_CHANSEL 1 /* DAC DC Channel Selection */ +#define BITP_AFE_DACDCBUFCON_RESERVED_0 0 /* Reserved */ +#define BITM_AFE_DACDCBUFCON_CHANSEL \ + (_ADI_MSK_3(0x00000002, 0x00000002UL, \ + uint32_t)) /* DAC DC Channel Selection */ +#define BITM_AFE_DACDCBUFCON_RESERVED_0 \ + (_ADI_MSK_3(0x00000001, 0x00000001UL, uint32_t)) /* Reserved */ +#define ENUM_AFE_DACDCBUFCON_CHAN0 \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, \ + uint32_t)) /* CHANSEL: ULPDAC0 Sets DC level */ +#define ENUM_AFE_DACDCBUFCON_CHAN1 \ + (_ADI_MSK_3(0x00000002, 0x00000002UL, \ + uint32_t)) /* CHANSEL: ULPDAC1 Sets DC level */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPMODEKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPMODEKEY_KEY 0 /* LP Key */ +#define BITM_AFE_LPMODEKEY_KEY 0x000FFFFF /* LP Key */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPMODECLKSEL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPMODECLKSEL_LFSYSCLKEN \ + 0 /* Enable Switching System Clock to 32KHz by Sequencer */ +#define BITM_AFE_LPMODECLKSEL_LFSYSCLKEN \ + 0x00000001 /* Enable Switching System Clock to 32KHz by Sequencer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPMODECON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPMODECON_ALDOEN 8 /* Set High to Power Down of Analog LDO \ + */ +#define BITP_AFE_LPMODECON_V1P1HPADCEN \ + 7 /* Set High to Enable 1.1V HP CM Buffer */ +#define BITP_AFE_LPMODECON_V1P8HPADCEN \ + 6 /* Set High to Enable HP 1.8V Reference Buffer */ +#define BITP_AFE_LPMODECON_PTATEN \ + 5 /* Set to High to Generate Ptat Current Bias */ +#define BITP_AFE_LPMODECON_ZTATEN \ + 4 /* Set High to Generate Ztat Current Bias */ +#define BITP_AFE_LPMODECON_REPEATADCCNVEN_P \ + 3 /* Set High to Enable Repeat ADC Conversion */ +#define BITP_AFE_LPMODECON_ADCCONVEN 2 /* Set High to Enable ADC Conversion \ + */ +#define BITP_AFE_LPMODECON_HPREFDIS 1 /* Set High to Power Down HP Reference \ + */ +#define BITP_AFE_LPMODECON_HFOSCPD \ + 0 /* Set High to Power Down HP Power Oscillator */ +#define BITM_AFE_LPMODECON_ALDOEN \ + 0x00000100 /* Set High to Power Down of Analog LDO */ +#define BITM_AFE_LPMODECON_V1P1HPADCEN \ + 0x00000080 /* Set High to Enable 1.1V HP CM Buffer */ +#define BITM_AFE_LPMODECON_V1P8HPADCEN \ + 0x00000040 /* Set High to Enable HP 1.8V Reference Buffer */ +#define BITM_AFE_LPMODECON_PTATEN \ + 0x00000020 /* Set to High to Generate Ptat Current Bias */ +#define BITM_AFE_LPMODECON_ZTATEN \ + 0x00000010 /* Set High to Generate Ztat Current Bias */ +#define BITM_AFE_LPMODECON_REPEATADCCNVEN_P \ + 0x00000008 /* Set High to Enable Repeat ADC Conversion */ +#define BITM_AFE_LPMODECON_ADCCONVEN \ + 0x00000004 /* Set High to Enable ADC Conversion */ +#define BITM_AFE_LPMODECON_HPREFDIS \ + 0x00000002 /* Set High to Power Down HP Reference */ +#define BITM_AFE_LPMODECON_HFOSCPD \ + 0x00000001 /* Set High to Power Down HP Power Oscillator */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQSLPLOCK Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQSLPLOCK_SEQ_SLP_PW 0 /* Password for SLPBYSEQ Register */ +#define BITM_AFE_SEQSLPLOCK_SEQ_SLP_PW \ + 0x000FFFFF /* Password for SLPBYSEQ Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQTRGSLP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQTRGSLP_TRGSLP 0 /* Trigger Sleep by Sequencer */ +#define BITM_AFE_SEQTRGSLP_TRGSLP 0x00000001 /* Trigger Sleep by Sequencer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACDAT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPDACDAT0_DACIN6 12 /* 6BITVAL, 1LSB=34.375mV */ +#define BITP_AFE_LPDACDAT0_DACIN12 0 /* 12BITVAL, 1LSB=537uV */ +#define BITM_AFE_LPDACDAT0_DACIN6 0x0003F000 /* 6BITVAL, 1LSB=34.375mV */ +#define BITM_AFE_LPDACDAT0_DACIN12 0x00000FFF /* 12BITVAL, 1LSB=537uV */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACSW0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPDACSW0_LPMODEDIS 5 /* Switch Control */ +#define BITP_AFE_LPDACSW0_LPDACSW 0 /* LPDAC0 Switches Matrix */ +#define BITM_AFE_LPDACSW0_LPMODEDIS 0x00000020 /* Switch Control */ +#define BITM_AFE_LPDACSW0_LPDACSW 0x0000001F /* LPDAC0 Switches Matrix */ +#define ENUM_AFE_LPDACSW0_DACCONBIT5 \ + 0x00000000 /* LPMODEDIS: REG_AFE_LPDACDAT0 Switch controlled by \ + REG_AFE_LPDACDAT0CON0 bit 5 */ +#define ENUM_AFE_LPDACSW0_OVRRIDE \ + 0x00000020 /* LPMODEDIS: REG_AFE_LPDACDAT0 Switches override */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACCON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPDACCON0_WAVETYPE 6 /* LPDAC Data Source */ +#define BITP_AFE_LPDACCON0_DACMDE 5 /* LPDAC0 Switch Settings */ +#define BITP_AFE_LPDACCON0_VZEROMUX 4 /* VZERO MUX Select */ +#define BITP_AFE_LPDACCON0_VBIASMUX 3 /* VBIAS MUX Select */ +#define BITP_AFE_LPDACCON0_REFSEL 2 /* Reference Select Bit */ +#define BITP_AFE_LPDACCON0_PWDEN 1 /* LPDAC0 Power Down */ +#define BITP_AFE_LPDACCON0_RSTEN 0 /* Enable Writes to REG_AFE_LPDACDAT00 */ +#define BITM_AFE_LPDACCON0_WAVETYPE 0x00000040 /* LPDAC Data Source */ +#define BITM_AFE_LPDACCON0_DACMDE 0x00000020 /* LPDAC0 Switch Settings */ +#define BITM_AFE_LPDACCON0_VZEROMUX 0x00000010 /* VZERO MUX Select */ +#define BITM_AFE_LPDACCON0_VBIASMUX 0x00000008 /* VBIAS MUX Select */ +#define BITM_AFE_LPDACCON0_REFSEL 0x00000004 /* Reference Select Bit */ +#define BITM_AFE_LPDACCON0_PWDEN 0x00000002 /* LPDAC0 Power Down */ +#define BITM_AFE_LPDACCON0_RSTEN \ + 0x00000001 /* Enable Writes to REG_AFE_LPDACDAT00 */ +#define ENUM_AFE_LPDACCON0_MMR \ + 0x00000000 /* WAVETYPE: Direct from REG_AFE_LPDACDAT0DAT0 */ +#define ENUM_AFE_LPDACCON0_WAVEGEN \ + 0x00000040 /* WAVETYPE: Waveform generator */ +#define ENUM_AFE_LPDACCON0_NORM \ + 0x00000000 /* DACMDE: REG_AFE_LPDACDAT00 switches set for normal mode */ +#define ENUM_AFE_LPDACCON0_DIAG \ + 0x00000020 /* DACMDE: REG_AFE_LPDACDAT00 switches set for Diagnostic mode \ + */ +#define ENUM_AFE_LPDACCON0_BITS6 0x00000000 /* VZEROMUX: VZERO 6BIT */ +#define ENUM_AFE_LPDACCON0_BITS12 0x00000010 /* VZEROMUX: VZERO 12BIT */ +#define ENUM_AFE_LPDACCON0_12BIT 0x00000000 /* VBIASMUX: Output 12Bit */ +#define ENUM_AFE_LPDACCON0_EN 0x00000008 /* VBIASMUX: output 6Bit */ +#define ENUM_AFE_LPDACCON0_ULPREF 0x00000000 /* REFSEL: ULP2P5V Ref */ +#define ENUM_AFE_LPDACCON0_AVDD 0x00000004 /* REFSEL: AVDD Reference */ +#define ENUM_AFE_LPDACCON0_PWREN \ + 0x00000000 /* PWDEN: REG_AFE_LPDACDAT00 Powered On */ +#define ENUM_AFE_LPDACCON0_PWRDIS \ + 0x00000002 /* PWDEN: REG_AFE_LPDACDAT00 Powered Off */ +#define ENUM_AFE_LPDACCON0_WRITEDIS \ + 0x00000000 /* RSTEN: Disable REG_AFE_LPDACDAT00 Writes */ +#define ENUM_AFE_LPDACCON0_WRITEEN \ + 0x00000001 /* RSTEN: Enable REG_AFE_LPDACDAT00 Writes */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACDAT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPDACDAT1_DACIN6 12 /* 6BITVAL, 1LSB=34.375mV */ +#define BITP_AFE_LPDACDAT1_DACIN12 0 /* 12BITVAL, 1LSB=537uV */ +#define BITM_AFE_LPDACDAT1_DACIN6 \ + (_ADI_MSK_3(0x0003F000, 0x0003F000UL, uint32_t)) /* 6BITVAL, 1LSB=34.375mV \ + */ +#define BITM_AFE_LPDACDAT1_DACIN12 \ + (_ADI_MSK_3(0x00000FFF, 0x00000FFFUL, uint32_t)) /* 12BITVAL, 1LSB=537uV */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACSW1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPDACSW1_LPMODEDIS 5 /* Switch Control */ +#define BITP_AFE_LPDACSW1_LPDACSW 0 /* ULPDAC0 Switches Matrix */ +#define BITM_AFE_LPDACSW1_LPMODEDIS \ + (_ADI_MSK_3(0x00000020, 0x00000020UL, uint32_t)) /* Switch Control */ +#define BITM_AFE_LPDACSW1_LPDACSW \ + (_ADI_MSK_3(0x0000001F, 0x0000001FUL, \ + uint32_t)) /* ULPDAC0 Switches Matrix */ +#define ENUM_AFE_LPDACSW1_DACCONBIT5 \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, \ + uint32_t)) /* LPMODEDIS: ULPDAC Switch controlled by ULPDACCON1 \ + bit 5 */ +#define ENUM_AFE_LPDACSW1_OVRRIDE \ + (_ADI_MSK_3(0x00000020, 0x00000020UL, \ + uint32_t)) /* LPMODEDIS: ULPDAC Switches override */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACCON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPDACCON1_WAVETYPE 6 /* DAC Input Source */ +#define BITP_AFE_LPDACCON1_DACMDE 5 /* LPDAC1 Switch Settings */ +#define BITP_AFE_LPDACCON1_VZEROMUX 4 /* VZEROOUT */ +#define BITP_AFE_LPDACCON1_VBIASMUX 3 /* BITSEL */ +#define BITP_AFE_LPDACCON1_REFSEL 2 /* REFSEL */ +#define BITP_AFE_LPDACCON1_PWDEN 1 /* ULPDAC0 Power */ +#define BITP_AFE_LPDACCON1_RSTEN 0 /* Enable Writes to ULPDAC1 */ +#define BITM_AFE_LPDACCON1_WAVETYPE \ + (_ADI_MSK_3(0x00000040, 0x00000040UL, uint32_t)) /* DAC Input Source */ +#define BITM_AFE_LPDACCON1_DACMDE \ + (_ADI_MSK_3(0x00000020, 0x00000020UL, uint32_t)) /* LPDAC1 Switch Settings \ + */ +#define BITM_AFE_LPDACCON1_VZEROMUX \ + (_ADI_MSK_3(0x00000010, 0x00000010UL, uint32_t)) /* VZEROOUT */ +#define BITM_AFE_LPDACCON1_VBIASMUX \ + (_ADI_MSK_3(0x00000008, 0x00000008UL, uint32_t)) /* BITSEL */ +#define BITM_AFE_LPDACCON1_REFSEL \ + (_ADI_MSK_3(0x00000004, 0x00000004UL, uint32_t)) /* REFSEL */ +#define BITM_AFE_LPDACCON1_PWDEN \ + (_ADI_MSK_3(0x00000002, 0x00000002UL, uint32_t)) /* ULPDAC0 Power */ +#define BITM_AFE_LPDACCON1_RSTEN \ + (_ADI_MSK_3(0x00000001, 0x00000001UL, \ + uint32_t)) /* Enable Writes to ULPDAC1 */ +#define ENUM_AFE_LPDACCON1_NORM \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, \ + uint32_t)) /* DACMDE: ULPDAC1 switches set for normal mode */ +#define ENUM_AFE_LPDACCON1_DIAG \ + (_ADI_MSK_3( \ + 0x00000020, 0x00000020UL, \ + uint32_t)) /* DACMDE: ULPDAC1 switches set for Diagnostic mode */ +#define ENUM_AFE_LPDACCON1_BITS6 \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, uint32_t)) /* VZEROMUX: VZERO 6BIT */ +#define ENUM_AFE_LPDACCON1_BITS12 \ + (_ADI_MSK_3(0x00000010, 0x00000010UL, uint32_t)) /* VZEROMUX: VZERO 12BIT \ + */ +#define ENUM_AFE_LPDACCON1_DIS \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, uint32_t)) /* VBIASMUX: 12BIT Output \ + */ +#define ENUM_AFE_LPDACCON1_EN \ + (_ADI_MSK_3(0x00000008, 0x00000008UL, uint32_t)) /* VBIASMUX: 6BIT Output \ + */ +#define ENUM_AFE_LPDACCON1_ULPREF \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, uint32_t)) +#define ENUM_AFE_LPDACCON1_AVDD (_ADI_MSK_3(0x00000004, 0x00000004UL, uint32_t)) +#define ENUM_AFE_LPDACCON1_PWREN \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, \ + uint32_t)) /* PWDEN: ULPDAC1 Powered On */ +#define ENUM_AFE_LPDACCON1_PWRDIS \ + (_ADI_MSK_3(0x00000002, 0x00000002UL, \ + uint32_t)) /* PWDEN: ULPDAC1 Powered Off */ +#define ENUM_AFE_LPDACCON1_WRITEDIS \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, \ + uint32_t)) /* RSTEN: Disable ULPDAC1 Writes */ +#define ENUM_AFE_LPDACCON1_WRITEEN \ + (_ADI_MSK_3(0x00000001, 0x00000001UL, \ + uint32_t)) /* RSTEN: Enable ULPDAC1 Writes */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DSWFULLCON_D8 7 /* Control of D8 Switch. */ +#define BITP_AFE_DSWFULLCON_D7 6 /* Control of D7 Switch. */ +#define BITP_AFE_DSWFULLCON_D6 5 /* Control of D6 Switch. */ +#define BITP_AFE_DSWFULLCON_D5 4 /* Control of D5 Switch. */ +#define BITP_AFE_DSWFULLCON_D4 3 /* Control of D4 Switch. */ +#define BITP_AFE_DSWFULLCON_D3 2 /* Control of D3 Switch. */ +#define BITP_AFE_DSWFULLCON_D2 1 /* Control of D2 Switch. */ +#define BITP_AFE_DSWFULLCON_DR0 0 /* Control of Dr0 Switch. */ +#define BITM_AFE_DSWFULLCON_D8 0x00000080 /* Control of D8 Switch. */ +#define BITM_AFE_DSWFULLCON_D7 0x00000040 /* Control of D7 Switch. */ +#define BITM_AFE_DSWFULLCON_D6 0x00000020 /* Control of D6 Switch. */ +#define BITM_AFE_DSWFULLCON_D5 0x00000010 /* Control of D5 Switch. */ +#define BITM_AFE_DSWFULLCON_D4 0x00000008 /* Control of D4 Switch. */ +#define BITM_AFE_DSWFULLCON_D3 0x00000004 /* Control of D3 Switch. */ +#define BITM_AFE_DSWFULLCON_D2 0x00000002 /* Control of D2 Switch. */ +#define BITM_AFE_DSWFULLCON_DR0 0x00000001 /* Control of Dr0 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_NSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_NSWFULLCON_NL2 11 /* Control of NL2 Switch. */ +#define BITP_AFE_NSWFULLCON_NL 10 /* Control of NL Switch. */ +#define BITP_AFE_NSWFULLCON_NR1 \ + 9 /* Control of Nr1 Switch. Set Will Close Nr1, Unset Open */ +#define BITP_AFE_NSWFULLCON_N9 \ + 8 /* Control of N9 Switch. Set Will Close N9, Unset Open */ +#define BITP_AFE_NSWFULLCON_N8 \ + 7 /* Control of N8 Switch. Set Will Close N8, Unset Open */ +#define BITP_AFE_NSWFULLCON_N7 \ + 6 /* Control of N7 Switch. Set Will Close N7, Unset Open */ +#define BITP_AFE_NSWFULLCON_N6 \ + 5 /* Control of N6 Switch. Set Will Close N6, Unset Open */ +#define BITP_AFE_NSWFULLCON_N5 \ + 4 /* Control of N5 Switch. Set Will Close N5, Unset Open */ +#define BITP_AFE_NSWFULLCON_N4 \ + 3 /* Control of N4 Switch. Set Will Close N4, Unset Open */ +#define BITP_AFE_NSWFULLCON_N3 \ + 2 /* Control of N3 Switch. Set Will Close N3, Unset Open */ +#define BITP_AFE_NSWFULLCON_N2 \ + 1 /* Control of N2 Switch. Set Will Close N2, Unset Open */ +#define BITP_AFE_NSWFULLCON_N1 \ + 0 /* Control of N1 Switch. Set Will Close N1, Unset Open */ +#define BITM_AFE_NSWFULLCON_NL2 0x00000800 /* Control of NL2 Switch. */ +#define BITM_AFE_NSWFULLCON_NL 0x00000400 /* Control of NL Switch. */ +#define BITM_AFE_NSWFULLCON_NR1 \ + 0x00000200 /* Control of Nr1 Switch. Set Will Close Nr1, Unset Open */ +#define BITM_AFE_NSWFULLCON_N9 \ + 0x00000100 /* Control of N9 Switch. Set Will Close N9, Unset Open */ +#define BITM_AFE_NSWFULLCON_N8 \ + 0x00000080 /* Control of N8 Switch. Set Will Close N8, Unset Open */ +#define BITM_AFE_NSWFULLCON_N7 \ + 0x00000040 /* Control of N7 Switch. Set Will Close N7, Unset Open */ +#define BITM_AFE_NSWFULLCON_N6 \ + 0x00000020 /* Control of N6 Switch. Set Will Close N6, Unset Open */ +#define BITM_AFE_NSWFULLCON_N5 \ + 0x00000010 /* Control of N5 Switch. Set Will Close N5, Unset Open */ +#define BITM_AFE_NSWFULLCON_N4 \ + 0x00000008 /* Control of N4 Switch. Set Will Close N4, Unset Open */ +#define BITM_AFE_NSWFULLCON_N3 \ + 0x00000004 /* Control of N3 Switch. Set Will Close N3, Unset Open */ +#define BITM_AFE_NSWFULLCON_N2 \ + 0x00000002 /* Control of N2 Switch. Set Will Close N2, Unset Open */ +#define BITM_AFE_NSWFULLCON_N1 \ + 0x00000001 /* Control of N1 Switch. Set Will Close N1, Unset Open */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_PSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_PSWFULLCON_PL2 14 /* PL2 Switch Control */ +#define BITP_AFE_PSWFULLCON_PL 13 /* PL Switch Control */ +#define BITP_AFE_PSWFULLCON_P12 \ + 11 /* Control of P12 Switch. Set Will Close P12, Unset Open */ +#define BITP_AFE_PSWFULLCON_P11 \ + 10 /* Control of P11 Switch. Set Will Close P11, Unset Open */ +#define BITP_AFE_PSWFULLCON_P10 9 /* P10 Switch Control */ +#define BITP_AFE_PSWFULLCON_P9 \ + 8 /* Control of P9 Switch. Set Will Close P9, Unset Open */ +#define BITP_AFE_PSWFULLCON_P8 \ + 7 /* Control of P8 Switch. Set Will Close P8, Unset Open */ +#define BITP_AFE_PSWFULLCON_P7 \ + 6 /* Control of P7 Switch. Set Will Close P7, Unset Open */ +#define BITP_AFE_PSWFULLCON_P6 \ + 5 /* Control of P6 Switch. Set Will Close P6, Unset Open */ +#define BITP_AFE_PSWFULLCON_P5 \ + 4 /* Control of P5 Switch. Set Will Close P5, Unset Open */ +#define BITP_AFE_PSWFULLCON_P4 \ + 3 /* Control of P4 Switch. Set Will Close P4, Unset Open */ +#define BITP_AFE_PSWFULLCON_P3 \ + 2 /* Control of P3 Switch. Set Will Close P3, Unset Open */ +#define BITP_AFE_PSWFULLCON_P2 \ + 1 /* Control of P2 Switch. Set Will Close P2, Unset Open */ +#define BITP_AFE_PSWFULLCON_PR0 0 /* PR0 Switch Control */ +#define BITM_AFE_PSWFULLCON_PL2 0x00004000 /* PL2 Switch Control */ +#define BITM_AFE_PSWFULLCON_PL 0x00002000 /* PL Switch Control */ +#define BITM_AFE_PSWFULLCON_P12 \ + 0x00000800 /* Control of P12 Switch. Set Will Close P12, Unset Open */ +#define BITM_AFE_PSWFULLCON_P11 \ + 0x00000400 /* Control of P11 Switch. Set Will Close P11, Unset Open */ +#define BITM_AFE_PSWFULLCON_P10 0x00000200 /* P10 Switch Control */ +#define BITM_AFE_PSWFULLCON_P9 \ + 0x00000100 /* Control of P9 Switch. Set Will Close P9, Unset Open */ +#define BITM_AFE_PSWFULLCON_P8 \ + 0x00000080 /* Control of P8 Switch. Set Will Close P8, Unset Open */ +#define BITM_AFE_PSWFULLCON_P7 \ + 0x00000040 /* Control of P7 Switch. Set Will Close P7, Unset Open */ +#define BITM_AFE_PSWFULLCON_P6 \ + 0x00000020 /* Control of P6 Switch. Set Will Close P6, Unset Open */ +#define BITM_AFE_PSWFULLCON_P5 \ + 0x00000010 /* Control of P5 Switch. Set Will Close P5, Unset Open */ +#define BITM_AFE_PSWFULLCON_P4 \ + 0x00000008 /* Control of P4 Switch. Set Will Close P4, Unset Open */ +#define BITM_AFE_PSWFULLCON_P3 \ + 0x00000004 /* Control of P3 Switch. Set Will Close P3, Unset Open */ +#define BITM_AFE_PSWFULLCON_P2 \ + 0x00000002 /* Control of P2 Switch. Set Will Close P2, Unset Open */ +#define BITM_AFE_PSWFULLCON_PR0 0x00000001 /* PR0 Switch Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_TSWFULLCON_TR1 \ + 11 /* Control of Tr1 Switch. Set Will Close Tr1, Unset Open */ +#define BITP_AFE_TSWFULLCON_T11 \ + 10 /* Control of T11 Switch. Set Will Close T11, Unset Open */ +#define BITP_AFE_TSWFULLCON_T10 \ + 9 /* Control of T10 Switch. Set Will Close T10, Unset Open */ +#define BITP_AFE_TSWFULLCON_T9 \ + 8 /* Control of T9 Switch. Set Will Close T9, Unset Open */ +#define BITP_AFE_TSWFULLCON_T7 \ + 6 /* Control of T7 Switch. Set Will Close T7, Unset Open */ +#define BITP_AFE_TSWFULLCON_T5 \ + 4 /* Control of T5 Switch. Set Will Close T5, Unset Open */ +#define BITP_AFE_TSWFULLCON_T4 \ + 3 /* Control of T4 Switch. Set Will Close T4, Unset Open */ +#define BITP_AFE_TSWFULLCON_T3 \ + 2 /* Control of T3 Switch. Set Will Close T3, Unset Open */ +#define BITP_AFE_TSWFULLCON_T2 \ + 1 /* Control of T2 Switch. Set Will Close T2, Unset Open */ +#define BITP_AFE_TSWFULLCON_T1 \ + 0 /* Control of T1 Switch. Set Will Close T1, Unset Open */ +#define BITM_AFE_TSWFULLCON_TR1 \ + 0x00000800 /* Control of Tr1 Switch. Set Will Close Tr1, Unset Open */ +#define BITM_AFE_TSWFULLCON_T11 \ + 0x00000400 /* Control of T11 Switch. Set Will Close T11, Unset Open */ +#define BITM_AFE_TSWFULLCON_T10 \ + 0x00000200 /* Control of T10 Switch. Set Will Close T10, Unset Open */ +#define BITM_AFE_TSWFULLCON_T9 \ + 0x00000100 /* Control of T9 Switch. Set Will Close T9, Unset Open */ +#define BITM_AFE_TSWFULLCON_T7 \ + 0x00000040 /* Control of T7 Switch. Set Will Close T7, Unset Open */ +#define BITM_AFE_TSWFULLCON_T5 \ + 0x00000010 /* Control of T5 Switch. Set Will Close T5, Unset Open */ +#define BITM_AFE_TSWFULLCON_T4 \ + 0x00000008 /* Control of T4 Switch. Set Will Close T4, Unset Open */ +#define BITM_AFE_TSWFULLCON_T3 \ + 0x00000004 /* Control of T3 Switch. Set Will Close T3, Unset Open */ +#define BITM_AFE_TSWFULLCON_T2 \ + 0x00000002 /* Control of T2 Switch. Set Will Close T2, Unset Open */ +#define BITM_AFE_TSWFULLCON_T1 \ + 0x00000001 /* Control of T1 Switch. Set Will Close T1, Unset Open */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TEMPSENS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_TEMPSENS_CHOPFRESEL 2 /* Chop Mode Frequency Setting */ +#define BITP_AFE_TEMPSENS_CHOPCON 1 /* Temp Sensor Chop Mode */ +#define BITP_AFE_TEMPSENS_ENABLE 0 /* Unused */ +#define BITM_AFE_TEMPSENS_CHOPFRESEL \ + 0x0000000C /* Chop Mode Frequency Setting */ +#define BITM_AFE_TEMPSENS_CHOPCON 0x00000002 /* Temp Sensor Chop Mode */ +#define BITM_AFE_TEMPSENS_ENABLE 0x00000001 /* Unused */ +#define ENUM_AFE_TEMPSENS_DIS 0x00000000 /* CHOPCON: Disable chop */ +#define ENUM_AFE_TEMPSENS_EN 0x00000002 /* CHOPCON: Enable chop */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_BUFSENCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_BUFSENCON_V1P8THERMSTEN 8 /* Buffered Reference Output */ +#define BITP_AFE_BUFSENCON_V1P1LPADCCHGDIS \ + 6 /* Controls Decoupling Cap Discharge Switch */ +#define BITP_AFE_BUFSENCON_V1P1LPADCEN 5 /* ADC 1.1V LP Buffer */ +#define BITP_AFE_BUFSENCON_V1P1HPADCEN 4 /* Enable 1.1V HP CM Buffer */ +#define BITP_AFE_BUFSENCON_V1P8HPADCCHGDIS \ + 3 /* Controls Decoupling Cap Discharge Switch */ +#define BITP_AFE_BUFSENCON_V1P8LPADCEN 2 /* ADC 1.8V LP Reference Buffer */ +#define BITP_AFE_BUFSENCON_V1P8HPADCILIMITEN 1 /* HP ADC Input Current Limit \ + */ +#define BITP_AFE_BUFSENCON_V1P8HPADCEN 0 /* HP 1.8V Reference Buffer */ +#define BITM_AFE_BUFSENCON_V1P8THERMSTEN \ + 0x00000100 /* Buffered Reference Output */ +#define BITM_AFE_BUFSENCON_V1P1LPADCCHGDIS \ + 0x00000040 /* Controls Decoupling Cap Discharge Switch */ +#define BITM_AFE_BUFSENCON_V1P1LPADCEN 0x00000020 /* ADC 1.1V LP Buffer */ +#define BITM_AFE_BUFSENCON_V1P1HPADCEN \ + 0x00000010 /* Enable 1.1V HP CM Buffer */ +#define BITM_AFE_BUFSENCON_V1P8HPADCCHGDIS \ + 0x00000008 /* Controls Decoupling Cap Discharge Switch */ +#define BITM_AFE_BUFSENCON_V1P8LPADCEN \ + 0x00000004 /* ADC 1.8V LP Reference Buffer */ +#define BITM_AFE_BUFSENCON_V1P8HPADCILIMITEN \ + 0x00000002 /* HP ADC Input Current Limit */ +#define BITM_AFE_BUFSENCON_V1P8HPADCEN \ + 0x00000001 /* HP 1.8V Reference Buffer */ +#define ENUM_AFE_BUFSENCON_DIS \ + 0x00000000 /* V1P8THERMSTEN: Disable 1.8V Buffered Reference output */ +#define ENUM_AFE_BUFSENCON_EN \ + 0x00000100 /* V1P8THERMSTEN: Enable 1.8V Buffered Reference output */ +#define ENUM_AFE_BUFSENCON_ENCHRG 0x00000000 /* V1P1LPADCCHGDIS: Open switch \ + */ +#define ENUM_AFE_BUFSENCON_DISCHRG \ + 0x00000040 /* V1P1LPADCCHGDIS: Close Switch */ +#define ENUM_AFE_BUFSENCON_DISABLE \ + 0x00000000 /* V1P1LPADCEN: Disable ADC 1.8V LP Reference Buffer */ +#define ENUM_AFE_BUFSENCON_ENABLE \ + 0x00000020 /* V1P1LPADCEN: Enable ADC 1.8V LP Reference Buffer */ +#define ENUM_AFE_BUFSENCON_OFF \ + 0x00000000 /* V1P1HPADCEN: Disable 1.1V HP Common Mode Buffer */ +#define ENUM_AFE_BUFSENCON_ON \ + 0x00000010 /* V1P1HPADCEN: Enable 1.1V HP Common Mode Buffer */ +#define ENUM_AFE_BUFSENCON_OPEN 0x00000000 /* V1P8HPADCCHGDIS: Open switch */ +#define ENUM_AFE_BUFSENCON_CLOSED \ + 0x00000008 /* V1P8HPADCCHGDIS: Close Switch */ +#define ENUM_AFE_BUFSENCON_LPADCREF_DIS \ + 0x00000000 /* V1P8LPADCEN: Disable LP 1.8V Reference Buffer */ +#define ENUM_AFE_BUFSENCON_LPADCREF_EN \ + 0x00000004 /* V1P8LPADCEN: Enable LP 1.8V Reference Buffer */ +#define ENUM_AFE_BUFSENCON_LIMIT_DIS \ + 0x00000000 /* V1P8HPADCILIMITEN: Disable buffer Current Limit */ +#define ENUM_AFE_BUFSENCON_LIMIT_EN \ + 0x00000002 /* V1P8HPADCILIMITEN: Enable buffer Current Limit */ +#define ENUM_AFE_BUFSENCON_HPBUF_DIS \ + 0x00000000 /* V1P8HPADCEN: Disable 1.8V HP ADC Reference Buffer */ +#define ENUM_AFE_BUFSENCON_HPBUF_EN \ + 0x00000001 /* V1P8HPADCEN: Enable 1.8V HP ADC Reference Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCCON_GNPGA 16 /* PGA Gain Setup */ +#define BITP_AFE_ADCCON_GNOFSELPGA 15 /* Internal Offset/Gain Cancellation */ +#define BITP_AFE_ADCCON_GNOFFSEL 13 /* Obsolete */ +#define BITP_AFE_ADCCON_MUXSELN 8 /* Select Negative Input */ +#define BITP_AFE_ADCCON_MUXSELP 0 /* Select Positive Input */ +#define BITM_AFE_ADCCON_GNPGA 0x00070000 /* PGA Gain Setup */ +#define BITM_AFE_ADCCON_GNOFSELPGA \ + 0x00008000 /* Internal Offset/Gain Cancellation */ +#define BITM_AFE_ADCCON_GNOFFSEL 0x00006000 /* Obsolete */ +#define BITM_AFE_ADCCON_MUXSELN 0x00001F00 /* Select Negative Input */ +#define BITM_AFE_ADCCON_MUXSELP 0x0000003F /* Select Positive Input */ +#define ENUM_AFE_ADCCON_RESERVED 0x00000011 /* MUXSELP: Reserved */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DSWSTA_D8STA 7 /* Status of D8 Switch. */ +#define BITP_AFE_DSWSTA_D7STA 6 /* Status of D7 Switch. */ +#define BITP_AFE_DSWSTA_D6STA 5 /* Status of D6 Switch. */ +#define BITP_AFE_DSWSTA_D5STA 4 /* Status of D5 Switch. */ +#define BITP_AFE_DSWSTA_D4STA 3 /* Status of D4 Switch. */ +#define BITP_AFE_DSWSTA_D3STA 2 /* Status of D3 Switch. */ +#define BITP_AFE_DSWSTA_D2STA 1 /* Status of D2 Switch. */ +#define BITP_AFE_DSWSTA_D1STA 0 /* Status of Dr0 Switch. */ +#define BITM_AFE_DSWSTA_D8STA 0x00000080 /* Status of D8 Switch. */ +#define BITM_AFE_DSWSTA_D7STA 0x00000040 /* Status of D7 Switch. */ +#define BITM_AFE_DSWSTA_D6STA 0x00000020 /* Status of D6 Switch. */ +#define BITM_AFE_DSWSTA_D5STA 0x00000010 /* Status of D5 Switch. */ +#define BITM_AFE_DSWSTA_D4STA 0x00000008 /* Status of D4 Switch. */ +#define BITM_AFE_DSWSTA_D3STA 0x00000004 /* Status of D3 Switch. */ +#define BITM_AFE_DSWSTA_D2STA 0x00000002 /* Status of D2 Switch. */ +#define BITM_AFE_DSWSTA_D1STA 0x00000001 /* Status of Dr0 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_PSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_PSWSTA_PL2STA 14 /* PL Switch Control */ +#define BITP_AFE_PSWSTA_PLSTA 13 /* PL Switch Control */ +#define BITP_AFE_PSWSTA_P13STA 12 /* Status of P13 Switch. */ +#define BITP_AFE_PSWSTA_P12STA 11 /* Status of P12 Switch. */ +#define BITP_AFE_PSWSTA_P11STA 10 /* Status of P11 Switch. */ +#define BITP_AFE_PSWSTA_P10STA 9 /* Status of P10 Switch. */ +#define BITP_AFE_PSWSTA_P9STA 8 /* Status of P9 Switch. */ +#define BITP_AFE_PSWSTA_P8STA 7 /* Status of P8 Switch. */ +#define BITP_AFE_PSWSTA_P7STA 6 /* Status of P7 Switch. */ +#define BITP_AFE_PSWSTA_P6STA 5 /* Status of P6 Switch. */ +#define BITP_AFE_PSWSTA_P5STA 4 /* Status of P5 Switch. */ +#define BITP_AFE_PSWSTA_P4STA 3 /* Status of P4 Switch. */ +#define BITP_AFE_PSWSTA_P3STA 2 /* Status of P3 Switch. */ +#define BITP_AFE_PSWSTA_P2STA 1 /* Status of P2 Switch. */ +#define BITP_AFE_PSWSTA_PR0STA 0 /* PR0 Switch Control */ +#define BITM_AFE_PSWSTA_PL2STA 0x00004000 /* PL Switch Control */ +#define BITM_AFE_PSWSTA_PLSTA 0x00002000 /* PL Switch Control */ +#define BITM_AFE_PSWSTA_P13STA 0x00001000 /* Status of P13 Switch. */ +#define BITM_AFE_PSWSTA_P12STA 0x00000800 /* Status of P12 Switch. */ +#define BITM_AFE_PSWSTA_P11STA 0x00000400 /* Status of P11 Switch. */ +#define BITM_AFE_PSWSTA_P10STA 0x00000200 /* Status of P10 Switch. */ +#define BITM_AFE_PSWSTA_P9STA 0x00000100 /* Status of P9 Switch. */ +#define BITM_AFE_PSWSTA_P8STA 0x00000080 /* Status of P8 Switch. */ +#define BITM_AFE_PSWSTA_P7STA 0x00000040 /* Status of P7 Switch. */ +#define BITM_AFE_PSWSTA_P6STA 0x00000020 /* Status of P6 Switch. */ +#define BITM_AFE_PSWSTA_P5STA 0x00000010 /* Status of P5 Switch. */ +#define BITM_AFE_PSWSTA_P4STA 0x00000008 /* Status of P4 Switch. */ +#define BITM_AFE_PSWSTA_P3STA 0x00000004 /* Status of P3 Switch. */ +#define BITM_AFE_PSWSTA_P2STA 0x00000002 /* Status of P2 Switch. */ +#define BITM_AFE_PSWSTA_PR0STA 0x00000001 /* PR0 Switch Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_NSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_NSWSTA_NL2STA 11 /* Status of NL2 Switch. */ +#define BITP_AFE_NSWSTA_NLSTA 10 /* Status of NL Switch. */ +#define BITP_AFE_NSWSTA_NR1STA 9 /* Status of NR1 Switch. */ +#define BITP_AFE_NSWSTA_N9STA 8 /* Status of N9 Switch. */ +#define BITP_AFE_NSWSTA_N8STA 7 /* Status of N8 Switch. */ +#define BITP_AFE_NSWSTA_N7STA 6 /* Status of N7 Switch. */ +#define BITP_AFE_NSWSTA_N6STA 5 /* Status of N6 Switch. */ +#define BITP_AFE_NSWSTA_N5STA 4 /* Status of N5 Switch. */ +#define BITP_AFE_NSWSTA_N4STA 3 /* Status of N4 Switch. */ +#define BITP_AFE_NSWSTA_N3STA 2 /* Status of N3 Switch. */ +#define BITP_AFE_NSWSTA_N2STA 1 /* Status of N2 Switch. */ +#define BITP_AFE_NSWSTA_N1STA 0 /* Status of N1 Switch. */ +#define BITM_AFE_NSWSTA_NL2STA 0x00000800 /* Status of NL2 Switch. */ +#define BITM_AFE_NSWSTA_NLSTA 0x00000400 /* Status of NL Switch. */ +#define BITM_AFE_NSWSTA_NR1STA 0x00000200 /* Status of NR1 Switch. */ +#define BITM_AFE_NSWSTA_N9STA 0x00000100 /* Status of N9 Switch. */ +#define BITM_AFE_NSWSTA_N8STA 0x00000080 /* Status of N8 Switch. */ +#define BITM_AFE_NSWSTA_N7STA 0x00000040 /* Status of N7 Switch. */ +#define BITM_AFE_NSWSTA_N6STA 0x00000020 /* Status of N6 Switch. */ +#define BITM_AFE_NSWSTA_N5STA 0x00000010 /* Status of N5 Switch. */ +#define BITM_AFE_NSWSTA_N4STA 0x00000008 /* Status of N4 Switch. */ +#define BITM_AFE_NSWSTA_N3STA 0x00000004 /* Status of N3 Switch. */ +#define BITM_AFE_NSWSTA_N2STA 0x00000002 /* Status of N2 Switch. */ +#define BITM_AFE_NSWSTA_N1STA 0x00000001 /* Status of N1 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_TSWSTA_TR1STA 11 /* Status of TR1 Switch. */ +#define BITP_AFE_TSWSTA_T11STA 10 /* Status of T11 Switch. */ +#define BITP_AFE_TSWSTA_T10STA 9 /* Status of T10 Switch. */ +#define BITP_AFE_TSWSTA_T9STA 8 /* Status of T9 Switch. */ +#define BITP_AFE_TSWSTA_T8STA 7 /* Status of T8 Switch. */ +#define BITP_AFE_TSWSTA_T7STA 6 /* Status of T7 Switch. */ +#define BITP_AFE_TSWSTA_T6STA 5 /* Status of T6 Switch. */ +#define BITP_AFE_TSWSTA_T5STA 4 /* Status of T5 Switch. */ +#define BITP_AFE_TSWSTA_T4STA 3 /* Status of T4 Switch. */ +#define BITP_AFE_TSWSTA_T3STA 2 /* Status of T3 Switch. */ +#define BITP_AFE_TSWSTA_T2STA 1 /* Status of T2 Switch. */ +#define BITP_AFE_TSWSTA_T1STA 0 /* Status of T1 Switch. */ +#define BITM_AFE_TSWSTA_TR1STA 0x00000800 /* Status of TR1 Switch. */ +#define BITM_AFE_TSWSTA_T11STA 0x00000400 /* Status of T11 Switch. */ +#define BITM_AFE_TSWSTA_T10STA 0x00000200 /* Status of T10 Switch. */ +#define BITM_AFE_TSWSTA_T9STA 0x00000100 /* Status of T9 Switch. */ +#define BITM_AFE_TSWSTA_T8STA 0x00000080 /* Status of T8 Switch. */ +#define BITM_AFE_TSWSTA_T7STA 0x00000040 /* Status of T7 Switch. */ +#define BITM_AFE_TSWSTA_T6STA 0x00000020 /* Status of T6 Switch. */ +#define BITM_AFE_TSWSTA_T5STA 0x00000010 /* Status of T5 Switch. */ +#define BITM_AFE_TSWSTA_T4STA 0x00000008 /* Status of T4 Switch. */ +#define BITM_AFE_TSWSTA_T3STA 0x00000004 /* Status of T3 Switch. */ +#define BITM_AFE_TSWSTA_T2STA 0x00000002 /* Status of T2 Switch. */ +#define BITM_AFE_TSWSTA_T1STA 0x00000001 /* Status of T1 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_STATSVAR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_STATSVAR_VARIANCE 0 /* Statistical Variance Value */ +#define BITM_AFE_STATSVAR_VARIANCE 0x7FFFFFFF /* Statistical Variance Value \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_STATSCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_STATSCON_STDDEV 7 /* Standard Deviation Configuration */ +#define BITP_AFE_STATSCON_SAMPLENUM 4 /* Sample Size */ +#define BITP_AFE_STATSCON_RESRVED 1 /* Reserved */ +#define BITP_AFE_STATSCON_STATSEN 0 /* Statistics Enable */ +#define BITM_AFE_STATSCON_STDDEV \ + 0x00000F80 /* Standard Deviation Configuration */ +#define BITM_AFE_STATSCON_SAMPLENUM 0x00000070 /* Sample Size */ +#define BITM_AFE_STATSCON_RESRVED 0x0000000E /* Reserved */ +#define BITM_AFE_STATSCON_STATSEN 0x00000001 /* Statistics Enable */ +#define ENUM_AFE_STATSCON_DIS 0x00000000 /* STATSEN: Disable Statistics */ +#define ENUM_AFE_STATSCON_EN 0x00000001 /* STATSEN: Enable Statistics */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_STATSMEAN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_STATSMEAN_MEAN 0 /* Mean Output */ +#define BITM_AFE_STATSMEAN_MEAN 0x0000FFFF /* Mean Output */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ0INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQ0INFO_LEN 16 /* SEQ0 Instruction Number */ +#define BITP_AFE_SEQ0INFO_ADDR 0 /* SEQ0 Start Address */ +#define BITM_AFE_SEQ0INFO_LEN 0x07FF0000 /* SEQ0 Instruction Number */ +#define BITM_AFE_SEQ0INFO_ADDR 0x000007FF /* SEQ0 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ2INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQ2INFO_LEN 16 /* SEQ2 Instruction Number */ +#define BITP_AFE_SEQ2INFO_ADDR 0 /* SEQ2 Start Address */ +#define BITM_AFE_SEQ2INFO_LEN 0x07FF0000 /* SEQ2 Instruction Number */ +#define BITM_AFE_SEQ2INFO_ADDR 0x000007FF /* SEQ2 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CMDFIFOWADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_CMDFIFOWADDR_WADDR 0 /* Write Address */ +#define BITM_AFE_CMDFIFOWADDR_WADDR 0x000007FF /* Write Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CMDDATACON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_CMDDATACON_DATAMEMMDE 9 /* Data FIFO Mode Select */ +#define BITP_AFE_CMDDATACON_DATA_MEM_SEL 6 /* Data FIFO Size Select */ +#define BITP_AFE_CMDDATACON_CMDMEMMDE \ + 3 /* This is Command Fifo Mode Register */ +#define BITP_AFE_CMDDATACON_CMD_MEM_SEL 0 /* Command Memory Select */ +#define BITM_AFE_CMDDATACON_DATAMEMMDE 0x00000E00 /* Data FIFO Mode Select */ +#define BITM_AFE_CMDDATACON_DATA_MEM_SEL 0x000001C0 /* Data FIFO Size Select \ + */ +#define BITM_AFE_CMDDATACON_CMDMEMMDE \ + 0x00000038 /* This is Command Fifo Mode Register */ +#define BITM_AFE_CMDDATACON_CMD_MEM_SEL 0x00000007 /* Command Memory Select \ + */ +#define ENUM_AFE_CMDDATACON_DFIFO 0x00000400 /* DATAMEMMDE: FIFO MODE */ +#define ENUM_AFE_CMDDATACON_DSTM 0x00000600 /* DATAMEMMDE: STREAM MODE */ +#define ENUM_AFE_CMDDATACON_DMEM32B \ + 0x00000000 /* DATA_MEM_SEL: 32B_1 Local Memory */ +#define ENUM_AFE_CMDDATACON_DMEM2K 0x00000040 /* DATA_MEM_SEL: 2K_2 SRAM */ +#define ENUM_AFE_CMDDATACON_DMEM4K 0x00000080 /* DATA_MEM_SEL: 2K_2~1 SRAM */ +#define ENUM_AFE_CMDDATACON_DMEM6K 0x000000C0 /* DATA_MEM_SEL: 2K_2~0 SRAM */ +#define ENUM_AFE_CMDDATACON_CMEM 0x00000008 /* CMDMEMMDE: MEMORY MODE */ +#define ENUM_AFE_CMDDATACON_CFIFO 0x00000010 /* CMDMEMMDE: FIFO MODE */ +#define ENUM_AFE_CMDDATACON_CSTM 0x00000018 /* CMDMEMMDE: STREAM MODE */ +#define ENUM_AFE_CMDDATACON_CMEM32B \ + 0x00000000 /* CMD_MEM_SEL: 32B_0 Local Memory */ +#define ENUM_AFE_CMDDATACON_CMEM2K 0x00000001 /* CMD_MEM_SEL: 2K_0 SRAM */ +#define ENUM_AFE_CMDDATACON_CMEM4K 0x00000002 /* CMD_MEM_SEL: 2K_0~1 SRAM */ +#define ENUM_AFE_CMDDATACON_CMEM6K 0x00000003 /* CMD_MEM_SEL: 2K_0~2 SRAM */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DATAFIFOTHRES Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DATAFIFOTHRES_HIGHTHRES 16 /* High Threshold */ +#define BITM_AFE_DATAFIFOTHRES_HIGHTHRES 0x07FF0000 /* High Threshold */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ3INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQ3INFO_LEN 16 /* SEQ3 Instruction Number */ +#define BITP_AFE_SEQ3INFO_ADDR 0 /* SEQ3 Start Address */ +#define BITM_AFE_SEQ3INFO_LEN 0x07FF0000 /* SEQ3 Instruction Number */ +#define BITM_AFE_SEQ3INFO_ADDR 0x000007FF /* SEQ3 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ1INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQ1INFO_LEN 16 /* SEQ1 Instruction Number */ +#define BITP_AFE_SEQ1INFO_ADDR 0 /* SEQ1 Start Address */ +#define BITM_AFE_SEQ1INFO_LEN 0x07FF0000 /* SEQ1 Instruction Number */ +#define BITM_AFE_SEQ1INFO_ADDR 0x000007FF /* SEQ1 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_REPEATADCCNV Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_REPEATADCCNV_NUM 4 /* Repeat Value */ +#define BITP_AFE_REPEATADCCNV_EN 0 /* Enable Repeat ADC Conversions */ +#define BITM_AFE_REPEATADCCNV_NUM 0x00000FF0 /* Repeat Value */ +#define BITM_AFE_REPEATADCCNV_EN 0x00000001 /* Enable Repeat ADC Conversions \ + */ +#define ENUM_AFE_REPEATADCCNV_DIS \ + 0x00000000 /* EN: Disable Repeat ADC Conversions */ +#define ENUM_AFE_REPEATADCCNV_EN \ + 0x00000001 /* EN: Enable Repeat ADC Conversions */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_FIFOCNTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_FIFOCNTSTA_DATAFIFOCNTSTA \ + 16 /* Current Number of Words in the Data FIFO */ +#define BITM_AFE_FIFOCNTSTA_DATAFIFOCNTSTA \ + 0x07FF0000 /* Current Number of Words in the Data FIFO */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CALDATLOCK Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_CALDATLOCK_KEY 0 /* Password for Calibration Data Registers \ + */ +#define BITM_AFE_CALDATLOCK_KEY \ + 0xFFFFFFFF /* Password for Calibration Data Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETHSTIA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETHSTIA_VALUE 0 /* HSTIA Offset Calibration */ +#define BITM_AFE_ADCOFFSETHSTIA_VALUE 0x00007FFF /* HSTIA Offset Calibration \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINTEMPSENS0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGAINTEMPSENS0_VALUE \ + 0 /* Gain Calibration Temp Sensor Channel */ +#define BITM_AFE_ADCGAINTEMPSENS0_VALUE \ + 0x00007FFF /* Gain Calibration Temp Sensor Channel */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETTEMPSENS0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETTEMPSENS0_VALUE \ + 0 /* Offset Calibration Temp Sensor */ +#define BITM_AFE_ADCOFFSETTEMPSENS0_VALUE \ + 0x00007FFF /* Offset Calibration Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGAINGN1_VALUE 0 /* Gain Calibration PGA Gain 1x */ +#define BITM_AFE_ADCGAINGN1_VALUE 0x00007FFF /* Gain Calibration PGA Gain 1x \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETGN1_VALUE 0 /* Offset Calibration Gain1 */ +#define BITM_AFE_ADCOFFSETGN1_VALUE 0x00007FFF /* Offset Calibration Gain1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACGAIN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DACGAIN_VALUE 0 /* HS DAC Gain Correction Factor */ +#define BITM_AFE_DACGAIN_VALUE 0x00000FFF /* HS DAC Gain Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSETATTEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DACOFFSETATTEN_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSETATTEN_VALUE \ + 0x00000FFF /* DAC Offset Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DACOFFSET_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSET_VALUE 0x00000FFF /* DAC Offset Correction Factor \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN1P5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGAINGN1P5_VALUE 0 /* Gain Calibration PGA Gain 1.5x */ +#define BITM_AFE_ADCGAINGN1P5_VALUE \ + 0x00007FFF /* Gain Calibration PGA Gain 1.5x */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGAINGN2_VALUE 0 /* Gain Calibration PGA Gain 2x */ +#define BITM_AFE_ADCGAINGN2_VALUE 0x00007FFF /* Gain Calibration PGA Gain 2x \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGAINGN4_VALUE 0 /* Gain Calibration PGA Gain 4x */ +#define BITM_AFE_ADCGAINGN4_VALUE 0x00007FFF /* Gain Calibration PGA Gain 4x \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCPGAOFFSETCANCEL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCPGAOFFSETCANCEL_OFFSETCANCEL 0 /* Offset Cancellation */ +#define BITM_AFE_ADCPGAOFFSETCANCEL_OFFSETCANCEL \ + 0x00007FFF /* Offset Cancellation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGNHSTIA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGNHSTIA_VALUE 0 /* Gain Error Calibration HS TIA Channel \ + */ +#define BITM_AFE_ADCGNHSTIA_VALUE \ + 0x00007FFF /* Gain Error Calibration HS TIA Channel */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETLPTIA0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETLPTIA0_VALUE 0 /* Offset Calibration for ULP-TIA0 \ + */ +#define BITM_AFE_ADCOFFSETLPTIA0_VALUE \ + 0x00007FFF /* Offset Calibration for ULP-TIA0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGNLPTIA0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGNLPTIA0_VALUE 0 /* Gain Error Calibration ULPTIA0 */ +#define BITM_AFE_ADCGNLPTIA0_VALUE \ + 0x00007FFF /* Gain Error Calibration ULPTIA0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCPGAGN4OFCAL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCPGAGN4OFCAL_ADCGAINAUX 0 /* DC Calibration Gain=4 */ +#define BITM_AFE_ADCPGAGN4OFCAL_ADCGAINAUX \ + 0x00007FFF /* DC Calibration Gain=4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN9 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGAINGN9_VALUE 0 /* Gain Calibration PGA Gain 9x */ +#define BITM_AFE_ADCGAINGN9_VALUE 0x00007FFF /* Gain Calibration PGA Gain 9x \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETEMPSENS1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETEMPSENS1_VALUE 0 /* Offset Calibration Temp Sensor \ + */ +#define BITM_AFE_ADCOFFSETEMPSENS1_VALUE \ + 0x00007FFF /* Offset Calibration Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINDIOTEMPSENS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGAINDIOTEMPSENS_VALUE \ + 0 /* Gain Calibration for Diode Temp Sensor */ +#define BITM_AFE_ADCGAINDIOTEMPSENS_VALUE \ + 0x00007FFF /* Gain Calibration for Diode Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSETATTENHP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DACOFFSETATTENHP_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSETATTENHP_VALUE \ + 0x00000FFF /* DAC Offset Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSETHP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DACOFFSETHP_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSETHP_VALUE \ + 0x00000FFF /* DAC Offset Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETLPTIA1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETLPTIA1_VALUE 0 /* Offset Calibration for ULP-TIA1 \ + */ +#define BITM_AFE_ADCOFFSETLPTIA1_VALUE \ + (_ADI_MSK_3(0x00007FFF, 0x00007FFFUL, \ + uint32_t)) /* Offset Calibration for ULP-TIA1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGNLPTIA1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGNLPTIA1_ULPTIA1GN 0 /* Gain Calibration ULP-TIA1 */ +#define BITM_AFE_ADCGNLPTIA1_ULPTIA1GN \ + 0x00007FFF /* Gain Calibration ULP-TIA1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETGN2_VALUE \ + 0 /* Offset Calibration Auxiliary Channel (PGA Gain =2) */ +#define BITM_AFE_ADCOFFSETGN2_VALUE \ + 0x00007FFF /* Offset Calibration Auxiliary Channel (PGA Gain =2) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN1P5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETGN1P5_VALUE 0 /* Offset Calibration Gain1.5 */ +#define BITM_AFE_ADCOFFSETGN1P5_VALUE \ + 0x00007FFF /* Offset Calibration Gain1.5 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN9 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETGN9_VALUE 0 /* Offset Calibration Gain9 */ +#define BITM_AFE_ADCOFFSETGN9_VALUE 0x00007FFF /* Offset Calibration Gain9 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETGN4_VALUE 0 /* Offset Calibration Gain4 */ +#define BITM_AFE_ADCOFFSETGN4_VALUE 0x00007FFF /* Offset Calibration Gain4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_PMBW Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_PMBW_SYSBW 2 /* Configure System Bandwidth */ +#define BITP_AFE_PMBW_SYSHP \ + 0 /* Set High Speed DAC and ADC in High Power Mode */ +#define BITM_AFE_PMBW_SYSBW 0x0000000C /* Configure System Bandwidth */ +#define BITM_AFE_PMBW_SYSHP \ + 0x00000001 /* Set High Speed DAC and ADC in High Power Mode */ +#define ENUM_AFE_PMBW_BWNA \ + 0x00000000 /* SYSBW: no action for system configuration */ +#define ENUM_AFE_PMBW_BW50 0x00000004 /* SYSBW: 50kHz -3dB bandwidth */ +#define ENUM_AFE_PMBW_BW100 0x00000008 /* SYSBW: 100kHz -3dB bandwidth */ +#define ENUM_AFE_PMBW_BW250 0x0000000C /* SYSBW: 250kHz -3dB bandwidth */ +#define ENUM_AFE_PMBW_LP 0x00000000 /* SYSHP: LP mode */ +#define ENUM_AFE_PMBW_HP 0x00000001 /* SYSHP: HP mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SWMUX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SWMUX_CMMUX 3 /* CM Resistor Select for Ain2, Ain3 */ +#define BITM_AFE_SWMUX_CMMUX 0x00000008 /* CM Resistor Select for Ain2, Ain3 \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_AFE_TEMPSEN_DIO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_AFE_TEMPSEN_DIO_TSDIO_PD 17 /* Power Down Control */ +#define BITP_AFE_AFE_TEMPSEN_DIO_TSDIO_EN 16 /* Test Signal Enable */ +#define BITP_AFE_AFE_TEMPSEN_DIO_TSDIO_CON 0 /* Bias Current Selection */ +#define BITM_AFE_AFE_TEMPSEN_DIO_TSDIO_PD 0x00020000 /* Power Down Control */ +#define BITM_AFE_AFE_TEMPSEN_DIO_TSDIO_EN 0x00010000 /* Test Signal Enable */ +#define BITM_AFE_AFE_TEMPSEN_DIO_TSDIO_CON \ + 0x0000FFFF /* Bias Current Selection */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCBUFCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCBUFCON_AMPDIS 4 /* Disable OpAmp. */ +#define BITP_AFE_ADCBUFCON_CHOPDIS 0 /* Disable Chop */ +#define BITM_AFE_ADCBUFCON_AMPDIS 0x000001F0 /* Disable OpAmp. */ +#define BITM_AFE_ADCBUFCON_CHOPDIS 0x0000000F /* Disable Chop */ + +/* ============================================================================================================================ + Interrupt Controller Register Map + ============================================================================================================================ + */ + +/* ============================================================================================================================ + INTC + ============================================================================================================================ + */ +#define REG_INTC_INTCPOL_RESET 0x00000000 /* Reset Value for INTCPOL */ +#define REG_INTC_INTCPOL 0x00003000 /* INTC Interrupt Polarity Register */ +#define REG_INTC_INTCCLR_RESET 0x00000000 /* Reset Value for INTCCLR */ +#define REG_INTC_INTCCLR 0x00003004 /* INTC Interrupt Clear Register */ +#define REG_INTC_INTCSEL0_RESET 0x00002000 /* Reset Value for INTCSEL0 */ +#define REG_INTC_INTCSEL0 0x00003008 /* INTC INT0 Select Register */ +#define REG_INTC_INTCSEL1_RESET 0x00000000 /* Reset Value for INTCSEL1 */ +#define REG_INTC_INTCSEL1 0x0000300C /* INTC INT1 Select Register */ +#define REG_INTC_INTCFLAG0_RESET \ + 0x00000000 /* Reset Value for INTCFLAG0 */ +#define REG_INTC_INTCFLAG0 0x00003010 /* INTC INT0 FLAG Register */ +#define REG_INTC_INTCFLAG1_RESET \ + 0x00000000 /* Reset Value for INTCFLAG1 */ +#define REG_INTC_INTCFLAG1 0x00003014 /* INTC INT1 FLAG Register */ + +/* ============================================================================================================================ + INTC Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCPOL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_INTC_INTCPOL_INTPOL 0 +#define BITM_INTC_INTCPOL_INTPOL 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCCLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_INTC_INTCCLR_INTCLR31 31 +#define BITP_INTC_INTCCLR_INTCLR30 30 +#define BITP_INTC_INTCCLR_INTCLR29 29 +#define BITP_INTC_INTCCLR_INTCLR28 28 +#define BITP_INTC_INTCCLR_INTCLR27 27 +#define BITP_INTC_INTCCLR_INTCLR26 26 +#define BITP_INTC_INTCCLR_INTCLR25 25 +#define BITP_INTC_INTCCLR_INTCLR24 24 +#define BITP_INTC_INTCCLR_INTCLR23 23 +#define BITP_INTC_INTCCLR_INTCLR22 22 +#define BITP_INTC_INTCCLR_INTCLR21 21 +#define BITP_INTC_INTCCLR_INTCLR20 20 +#define BITP_INTC_INTCCLR_INTCLR19 19 +#define BITP_INTC_INTCCLR_INTCLR18 18 +#define BITP_INTC_INTCCLR_INTCLR17 17 +#define BITP_INTC_INTCCLR_INTCLR16 16 +#define BITP_INTC_INTCCLR_INTCLR15 15 +#define BITP_INTC_INTCCLR_INTCLR14 14 +#define BITP_INTC_INTCCLR_INTCLR13 13 +#define BITP_INTC_INTCCLR_INTCLR12 12 /* Custom IRQ 3. Write 1 to clear. */ +#define BITP_INTC_INTCCLR_INTCLR11 11 /* Custom IRQ 2. Write 1 to clear. */ +#define BITP_INTC_INTCCLR_INTCLR10 10 /* Custom IRQ 1. Write 1 to clear. */ +#define BITP_INTC_INTCCLR_INTCLR9 9 /* Custom IRQ 0. Write 1 to clear */ +#define BITP_INTC_INTCCLR_INTCLR8 8 +#define BITP_INTC_INTCCLR_INTCLR7 7 +#define BITP_INTC_INTCCLR_INTCLR6 6 +#define BITP_INTC_INTCCLR_INTCLR5 5 +#define BITP_INTC_INTCCLR_INTCLR4 4 +#define BITP_INTC_INTCCLR_INTCLR3 3 +#define BITP_INTC_INTCCLR_INTCLR2 2 +#define BITP_INTC_INTCCLR_INTCLR1 1 +#define BITP_INTC_INTCCLR_INTCLR0 0 +#define BITM_INTC_INTCCLR_INTCLR31 0x80000000 +#define BITM_INTC_INTCCLR_INTCLR30 0x40000000 +#define BITM_INTC_INTCCLR_INTCLR29 0x20000000 +#define BITM_INTC_INTCCLR_INTCLR28 0x10000000 +#define BITM_INTC_INTCCLR_INTCLR27 0x08000000 +#define BITM_INTC_INTCCLR_INTCLR26 0x04000000 +#define BITM_INTC_INTCCLR_INTCLR25 0x02000000 +#define BITM_INTC_INTCCLR_INTCLR24 0x01000000 +#define BITM_INTC_INTCCLR_INTCLR23 0x00800000 +#define BITM_INTC_INTCCLR_INTCLR22 0x00400000 +#define BITM_INTC_INTCCLR_INTCLR21 0x00200000 +#define BITM_INTC_INTCCLR_INTCLR20 0x00100000 +#define BITM_INTC_INTCCLR_INTCLR19 0x00080000 +#define BITM_INTC_INTCCLR_INTCLR18 0x00040000 +#define BITM_INTC_INTCCLR_INTCLR17 0x00020000 +#define BITM_INTC_INTCCLR_INTCLR16 0x00010000 +#define BITM_INTC_INTCCLR_INTCLR15 0x00008000 +#define BITM_INTC_INTCCLR_INTCLR14 0x00004000 +#define BITM_INTC_INTCCLR_INTCLR13 0x00002000 +#define BITM_INTC_INTCCLR_INTCLR12 \ + 0x00001000 /* Custom IRQ 3. Write 1 to clear. */ +#define BITM_INTC_INTCCLR_INTCLR11 \ + 0x00000800 /* Custom IRQ 2. Write 1 to clear. */ +#define BITM_INTC_INTCCLR_INTCLR10 \ + 0x00000400 /* Custom IRQ 1. Write 1 to clear. */ +#define BITM_INTC_INTCCLR_INTCLR9 \ + 0x00000200 /* Custom IRQ 0. Write 1 to clear */ +#define BITM_INTC_INTCCLR_INTCLR8 0x00000100 +#define BITM_INTC_INTCCLR_INTCLR7 0x00000080 +#define BITM_INTC_INTCCLR_INTCLR6 0x00000040 +#define BITM_INTC_INTCCLR_INTCLR5 0x00000020 +#define BITM_INTC_INTCCLR_INTCLR4 0x00000010 +#define BITM_INTC_INTCCLR_INTCLR3 0x00000008 +#define BITM_INTC_INTCCLR_INTCLR2 0x00000004 +#define BITM_INTC_INTCCLR_INTCLR1 0x00000002 +#define BITM_INTC_INTCCLR_INTCLR0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCSEL0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_INTC_INTCSEL0_INTSEL31 31 +#define BITP_INTC_INTCSEL0_INTSEL30 30 +#define BITP_INTC_INTCSEL0_INTSEL29 29 +#define BITP_INTC_INTCSEL0_INTSEL28 28 +#define BITP_INTC_INTCSEL0_INTSEL27 27 +#define BITP_INTC_INTCSEL0_INTSEL26 26 +#define BITP_INTC_INTCSEL0_INTSEL25 25 +#define BITP_INTC_INTCSEL0_INTSEL24 24 +#define BITP_INTC_INTCSEL0_INTSEL23 23 +#define BITP_INTC_INTCSEL0_INTSEL22 22 +#define BITP_INTC_INTCSEL0_INTSEL21 21 +#define BITP_INTC_INTCSEL0_INTSEL20 20 +#define BITP_INTC_INTCSEL0_INTSEL19 19 +#define BITP_INTC_INTCSEL0_INTSEL18 18 +#define BITP_INTC_INTCSEL0_INTSEL17 17 +#define BITP_INTC_INTCSEL0_INTSEL16 16 +#define BITP_INTC_INTCSEL0_INTSEL15 15 +#define BITP_INTC_INTCSEL0_INTSEL14 14 +#define BITP_INTC_INTCSEL0_INTSEL13 13 +#define BITP_INTC_INTCSEL0_INTSEL12 12 /* Custom IRQ 3 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL11 11 /* Custom IRQ 2 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL10 10 /* Custom IRQ 1 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL9 9 /* Custom IRQ 0 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL8 8 +#define BITP_INTC_INTCSEL0_INTSEL7 7 +#define BITP_INTC_INTCSEL0_INTSEL6 6 +#define BITP_INTC_INTCSEL0_INTSEL5 5 +#define BITP_INTC_INTCSEL0_INTSEL4 4 +#define BITP_INTC_INTCSEL0_INTSEL3 3 +#define BITP_INTC_INTCSEL0_INTSEL2 2 +#define BITP_INTC_INTCSEL0_INTSEL1 1 +#define BITP_INTC_INTCSEL0_INTSEL0 0 +#define BITM_INTC_INTCSEL0_INTSEL31 0x80000000 +#define BITM_INTC_INTCSEL0_INTSEL30 0x40000000 +#define BITM_INTC_INTCSEL0_INTSEL29 0x20000000 +#define BITM_INTC_INTCSEL0_INTSEL28 0x10000000 +#define BITM_INTC_INTCSEL0_INTSEL27 0x08000000 +#define BITM_INTC_INTCSEL0_INTSEL26 0x04000000 +#define BITM_INTC_INTCSEL0_INTSEL25 0x02000000 +#define BITM_INTC_INTCSEL0_INTSEL24 0x01000000 +#define BITM_INTC_INTCSEL0_INTSEL23 0x00800000 +#define BITM_INTC_INTCSEL0_INTSEL22 0x00400000 +#define BITM_INTC_INTCSEL0_INTSEL21 0x00200000 +#define BITM_INTC_INTCSEL0_INTSEL20 0x00100000 +#define BITM_INTC_INTCSEL0_INTSEL19 0x00080000 +#define BITM_INTC_INTCSEL0_INTSEL18 0x00040000 +#define BITM_INTC_INTCSEL0_INTSEL17 0x00020000 +#define BITM_INTC_INTCSEL0_INTSEL16 0x00010000 +#define BITM_INTC_INTCSEL0_INTSEL15 0x00008000 +#define BITM_INTC_INTCSEL0_INTSEL14 0x00004000 +#define BITM_INTC_INTCSEL0_INTSEL13 0x00002000 +#define BITM_INTC_INTCSEL0_INTSEL12 0x00001000 /* Custom IRQ 3 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL11 0x00000800 /* Custom IRQ 2 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL10 0x00000400 /* Custom IRQ 1 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL9 0x00000200 /* Custom IRQ 0 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL8 0x00000100 +#define BITM_INTC_INTCSEL0_INTSEL7 0x00000080 +#define BITM_INTC_INTCSEL0_INTSEL6 0x00000040 +#define BITM_INTC_INTCSEL0_INTSEL5 0x00000020 +#define BITM_INTC_INTCSEL0_INTSEL4 0x00000010 +#define BITM_INTC_INTCSEL0_INTSEL3 0x00000008 +#define BITM_INTC_INTCSEL0_INTSEL2 0x00000004 +#define BITM_INTC_INTCSEL0_INTSEL1 0x00000002 +#define BITM_INTC_INTCSEL0_INTSEL0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCSEL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_INTC_INTCSEL1_INTSEL31 31 +#define BITP_INTC_INTCSEL1_INTSEL30 30 +#define BITP_INTC_INTCSEL1_INTSEL29 29 +#define BITP_INTC_INTCSEL1_INTSEL28 28 +#define BITP_INTC_INTCSEL1_INTSEL27 27 +#define BITP_INTC_INTCSEL1_INTSEL26 26 +#define BITP_INTC_INTCSEL1_INTSEL25 25 +#define BITP_INTC_INTCSEL1_INTSEL24 24 +#define BITP_INTC_INTCSEL1_INTSEL23 23 +#define BITP_INTC_INTCSEL1_INTSEL22 22 +#define BITP_INTC_INTCSEL1_INTSEL21 21 +#define BITP_INTC_INTCSEL1_INTSEL20 20 +#define BITP_INTC_INTCSEL1_INTSEL19 19 +#define BITP_INTC_INTCSEL1_INTSEL18 18 +#define BITP_INTC_INTCSEL1_INTSEL17 17 +#define BITP_INTC_INTCSEL1_INTSEL16 16 +#define BITP_INTC_INTCSEL1_INTSEL15 15 +#define BITP_INTC_INTCSEL1_INTSEL14 14 +#define BITP_INTC_INTCSEL1_INTSEL13 13 +#define BITP_INTC_INTCSEL1_INTSEL12 12 /* Custom IRQ 3 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL11 11 /* Custom IRQ 2 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL10 10 /* Custom IRQ 1 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL9 9 /* Custom IRQ 0 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL8 8 +#define BITP_INTC_INTCSEL1_INTSEL7 7 +#define BITP_INTC_INTCSEL1_INTSEL6 6 +#define BITP_INTC_INTCSEL1_INTSEL5 5 +#define BITP_INTC_INTCSEL1_INTSEL4 4 +#define BITP_INTC_INTCSEL1_INTSEL3 3 +#define BITP_INTC_INTCSEL1_INTSEL2 2 +#define BITP_INTC_INTCSEL1_INTSEL1 1 +#define BITP_INTC_INTCSEL1_INTSEL0 0 +#define BITM_INTC_INTCSEL1_INTSEL31 0x80000000 +#define BITM_INTC_INTCSEL1_INTSEL30 0x40000000 +#define BITM_INTC_INTCSEL1_INTSEL29 0x20000000 +#define BITM_INTC_INTCSEL1_INTSEL28 0x10000000 +#define BITM_INTC_INTCSEL1_INTSEL27 0x08000000 +#define BITM_INTC_INTCSEL1_INTSEL26 0x04000000 +#define BITM_INTC_INTCSEL1_INTSEL25 0x02000000 +#define BITM_INTC_INTCSEL1_INTSEL24 0x01000000 +#define BITM_INTC_INTCSEL1_INTSEL23 0x00800000 +#define BITM_INTC_INTCSEL1_INTSEL22 0x00400000 +#define BITM_INTC_INTCSEL1_INTSEL21 0x00200000 +#define BITM_INTC_INTCSEL1_INTSEL20 0x00100000 +#define BITM_INTC_INTCSEL1_INTSEL19 0x00080000 +#define BITM_INTC_INTCSEL1_INTSEL18 0x00040000 +#define BITM_INTC_INTCSEL1_INTSEL17 0x00020000 +#define BITM_INTC_INTCSEL1_INTSEL16 0x00010000 +#define BITM_INTC_INTCSEL1_INTSEL15 0x00008000 +#define BITM_INTC_INTCSEL1_INTSEL14 0x00004000 +#define BITM_INTC_INTCSEL1_INTSEL13 0x00002000 +#define BITM_INTC_INTCSEL1_INTSEL12 0x00001000 /* Custom IRQ 3 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL11 0x00000800 /* Custom IRQ 2 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL10 0x00000400 /* Custom IRQ 1 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL9 0x00000200 /* Custom IRQ 0 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL8 0x00000100 +#define BITM_INTC_INTCSEL1_INTSEL7 0x00000080 +#define BITM_INTC_INTCSEL1_INTSEL6 0x00000040 +#define BITM_INTC_INTCSEL1_INTSEL5 0x00000020 +#define BITM_INTC_INTCSEL1_INTSEL4 0x00000010 +#define BITM_INTC_INTCSEL1_INTSEL3 0x00000008 +#define BITM_INTC_INTCSEL1_INTSEL2 0x00000004 +#define BITM_INTC_INTCSEL1_INTSEL1 0x00000002 +#define BITM_INTC_INTCSEL1_INTSEL0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCFLAG0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_INTC_INTCFLAG0_FLAG31 31 +#define BITP_INTC_INTCFLAG0_FLAG30 30 +#define BITP_INTC_INTCFLAG0_FLAG29 29 +#define BITP_INTC_INTCFLAG0_FLAG28 28 +#define BITP_INTC_INTCFLAG0_FLAG27 27 +#define BITP_INTC_INTCFLAG0_FLAG26 26 +#define BITP_INTC_INTCFLAG0_FLAG25 25 +#define BITP_INTC_INTCFLAG0_FLAG24 24 +#define BITP_INTC_INTCFLAG0_FLAG23 23 +#define BITP_INTC_INTCFLAG0_FLAG22 22 +#define BITP_INTC_INTCFLAG0_FLAG21 21 +#define BITP_INTC_INTCFLAG0_FLAG20 20 +#define BITP_INTC_INTCFLAG0_FLAG19 19 +#define BITP_INTC_INTCFLAG0_FLAG18 18 +#define BITP_INTC_INTCFLAG0_FLAG17 17 +#define BITP_INTC_INTCFLAG0_FLAG16 16 +#define BITP_INTC_INTCFLAG0_FLAG15 15 +#define BITP_INTC_INTCFLAG0_FLAG14 14 +#define BITP_INTC_INTCFLAG0_FLAG13 13 +#define BITP_INTC_INTCFLAG0_FLAG12 12 /* Custom IRQ 3 Status */ +#define BITP_INTC_INTCFLAG0_FLAG11 11 /* Custom IRQ 2 Status */ +#define BITP_INTC_INTCFLAG0_FLAG10 10 /* Custom IRQ 1 Status */ +#define BITP_INTC_INTCFLAG0_FLAG9 9 /* Custom IRQ 0 Status */ +#define BITP_INTC_INTCFLAG0_FLAG8 8 /* Variance IRQ status. */ +#define BITP_INTC_INTCFLAG0_FLAG7 7 +#define BITP_INTC_INTCFLAG0_FLAG6 6 +#define BITP_INTC_INTCFLAG0_FLAG5 5 +#define BITP_INTC_INTCFLAG0_FLAG4 4 +#define BITP_INTC_INTCFLAG0_FLAG3 3 +#define BITP_INTC_INTCFLAG0_FLAG2 2 +#define BITP_INTC_INTCFLAG0_FLAG1 1 +#define BITP_INTC_INTCFLAG0_FLAG0 0 +#define BITM_INTC_INTCFLAG0_FLAG31 0x80000000 +#define BITM_INTC_INTCFLAG0_FLAG30 0x40000000 +#define BITM_INTC_INTCFLAG0_FLAG29 0x20000000 +#define BITM_INTC_INTCFLAG0_FLAG28 0x10000000 +#define BITM_INTC_INTCFLAG0_FLAG27 0x08000000 +#define BITM_INTC_INTCFLAG0_FLAG26 0x04000000 +#define BITM_INTC_INTCFLAG0_FLAG25 0x02000000 +#define BITM_INTC_INTCFLAG0_FLAG24 0x01000000 +#define BITM_INTC_INTCFLAG0_FLAG23 0x00800000 +#define BITM_INTC_INTCFLAG0_FLAG22 0x00400000 +#define BITM_INTC_INTCFLAG0_FLAG21 0x00200000 +#define BITM_INTC_INTCFLAG0_FLAG20 0x00100000 +#define BITM_INTC_INTCFLAG0_FLAG19 0x00080000 +#define BITM_INTC_INTCFLAG0_FLAG18 0x00040000 +#define BITM_INTC_INTCFLAG0_FLAG17 0x00020000 +#define BITM_INTC_INTCFLAG0_FLAG16 0x00010000 +#define BITM_INTC_INTCFLAG0_FLAG15 0x00008000 +#define BITM_INTC_INTCFLAG0_FLAG14 0x00004000 +#define BITM_INTC_INTCFLAG0_FLAG13 0x00002000 +#define BITM_INTC_INTCFLAG0_FLAG12 0x00001000 /* Custom IRQ 3 Status */ +#define BITM_INTC_INTCFLAG0_FLAG11 0x00000800 /* Custom IRQ 2 Status */ +#define BITM_INTC_INTCFLAG0_FLAG10 0x00000400 /* Custom IRQ 1 Status */ +#define BITM_INTC_INTCFLAG0_FLAG9 0x00000200 /* Custom IRQ 0 Status */ +#define BITM_INTC_INTCFLAG0_FLAG8 0x00000100 /* Variance IRQ status. */ +#define BITM_INTC_INTCFLAG0_FLAG7 0x00000080 +#define BITM_INTC_INTCFLAG0_FLAG6 0x00000040 +#define BITM_INTC_INTCFLAG0_FLAG5 0x00000020 +#define BITM_INTC_INTCFLAG0_FLAG4 0x00000010 +#define BITM_INTC_INTCFLAG0_FLAG3 0x00000008 +#define BITM_INTC_INTCFLAG0_FLAG2 0x00000004 +#define BITM_INTC_INTCFLAG0_FLAG1 0x00000002 +#define BITM_INTC_INTCFLAG0_FLAG0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCFLAG1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_INTC_INTCFLAG1_FLAG31 31 +#define BITP_INTC_INTCFLAG1_FLAG30 30 +#define BITP_INTC_INTCFLAG1_FLAG29 29 +#define BITP_INTC_INTCFLAG1_FLAG28 28 +#define BITP_INTC_INTCFLAG1_FLAG27 27 +#define BITP_INTC_INTCFLAG1_FLAG26 26 +#define BITP_INTC_INTCFLAG1_FLAG25 25 +#define BITP_INTC_INTCFLAG1_FLAG24 24 +#define BITP_INTC_INTCFLAG1_FLAG23 23 +#define BITP_INTC_INTCFLAG1_FLAG22 22 +#define BITP_INTC_INTCFLAG1_FLAG21 21 +#define BITP_INTC_INTCFLAG1_FLAG20 20 +#define BITP_INTC_INTCFLAG1_FLAG19 19 +#define BITP_INTC_INTCFLAG1_FLAG18 18 +#define BITP_INTC_INTCFLAG1_FLAG17 17 +#define BITP_INTC_INTCFLAG1_FLAG16 16 +#define BITP_INTC_INTCFLAG1_FLAG15 15 +#define BITP_INTC_INTCFLAG1_FLAG14 14 +#define BITP_INTC_INTCFLAG1_FLAG13 13 +#define BITP_INTC_INTCFLAG1_FLAG12 12 /* Custom IRQ 3 Status */ +#define BITP_INTC_INTCFLAG1_FLAG11 11 /* Custom IRQ 2 Status */ +#define BITP_INTC_INTCFLAG1_FLAG10 10 /* Custom IRQ 1 Status */ +#define BITP_INTC_INTCFLAG1_FLAG9 9 /* Custom IRQ 0 Status */ +#define BITP_INTC_INTCFLAG1_FLAG8 8 /* Variance IRQ status. */ +#define BITP_INTC_INTCFLAG1_FLAG7 7 +#define BITP_INTC_INTCFLAG1_FLAG6 6 +#define BITP_INTC_INTCFLAG1_FLAG5 5 +#define BITP_INTC_INTCFLAG1_FLAG4 4 +#define BITP_INTC_INTCFLAG1_FLAG3 3 +#define BITP_INTC_INTCFLAG1_FLAG2 2 +#define BITP_INTC_INTCFLAG1_FLAG1 1 +#define BITP_INTC_INTCFLAG1_FLAG0 0 +#define BITM_INTC_INTCFLAG1_FLAG31 0x80000000 +#define BITM_INTC_INTCFLAG1_FLAG30 0x40000000 +#define BITM_INTC_INTCFLAG1_FLAG29 0x20000000 +#define BITM_INTC_INTCFLAG1_FLAG28 0x10000000 +#define BITM_INTC_INTCFLAG1_FLAG27 0x08000000 +#define BITM_INTC_INTCFLAG1_FLAG26 0x04000000 +#define BITM_INTC_INTCFLAG1_FLAG25 0x02000000 +#define BITM_INTC_INTCFLAG1_FLAG24 0x01000000 +#define BITM_INTC_INTCFLAG1_FLAG23 0x00800000 +#define BITM_INTC_INTCFLAG1_FLAG22 0x00400000 +#define BITM_INTC_INTCFLAG1_FLAG21 0x00200000 +#define BITM_INTC_INTCFLAG1_FLAG20 0x00100000 +#define BITM_INTC_INTCFLAG1_FLAG19 0x00080000 +#define BITM_INTC_INTCFLAG1_FLAG18 0x00040000 +#define BITM_INTC_INTCFLAG1_FLAG17 0x00020000 +#define BITM_INTC_INTCFLAG1_FLAG16 0x00010000 +#define BITM_INTC_INTCFLAG1_FLAG15 0x00008000 +#define BITM_INTC_INTCFLAG1_FLAG14 0x00004000 +#define BITM_INTC_INTCFLAG1_FLAG13 0x00002000 +#define BITM_INTC_INTCFLAG1_FLAG12 0x00001000 /* Custom IRQ 3 Status */ +#define BITM_INTC_INTCFLAG1_FLAG11 0x00000800 /* Custom IRQ 2 Status */ +#define BITM_INTC_INTCFLAG1_FLAG10 0x00000400 /* Custom IRQ 1 Status */ +#define BITM_INTC_INTCFLAG1_FLAG9 0x00000200 /* Custom IRQ 0 Status */ +#define BITM_INTC_INTCFLAG1_FLAG8 0x00000100 /* Variance IRQ status. */ +#define BITM_INTC_INTCFLAG1_FLAG7 0x00000080 +#define BITM_INTC_INTCFLAG1_FLAG6 0x00000040 +#define BITM_INTC_INTCFLAG1_FLAG5 0x00000020 +#define BITM_INTC_INTCFLAG1_FLAG4 0x00000010 +#define BITM_INTC_INTCFLAG1_FLAG3 0x00000008 +#define BITM_INTC_INTCFLAG1_FLAG2 0x00000004 +#define BITM_INTC_INTCFLAG1_FLAG1 0x00000002 +#define BITM_INTC_INTCFLAG1_FLAG0 0x00000001 +/** + * @} AD5940RegistersBitfields + * @endcond + * */ + +/** + * @addtogroup SPI_Block + * @{ + * @defgroup SPI_Block_Const + * @{ + * + */ +#define SPICMD_SETADDR \ + 0x20 /**< set the register address that is going to operate. */ +#define SPICMD_READREG 0x6d /**< command to read register */ +#define SPICMD_WRITEREG 0x2d /**< command to write register */ +#define SPICMD_READFIFO 0x5f /**< command to read FIFO */ +/** + * @} SPI_Block_Const + * @} SPI_Block + */ + +/** + * @addtogroup AFE_Control + * @{ + * */ + +/** + * @defgroup AFE_Control_Const + * @{ + * */ + +/** + * @defgroup AFEINTC_Const + * @brief AD5940 has two interrupt controller INTC0 and INTC1. Both of them have + * ability to generate interrupt signal from GPIO. + * @{ + * */ +/* AFE Interrupt controller selection */ +#define AFEINTC_0 0 /**< Interrupt controller 0 */ +#define AFEINTC_1 1 /**< Interrupt controller 1 */ +/** @} */ + +/** + * @defgroup AFEINTC_SRC_Const + * @brief Interrupt source selection. These sources are defined as bit mask. + * They are available for register INTCCLR, INTCSEL0/1, INTCFLAG0/1 + * @{ + * */ +#define AFEINTSRC_ADCRDY 0x00000001 /**< Bit0, ADC Result Ready Status */ +#define AFEINTSRC_DFTRDY 0x00000002 /**< Bit1, DFT Result Ready Status */ +#define AFEINTSRC_SINC2RDY \ + 0x00000004 /**< Bit2, SINC2/Low Pass Filter Result Status */ +#define AFEINTSRC_TEMPRDY 0x00000008 /**< Bit3, Temp Sensor Result Ready */ +#define AFEINTSRC_ADCMINERR 0x00000010 /**< Bit4, ADC Minimum Value */ +#define AFEINTSRC_ADCMAXERR 0x00000020 /**< Bit5, ADC Maximum Value */ +#define AFEINTSRC_ADCDIFFERR 0x00000040 /**< Bit6, ADC Delta Ready */ +#define AFEINTSRC_MEANRDY 0x00000080 /**< Bit7, Mean Result Ready */ +#define AFEINTSRC_VARRDY 0x00000100 /**< Bit8, Variance Result Ready */ +#define AFEINTSRC_CUSTOMINT0 \ + 0x00000200 /**< Bit9, Custom interrupt source 0. It happens when \ + **sequencer** writes 1 to register AFEGENINTSTA.BIT0 */ +#define AFEINTSRC_CUSTOMINT1 \ + 0x00000400 /**< Bit10, Custom interrupt source 1. It happens when \ + **sequencer** writes 1 to register AFEGENINTSTA.BIT1*/ +#define AFEINTSRC_CUSTOMINT2 \ + 0x00000800 /**< Bit11, Custom interrupt source 2. It happens when \ + **sequencer** writes 1 to register AFEGENINTSTA.BIT2 */ +#define AFEINTSRC_CUSTOMINT3 \ + 0x00001000 /**< Bit12, Custom interrupt source 3. It happens when \ + **sequencer** writes 1 to register AFEGENINTSTA.BIT3 */ +#define AFEINTSRC_BOOTLDDONE 0x00002000 /**< Bit13, OTP Boot Loading Done */ +#define AFEINTSRC_WAKEUP 0x00004000 /**< Bit14, AFE Woken up*/ +#define AFEINTSRC_ENDSEQ 0x00008000 /**< Bit15, End of Sequence Interrupt. */ +#define AFEINTSRC_SEQTIMEOUT \ + 0x00010000 /**< Bit16, Sequencer Timeout Command Finished. */ +#define AFEINTSRC_SEQTIMEOUTERR \ + 0x00020000 /**< Bit17, Sequencer Timeout Command Error. */ +#define AFEINTSRC_CMDFIFOFULL \ + 0x00040000 /**< Bit18, Command FIFO Full Interrupt. */ +#define AFEINTSRC_CMDFIFOEMPTY 0x00080000 /**< Bit19, Command FIFO Empty */ +#define AFEINTSRC_CMDFIFOTHRESH \ + 0x00100000 /**< Bit20, Command FIFO Threshold Interrupt. */ +#define AFEINTSRC_CMDFIFOOF \ + 0x00200000 /**< Bit21, Command FIFO Overflow Interrupt. */ +#define AFEINTSRC_CMDFIFOUF \ + 0x00400000 /**< Bit22, Command FIFO Underflow Interrupt. */ +#define AFEINTSRC_DATAFIFOFULL \ + 0x00800000 /**< Bit23, Data FIFO Full Interrupt. */ +#define AFEINTSRC_DATAFIFOEMPTY 0x01000000 /**< Bit24, Data FIFO Empty */ +#define AFEINTSRC_DATAFIFOTHRESH \ + 0x02000000 /**< Bit25, Data FIFO Threshold Interrupt. */ +#define AFEINTSRC_DATAFIFOOF \ + 0x04000000 /**< Bit26, Data FIFO Overflow Interrupt. */ +#define AFEINTSRC_DATAFIFOUF \ + 0x08000000 /**< Bit27, Data FIFO Underflow Interrupt. */ +#define AFEINTSRC_WDTIRQ 0x10000000 /**< Bit28, WDT Timeout Interrupt. */ +#define AFEINTSRC_CRC_OUTLIER \ + 0x20000000 /**< Bit29, CRC interrupt for M355, Outlier Int for AD5940 */ +#define AFEINTSRC_GPT0INT_SLPWUT \ + 0x40000000 /**< Bit30, Gneral Pupose Timer0 IRQ for M355. Sleep or Wakeup \ + Tiemr timeout for AD5940*/ +#define AFEINTSRC_GPT1INT_TRYBRK \ + 0x80000000 /**< Bit31, Gneral Pupose Timer1 IRQ for M355. Tried to Break \ + IRQ for AD5940*/ +#define AFEINTSRC_ALLINT 0xffffffff /**< mask of all interrupt */ +/** @} */ + +/** + * @defgroup AFEPWR_Const + * @brief AFE power mode. + * @details It will set the whole analog system power mode include HSDAC, + * Excitation Buffer, HSTIA, ADC front-buffer etc. + * @{ + */ +#define AFEPWR_LP \ + 0 /**< Set AFE to Low Power mode. For signal <80kHz, use it. */ +#define AFEPWR_HP \ + 1 /**< Set AFE to High Power mode. For signal >80kHz, use it. */ +/** + * @} + */ + +/** + * @defgroup AFEBW_Const + * @brief AFE system bandwidth. + * @details It will set the whole analog bandwidth include HSDAC, Excitation + * Buffer, HSTIA, ADC front-buffer etc. + * @{ + */ +#define AFEBW_AUTOSET \ + 0 /**< Set the bandwidth automatically based on WGFCW frequency word. */ +#define AFEBW_50KHZ 1 /**< 50kHZ system bandwidth(DAC/ADC) */ +#define AFEBW_100KHZ 2 /**< 100kHZ system bandwidth(DAC/ADC) */ +#define AFEBW_250KHZ 3 /**< 250kHZ system bandwidth(DAC/ADC) */ +/** + * @} + */ + +/** + * @defgroup AFECTRL_Const + * @brief AFE Control signal set. Bit masks for register AFECON. + * @details This is all the available control signal for function @ref + * AD5940_AFECtrlS + * @warning Bit field in register AFECON has some opposite meaning as below + * definitions. We use all positive word here like HPREF instead of HPREFDIS. + * This set is only used in function @ref AD5940_AFECtrlS, the second parameter + * decides whether enable it or disable it. + * @{ + */ +#define AFECTRL_HPREFPWR (1L << 5) /**< High power reference on-off control */ +#define AFECTRL_HSDACPWR (1L << 6) /**< High speed DAC on-off control */ +#define AFECTRL_ADCPWR (1L << 7) /**< ADC power on-off control */ +#define AFECTRL_ADCCNV (1L << 8) /**< Start ADC convert enable */ +#define AFECTRL_EXTBUFPWR (1L << 9) /**< Excitation buffer power control */ +#define AFECTRL_INAMPPWR \ + (1L << 10) /**< Excitation loop input amplifier before P/N node power \ + control */ +#define AFECTRL_HSTIAPWR \ + (1L << 11) /**< High speed TIA amplifier power control */ +#define AFECTRL_TEMPSPWR (1L << 12) /**< Temperature sensor power */ +#define AFECTRL_TEMPCNV (1L << 13) /**< Start Temperature sensor convert */ +#define AFECTRL_WG (1L << 14) /**< Waveform generator on-off control */ +#define AFECTRL_DFT (1L << 15) /**< DFT engine on-off control */ +#define AFECTRL_SINC2NOTCH (1L << 16) /**< SIN2+Notch block on-off control */ +#define AFECTRL_ALDOLIMIT (1L << 19) /**< ALDO current limit on-off control */ +#define AFECTRL_DACREFPWR (1L << 20) /**< DAC reference buffer power control \ + */ +#define AFECTRL_DCBUFPWR \ + (1L << 21) /**< Excitation loop DC offset buffer sourced from LPDAC power \ + control */ +#define AFECTRL_ALL 0x39ffe0 /**< All control signals */ +/** + * @} + */ + +/** + * @defgroup LPMODECTRL_Const + * @brief LP Control signal(bit mask) for register LPMODECON + * @details This is all the available control signal for function @ref + * AD5940_LPModeCtrlS + * @warning Bit field in register LPMODECON has some opposite meaning as below + * definitions. We use all positive word here like HPREFPWR instead of HPREFDIS. + * This set is only used in function @ref AD5940_AFECtrlS, the second parameter + * decides whether enable or disable selected block(s). + * @{ + */ +#define LPMODECTRL_HFOSCEN \ + (1 << 0) /**< Enable internal HFOSC. Note: the register defination is set \ + this bit to 1 to disable it. */ +#define LPMODECTRL_HPREFPWR \ + (1 << 1) /**< High power reference power EN. Note: the register defination \ + is set this bit to 1 to disable it. */ +#define LPMODECTRL_ADCCNV (1 << 2) /**< Start ADC convert enable */ +#define LPMODECTRL_REPEATEN \ + (1 << 3) /**< Enable repeat convert function. This will enable ADC power \ + automatically */ +#define LPMODECTRL_GLBBIASZ \ + (1 << 4) /**< Enable Global ZTAT bias. Disable it to save more power */ +#define LPMODECTRL_GLBBIASP \ + (1 << 5) /**< Enable Global PTAT bias. Disable it to save more power */ +#define LPMODECTRL_BUFHP1P8V (1 << 6) /**< High power 1.8V reference buffer */ +#define LPMODECTRL_BUFHP1P1V (1 << 7) /**< High power 1.1V reference buffer */ +#define LPMODECTRL_ALDOPWR \ + (1 << 8) /**< Enable ALDO. Note: register defination is set this bit to 1 to \ + disable ALDO. */ +#define LPMODECTRL_ALL 0x1ff /**< All Control signal Or'ed together*/ +#define LPMODECTRL_NONE 0 /**< No blocks selected */ +/** @} */ + +/** + * @defgroup AFERESULT_Const + * @brief The available AFE results type. Used for function @ref + * AD5940_ReadAfeResult + * @{ + */ +#define AFERESULT_SINC3 0 /**< SINC3 result */ +#define AFERESULT_SINC2 1 /**< SINC2+NOTCH result */ +#define AFERESULT_TEMPSENSOR 2 /**< Temperature sensor result */ +#define AFERESULT_DFTREAL 3 /**< DFT Real result */ +#define AFERESULT_DFTIMAGE 4 /**< DFT Imaginary result */ +#define AFERESULT_STATSMEAN 5 /**< Statistic Mean result */ +#define AFERESULT_STATSVAR 6 /**< Statistic Variance result */ +/** @} */ + +/** + * @} AFE_Control_Const + * @} AFE_Control + * */ + +/** + * @addtogroup High_Speed_Loop + * @{ + * @defgroup High_Speed_Loop_Const + * @{ + */ + +/** + * @defgroup Switch_Matrix_Block_Const + * @{ + * @defgroup SWD_Const + * @brief Switch D set. This is bit mask for register DSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type + * The bit masks can be OR'ed together. For example + * - `SWD_AIN1|SWD_RCAL0` means close SWD_AIN1 and SWD_RCAL0 in same + * time, and open all other D switches. + * - `SWD_AIN2` means close SWD_AIN2 and open all other D switches. + * @{ + */ +#define SWD_OPEN (0 << 0) /**< Open all D switch. */ +#define SWD_RCAL0 (1 << 0) /**< pin RCAL0 */ +#define SWD_AIN1 (1 << 1) /**< Pin AIN1 */ +#define SWD_AIN2 (1 << 2) /**< Pin AIN2 */ +#define SWD_AIN3 (1 << 3) /**< Pin AIN3 */ +#define SWD_CE0 (1 << 4) /**< Pin CE0 */ +#define SWD_CE1 (1 << 5) /**< CE1 in ADuCM355 */ +#define SWD_AFE1 (1 << 5) /**< AFE1 in AD594x */ +#define SWD_SE0 (1 << 6) /**< Pin SE0 */ +#define SWD_SE1 (1 << 7) /**< SE1 in ADuCM355 */ +#define SWD_AFE3 (1 << 7) /**< AFE3 in AD594x */ +/** @} */ + +/** + * @defgroup SWP_Const + * @brief Switch P set. This is bit mask for register PSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type. + * The bit masks can be OR'ed together. For example + * - `SWP_RCAL0|SWP_AIN1` means close SWP_RCAL0 and SWP_AIN1 in same + * time, and open all other P switches. + * - `SWP_SE0` means close SWP_SE0 and open all other P switches. + * @{ + */ +#define SWP_OPEN 0 /**< Open all P switches */ +#define SWP_RCAL0 (1 << 0) /**< Pin RCAL0 */ +#define SWP_AIN1 (1 << 1) /**< Pin AIN1 */ +#define SWP_AIN2 (1 << 2) /**< Pin AIN2 */ +#define SWP_AIN3 (1 << 3) /**< Pin AIN3 */ +#define SWP_RE0 (1 << 4) /**< Pin RE0 */ +#define SWP_RE1 (1 << 5) /**< RE1 in ADuCM355 */ +#define SWP_AFE2 (1 << 5) /**< AFE2 in AD5940 */ +#define SWP_SE0 (1 << 6) /**< Pin SE0 */ +#define SWP_DE0 (1 << 7) /**< Pin DE0 */ +#define SWP_SE1 (1 << 8) /**< SE1 in ADuCM355 */ +#define SWP_AFE3 (1 << 8) /**< AFE3 in AD5940 */ +#define SWP_DE1 (1 << 9) /**< ADuCM355 Only. */ +#define SWP_CE0 (1 << 10) /**< Pin CE0 */ +#define SWP_CE1 (1 << 11) /**< CE1 in ADuCM355 */ +#define SWP_AFE1 (1 << 11) /**< AFE1 in AD5940 */ +#define SWP_PL (1 << 13) /**< Internal PL switch */ +#define SWP_PL2 (1 << 14) /**< Internal PL2 switch */ +/** @} */ + +/** + * @defgroup SWN_Const + * @brief Switch N set. This is bit mask for register NSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type. + * The bit masks can be OR'ed together. For example + * - `SWN_RCAL0|SWN_AIN1` means close SWN_RCAL0 and SWN_AIN1 in same + * time, and open all other N switches. + * - `SWN_SE0` means close SWN_SE0 and open all other N switches. + * @{ + */ +#define SWN_OPEN 0 /**< Open all N switches */ +#define SWN_RCAL1 (1 << 9) /**< Pin RCAL1 */ +#define SWN_AIN0 (1 << 0) /**< Pin AIN0 */ +#define SWN_AIN1 (1 << 1) /**< Pin AIN1 */ +#define SWN_AIN2 (1 << 2) /**< Pin AIN2 */ +#define SWN_AIN3 (1 << 3) /**< Pin AIN3 */ +#define SWN_SE0LOAD \ + (1 << 4) /**< SE0_LOAD is different from PIN SE0. It's the point after \ + 100Ohm load resistor */ +#define SWN_DE0LOAD (1 << 5) /**< DE0_Load is after Rload resistor */ +#define SWN_SE1LOAD (1 << 6) /**< SE1_LOAD in ADuCM355 */ +#define SWN_AFE3LOAD (1 << 6) /**< AFE3LOAD in ADuCM355 */ +#define SWN_DE1LOAD (1 << 7) /**< ADuCM355 Only*/ +#define SWN_SE0 (1 << 8) /**< SE0 here means the PIN SE0. */ +#define SWN_NL (1 << 10) /**< Internal NL switch */ +#define SWN_NL2 (1 << 11) /**< Internal NL2 switch */ +/** @} */ + +/** + * @defgroup SWT_Const + * @brief Switch T set. This is bit mask for register TSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type. + * The bit masks can be OR'ed together. For example + * - SWT_RCAL0|SWT_AIN1 means close SWT_RCAL0 and SWT_AIN1 in same + * time, and open all other T switches. + * - SWT_SE0LOAD means close SWT_SE0LOAD and open all other T switches. + * @{ + */ +#define SWT_OPEN 0 /**< Open all T switches */ +#define SWT_RCAL1 (1 << 11) /**< Pin RCAL1 */ +#define SWT_AIN0 (1 << 0) /**< Pin AIN0 */ +#define SWT_AIN1 (1 << 1) /**< Pin AIN1 */ +#define SWT_AIN2 (1 << 2) /**< Pin AIN2 */ +#define SWT_AIN3 (1 << 3) /**< Pin AIN3 */ +#define SWT_SE0LOAD \ + (1 << 4) /**< SE0_LOAD is different from PIN SE0. It's the point after \ + 100Ohm load resistor */ +#define SWT_DE0 (1 << 5) /**< DE0 pin. */ +#define SWT_SE1LOAD (1 << 6) /**< SE1_LOAD on ADuCM355*/ +#define SWT_AFE3LOAD (1 << 6) /**< AFE3_LOAD on ADuCM355*/ +#define SWT_DE1 (1 << 7) /**< ADuCM355 Only*/ +#define SWT_TRTIA (1 << 8) /**< T9 switch. Connect RTIA to T matrix */ +#define SWT_DE0LOAD (1 << 9) /**< DE0Load is the position after Rload Resisor \ + */ +#define SWT_DE1LOAD \ + (1 << 10) /**< DE1Load is the position after Rload Resisor */ +/** @} */ + +/** @} Switch_Matrix_Block_Const */ + +/** + * @defgroup Waveform_Generator_Block_Const + * @{ + */ +/** + * @defgroup WGTYPE_Const + * @brief Waveform generator signal type + * @{ + */ +#define WGTYPE_MMR 0 /**< Direct write to DAC using register */ +#define WGTYPE_SIN 2 /**< Sine wave generator */ +#define WGTYPE_TRAPZ 3 /**< Trapezoid generator */ +/** @} */ +/** @} Waveform_Generator_Block_Const */ + +/** + * @defgroup HSDAC_Block_Const + * @{ + */ +/* Excitation buffer gain selection */ +/** + * @defgroup EXCITBUFGAIN_Const + * @{ + */ +#define EXCITBUFGAIN_2 0 /**< Excitation buffer gain is x2 */ +#define EXCITBUFGAIN_0P25 1 /**< Excitation buffer gain is x1/4 */ +/** @} */ + +/** + * @defgroup HSDACGAIN_Const + * @{ + */ +/* HSDAC PGA Gain selection(DACCON.BIT0) */ +#define HSDACGAIN_1 0 /**< Gain is x1 */ +#define HSDACGAIN_0P2 1 /**< Gain is x1/5 */ +/** @} */ +/** @} */ // HSDAC_Block_Const + +/** + * @defgroup HSTIA_Block_Const + * @{ + * */ +/* HSTIA Amplifier Positive Input selection */ + +/** + * @defgroup HSTIABIAS_Const + * @warning When select Vzero0 as bias, close LPDAC switch + * @{ + */ +#define HSTIABIAS_1P1 \ + 0 /**< Internal 1.1V common voltage from internal 1.1V reference buffer */ +#define HSTIABIAS_VZERO0 1 /**< From LPDAC0 Vzero0 output */ +#define HSTIABIAS_VZERO1 \ + 2 /**< From LPDAC1 Vzero1 output. Only available on ADuCM355. */ +/** @} */ + +/* HSTIA Internal RTIA selection */ + +/** + * @defgroup HSTIARTIA_Const + * @{ + */ +#define HSTIARTIA_200 0 /**< HSTIA Internal RTIA resistor 200 */ +#define HSTIARTIA_1K 1 /**< HSTIA Internal RTIA resistor 1K */ +#define HSTIARTIA_5K 2 /**< HSTIA Internal RTIA resistor 5K */ +#define HSTIARTIA_10K 3 /**< HSTIA Internal RTIA resistor 10K */ +#define HSTIARTIA_20K 4 /**< HSTIA Internal RTIA resistor 20K */ +#define HSTIARTIA_40K 5 /**< HSTIA Internal RTIA resistor 40K */ +#define HSTIARTIA_80K 6 /**< HSTIA Internal RTIA resistor 80K */ +#define HSTIARTIA_160K 7 /**< HSTIA Internal RTIA resistor 160K */ +#define HSTIARTIA_OPEN 8 /**< Open internal resistor */ +/** @} */ + +/** + * @defgroup HSTIADERTIA_Const + * @{ + */ +#define HSTIADERTIA_50 0 /**< 50Ohm Settings depends on RLOAD resistor. */ +#define HSTIADERTIA_100 1 /**< 100Ohm Settings depends on RLOAD resistor.*/ +#define HSTIADERTIA_200 2 /**< 200Ohm Settings depends on RLOAD resistor.*/ +#define HSTIADERTIA_1K 3 /**< set bit[7:3] to 0x0b(11) */ +#define HSTIADERTIA_5K 4 /**< set bit[7:3] to 0x0c(12) */ +#define HSTIADERTIA_10K 5 /**< set bit[7:3] to 0x0d(13) */ +#define HSTIADERTIA_20K 6 /**< set bit[7:3] to 0x0e(14) */ +#define HSTIADERTIA_40K 7 /**< set bit[7:3] to 0x0f(15) */ +#define HSTIADERTIA_80K 8 /**< set bit[7:3] to 0x10(16) */ +#define HSTIADERTIA_160K 9 /**< set bit[7:3] to 0x11(17) */ +#define HSTIADERTIA_TODE \ + 10 /**< short HSTIA output to DE0 pin. set bit[7:3] to 0x12(18) */ +#define HSTIADERTIA_OPEN \ + 11 /**< Default state is set to OPEN RTIA by setting bit[7:3] to 0x1f */ +/** @} */ + +/* HSTIA DE0 Terminal internal RLOAD selection */ +/** + * @defgroup HSTIADERLOAD_Const + * @{ + */ +#define HSTIADERLOAD_0R 0 /**< set bit[2:0] to 0x00 */ +#define HSTIADERLOAD_10R 1 /**< set bit[2:0] to 0x01 */ +#define HSTIADERLOAD_30R 2 /**< set bit[2:0] to 0x02 */ +#define HSTIADERLOAD_50R 3 /**< set bit[2:0] to 0x03 */ +#define HSTIADERLOAD_100R 4 /**< set bit[2:0] to 0x04 */ +#define HSTIADERLOAD_OPEN \ + 5 /**< RLOAD open means open switch between HSTIA negative input and Rload \ + resistor().Default state is OPEN RLOAD by setting \ + HSTIARES03CON[2:0] to 0x5, 0x6 or 0x7 */ +/** @} */ + +/** + * @defgroup HSTIAPWRMOE_Const + * @{ + */ +#define HSTIAPWRMOE_LP 0 /**< HSTIA in LP mode */ +#define HSTIAPWRMOE_HP 1 /**< HSTIA in HP mode */ +/** @} */ + +/** @} HSTIA_Block_Const */ +/** + * @} High_Speed_Loop_Const + * @} High_Speed_Loop + */ + +/** + * @addtogroup Low_Power_Loop + * Low power includes low power DAC and two low power amplifiers(PA and TIA) + * @{ + * @defgroup Low_Power_Loop_Const + * The constant used in Low power loop. + * @{ + */ + +/** + * @defgroup LPDAC_Block_Const + * @{ + * */ +/** + * @defgroup LPDAC_Const + * Select which LPDAC is accessing. + * @note This parameter must be configured correctly + * @{ + */ +#define LPDAC0 0 /**< LPDAC0 */ +#define LPDAC1 1 /**< LPDAC1, ADuCM355 Only */ +/** @} */ +/** + * @defgroup LPDACSRC_Const + * LPDAC data source selection. Either from MMR or from waveform generator. + * @{ + */ +#define LPDACSRC_MMR 0 /**< Get data from register REG_AFE_LPDACDAT0DATA0 */ +#define LPDACSRC_WG 1 /**< Get data from waveform generator */ +/** @} */ + +/** + * @defgroup LPDACSW_Const + * @brief LPDAC switch settings + * @{ + */ +#define LPDACSW_VBIAS2LPPA \ + 0x10 /**< switch between LPDAC Vbias output and LPPA(low power PA(Potential \ + Amplifier)) */ +#define LPDACSW_VBIAS2PIN \ + 0x08 /**< Switch between LPDAC Vbias output and Vbias pin */ +#define LPDACSW_VZERO2LPTIA \ + 0x04 /**< Switch between LPDAC Vzero output and LPTIA positive input */ +#define LPDACSW_VZERO2PIN \ + 0x02 /**< Switch between LPDAC Vzero output and Vzero pin */ +#define LPDACSW_VZERO2HSTIA \ + 0x01 /**< Switch between LPDAC Vzero output and HSTIA positive input MUX */ +/** @} */ + +/** + * @defgroup LPDACVZERO_Const + * @brief Vzero MUX selection + * @{ + */ +#define LPDACVZERO_6BIT 0 /**< Connect Vzero to 6bit LPDAC output */ +#define LPDACVZERO_12BIT 1 /**< Connect Vzero to 12bit LPDAC output */ +/** @} */ + +/** + * @defgroup LPDACVBIAS_Const + * @brief Vbias MUX selection + * @{ + */ +#define LPDACVBIAS_6BIT 1 /**< Connect Vbias to 6bit LPDAC output */ +#define LPDACVBIAS_12BIT 0 /**< Connect Vbias to 12bit LPDAC output */ +/** @} */ + +/** + * @defgroup LPDACREF_Const + * @brief LPDAC reference selection + * @{ + */ +#define LPDACREF_2P5 0 /**< Internal 2.5V reference */ +#define LPDACREF_AVDD 1 /**< Use AVDD as reference */ +/** @} */ + +/** @} */ // LPDAC_Block_Const + +/** + * @defgroup LPAMP_Block_Const + * @brief Low power amplifies include potential-state amplifier(PA in short) and + * TIA. + * @{ + * */ + +/** + * @defgroup LPTIA_Const + * @brief LPTIA selecion + * @{ + * */ +#define LPTIA0 0 /**< LPTIA0 */ +#define LPTIA1 1 /**< LPTIA1, ADuCM355 Only */ +/** @} */ + +/** + * @defgroup LPTIARF_Const + * @brief LPTIA LPF Resistor selection + * @{ + * */ +#define LPTIARF_OPEN 0 /**< Disconnect Rf resistor */ +#define LPTIARF_SHORT 1 /**< Bypass Rf resistor */ +#define LPTIARF_20K 2 /**< 20kOhm Rf */ +#define LPTIARF_100K 3 /**< Rf resistor 100kOhm */ +#define LPTIARF_200K 4 /**< Rf resistor 200kOhm */ +#define LPTIARF_400K 5 /**< Rf resistor 400kOhm */ +#define LPTIARF_600K 6 /**< Rf resistor 600kOhm */ +#define LPTIARF_1M 7 /**< Rf resistor 1MOhm */ +/** @} */ + +/** + * @defgroup LPTIARLOAD_Const + * @brief LPTIA Rload Selection + * @{ + */ +#define LPTIARLOAD_SHORT 0 /**< 0Ohm Rload */ +#define LPTIARLOAD_10R 1 /**< 10Ohm Rload */ +#define LPTIARLOAD_30R 2 /**< Rload resistor 30Ohm */ +#define LPTIARLOAD_50R 3 /**< Rload resistor 50Ohm */ +#define LPTIARLOAD_100R 4 /**< Rload resistor 100Ohm */ +#define LPTIARLOAD_1K6 5 /**< Only available when RTIA setting >= 2KOHM */ +#define LPTIARLOAD_3K1 6 /**< Only available when RTIA setting >= 4KOHM */ +#define LPTIARLOAD_3K6 7 /**< Only available when RTIA setting >= 4KOHM */ +/** @} */ + +/** + * @defgroup LPTIARTIA_Const + * @brief LPTIA RTIA Selection + * @note The real RTIA resistor value dependents on Rload settings. + * @{ + */ +#define LPTIARTIA_OPEN 0 /**< Disconnect LPTIA Internal RTIA */ +#define LPTIARTIA_200R 1 /**< 200Ohm Internal RTIA */ +#define LPTIARTIA_1K 2 /**< 1KOHM */ +#define LPTIARTIA_2K 3 /**< 2KOHM */ +#define LPTIARTIA_3K 4 /**< 3KOHM */ +#define LPTIARTIA_4K 5 /**< 4KOHM */ +#define LPTIARTIA_6K 6 /**< 6KOHM */ +#define LPTIARTIA_8K 7 /**< 8KOHM */ +#define LPTIARTIA_10K 8 /**< 10KOHM */ +#define LPTIARTIA_12K 9 /**< 12KOHM */ +#define LPTIARTIA_16K 10 /**< 16KOHM */ +#define LPTIARTIA_20K 11 /**< 20KOHM */ +#define LPTIARTIA_24K 12 /**< 24KOHM */ +#define LPTIARTIA_30K 13 /**< 30KOHM */ +#define LPTIARTIA_32K 14 /**< 32KOHM */ +#define LPTIARTIA_40K 15 /**< 40KOHM */ +#define LPTIARTIA_48K 16 /**< 48KOHM */ +#define LPTIARTIA_64K 17 /**< 64KOHM */ +#define LPTIARTIA_85K 18 /**< 85KOHM */ +#define LPTIARTIA_96K 19 /**< 96KOHM */ +#define LPTIARTIA_100K 20 /**< 100KOHM */ +#define LPTIARTIA_120K 21 /**< 120KOHM */ +#define LPTIARTIA_128K 22 /**< 128KOHM */ +#define LPTIARTIA_160K 23 /**< 160KOHM */ +#define LPTIARTIA_196K 24 /**< 196KOHM */ +#define LPTIARTIA_256K 25 /**< 256KOHM */ +#define LPTIARTIA_512K 26 /**< 512KOHM */ +/** @} */ + +/** + * @defgroup LPAMP_Const + * LPAMP selecion. On AD594x, only LPAMP0 is available. + * @note This parameter must be configured correctly. + * @{ + * */ +#define LPAMP0 \ + 0 /**< LPAMP0, AMP include both LPTIA and Potentio-stat amplifiers */ +#define LPAMP1 1 /**< LPAMP1, ADuCM355 Only */ +/** @} */ + +/** + * @defgroup LPAMPPWR_Const + * @brief Low power amplifier(PA and TIA) power mode selection. + * @{ + */ +#define LPAMPPWR_NORM 0 /**< Normal Power mode */ +#define LPAMPPWR_BOOST1 1 /**< Boost power to level 1 */ +#define LPAMPPWR_BOOST2 2 /**< Boost power to level 2 */ +#define LPAMPPWR_BOOST3 3 /**< Boost power to level 3 */ +#define LPAMPPWR_HALF 4 /**< Put PA and TIA in half power mode */ +/** @} */ + +#define LPTIASW(n) \ + (1L << n) /**< LPTIA switch control. Use this macro to set LpTiaSW field of \ + @ref LPAmpCfg_Type */ + +/** + * @} LPAMP_Block_Const + * @} Low_Power_Loop_Const + * @} Low_Power_Loop + * + * */ + +/** + * @addtogroup DSP_Block + * DSP block include signal chain from raw ADC data to various filters, DFT + * engine and Statistic Functions etc. + * @{ + * @defgroup DSP_Block_Const + * @{ + * @defgroup ADC_Block_Const + * @{ + */ + +/** + * @defgroup ADCPGA_Const + * @brief ADC PGA Selection + * @note Only gain 1.5 is factory calibrated. + * @{ + */ +#define ADCPGA_1 0 /**< ADC PGA Gain of 1 */ +#define ADCPGA_1P5 1 /**< ADC PGA Gain of 1.5 */ +#define ADCPGA_2 2 /**< ADC PGA Gain of 2 */ +#define ADCPGA_4 3 /**< ADC PGA Gain of 4 */ +#define ADCPGA_9 4 /**< ADC PGA Gain of 9 */ +#define IS_ADCPGA(pga) (((pga) == ADCPGA_1) ||\ + (pga) == ADCPGA_1P5) ||\ + (pga) == ADCPGA_2) ||\ + (pga) == ADCPGA_4) ||\ + (pga) == ADCPGA_9)) +/** + * @} + * */ + +/** + * @defgroup ADCMUXP_Const + * @brief ADC Channel P Configuration + * @{ + */ +#define ADCMUXP_FLOAT 0x0 /**< float */ +#define ADCMUXP_HSTIA_P 0x1 /**< output of HSTIA */ +#define ADCMUXP_AIN0 0x4 /**< pin AIN0 */ +#define ADCMUXP_AIN1 0x5 /**< pin AIN1 */ +#define ADCMUXP_AIN2 0x6 /**< pin AIN2 */ +#define ADCMUXP_AIN3 0x7 /**< pin AIN3 */ +#define ADCMUXP_AVDD_2 0x8 /**< AVDD/2 */ +#define ADCMUXP_DVDD_2 0x9 /**< DVDD/2 */ +#define ADCMUXP_AVDDREG \ + 0xA /**< AVDD internal regulator output. It's around 1.8V */ +#define ADCMUXP_TEMPP 0xB /**< Internal temperature output postive terminal */ +#define ADCMUXP_VSET1P1 0xC /**< Internal 1.1V bias voltage */ +#define ADCMUXP_VDE0 0xD /**< Voltage of DE0 pin */ +#define ADCMUXP_VSE0 0xE /**< Voltage of SE0 pin */ +#define ADCMUXP_VSE1 0xF /**< Voltage of SE1 pin on ADuCM355 */ +#define ADCMUXP_VAFE3 0xF /**< Voltage of AFE3 pin on AD5940. */ +#define ADCMUXP_VREF2P5 \ + 0x10 /**< 1.25V. The internal 2.5V reference buffer output divided by 2. */ +#define ADCMUXP_VREF1P8DAC \ + 0x12 /**< HSDAC 1.8V internal reference. It's only available when both \ + AFECON.BIT20 and AFECON.BIT6 are set. */ +#define ADCMUXP_TEMPN 0x13 /**< Internal temperature output negative terminal \ + */ +#define ADCMUXP_AIN4 0x14 /**< Voltage of AIN4/LPF0 pin */ +#define ADCMUXP_AIN5 0x15 /**< Voltage of AIN5 pin */ +#define ADCMUXP_AIN6 0x16 /**< Voltage of AIN6 pin, not available on AD5941 */ +#define ADCMUXP_VZERO0 0x17 /**< Voltage of Vzero0 pin */ +#define ADCMUXP_VBIAS0 0x18 /**< Voltage of Vbias0 pin */ +#define ADCMUXP_VCE0 0x19 /**< Pin CE0 */ +#define ADCMUXP_VRE0 0x1A /**< Pin RE0 */ +#define ADCMUXP_VZERO1 0x1B /**< Voltage of Vzero1 pin on ADuCM355 */ +#define ADCMUXP_VAFE4 0x1B /**< Voltage of AFE4 pin on AD5940. */ +#define ADCMUXP_VBIAS1 0x1C /**< Voltage of Vbias1 pin */ +#define ADCMUXP_VCE1 0x1D /**< Voltage of CE1 pin on ADuCM355. */ +#define ADCMUXP_VAFE1 0x1D /**< Voltage of AFE1 pin on AD5940. */ +#define ADCMUXP_VRE1 0x1E /**< Voltage of RE1 pin on ADuCM355. */ +#define ADCMUXP_VAFE2 0x1E /**< Voltage of AFE2 pin on AD5940. */ +#define ADCMUXP_VCE0_2 0x1F /**< VCE0 divide by 2 */ +#define ADCMUXP_VCE1_2 0x20 /**< VCE1 divide by 2 */ +#define ADCMUXP_LPTIA0_P 0x21 /**< Output of LPTIA0 */ +#define ADCMUXP_LPTIA1_P 0x22 /**< Output of LPTIA1 */ +#define ADCMUXP_AGND 0x23 /**< Internal AGND node */ +#define ADCMUXP_P_NODE \ + 0x24 /**< Buffered voltage of excitation buffer P node. */ +#define ADCMUXP_IOVDD_2 0x27 /**< IOVDD/2 */ +/**@}*/ + +/** + * @defgroup ADCMUXN_Const + * @brief ADC Channel N Configuration + * @{ + */ +#define ADCMUXN_FLOAT 0x0 /**< float */ +#define ADCMUXN_HSTIA_N 0x1 /**< HSTIA negative input node. */ +#define ADCMUXN_LPTIA0_N 0x2 /**< LPTIA0 negative input node. */ +#define ADCMUXN_LPTIA1_N 0x3 /**< LPTIA1 negative input node. */ +#define ADCMUXN_AIN0 0x4 /**< Pin AIN0 */ +#define ADCMUXN_AIN1 0x5 /**< Pin AIN1 */ +#define ADCMUXN_AIN2 0x6 /**< Pin AIN2 */ +#define ADCMUXN_AIN3 0x7 /**< Pin AIN3 */ +#define ADCMUXN_VSET1P1 0x8 /**< Internal 1.11V reference */ +#define ADCMUXN_VREF1P1 \ + 0x8 /**< Internal 1.11V reference, same as ADCMUXN_VSET1P1 */ +#define ADCMUXN_TEMPN 0xB /**< Temperature sensor output. */ +#define ADCMUXN_AIN4 0xC /**< AIN4 */ +#define ADCMUXN_AIN5 0xD /**< AIN5 */ +#define ADCMUXN_AIN6 0xE /**< AIN6 */ +#define ADCMUXN_VZERO0 0x10 /**< pin Vzero0 */ +#define ADCMUXN_VBIAS0 0x11 /**< pin Vbias0 */ +#define ADCMUXN_VZERO1 0x12 /**< pin Vzero1 */ +#define ADCMUXN_AFE4 0x12 /**< Pin AFE4 on AD5940. */ +#define ADCMUXN_VBIAS1 0x13 /**< pin Vbias1 */ +#define ADCMUXN_N_NODE \ + 0x14 /**< Buffered voltage of excitation buffer N node. */ +/** @} */ + +/** + * @defgroup ADCRATE_Const + * @brief ADC Current Sample Rate. If ADC clock is 32MHz, set it to + * ADCRATE_1P6MHZ. Otherwise, set it to ADCRATE_800KHZ. + * @{ + */ +#define ADCRATE_800KHZ 1 /**< ADC input clock is 16MHz, sample rate is 800kHz \ + */ +#define ADCRATE_1P6MHZ 0 /**< ADC input clock is 32MHz, sample rate is 1.6MHz \ + */ +#define IS_ADCRATE(rate) (((rate) == ADCRATE_800KHZ) ||\ + (rate) == ADCRATE_1P6MHZ)) +/** @} */ + +/** + * @defgroup ADCSINC3OSR_Const + * @brief ADC SINC3 Filter OSR. 2, 4 is recommended value. 5 is not recommended. + * @{ + */ +#define ADCSINC3OSR_2 2 /**< ADC SINC3 OSR 2 */ +#define ADCSINC3OSR_4 1 /**< ADC SINC3 OSR 4 */ +#define ADCSINC3OSR_5 0 /**< ADC SINC3 OSR 5 */ +#define IS_ADCSINC3OSR(osr) (((osr) == ADCSINC3OSR_2) ||\ + (osr) == ADCSINC3OSR_4) ||\ + (osr) == ADCSINC3OSR_5)) /**< checker of ADCSINC3OSR */ +/** @} */ + +/** + * @defgroup ADCSINC2OSR_Const + * @brief ADC SINC2 Filter OSR. + * @{ + */ +#define ADCSINC2OSR_22 0 /**< ADC SINC2 OSR 22 */ +#define ADCSINC2OSR_44 1 /**< ADC SINC2 OSR 44 */ +#define ADCSINC2OSR_89 2 /**< ADC SINC2 OSR 89 */ +#define ADCSINC2OSR_178 3 /**< ADC SINC2 OSR 178 */ +#define ADCSINC2OSR_267 4 /**< ADC SINC2 OSR 267 */ +#define ADCSINC2OSR_533 5 /**< ADC SINC2 OSR 533 */ +#define ADCSINC2OSR_640 6 /**< ADC SINC2 OSR 640 */ +#define ADCSINC2OSR_667 7 /**< ADC SINC2 OSR 667 */ +#define ADCSINC2OSR_800 8 /**< ADC SINC2 OSR 800 */ +#define ADCSINC2OSR_889 9 /**< ADC SINC2 OSR 889 */ +#define ADCSINC2OSR_1067 10 /**< ADC SINC2 OSR 1067 */ +#define ADCSINC2OSR_1333 11 /**< ADC SINC2 OSR 1333 */ +#define IS_ADCSINC2OSR(osr) (((osr) == ADCSINC2OSR_22) ||\ + (osr) == ADCSINC2OSR_44) ||\ + (osr) == ADCSINC2OSR_89) ||\ + (osr) == ADCSINC2OSR_178) ||\ + (osr) == ADCSINC2OSR_267) ||\ + (osr) == ADCSINC2OSR_533) ||\ + (osr) == ADCSINC2OSR_640) ||\ + (osr) == ADCSINC2OSR_667) ||\ + (osr) == ADCSINC2OSR_800) ||\ + (osr) == ADCSINC2OSR_889) ||\ + (osr) == ADCSINC2OSR_1067) ||\ + (osr) == ADCSINC2OSR_1333)) /**< checker of ADCSINC2OSR */ +/** @} */ + +/** + * @defgroup ADCAVGNUM_Const + * @brief ADC Average filter for DFT. The average block locates after SINC3 + * filter. The output of average filter is directly feed into DFT block. + * @warning Once average filter is enabled, DFT source is automatically changed + * to averaged data. + * @{ + */ +#define ADCAVGNUM_2 0 /**< Take 2 input to do average. */ +#define ADCAVGNUM_4 1 /**< Take 4 input to do average. */ +#define ADCAVGNUM_8 2 /**< Take 8 input to do average. */ +#define ADCAVGNUM_16 3 /**< Take 16 input to do average. */ +#define IS_ADCAVGNUM(num) (((num) == ADCAVGNUM_2) ||\ + (num) == ADCAVGNUM_4) ||\ + (num) == ADCAVGNUM_8) ||\ + (num) == ADCAVGNUM_16)) /**< checker of ADCAVGNUM macro */ +/** @} */ + +/** @} ADC_Block_Const */ + +/** + * @defgroup DFT_Block_Const + * @{ + * */ + +/** + * @defgroup DFTSRC_Const + * @brief DFT source selection. When average function is enabled, DFT source + * automatically switch to average output. + * @{ + * */ +#define DFTSRC_SINC2NOTCH \ + 0 /**< SINC2+Notch filter block output. Bypass Notch to use SINC2 data */ +#define DFTSRC_SINC3 1 /**< SINC3 filter */ +#define DFTSRC_ADCRAW 2 /**< Raw ADC data */ +#define DFTSRC_AVG 3 /**< Average output of SINC3. */ +/** @} */ + +/** + * @defgroup DFTNUM_Const + * @brief DFT number selection. + * @{ + * */ +#define DFTNUM_4 0 /**< 4 Point */ +#define DFTNUM_8 1 /**< 8 Point */ +#define DFTNUM_16 2 /**< 16 Point */ +#define DFTNUM_32 3 /**< 32 Point */ +#define DFTNUM_64 4 /**< 64 Point */ +#define DFTNUM_128 5 /**< 128 Point */ +#define DFTNUM_256 6 /**< 256 Point */ +#define DFTNUM_512 7 /**< 512 Point */ +#define DFTNUM_1024 8 /**< 1024 Point */ +#define DFTNUM_2048 9 /**< 2048 Point */ +#define DFTNUM_4096 10 /**< 4096 Point */ +#define DFTNUM_8192 11 /**< 8192 Point */ +#define DFTNUM_16384 12 /**< 16384 Point */ +/** @} */ + +/** + * @} DFT_Block_Const + */ + +/** + * @defgroup Statistic_Block_Const + * @{ + */ +/** + * @defgroup STATSAMPLE_Const + * @brief The statistic module sample size. It decides how much data is used to + * do calculation. + * @{ + */ +#define STATSAMPLE_128 0 /**< Sample size 128 */ +#define STATSAMPLE_64 1 /**< Sample size 64 */ +#define STATSAMPLE_32 2 /**< Sample size 32 */ +#define STATSAMPLE_16 3 /**< Sample size 16 */ +#define STATSAMPLE_8 4 /**< Sample size 8 */ +/** @} */ + +/* Statistic standard deviation configure */ +/** + * @defgroup STATDEV_Const + * @brief The standard deviation configure + * @{ + */ +#define STATDEV_1 1 /**< Used for check outlier of ADC result */ +#define STATDEV_4 4 /**< Used for check outlier of ADC result */ +#define STATDEV_9 9 /**< Used for check outlier of ADC result */ +#define STATDEV_16 16 /**< Used for check outlier of ADC result */ +#define STATDEV_25 25 /**< Used for check outlier of ADC result */ +/** @} */ + +/** + * @} Statistic_Block_Const + * @} DSP_Block_Const + * @} DSP_Block + * + */ + +/** + * @addtogroup Sequencer_FIFO + * @{ + * @defgroup Sequencer_FIFO_Const + * @brief This block includes sequencer and FIFO related all parameters. + * @{ + */ + +/** + * @defgroup SEQID_Const + * @{ + */ +#define SEQID_0 0 /**< Sequence0 */ +#define SEQID_1 1 /**< Sequence1 */ +#define SEQID_2 2 /**< Sequence2 */ +#define SEQID_3 3 /**< Sequence3 */ +/** @} */ + +/** + * @defgroup SEQID_Const + * @brief Sequencer memory size. SRAM is shared between FIFO and Sequencer + * @warning The total available SRAM is 6kB. It's shared by FIFO and sequencer. + * @{ + */ +#define SEQMEMSIZE_32B \ + 0 /**< The selfbuild in 32Byte for sequencer. All 6kB SRAM can be used for \ + data FIFO */ +#define SEQMEMSIZE_2KB \ + 1 /**< Sequencer use 2kB. The reset 4kB can be used for data FIFO */ +#define SEQMEMSIZE_4KB 2 /**< 4kB for Sequencer. 2kB for data FIFO */ +#define SEQMEMSIZE_6KB \ + 3 /**< All 6kB for Sequencer. Build in 32Bytes memory can be used for data \ + FIFO */ +/** @} */ + +/* Mode of GPIO detecting used for triggering sequence */ +/** + * @defgroup SEQPINTRIGMODE_Const + * @{ + */ +#define SEQPINTRIGMODE_RISING 0 /**< Rising edge */ +#define SEQPINTRIGMODE_FALLING 1 /**< Falling edge */ +#define SEQPINTRIGMODE_BOTHEDGE 2 /**< Rising or falling */ +#define SEQPINTRIGMODE_HIGHL 3 /**< High level */ +#define SEQPINTRIGMODE_LOWL 4 /**< Low level */ +/** @} */ + +/* Sequencer helper */ +/** + * @defgroup Sequencer_Helper + * @{ + */ + +/* Three kinds of sequencer commands: wait, time-out, write */ +/* Decoded by BIT[31:30] */ +/** + * Wait command. Wait some clocks-code Command Code: 'b00 + * @warning Maximum wait time is 0x3fff_ffff/System clock. + */ +#define SEQ_WAIT(ClkNum) (0x00000000 | ((uint32_t)(ClkNum) & 0x3fffffff)) + +/** + * Time-Out command. Set time-out count down value. Command Code: 'b01 + * @warning maximum time-out timer value is 0x3fffffff + * */ +#define SEQ_TOUT(ClkNum) (0x40000000 | ((uint32_t)(ClkNum) & 0x3fffffff)) + +/** + * Write register command. Command Code: 'b10 or 'b11 + * @warning Address range is 0x2000 to 0x21FF. Data is limited to 24bit width. + * */ +#define SEQ_WR(addr, data) \ + (0x80000000 | (((((uint32_t)(addr)) >> 2) & 0x7f) << 24) | \ + (((uint32_t)(data)) & 0xffffff)) + +/* Some commands used frequently */ +#define SEQ_NOP() \ + SEQ_WAIT(0) /**< SEQ_NOP is just a simple wait command that wait one system \ + clock */ +#define SEQ_HALT() \ + SEQ_WR(REG_AFE_SEQCON, 0x12) /**< Can halt sequencer. Used for debug */ +#define SEQ_STOP() \ + SEQ_WR(REG_AFE_SEQCON, 0x00) /**< Disable sequencer, this will generate End \ + of Sequence interrupt */ + +#define SEQ_SLP() \ + SEQ_WR(REG_AFE_SEQTRGSLP, 1) /**< Trigger sleep. If sleep is allowed, AFE \ + will go to sleep/hibernate mode */ + +#define SEQ_INT0() \ + SEQ_WR(REG_AFE_AFEGENINTSTA, (1L << 0)) /**< Generate custom interrupt 0 */ +#define SEQ_INT1() \ + SEQ_WR(REG_AFE_AFEGENINTSTA, (1L << 1)) /**< Generate custom interrupt 1 */ +#define SEQ_INT2() \ + SEQ_WR(REG_AFE_AFEGENINTSTA, (1L << 2)) /**< Generate custom interrupt 2 */ +#define SEQ_INT3() \ + SEQ_WR(REG_AFE_AFEGENINTSTA, (1L << 3)) /**< Generate custom interrupt 3 */ + +/* Helper to calculate sequence length in array */ +#define SEQ_LEN(n) \ + (sizeof(n) / 4) /**< Calculate how many commands are in sepecified array. */ +/** @} */ // Sequencer_Helper + +/* FIFO */ +/** + * @defgroup FIFOMODE_Const + * @{ + */ +#define FIFOMODE_FIFO \ + 2 /**< Standard FIFO mode. If FIFO is full, reject all comming data and put \ + FIFO to fault state, report interrupt if enabled */ +#define FIFOMODE_STREAM \ + 3 /**< Stream mode. If FIFO is full, discard older data. Report FIFO full \ + interrupt if enabled */ +/** @} */ + +/** + * @defgroup FIFOSRC_Const + * @{ + */ +#define FIFOSRC_SINC3 0 /**< SINC3 data */ +#define FIFOSRC_DFT 2 /**< DFT real and imaginary part */ +#define FIFOSRC_SINC2NOTCH \ + 3 /**< SINC2+NOTCH block. Notch can be bypassed, so SINC2 data can be feed \ + to FIFO */ +#define FIFOSRC_VAR 4 /**< Statistic variarance output */ +#define FIFOSRC_MEAN 5 /**< Statistic mean output */ +/** @} */ + +/** + * @defgroup FIFO_Helper + * @{ + */ +/** + * Method to identify FIFO channel ID: + * [31:25][24:23][22:16][15:0] + * [ ECC ][SEQID][CH_ID][DATA] + * + * CH_ID: [22:16] 7bit in total: + * xxxxx_xx + * 11111_xx : DFT results + * 11110_xx : Mean of statistic block + * 11101_xx : Variance of statistic block + * 1xxxx_xx : Notch filter result, where xxx_xx is the ADC MUX P + * settings(6bits of reg ADCCON[5:0]). 0xxxx_xx : SINC3 filter result, where + * xxx_xx is the ADC MUX P settings(6bits of reg ADCCON[5:0]). + */ +#define FIFO_SEQID(data) \ + ((((uint32_t)data) >> 23) & 0x3) /**< Return seqid of this FIFO result */ +#define FIFO_ECC(data) \ + ((((uint32_t)data) >> 25) & 0x7f) /**< Return ECC of this FIFO result */ +#define FIFO_CHANID(data) \ + ((((uint32_t)data) >> 16) & 0x7f) /**< Return Channel ID */ +#define FIFOCHANID_MUXP(data) \ + ((((uint32_t)data) >> 16) & 0x3f) /**< Return the ADC MUXP selection */ + +#define ISCHANID_DFT(data) \ + ((((((uint32_t)data) >> 18) & 0x1f) == 0x1f) \ + ? bTRUE \ + : bFALSE) /**< If the channel id is DFT */ +#define ISCHANID_MEAN(data) \ + ((((((uint32_t)data) >> 18) & 0x1f) == 0x1e) \ + ? bTRUE \ + : bFALSE) /**< If the channel id is MEAN */ +#define ISCHANID_VAR(data) \ + ((((((uint32_t)data) >> 18) & 0x1f) == 0x1d) \ + ? bTRUE \ + : bFALSE) /**< If the channel id is Variance */ +#define ISCHANID_SINC3(data) \ + ((((((uint32_t)data) >> 18) & 0x1f) < 0x10) \ + ? bTRUE \ + : bFALSE) /**< If the channel id is SINC3 */ +#define ISCHANID_NOTCH(data) \ + ((((((uint32_t)data) >> 18) & 0x1f) >= 0x10) && \ + (((((uint32_t)data >> 18) & 0x1f) < 0x1d) \ + ? bTRUE \ + : bFALSE)) /**< If the channel id is Notch */ +/** @} */ + +/** + * @defgroup FIFOSIZE_Const + * @brief Set FIFO size. + * @warning The total available SRAM is 6kB. It's shared by FIFO and sequencer. + * @{ + */ +#define FIFOSIZE_32B \ + 0 /**< The selfbuild in 32Byte for data FIFO. All 6kB SRAM for sequencer */ +#define FIFOSIZE_2KB \ + 1 /**< DATA FIFO use 2kB. The reset 4kB is used for sequencer */ +#define FIFOSIZE_4KB 2 /**< 4kB for Data FIFO. 2kB for sequencer */ +#define FIFOSIZE_6KB \ + 3 /**< All 6kB for Data FIFO. Build in 32Bytes memory for sequencer */ +/** @} */ + +/* Wake up timer */ +/** + * @defgroup WUPTENDSEQ_Const + * @{ + */ +#define WUPTENDSEQ_A 0 /**< End at slot A */ +#define WUPTENDSEQ_B 1 /**< End at slot B */ +#define WUPTENDSEQ_C 2 /**< End at slot C */ +#define WUPTENDSEQ_D 3 /**< End at slot D */ +#define WUPTENDSEQ_E 4 /**< End at slot E */ +#define WUPTENDSEQ_F 5 /**< End at slot F */ +#define WUPTENDSEQ_G 6 /**< End at slot G */ +#define WUPTENDSEQ_H 7 /**< End at slot H */ +/** @} */ + +/** + * @} End of sequencer_and_FIFO block + * @} Sequencer_FIFO + * */ + +/** + * @addtogroup MISC_Block + * @{ + * @defgroup MISC_Block_Const + * @brief This block includes clock, GPIO, configuration. + * @{ + */ + +/* Helper for calculate clocks needed for various of data type */ +/** + * @defgroup DATATYPE_Const + * @{ + */ +#define DATATYPE_ADCRAW 0 /**< ADC raw data */ +#define DATATYPE_SINC3 1 /**< SINC3 data */ +#define DATATYPE_SINC2 2 /**< SINC2 Data */ +#define DATATYPE_DFT 3 /**< DFT */ +#define DATATYPE_NOTCH \ + 4 /**< Notch filter output. (when notch is not bypassed) */ +// #define DATATYPE_MEAN +/** @} */ + +/** + * @defgroup SLPKEY_Const + * @{ + */ +#define SLPKEY_LOCK 0 /**< any incorrect value will lock the key */ +#define SLPKEY_UNLOCK 0xa47e5 /**< The correct key for register SEQSLPLOCK */ +/** @} */ + +/** + * @defgroup HPOSCOUT_Const + * @brief Set HPOSC output clock frequency, 16MHz or 32MHz. + * @{ + */ +#define HPOSCOUT_32MHZ 0 /**< Configure internal HFOSC output 32MHz clock */ +#define HPOSCOUT_16MHZ 1 /**< 16MHz Clock */ +/** @} */ + +/* GPIO */ +/** + * @defgroup AGPIOPIN_Const + * @brief The pin masks for register GP0OEN, GP0PE, GP0IEN,..., GP0TGL + * @{ + */ +#define AGPIO_Pin0 \ + 0x01 /**< AFE GPIO0, only available on AD5940 and AD5941, not ADuCM355 */ +#define AGPIO_Pin1 \ + 0x02 /**< AFE GPIO1, only available on AD5940 and AD5941, not ADuCM355 */ +#define AGPIO_Pin2 \ + 0x04 /**< AFE GPIO2, only available on AD5940 and AD5941, not ADuCM355 */ +#define AGPIO_Pin3 0x08 /**< AFE GPIO3, only available on AD5941. */ +#define AGPIO_Pin4 0x10 /**< AFE GPIO4, only available on AD5941. */ +#define AGPIO_Pin5 0x20 /**< AFE GPIO5, only available on AD5941. */ +#define AGPIO_Pin6 0x40 /**< AFE GPIO6, only available on AD5941. */ +#define AGPIO_Pin7 0x80 /**< AFE GPIO7, only available on AD5941. */ +/** @} */ + +/** + * @defgroup GP0FUNC_Const + * @{ + */ +#define GP0_INT 0 /**< Interrupt Controller 0 output */ +#define GP0_TRIG 1 /**< Sequence0 trigger */ +#define GP0_SYNC 2 /**< Use Sequencer to controll GP0 output level */ +#define GP0_GPIO 3 /**< Normal GPIO function */ +/** @} */ + +/** + * @defgroup GP1FUNC_Const + * @{ + */ +#define GP1_GPIO (0 << 2) /**< Normal GPIO function */ +#define GP1_TRIG (1 << 2) /**< Sequence1 trigger */ +#define GP1_SYNC (2 << 2) /**< Use Sequencer to controll GP1 output level */ +#define GP1_SLEEP (3 << 2) /**< Internal Sleep Signal */ +/** @} */ + +/** + * @defgroup GP2FUNC_Const + * @{ + */ +#define GP2_PORB (0 << 4) /**< Internal Power ON reset signal */ +#define GP2_TRIG (1 << 4) /**< Sequence1 trigger */ +#define GP2_SYNC (2 << 4) /**< Use Sequencer to controll GP2 output level */ +#define GP2_EXTCLK (3 << 4) /**< External Clock input(32kHz/16MHz/32MHz) */ +/** @} */ + +/** + * @defgroup GP3FUNC_Const + * @{ + */ +#define GP3_GPIO (0 << 6) /**< Normal GPIO function */ +#define GP3_TRIG (1 << 6) /**< Sequence3 trigger */ +#define GP3_SYNC (2 << 6) /**< Use Sequencer to controll GP3 output level */ +#define GP3_INT0 (3 << 6) /**< Interrupt Controller 0 output */ +/** @} */ + +/** + * @defgroup GP4FUNC_Const + * @note GP4 (Not available on AD5941) + * @{ + */ +#define GP4_GPIO (0 << 8) /**< Normal GPIO function */ +#define GP4_TRIG (1 << 8) /**< Sequence0 trigger */ +#define GP4_SYNC (2 << 8) /**< Use Sequencer to controll GP4 output level */ +#define GP4_INT1 (3 << 8) /**< Interrupt Controller 1 output */ +/** @} */ + +/** + * @defgroup GP5FUNC_Const + * @note GP5 (Not available on AD5941) + * @{ + */ +#define GP5_GPIO (0 << 10) /**< Internal Power ON reset signal */ +#define GP5_TRIG (1 << 10) /**< Sequence1 trigger */ +#define GP5_SYNC (2 << 10) /**< Use Sequencer to controll GP5 output level */ +#define GP5_EXTCLK (3 << 10) /**< External Clock input(32kHz/16MHz/32MHz) */ +/** @} */ + +/** + * @defgroup GP6FUNC_Const + * @note GP6 (Not available on AD5941) + * @{ + */ +#define GP6_GPIO (0 << 12) /**< Normal GPIO function */ +#define GP6_TRIG (1 << 12) /**< Sequence2 trigger */ +#define GP6_SYNC (2 << 12) /**< Use Sequencer to controll GP6 output level */ +#define GP6_INT0 (3 << 12) /**< Interrupt Controller 0 output */ +/** @} */ + +/** + * @defgroup GP7FUNC_Const + * @note GP7 (Not available on AD5941) + * @{ + */ +#define GP7_GPIO (0 << 14) /**< Normal GPIO function */ +#define GP7_TRIG (1 << 14) /**< Sequence2 trigger */ +#define GP7_SYNC (2 << 14) /**< Use Sequencer to controll GP7 output level */ +#define GP7_INT (3 << 14) /**< Interrupt Controller 1 output */ +/** @} */ + +// LPModeClk +/** + * @defgroup LPMODECLK_Const + * @{ + */ +#define LPMODECLK_HFOSC 0 /**< Use HFOSC 16MHz/32MHz clock as system clock */ +#define LPMODECLK_LFOSC 1 /**< Use LFOSC 32kHz clock as system clock */ +/** @} */ + +/* Clock */ +/** + * @defgroup SYSCLKSRC_Const + * @brief Select system clock source. The clock must be available. If + * unavailable clock is selected, we can reset AD5940. The system clock should + * be limited to 32MHz. If external clock or XTAL is faster than 16MHz, we use + * system clock divider to ensure it's always in range of 16MHz. + * @warning Maximum SPI clock has relation with system clock. Limit the SPI + * clock to ensure SPI clock is slower than system clock. + * @{ + */ +#define SYSCLKSRC_HFOSC \ + 0 /**< Internal HFOSC. CLock is 16MHz or 32MHz configurable. Set clock \ + divider to ensure system clock is always 16MHz */ +#define SYSCLKSRC_XTAL \ + 1 /**< External crystal. It can be 16MHz or 32MHz.Set clock divider to \ + ensure system clock is always 16MHz */ +#define SYSCLKSRC_LFOSC \ + 2 /**< Internal 32kHz clock. Note the SPI clock also sourced with 32kHz so \ + the register read/write frequency is lower down. */ +#define SYSCLKSRC_EXT 3 /**< External clock from GPIO, AD594x Only */ +/** @} */ + +/** + * @defgroup ADCCLKSRC_Const + * @brief Select ADC clock source. + * The maximum clock is 32MHz. + * @warning The ADC raw data update rate is equal to ADCClock/20. When ADC clock + * is 32MHz, sample rate is 1.6MSPS. The SINC3 filter clock are sourced from ADC + * clock and should be limited to 16MHz. When ADC clock is set to 32MHz. Clear + * bit ADCFILTERCON.BIT0 to enable the SINC3 clock divider. + * @{ + */ +#define ADCCLKSRC_HFOSC \ + 0 /**< Internal HFOSC. 16MHz or 32MHz which is configurable */ +#define ADCCLKSRC_XTAL \ + 1 /**< External crystal. Set ADC clock divider to get either 16MHz or 32MHz \ + clock */ +// #define ADCCLKSRC_LFOSC 2 /**< Do not use */ +#define ADCCLKSRC_EXT \ + 3 /**< External clock from GPIO. Set ADC clock divider to get the clock you \ + want */ +/** @} */ + +/** + * @defgroup ADCCLKDIV_Const + * @brief The divider for ADC clock. ADC clock = ClockSrc/Divider. + * @{ + */ +#define ADCCLKDIV_1 1 /**< Divider ADCClk = ClkSrc/1 */ +#define ADCCLKDIV_2 2 /**< Divider ADCClk = ClkSrc/2 */ +/** @} */ + +/** + * @defgroup SYSCLKDV_Const + * @brief The divider for system clock. System clock = ClockSrc/Divider. + * @{ + */ +#define SYSCLKDIV_1 1 /**< Divider SysClk = ClkSrc/1 */ +#define SYSCLKDIV_2 2 /**< Divider SysClk = ClkSrc/2 */ +/** @} */ + +/** + * @defgroup PGACALTYPE_Const + * @brief Calibration Type + * @{ + */ +#define PGACALTYPE_OFFSET 0 /**< Calibrate offset */ +#define PGACALTYPE_GAIN 1 /**< Calibrate gain */ +#define PGACALTYPE_OFFSETGAIN 2 /**< Calibrate offset and gain */ +/** @} */ + +/** + * @defgroup AD5940ERR_Const + * @brief AD5940 error code used by library and example codes. + * @{ + */ +#define AD5940ERR_OK 0 /**< No error */ +#define AD5940ERR_ERROR -1 /**< General error message */ +#define AD5940ERR_PARA -2 /**< Parameter is illegal */ +#define AD5940ERR_NULLP -3 /**< Null pointer */ +#define AD5940ERR_BUFF -4 /**< Buffer limited. */ +#define AD5940ERR_ADDROR \ + -5 /**< Out of Range. Register address is out of range. */ +#define AD5940ERR_SEQGEN -6 /**< Sequence generator error */ +#define AD5940ERR_SEQREG -7 /**< Register info is not found */ +#define AD5940ERR_SEQLEN -8 /**< Sequence length is too long. */ +#define AD5940ERR_WAKEUP -9 /**< Unable to wakeup AFE in specified time */ +#define AD5940ERR_TIMEOUT -10 /**< Time out error. */ +#define AD5940ERR_CALOR -11 /**< calibration out of range. */ +#define AD5940ERR_APPERROR \ + -100 /**< Used in example code to indicated the application has not been \ + initialized. */ +/** @} */ + +#ifndef NULL +#define NULL (void *)0 /**< Null, if it's not defined. */ +#endif +#define MATH_PI 3.1415926f /**< Pi defination. */ + +#define AD5940_ADIID 0x4144 /**< ADIID is fixed to 0x4144 */ +#define AD5940_CHIPID 0x0000 /**< CHIPID is changing with silicon version */ +#define M355_ADIID 0x4144 /**< ADIID is fixed to 0x4144 */ +#define M355_CHIPID 0x0000 /**< CHIPID is changing with silicon version */ + +#define AD5940_SWRST \ + 0xa158 /**< AD594x only. The value to perform software reset via reigster \ + SWRSTCON */ +#define KEY_OSCCON \ + 0xcb14 /**< key of register OSCCON. The key is auto locked after writing to \ + any other register */ +#define KEY_CALDATLOCK 0xde87a5af /**< Calibration key. */ +#define KEY_LPMODEKEY 0xc59d6 /**< LP mode key */ + +#define PARA_CHECK(n) /** add parameter check, Add DEBUG switch */ + +/** + * @} MISC_Block_Const + * @} MISC_Block + * */ +/** + * @defgroup TypeDefinitions + * @{ + */ + +typedef int32_t AD5940Err; /**< error number defination */ + +/** + * bool definition for ad5940lib. + */ +typedef enum { + bFALSE = 0, + bTRUE = !bFALSE, /**< True and False definition*/ +} BoolFlag; + +typedef struct { + /* ADC/DAC/TIA reference and buffer */ + BoolFlag HpBandgapEn; /**< Enable High power band-gap. Clear bit + AFECON.HPREFDIS will enable Bandgap, while set this + bit will disable bandgap */ + BoolFlag Hp1V8BuffEn; /**< High power 1.8V reference buffer enable */ + BoolFlag Hp1V1BuffEn; /**< High power 1.1V reference buffer enable */ + BoolFlag Lp1V8BuffEn; /**< Low power 1.8V reference buffer enable */ + BoolFlag Lp1V1BuffEn; /**< Low power 1.1V reference buffer enable */ + /* Low bandwidth loop reference and buffer */ + BoolFlag LpBandgapEn; /**< Enable Low power band-gap. */ + BoolFlag LpRefBufEn; /**< Enable the 2.5V low power reference buffer */ + BoolFlag LpRefBoostEn; /**< Boost buffer current */ + /* DAC Reference Buffer */ + BoolFlag HSDACRefEn; /**< Enable DAC reference buffer from HP Bandgap */ + /* Misc. control */ + BoolFlag Hp1V8ThemBuff; /**< Thermal Buffer for internal 1.8V reference to + AIN3 pin */ + BoolFlag + Hp1V8Ilimit; /**< Current limit for High power 1.8V reference buffer */ + BoolFlag + Disc1V8Cap; /**< Discharge 1.8V capacitor. Short external 1.8V decouple + capacitor to ground. Be careful when use this bit */ + BoolFlag + Disc1V1Cap; /**< Discharge 1.1V capacitor. Short external 1.1V decouple + capacitor to ground. Be careful when use this bit */ +} AFERefCfg_Type; + +/** + * @defgroup ADC_BlockType + * @{ + */ + +/** + * Structure for ADC Basic settings include MUX and PGA. + */ +typedef struct { + uint32_t ADCMuxP; /**< ADC Positive input channel selection. select from @ref + ADCMUXP */ + uint32_t ADCMuxN; /**< ADC negative input channel selection. select from @ref + ADCMUXN */ + uint32_t ADCPga; /**< ADC PGA settings, select from @ref ADCPGA */ +} ADCBaseCfg_Type; + +/** + * Structure for ADC filter settings. + */ +typedef struct { + uint32_t ADCSinc3Osr; + uint32_t ADCSinc2Osr; + uint32_t ADCAvgNum; /**< Average filter is enabled when DFT source is @ref + DFTSRC_AVG in function @ref AD5940_DFTCfgS. This + average filter is only used by DFT engine. */ + uint32_t ADCRate; /**< ADC Core sample rate */ + BoolFlag BpNotch; /**< Bypass Notch filter in SINC2+Notch block, so only SINC2 + is used. ADCFILTERCON.BIT4 */ + BoolFlag BpSinc3; /**< Bypass SINC3 Module */ + BoolFlag Sinc3ClkEnable; /**< Enable SINC3 clock */ + BoolFlag Sinc2NotchClkEnable; /**< Enable SINC2+Notch clock */ + BoolFlag Sinc2NotchEnable; /**< Enable SINC2+Notch block */ + BoolFlag DFTClkEnable; /**< Enable DFT clock */ + BoolFlag WGClkEnable; /**< Enable Waveform Generator clock */ +} ADCFilterCfg_Type; +/** @} */ + +/** + * DFT Configuration structure. + */ +typedef struct { + uint32_t DftNum; /**< DFT number */ + uint32_t DftSrc; /**< DFT Source */ + BoolFlag HanWinEn; /**< Enable Hanning window */ +} DFTCfg_Type; + +/** + * ADC digital comparator + */ +typedef struct { + uint16_t ADCMin; /**< The ADC code minimum limit value */ + uint16_t ADCMinHys; + uint16_t ADCMax; /**< The ADC code maximum limit value */ + uint16_t ADCMaxHys; +} ADCDigComp_Type; + +/** + * Statistic function + */ +typedef struct { + uint32_t StatDev; /**< Statistic standard deviation configure */ + uint32_t StatSample; /**< Sample size */ + BoolFlag StatEnable; /**< Set true to enable statistic block */ +} StatCfg_Type; + +/** + * Switch matrix configure */ +typedef struct { + uint32_t Dswitch; /**< D switch settings. Select from @ref SWD_Const*/ + uint32_t Pswitch; /**< P switch settings. Select from @ref SWP_Const */ + uint32_t Nswitch; /**< N switch settings. Select from @ref SWN_Const */ + uint32_t Tswitch; /**< T switch settings. Select from @ref SWT_Const */ +} SWMatrixCfg_Type; + +/** HSTIA Configure */ +typedef struct { + uint32_t HstiaBias; /**< When select Vzero as bias, the related + switch(VZERO2HSTIA) at LPDAC should be closed */ + uint32_t HstiaRtiaSel; /**< RTIA selection @ref HSTIARTIA_Const */ + uint32_t ExtRtia; /**< Value of external RTIA*/ + uint32_t HstiaCtia; /**< Set internal CTIA value from 1 to 32 pF */ + BoolFlag DiodeClose; /**< Close the switch for internal back to back diode */ + uint32_t HstiaDeRtia; /**< DE0 node RTIA selection @ref HSTIADERTIA_Const */ + uint32_t + HstiaDeRload; /**< DE0 node Rload selection @ref HSTIADERLOAD_Const */ + uint32_t HstiaDe1Rtia; /**< (ADuCM355 only, ignored on AD594x)DE1 node RTIA + selection @ref HSTIADERTIA_Const */ + uint32_t HstiaDe1Rload; /**< (ADuCM355 only)DE1 node Rload selection @ref + HSTIADERLOAD_Const */ +} HSTIACfg_Type; + +/** HSDAC Configure */ +typedef struct { + uint32_t ExcitBufGain; /**< Select from EXCITBUFGAIN_2, EXCITBUFGAIN_0P25 */ + uint32_t HsDacGain; /**< Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + uint32_t + HsDacUpdateRate; /**< Divider for DAC update. Available range is 7~255. */ +} HSDACCfg_Type; + +/** LPDAC Configure + * @note The LPDAC structure: + * @code + * Switch to select DAC output to Vzero and Vbias nodes. Vzero and Vbias can + * select from DAC6BIT and DAC12BIT output freely. LPDAC >DAC6BIT ---- Vzero + * LPDACVZERO_12BIT + * \--- Vbias LPDACVBIAS_6BIT + * >DAC12BIT---- Vzero LPDACVZERO_6BIT + * \--- Vbias LPDACVBIAS_12BIT + * Vzero/Vbias switch, controlled by @ref LPDACCfg_Type LpDacSW + * Vzero ------PIN + * \-----LPTIA LPDACSW_VZERO2LPTIA. LPTIA positive input + * \----HSTIA LPDACSW_VZERO2LPAMP. HSTIA positive input. Note, there is + * a MUX on HSTIA positive input pin to select the bias voltage between Vzero + * and 1.1V fixed internal reference. Vbias ------PIN LPDACSW_VBIAS2PIN + * \-----LPAMP LPDACSW_VBIAS2LPAMP positive input. The potential state + * amplifier input, or called LPAMP or PA(potential amplifier). + * @endcode + */ +typedef struct { + uint32_t LpdacSel; /**< Selectr from LPDAC0 or LPDAC1. LPDAC1 is only + available on ADuCM355. */ + uint32_t LpDacSrc; /**< LPDACSRC_MMR or LPDACSRC_WG. Note: HSDAC is always + connects to WG. Disable HSDAC if there is need. */ + uint32_t LpDacVzeroMux; /**< Select which DAC output connects to Vzero. 6Bit + or 12Bit DAC */ + uint32_t LpDacVbiasMux; /**< Select which DAC output connects to Vbias */ + uint32_t LpDacSW; /**< LPDAC switch set. Only available from Si2 */ + uint32_t LpDacRef; /**< Reference selection. Either internal 2.5V LPRef or + AVDD. select from @ref LPDACREF_Const*/ + BoolFlag DataRst; /**< Keep Reset register REG_AFE_LPDACDAT0DATA */ + BoolFlag PowerEn; /**< Power up REG_AFE_LPDACDAT0 */ + uint16_t DacData12Bit; /**< Data for 12bit DAC */ + uint16_t DacData6Bit; /**< Data for 6bit DAC */ +} LPDACCfg_Type; + +/** + * Low power amplifiers(PA and TIA) + */ +typedef struct { + uint32_t LpAmpSel; /**< Select from LPAMP0 and LPAMP1. LPAMP1 is only + available on ADuCM355. */ + uint32_t LpTiaRf; /**< The one order RC filter resistor selection. Select from + @ref LPTIARF_Const */ + uint32_t LpTiaRload; /**< The Rload resistor right in front of LPTIA negative + input terminal. Select from @ref LPTIARLOAD_Const*/ + uint32_t LpTiaRtia; /**< LPTIA RTIA resistor selection. Set it to open(@ref + LPTIARTIA_Const) when use external resistor. */ + uint32_t LpAmpPwrMod; /**< Power mode for LP PA and LPTIA */ + uint32_t + LpTiaSW; /**< Set of switches, using macro LPTIASW() to close switch */ + BoolFlag LpPaPwrEn; /**< Enable(bTRUE) or disable(bFALSE) power of + PA(potential amplifier) */ + BoolFlag LpTiaPwrEn; /**< Enable(bTRUE) or Disable(bFALSE) power of LPTIA + amplifier */ +} LPAmpCfg_Type; + +/** + * @brief Trapezoid Generator parameters + * The definition of the Trapezoid waveform is shown below. Note the Delay and + * Slope are all in clock unit. + * @code + * + * DCLevel2 _________ + * / \ + * / \ + * DCLevel1 _____/ \______ + * | | | | | + * Delay1|S1|Delay2 |S2| Delay1 repeat... + * Where S1 is slope1 and S2 is slop2 + * @endcode + * The DAC update rate from Trapezoid generator is SystemClock/50. The default + * SystemClock is internal HFOSC 16MHz. So the update rate is 320kHz. The time + * parameter specifies in clock number. For example, if Delay1 is set to 10, S1 + * is set 20, the time for Delay1 period is 10/320kHz = 31.25us, and time for S1 + * period is 20/320kHz = 62.5us. + */ +typedef struct { + uint32_t WGTrapzDCLevel1; /**< Trapezoid generator DC level1, this value is + written directly to corresponding register */ + uint32_t WGTrapzDCLevel2; /**< DC level2, similar to DCLevel1 */ + uint32_t WGTrapzDelay1; /**< Trapezoid generator delay 1 */ + uint32_t WGTrapzDelay2; /**< Trapezoid generator delay 2 */ + uint32_t WGTrapzSlope1; /**< Trapezoid generator Slope 1 */ + uint32_t WGTrapzSlope2; /**< Trapezoid generator Slope 2 */ +} WGTrapzCfg_Type; + +/** + * Sin wave generator parameters + */ +typedef struct { + uint32_t SinFreqWord; /**< Frequency word */ + uint32_t SinAmplitudeWord; /**< Amplitude word, range is 0 to 2047. Amplitude + range is 0 to 800mV */ + uint32_t SinOffsetWord; /**< Offset word, range is -2048 to 2047. Offset + voltage range is -800 to +800mV */ + uint32_t SinPhaseWord; /**< the start phase of sine wave. Use to tune start + phase of signal. */ +} WGSinCfg_Type; + +/** + * Waveform generator configuration + */ +typedef struct { + uint32_t WgType; /**< Select from WGTYPE_MMR, WGTYPE_SIN, WGTYPE_TRAPZ. HSDAC + is always connected to WG. */ + BoolFlag GainCalEn; /**< Enable Gain calibration */ + BoolFlag OffsetCalEn; /**< Enable offset calibration */ + WGTrapzCfg_Type TrapzCfg; /**< Configure Trapezoid generator */ + WGSinCfg_Type SinCfg; /**< Configure Sine wave generator */ + uint32_t WgCode; /**< The 12bit data WG will move to DAC data register. */ +} WGCfg_Type; + +/** + * High speed loop configuration + * */ +typedef struct { + SWMatrixCfg_Type SWMatCfg; /**< switch matrix configuration. */ + HSDACCfg_Type HsDacCfg; /**< HSDAC configuration. */ + WGCfg_Type WgCfg; /**< Waveform generator configuration. */ + HSTIACfg_Type HsTiaCfg; /**< HSTIA configuration. */ +} HSLoopCfg_Type; + +/** + * Low power loop Configure + * */ +typedef struct { + LPDACCfg_Type LpDacCfg; /**< LPDAC configuration. @note Must select LPDAC0 or + LPDAC1 in structure. */ + LPAmpCfg_Type LpAmpCfg; /**< LPAMP(LPTIA and PA) configuration. @note Must + select LPAMP0 or LPAMP1 in structure. */ +} LPLoopCfg_Type; + +/** + * DSP Configure + * */ +typedef struct { + ADCBaseCfg_Type ADCBaseCfg; /**< ADC base configuration */ + ADCFilterCfg_Type ADCFilterCfg; /**< ADC filter configuration include + SINC3/SINC2/Notch/Average(for DFT only) */ + ADCDigComp_Type ADCDigCompCfg; /**< ADC digital comparator */ + DFTCfg_Type DftCfg; /**< DFT configuration include data source, DFT number and + Hanning Window */ + StatCfg_Type StatCfg; /**< Statistic block */ +} DSPCfg_Type; + +/** + * GPIO Configure + * */ +typedef struct { + uint32_t FuncSet; /**< AGP0 to AGP7 function sets */ + uint32_t OutputEnSet; /**< AGPIO_Pin0|AGPIO_Pin1|...|AGPIO_Pin7, Enable output + of selected pins, disable other pins */ + uint32_t InputEnSet; /**< Enable input of selected pins, disable other pins */ + uint32_t PullEnSet; /**< Enable pull up or down on selected pin. disable other + pins */ + uint32_t OutVal; /**< Value for GPIOOUT register */ +} AGPIOCfg_Type; + +/** + * FIFO configure + */ +typedef struct { + BoolFlag FIFOEn; /**< Enable DATAFIFO. Disable FIFO will reset FIFO */ + uint32_t FIFOMode; /**< Stream mode or standard FIFO mode */ + uint32_t FIFOSize; /**< How to allocate the internal 6kB SRAM. Data FIFO and + sequencer share all 6kB SRAM */ + uint32_t FIFOSrc; /**< Select which data source will be stored to FIFO */ + uint32_t FIFOThresh; /**< FIFO threshold value, 0 to 1023. Threshold can be + used to generate interrupt so MCU can read back data + before FIFO is full */ +} FIFOCfg_Type; + +/** + * Sequencer configure + */ +typedef struct { + uint32_t SeqMemSize; /**< Sequencer memory size. SRAM is used by both FIFO and + Sequencer. Make sure the total SRAM used is less than + 6kB. */ + BoolFlag SeqEnable; /**< Enable sequencer. Only with valid trigger, sequencer + can run */ + BoolFlag SeqBreakEn; /**< Do not use it */ + BoolFlag SeqIgnoreEn; /**< Do not use it */ + BoolFlag SeqCntCRCClr; /**< Clear sequencer count and CRC */ + uint32_t + SeqWrTimer; /**< Set wait how much clocks after every commands executed */ +} SEQCfg_Type; + +/** + * Sequence info structure + */ +typedef struct { + uint32_t SeqId; /**< The Sequence ID @ref SEQID_Const */ + uint32_t SeqRamAddr; /**< The start address that in AF5940 SRAM */ + uint32_t SeqLen; /**< Sequence length */ + BoolFlag WriteSRAM; /**< Write command to SRAM or not. */ + const uint32_t + *pSeqCmd; /**< Pointer to the sequencer commands that stored in MCU */ +} SEQInfo_Type; + +typedef struct { + uint32_t PinSel; /**< Select which pin are going to be configured. @ref + AGPIOPIN_Const */ + uint32_t SeqPinTrigMode; /**< The pin detect mode. Select from @ref + SEQPINTRIGMODE_Const */ + BoolFlag bEnable; /**< Allow detected pin action to trigger corresponding + sequence. */ +} SeqGpioTrig_Cfg; + +/** + * Wakeup Timer Configure + * */ +typedef struct { + uint32_t WuptEndSeq; /**< end sequence selection @ref WUPTENDSEQ_Const. Wupt + will go back to slot A after this one is executed. */ + uint32_t WuptOrder[8]; /**< The 8 slots for WakeupTimer. Place @ref + SEQID_Const to this array. */ + uint32_t SeqxSleepTime[4]; /**< Time before put AFE to sleep. 0 to + 0x000f_ffff. We normally don't use this feature + and it's disabled in @ref AD5940_Initialize */ + uint32_t SeqxWakeupTime[4]; /**< Time before Wakeup AFE. */ + BoolFlag WuptEn; /**< Timer enable. Once enabled, it starts to run. */ +} WUPTCfg_Type; + +/** + * Clock configure + */ +typedef struct { + uint32_t SysClkSrc; /**< System clock source @ref SYSCLKSRC_Const */ + uint32_t ADCCLkSrc; /**< ADC clock source @ref ADCCLKSRC_Const */ + uint32_t SysClkDiv; /**< System clock divider. Use this to ensure System clock + < 16MHz. */ + uint32_t ADCClkDiv; /**< ADC control clock divider. ADC core clock is + @ADCCLkSrc, but control clock should be <16MHz. */ + BoolFlag HFOSCEn; /**< Enable internal 16MHz/32MHz HFOSC */ + BoolFlag HfOSC32MHzMode; /**< Enable internal HFOSC to output 32MHz */ + BoolFlag LFOSCEn; /**< Enable internal 32kHZ OSC */ + BoolFlag HFXTALEn; /**< Enable XTAL driver */ +} CLKCfg_Type; + +/** + * HSTIA internal RTIA calibration structure + * @note ADC filter settings and DFT should be configured properly based on + * signal frequency. + */ +typedef struct { + float fFreq; /**< Calibration frequency */ + float fRcal; /**< Rcal resistor value in Ohm*/ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + + HSTIACfg_Type HsTiaCfg; /**< HSTIA configuration */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + DFTCfg_Type DftCfg; /**< DFT configuration. */ + uint32_t bPolarResult; /**< bTRUE-Polar coordinate:Return results in Magnitude + and Phase. bFALSE-Cartesian coordinate: Return + results in Real part and Imaginary Part */ +} HSRTIACal_Type; + +/** + * LPTIA internal RTIA calibration structure + */ +typedef struct { + float fFreq; /**< Calibration frequency. Set it to 0.0 for DC calibration */ + float fRcal; /**< Rcal resistor value in Ohm*/ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + + uint32_t LpAmpSel; /**< Select from LPAMP0 and LPAMP1. LPAMP1 is only + available on ADuCM355. */ + BoolFlag bWithCtia; /**< Connect external CTIA or not. */ + uint32_t LpTiaRtia; /**< LPTIA RTIA selection. */ + uint32_t LpAmpPwrMod; /**< Amplifiers power mode setting */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + DFTCfg_Type DftCfg; /**< DFT configuration */ + uint32_t bPolarResult; /**< bTRUE-Polar coordinate:Return results in Magnitude + and Phase. bFALSE-Cartesian coordinate: Return + results in Real part and Imaginary Part */ +} LPRTIACal_Type; + +/** + * HSDAC calibration structure. + */ +typedef struct { + float fRcal; /**< Rcal resistor value in Ohm*/ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + + uint32_t AfePwrMode; /**< Calibrate DAC in High power mode */ + uint32_t ExcitBufGain; /**< Select from EXCITBUFGAIN_2, EXCITBUFGAIN_0P25 */ + uint32_t HsDacGain; /**< Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ +} HSDACCal_Type; + +/** + * LPDAC calibration structure. + */ +typedef struct { + uint32_t + LpdacSel; /**< Select from LPDAC0 and LPDAC1. LPDAC1 is ADuCM355 only. */ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + float ADCRefVolt; /**< ADC reference voltage. Default is 1.82V*/ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC2 OSR settings. */ + int32_t SettleTime10us; /**< Wait how much time after TIA is enabled? */ + int32_t TimeOut10us; /**< ADC converts signal need time. Specify the maximum + time allowed. Timeout in 10us. negative number means + wait no time. */ +} LPDACCal_Type; + +/** + * LPDAC parameters: LPDAC code to voltage transfer function. + * Voltage(mV) = kC2V_DACxB * Code + bC2V_DACxB; + * where x is 12 or 6 represent 12Bit DAC and 6Bit DAC. C2V means code to + * voltage. Code is the data register value for LPDAC. The equation gives real + * output voltage of LPDAC. Similarly, Code(LSB) = kV2C_DACxB * Voltage(mV) + + * bV2C_DACxB; + * + * Apparently, kV2C_DACxB = 1/kC2V_DACxB; + * bV2C_DACxB = -bC2V_DACxB/kC2V_DACxB; + */ +typedef struct { + /* Code to voltage equation parameters */ + float kC2V_DAC12B; /**< the k factor of code to voltage(in mV) transfer + function */ + float bC2V_DAC12B; /**< the offset of code to voltage transfer function. It's + the voltage in mV when code is zero. */ + float kC2V_DAC6B; /**< the k factor for LPDAC 6 bit output. */ + float bC2V_DAC6B; /**< the offset for LPDAC 6 bit output. */ + /* Code to voltage equation parameters */ + float kV2C_DAC12B; /**< the k factor for converting voltage to code for LPDAC + 12bit output. */ + float bV2C_DAC12B; /**< the offset for converting voltage to code for LPDAC + 12bit output. */ + float kV2C_DAC6B; /**< the k factor for converting voltage to code for LPDAC + 6bit output. */ + float bV2C_DAC6B; /**< the offset for converting voltage to code for LPDAC + 6bit output. */ +} LPDACPara_Type; + +/** + * LFOSC frequency measure structure + */ +typedef struct { + uint32_t CalSeqAddr; /**< Sequence start address */ + float CalDuration; /**< Time can be used for calibration in unit of ms. + Recommend to use tens of millisecond like 10ms */ + float SystemClkFreq; /**< System clock frequency. */ +} LFOSCMeasure_Type; + +/** + * ADC PGA calibration type + */ +typedef struct { + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + float VRef1p82; /**< The real voltage of 1.82 reference. Unit is volt. */ + float VRef1p11; /**< The real voltage of 1.1 reference. Unit is volt. */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCPga; /**< Which PGA gain we are going to calibrate? */ + uint32_t PGACalType; /**< Calibrate gain of offset or gain+offset? */ + int32_t TimeOut10us; /**< Timeout in 10us. -1 means no time-out*/ +} ADCPGACal_Type; + +/** + * LPTIA Offset calibration type + */ +typedef struct { + uint32_t LpAmpSel; /**< Select from LPAMP0 and LPAMP1. LPAMP1 is only + available on ADuCM355. */ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCPga; /**< PGA Gain selection */ + uint32_t DacData12Bit; /**< 12Bit DAC data */ + uint32_t DacData6Bit; /**< 6Bit DAC data */ + uint32_t LpDacVzeroMux; /**< Vzero is used as LPTIA bias voltage, select + 12Bit/6Bit DAC */ + uint32_t LpAmpPwrMod; /**< LP amplifiers power mode, select from + LPAMPPWR_NORM, LPAMPPWR_BOOSTn*/ + uint32_t LpTiaSW; /**< Switch configuration for LPTIA. Normally for SW(5) and + SW(9).*/ + uint32_t LpTiaRtia; /**< LPTIA RTIA resistor selection. */ + int32_t SettleTime10us; /**< Wait how much time after TIA is enabled? */ + int32_t TimeOut10us; /**< ADC converts signal need time. Specify the maximum + time allowed. Timeout in 10us. negative number means + wait no time. */ +} LPTIAOffsetCal_Type; + +/** + * Structure for calculating how much system clocks needed for specified number + * of data + */ +typedef struct { + uint32_t + DataType; /**< The final data output selection. @ref DATATYPE_Const */ + uint32_t DataCount; /**< How many data you want. */ + uint32_t ADCSinc3Osr; /**< ADC SINC3 filter OSR setting */ + uint32_t ADCSinc2Osr; /**< ADC SINC2 filter OSR setting */ + uint32_t ADCAvgNum; /**< Average number for DFT engine. Only used when data + type is DATATYPE_DFT and DftSrc is DFTSRC_AVG */ + uint32_t + DftSrc; /**< The DFT source. Only used when data type is DATATYPE_DFT */ + uint8_t ADCRate; /**< ADCRate @ref ADCRATE_Const. Only used when data type is + DATATYPE_NOTCH */ + BoolFlag BpNotch; /**< Bypass notch filter or not. Only used when data type is + DATATYPE_DFT and DftSrc is DFTSRC_SINC2NOTCH */ + float RatioSys2AdcClk; /**< Ratio of system clock to ADC clock frequency */ +} ClksCalInfo_Type; + +/** + * Software controlled Sweep Function + * */ +typedef struct { + BoolFlag SweepEn; /**< Software can automatically sweep frequency from + following parameters. Set value to 1 to enable it. */ + float SweepStart; /**< Sweep start frequency. Software will go back to the + start frequency when it reaches SWEEP_STOP */ + float SweepStop; /**< Sweep end frequency. */ + uint32_t SweepPoints; /**< How many points from START to STOP frequency */ + BoolFlag SweepLog; /**< The step is linear or logarithmic. 0: Linear, 1: + Logarithmic*/ + uint32_t SweepIndex; /**< Current position of sweep */ +} SoftSweepCfg_Type; + +/** + * Impedance result in Polar coordinate + */ +typedef struct { + float Magnitude; /**< The magnitude in polar coordinate */ + float Phase; /**< The phase in polar coordinate */ +} fImpPol_Type; // Polar + +/** + * Impedance result in Cartesian coordinate + */ +typedef struct { + float Real; /**< The real part in Cartesian coordinate */ + float Image; /**< The imaginary in Cartesian coordinate */ +} fImpCar_Type; // Cartesian + +/** + * int32_t type Impedance result in Cartesian coordinate + */ +typedef struct { + int32_t Real; /**< The real part in Cartesian coordinate */ + int32_t Image; /**< The real imaginary in Cartesian coordinate */ +} iImpCar_Type; + +/** + * FreqParams_Type - Structure to store optimum filter settings + */ +typedef struct { + BoolFlag HighPwrMode; + uint32_t DftNum; + uint32_t DftSrc; + uint32_t ADCSinc3Osr; + uint32_t ADCSinc2Osr; + uint32_t NumClks; +} FreqParams_Type; + +/** + * @} TypeDefinitions + */ + +/** + * @defgroup Exported_Functions + * @{ + */ +/* 1. Basic SPI functions */ +void AD5940_WriteReg(uint16_t RegAddr, uint32_t RegData); +uint32_t AD5940_ReadReg(uint16_t RegAddr); +void AD5940_FIFORd(uint32_t *pBuffer, uint32_t uiReadCount); + +/* 2. AD5940 Top Control functions */ +void AD5940_Initialize(void); /* Call this function firstly once AD5940 power on + or come from soft reset */ +void AD5940_AFECtrlS(uint32_t AfeCtrlSet, BoolFlag State); +AD5940Err AD5940_LPModeCtrlS(uint32_t EnSet); +void AD5940_AFEPwrBW( + uint32_t AfePwr, + uint32_t AfeBw); /* AFE power mode and system bandwidth control */ +void AD5940_REFCfgS(AFERefCfg_Type *pBufCfg); + +/* 3. High_Speed_Loop Functions */ +void AD5940_HSLoopCfgS(HSLoopCfg_Type *pHsLoopCfg); +void AD5940_SWMatrixCfgS(SWMatrixCfg_Type *pSwMatrix); +void AD5940_HSDacCfgS(HSDACCfg_Type *pHsDacCfg); +AD5940Err AD5940_HSTIACfgS(HSTIACfg_Type *pHsTiaCfg); +void AD5940_HSRTIACfgS(uint32_t HSTIARtia); +void __AD5940_SetDExRTIA(uint32_t DExPin, uint32_t DeRtia, uint32_t DeRload); + +/* 4. Low_Power_Loop Functions*/ +void AD5940_LPLoopCfgS(LPLoopCfg_Type *pLpLoopCfg); +void AD5940_LPDACCfgS(LPDACCfg_Type *pLpDacCfg); +// void AD5940_LPDACWriteS(uint16_t Data12Bit, uint8_t Data6Bit); +void AD5940_LPDAC0WriteS(uint16_t Data12Bit, uint8_t Data6Bit); +void AD5940_LPDAC1WriteS(uint16_t Data12Bit, uint8_t Data6Bit); +void AD5940_LPAMPCfgS(LPAmpCfg_Type *pLpAmpCfg); + +/* 5. DSP_Block_Functions */ +void AD5940_DSPCfgS(DSPCfg_Type *pDSPCfg); +uint32_t AD5940_ReadAfeResult(uint32_t AfeResultSel); +/* 5.1 ADC Block */ +void AD5940_ADCBaseCfgS(ADCBaseCfg_Type *pADCInit); +void AD5940_ADCFilterCfgS(ADCFilterCfg_Type *pFiltCfg); +void AD5940_ADCPowerCtrlS(BoolFlag State); +void AD5940_ADCConvtCtrlS(BoolFlag State); +void AD5940_ADCMuxCfgS(uint32_t ADCMuxP, uint32_t ADCMuxN); +void AD5940_ADCDigCompCfgS(ADCDigComp_Type *pCompCfg); +void AD5940_StatisticCfgS(StatCfg_Type *pStatCfg); +void AD5940_ADCRepeatCfgS(uint32_t Number); +void AD5940_DFTCfgS(DFTCfg_Type *pDftCfg); +/* 5.2 Waveform Generator Block */ +void AD5940_WGCfgS(WGCfg_Type *pWGInit); +AD5940Err AD5940_WGDACCodeS(uint32_t code); /* Directly write DAC Code */ +void AD5940_WGFreqCtrlS(float SinFreqHz, float WGClock); +uint32_t AD5940_WGFreqWordCal(float SinFreqHz, float WGClock); +// uint32_t AD5940_WGAmpWordCal(float Amp, BoolFlag DacGain, BoolFlag +// ExcitGain); + +/* 6. Sequencer_FIFO */ +void AD5940_FIFOCfg(FIFOCfg_Type *pFifoCfg); +AD5940Err +AD5940_FIFOGetCfg(FIFOCfg_Type *pFifoCfg); /* Read back current configuration */ +void AD5940_FIFOCtrlS( + uint32_t FifoSrc, + BoolFlag FifoEn); /* Configure FIFO data source. And disable/enable it.*/ +void AD5940_FIFOThrshSet(uint32_t FIFOThresh); +uint32_t AD5940_FIFOGetCnt(void); /* Get current FIFO count */ +void AD5940_SEQCfg(SEQCfg_Type *pSeqCfg); +AD5940Err +AD5940_SEQGetCfg(SEQCfg_Type *pSeqCfg); /* Read back current configuration */ +void AD5940_SEQCtrlS(BoolFlag SeqEn); +void AD5940_SEQHaltS(void); +void AD5940_SEQMmrTrig(uint32_t SeqId); /* Manually trigger sequence */ +void AD5940_SEQCmdWrite(uint32_t StartAddr, const uint32_t *pCommand, + uint32_t CmdCnt); +void AD5940_SEQInfoCfg(SEQInfo_Type *pSeq); +AD5940Err AD5940_SEQInfoGet(uint32_t SeqId, SEQInfo_Type *pSeqInfo); +void AD5940_SEQGpioCtrlS( + uint32_t GpioSet); /* Sequencer can control GPIO0~7 if the GPIO function is + set to SYNC */ +uint32_t +AD5940_SEQTimeOutRd(void); /* Read back current sequence time out value */ +AD5940Err AD5940_SEQGpioTrigCfg(SeqGpioTrig_Cfg *pSeqGpioTrigCfg); +void AD5940_WUPTCfg(WUPTCfg_Type *pWuptCfg); +void AD5940_WUPTCtrl(BoolFlag Enable); /* Enable or disable Wakeup timer */ +AD5940Err AD5940_WUPTTime(uint32_t SeqId, uint32_t SleepTime, + uint32_t WakeupTime); + +/* 7. MISC_Block */ +/* 7.1 Clock system */ +void AD5940_CLKCfg(CLKCfg_Type *pClkCfg); +void AD5940_HFOSC32MHzCtrl(BoolFlag Mode32MHz); +void AD5940_HPModeEn(BoolFlag Enable); /* Switch system clocks to high power + mode for EIS >80kHz)*/ +/* 7.2 AFE Interrupt */ +void AD5940_INTCCfg(uint32_t AfeIntcSel, uint32_t AFEIntSrc, BoolFlag State); +uint32_t AD5940_INTCGetCfg(uint32_t AfeIntcSel); +void AD5940_INTCClrFlag(uint32_t AfeIntSrcSel); +BoolFlag AD5940_INTCTestFlag( + uint32_t AfeIntcSel, + uint32_t AfeIntSrcSel); /* Check if selected interrupt happened */ +uint32_t +AD5940_INTCGetFlag(uint32_t AfeIntcSel); /* Get current INTC interrupt flag */ +/* 7.3 GPIO */ +void AD5940_AGPIOCfg(AGPIOCfg_Type *pAgpioCfg); +void AD5940_AGPIOFuncCfg(uint32_t uiCfgSet); +void AD5940_AGPIOOen(uint32_t uiPinSet); +void AD5940_AGPIOIen(uint32_t uiPinSet); +uint32_t AD5940_AGPIOIn(void); +void AD5940_AGPIOPen(uint32_t uiPinSet); +void AD5940_AGPIOSet(uint32_t uiPinSet); +void AD5940_AGPIOClr(uint32_t uiPinSet); +void AD5940_AGPIOToggle(uint32_t uiPinSet); + +/* 7.4 LPMODE */ +AD5940Err +AD5940_LPModeEnS(BoolFlag LPModeEn); /* Enable LP mode or disable it. */ +void AD5940_LPModeClkS(uint32_t LPModeClk); +void AD5940_ADCRepeatCfg(uint32_t Number); +/* 7.5 Power */ +void AD5940_SleepKeyCtrlS(uint32_t SlpKey); /* enter the correct key to allow + AFE to enter sleep mode */ +void AD5940_EnterSleepS(void); /* Put AFE to hibernate/sleep mode and keep LP + loop as the default settings. */ +void AD5940_ShutDownS( + void); /* Unlock the key, turn off LP loop and enter sleep/hibernate mode */ +uint32_t +AD5940_WakeUp(int32_t TryCount); /* Try to wakeup AFE by read register */ +uint32_t AD5940_GetADIID(void); /* Read ADIID */ +uint32_t AD5940_GetChipID(void); /* Read Chip ID */ +AD5940Err AD5940_SoftRst(void); +void AD5940_HWReset(void); /* Do hardware reset to AD5940 using RESET pin */ +/* Calibration functions */ +/* 8. Calibration */ +AD5940Err AD5940_ADCPGACal(ADCPGACal_Type *ADCPGACal); +AD5940Err AD5940_LPDACCal(LPDACCal_Type *pCalCfg, LPDACPara_Type *pResult); +AD5940Err AD5940_LPTIAOffsetCal(LPTIAOffsetCal_Type *pLPTIAOffsetCal); +AD5940Err AD5940_HSRtiaCal(HSRTIACal_Type *pCalCfg, void *pResult); +AD5940Err AD5940_HSDACCal(HSDACCal_Type *pCalCfg); +AD5940Err AD5940_LPRtiaCal(LPRTIACal_Type *pCalCfg, void *pResult); +AD5940Err AD5940_LFOSCMeasure(LFOSCMeasure_Type *pCfg, float *pFreq); +// void AD5940_LFOSCTrim(uint32_t TrimValue); /* TrimValue: 0 to 15 */ +// void AD5940_HFOSC16MHzTrim(uint32_t TrimValue); +// void AD5940_HFOSC32MHzTrim(uint32_t TrimValue); + +/* 9. Pure software functions. Functions with no register access. These + * functions are helpers */ +/* Sequence Generator */ +void AD5940_SEQGenInit( + uint32_t *pBuffer, + uint32_t BufferSize); /* Initialize sequence generator workspace */ +void AD5940_SEQGenCtrl( + BoolFlag bFlag); /* Enable or disable sequence generator */ +void AD5940_SEQGenInsert( + uint32_t CmdWord); /* Manually insert a sequence command */ +AD5940Err AD5940_SEQGenFetchSeq( + const uint32_t **ppSeqCmd, + uint32_t + *pSeqCount); /* Fetch generated sequence and start a new sequence */ +void AD5940_ClksCalculate(ClksCalInfo_Type *pFilterInfo, uint32_t *pClocks); +uint32_t AD5940_SEQCycleTime(void); +void AD5940_SweepNext(SoftSweepCfg_Type *pSweepCfg, float *pNextFreq); +void AD5940_StructInit(void *pStruct, uint32_t StructSize); +float AD5940_ADCCode2Volt(uint32_t code, uint32_t ADCPga, + float VRef1p82); /* Calculate ADC code to voltage */ +BoolFlag AD5940_Notch50HzAvailable(ADCFilterCfg_Type *pFilterInfo, uint8_t *dl); +BoolFlag AD5940_Notch60HzAvailable(ADCFilterCfg_Type *pFilterInfo, uint8_t *dl); +fImpCar_Type AD5940_ComplexDivFloat(fImpCar_Type *a, fImpCar_Type *b); +fImpCar_Type AD5940_ComplexMulFloat(fImpCar_Type *a, fImpCar_Type *b); +fImpCar_Type AD5940_ComplexAddFloat(fImpCar_Type *a, fImpCar_Type *b); +fImpCar_Type AD5940_ComplexSubFloat(fImpCar_Type *a, fImpCar_Type *b); + +fImpCar_Type AD5940_ComplexDivInt(iImpCar_Type *a, iImpCar_Type *b); +fImpCar_Type AD5940_ComplexMulInt(iImpCar_Type *a, iImpCar_Type *b); +float AD5940_ComplexMag(fImpCar_Type *a); +float AD5940_ComplexPhase(fImpCar_Type *a); +FreqParams_Type AD5940_GetFreqParameters(float freq); +/** + * @} Exported_Functions + */ + +/** + * @defgroup Library_Interface + * The functions user should provide for specific MCU platform + * @{ + */ +void AD5940_CsClr(void); +void AD5940_CsSet(void); +void AD5940_RstClr(void); +void AD5940_RstSet(void); +void AD5940_Delay10us(uint32_t time); +/* (Not used for now.)AD5940 has 8 GPIOs, some of them are connected to MCU. MCU + * can set or read the status of these pins. */ +void AD5940_MCUGpioWrite(uint32_t data); /* */ +uint32_t AD5940_MCUGpioRead(uint32_t); +void AD5940_MCUGpioCtrl(uint32_t, BoolFlag); +void AD5940_ReadWriteNBytes(unsigned char *pSendBuffer, + unsigned char *pRecvBuff, unsigned long length); +/* Below functions are frequently used in example code but not necessary for + * library */ +uint32_t AD5940_GetMCUIntFlag(void); +uint32_t AD5940_ClrMCUIntFlag(void); +uint32_t AD5940_MCUResourceInit(void *pCfg); +/** + * @} Library_Interface + */ + +/** + * @} AD5940_Library + */ + +#endif diff --git a/examples/rp2040_port/AD5940_Platform.c b/examples/rp2040_port/AD5940_Platform.c new file mode 100644 index 0000000..a188c16 --- /dev/null +++ b/examples/rp2040_port/AD5940_Platform.c @@ -0,0 +1,158 @@ +// File: AD5940_Platform.c +#include "App_Common.h" +#include "rp2040port.h" + +// --- Platform Interface Implementation --- +// NOTE: Low-level hardware interface functions are now in rp2040port.c + +int32_t AD5940PlatformCfg(void) { + CLKCfg_Type clk_cfg; + FIFOCfg_Type fifo_cfg; + AGPIOCfg_Type gpio_cfg; + + clk_cfg.ADCClkDiv = ADCCLKDIV_1; + clk_cfg.ADCCLkSrc = ADCCLKSRC_HFOSC; + clk_cfg.SysClkDiv = SYSCLKDIV_1; + clk_cfg.SysClkSrc = SYSCLKSRC_HFOSC; + clk_cfg.HfOSC32MHzMode = bFALSE; + clk_cfg.HFOSCEn = bTRUE; + clk_cfg.HFXTALEn = bFALSE; + clk_cfg.LFOSCEn = bTRUE; + AD5940_CLKCfg(&clk_cfg); + + fifo_cfg.FIFOEn = bFALSE; + fifo_cfg.FIFOMode = FIFOMODE_FIFO; + fifo_cfg.FIFOSize = FIFOSIZE_4KB; + fifo_cfg.FIFOSrc = FIFOSRC_DFT; + fifo_cfg.FIFOThresh = 6; + AD5940_FIFOCfg(&fifo_cfg); + fifo_cfg.FIFOEn = bTRUE; + AD5940_FIFOCfg(&fifo_cfg); + + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_ALLINT, bTRUE); + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + AD5940_INTCCfg(AFEINTC_0, AFEINTSRC_DATAFIFOTHRESH | AFEINTSRC_CUSTOMINT0, + bTRUE); + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + + gpio_cfg.FuncSet = GP0_INT; + gpio_cfg.InputEnSet = 0; + gpio_cfg.OutputEnSet = AGPIO_Pin0; + gpio_cfg.OutVal = 0; + gpio_cfg.PullEnSet = 0; + AD5940_AGPIOCfg(&gpio_cfg); + + AD5940_SleepKeyCtrlS(SLPKEY_UNLOCK); + return 0; +} + +void SystemReset(void) { + sleep_ms(100); + AD5940_SoftRst(); + sleep_ms(1); + AD5940_Initialize(); + AD5940PlatformCfg(); +} + +// --- Helpers --- +uint32_t GetHSTIARtia(uint32_t val) { + switch (val) { + case 100: + return HSTIARTIA_200; // Map 100 request to 200 Internal + case 200: + return HSTIARTIA_200; + case 1000: + return HSTIARTIA_1K; + case 5000: + return HSTIARTIA_5K; + case 10000: + return HSTIARTIA_10K; + case 20000: + return HSTIARTIA_20K; + case 40000: + return HSTIARTIA_40K; + case 80000: + return HSTIARTIA_80K; + case 160000: + return HSTIARTIA_160K; + default: + return HSTIARTIA_1K; + } +} + +uint32_t GetLPTIARtia(uint32_t val) { + switch (val) { + case 200: + return LPTIARTIA_200R; + case 1000: + return LPTIARTIA_1K; + case 2000: + return LPTIARTIA_2K; + case 3000: + return LPTIARTIA_3K; + case 4000: + return LPTIARTIA_4K; + case 6000: + return LPTIARTIA_6K; + case 8000: + return LPTIARTIA_8K; + case 10000: + return LPTIARTIA_10K; + case 12000: + return LPTIARTIA_12K; + case 16000: + return LPTIARTIA_16K; + case 20000: + return LPTIARTIA_20K; + case 24000: + return LPTIARTIA_24K; + case 30000: + return LPTIARTIA_30K; + case 32000: + return LPTIARTIA_32K; + case 40000: + return LPTIARTIA_40K; + case 48000: + return LPTIARTIA_48K; + case 64000: + return LPTIARTIA_64K; + case 85000: + return LPTIARTIA_85K; + case 96000: + return LPTIARTIA_96K; + case 100000: + return LPTIARTIA_100K; + case 120000: + return LPTIARTIA_120K; + case 128000: + return LPTIARTIA_128K; + case 160000: + return LPTIARTIA_160K; + case 196000: + return LPTIARTIA_196K; + case 256000: + return LPTIARTIA_256K; + case 512000: + return LPTIARTIA_512K; + default: + return LPTIARTIA_1K; + } +} + +uint32_t GetLPTIARload(uint32_t val) { + if (val <= 200) + return LPTIARLOAD_10R; + return LPTIARLOAD_100R; +} + +void AmperometricShowResult(float *pData, uint32_t DataCount) { + for (int i = 0; i < DataCount; i++) { + printf("AMP,%d,%.4f\n", g_AmpIndex++, pData[i]); + } +} + +void RampShowResult(float *pData, uint32_t DataCount) { + for (int i = 0; i < DataCount; i++) { + printf("RAMP,%d,%.4f\n", g_RampIndex++, pData[i]); + } +} \ No newline at end of file diff --git a/examples/rp2040_port/Amperometric.c b/examples/rp2040_port/Amperometric.c new file mode 100644 index 0000000..c98dca8 --- /dev/null +++ b/examples/rp2040_port/Amperometric.c @@ -0,0 +1,486 @@ +// File: Amperometric.c +#include "Amperometric.h" + +#define AD5940ERR_STOP 10 + +/* + Application configuration structure. Specified by user from template. + The variables are usable in this whole application. + It includes basic configuration for sequencer generator and application related parameters +*/ +AppAMPCfg_Type AppAMPCfg = +{ + .bParaChanged = bFALSE, + .SeqStartAddr = 0, + .MaxSeqLen = 0, + + .SeqStartAddrCal = 0, + .MaxSeqLenCal = 0, + .FifoThresh = 5, /* Number of points for FIFO */ + + .SysClkFreq = 16000000.0, + .WuptClkFreq = 32000.0, + .AdcClkFreq = 16000000.0, + .AmpODR = 1.0, /* Sample time in seconds. I.e. every 5 seconds make a measurement */ + .NumOfData = -1, + .RcalVal = 100.0, /* RCAL = 100 Ohms */ + .PwrMod = AFEPWR_LP, + .AMPInited = bFALSE, + .StopRequired = bFALSE, + + /* LPTIA Configure */ + .ExtRtia = bFALSE, /* Set to true if using external RTIA */ + .LptiaRtiaSel = LPTIARTIA_4K, /* COnfigure RTIA */ + .LpTiaRf = LPTIARF_1M, /* Configure LPF resistor */ + .LpTiaRl = LPTIARLOAD_100R, + .ReDoRtiaCal = bTRUE, + .RtiaCalValue = 0, + .ExtRtiaVal = 0, + +/*LPDAC Configure */ + .Vzero = 1100, /* Sets voltage on SE0 and LPTIA */ + .SensorBias = 500, /* Sets voltage between RE0 and SE0 */ + +/* ADC Configure*/ + .ADCPgaGain = ADCPGA_1P5, + .ADCSinc3Osr = ADCSINC3OSR_4, + .ADCSinc2Osr = ADCSINC2OSR_22, + .DataFifoSrc = FIFOSRC_SINC2NOTCH, + .ADCRefVolt = 1.8162, /* Measure voltage on ADCRefVolt pin and enter here*/ + .ShortRe0Se0 = bFALSE, +}; + +/** + This function is provided for upper controllers that want to change + application parameters specially for user defined parameters. +*/ +AD5940Err AppAMPGetCfg(void *pCfg) +{ + if(pCfg){ + *(AppAMPCfg_Type**)pCfg = &AppAMPCfg; + return AD5940ERR_OK; + } + return AD5940ERR_PARA; +} + +AD5940Err AppAMPCtrl(int32_t AmpCtrl, void *pPara) +{ + switch (AmpCtrl) + { + case AMPCTRL_START: + { + WUPTCfg_Type wupt_cfg; + + AD5940_ReadReg(REG_AFE_ADCDAT); /* Any SPI Operation can wakeup AFE */ + if(AppAMPCfg.AMPInited == bFALSE) + return AD5940ERR_APPERROR; + /* Start it */ + wupt_cfg.WuptEn = bTRUE; + wupt_cfg.WuptEndSeq = WUPTENDSEQ_A; + wupt_cfg.WuptOrder[0] = SEQID_0; + wupt_cfg.SeqxSleepTime[SEQID_0] = 4-1; + wupt_cfg.SeqxWakeupTime[SEQID_0] = (uint32_t)(AppAMPCfg.WuptClkFreq*AppAMPCfg.AmpODR)-4-1; + AD5940_WUPTCfg(&wupt_cfg); + + AppAMPCfg.FifoDataCount = 0; /* restart */ + break; + } + case AMPCTRL_STOPNOW: + { + AD5940_ReadReg(REG_AFE_ADCDAT); /* Any SPI Operation can wakeup AFE */ + /* Start Wupt right now */ + AD5940_WUPTCtrl(bFALSE); + /* There is chance this operation will fail because sequencer could put AFE back + to hibernate mode just after waking up. Use STOPSYNC is better. */ + AD5940_WUPTCtrl(bFALSE); + break; + } + case AMPCTRL_STOPSYNC: + { + AppAMPCfg.StopRequired = bTRUE; + break; + } + case AMPCTRL_SHUTDOWN: + { + AppAMPCtrl(AMPCTRL_STOPNOW, 0); /* Stop the measurement if it's running. */ + /* Turn off LPloop related blocks which are not controlled automatically by sleep operation */ + AFERefCfg_Type aferef_cfg; + LPLoopCfg_Type lp_loop; + memset(&aferef_cfg, 0, sizeof(aferef_cfg)); + AD5940_REFCfgS(&aferef_cfg); + memset(&lp_loop, 0, sizeof(lp_loop)); + AD5940_LPLoopCfgS(&lp_loop); + AD5940_EnterSleepS(); /* Enter Hibernate */ + } + break; + default: + break; + } + return AD5940ERR_OK; +} + +/* Generate init sequence */ +static AD5940Err AppAMPSeqCfgGen(void) +{ + AD5940Err error = AD5940ERR_OK; + uint32_t const *pSeqCmd; + uint32_t SeqLen; + + AFERefCfg_Type aferef_cfg; + LPLoopCfg_Type lp_loop; + DSPCfg_Type dsp_cfg; + SWMatrixCfg_Type sw_cfg; + /* Start sequence generator here */ + AD5940_SEQGenCtrl(bTRUE); + + //AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Init all to disable state */ + + aferef_cfg.HpBandgapEn = bTRUE; + aferef_cfg.Hp1V1BuffEn = bTRUE; + aferef_cfg.Hp1V8BuffEn = bTRUE; + aferef_cfg.Disc1V1Cap = bFALSE; + aferef_cfg.Disc1V8Cap = bFALSE; + aferef_cfg.Hp1V8ThemBuff = bFALSE; + aferef_cfg.Hp1V8Ilimit = bFALSE; + aferef_cfg.Lp1V1BuffEn = bTRUE; + aferef_cfg.Lp1V8BuffEn = bTRUE; + /* LP reference control - turn off them to save power*/ + aferef_cfg.LpBandgapEn = bTRUE; + aferef_cfg.LpRefBufEn = bTRUE; + aferef_cfg.LpRefBoostEn = bFALSE; + AD5940_REFCfgS(&aferef_cfg); + + lp_loop.LpDacCfg.LpdacSel = LPDAC0; + lp_loop.LpDacCfg.LpDacSrc = LPDACSRC_MMR; + lp_loop.LpDacCfg.LpDacSW = LPDACSW_VBIAS2LPPA|LPDACSW_VBIAS2PIN|LPDACSW_VZERO2LPTIA|LPDACSW_VZERO2PIN; + lp_loop.LpDacCfg.LpDacVzeroMux = LPDACVZERO_6BIT; + lp_loop.LpDacCfg.LpDacVbiasMux = LPDACVBIAS_12BIT; + lp_loop.LpDacCfg.LpDacRef = LPDACREF_2P5; + lp_loop.LpDacCfg.DataRst = bFALSE; + lp_loop.LpDacCfg.PowerEn = bTRUE; + lp_loop.LpDacCfg.DacData6Bit = (uint32_t)((AppAMPCfg.Vzero-200)/DAC6BITVOLT_1LSB); + lp_loop.LpDacCfg.DacData12Bit =(int32_t)((AppAMPCfg.SensorBias)/DAC12BITVOLT_1LSB) + lp_loop.LpDacCfg.DacData6Bit*64; + if(lp_loop.LpDacCfg.DacData12Bit>lp_loop.LpDacCfg.DacData6Bit*64) + lp_loop.LpDacCfg.DacData12Bit--; + lp_loop.LpAmpCfg.LpAmpSel = LPAMP0; + lp_loop.LpAmpCfg.LpAmpPwrMod = LPAMPPWR_NORM; + lp_loop.LpAmpCfg.LpPaPwrEn = bTRUE; + lp_loop.LpAmpCfg.LpTiaPwrEn = bTRUE; + lp_loop.LpAmpCfg.LpTiaRf = AppAMPCfg.LpTiaRf; + lp_loop.LpAmpCfg.LpTiaRload = AppAMPCfg.LpTiaRl; + if(AppAMPCfg.ExtRtia == bTRUE) + { + lp_loop.LpAmpCfg.LpTiaRtia = LPTIARTIA_OPEN; + lp_loop.LpAmpCfg.LpTiaSW = LPTIASW(9)|LPTIASW(2)|LPTIASW(4)|LPTIASW(5)|LPTIASW(12)|LPTIASW(13); + }else + { + lp_loop.LpAmpCfg.LpTiaRtia = AppAMPCfg.LptiaRtiaSel; + lp_loop.LpAmpCfg.LpTiaSW = LPTIASW(5)|LPTIASW(2)|LPTIASW(4)|LPTIASW(12)|LPTIASW(13); + } + + // Apply Short Option + if(AppAMPCfg.ShortRe0Se0) { + lp_loop.LpAmpCfg.LpTiaSW |= LPTIASW(11); + } + + AD5940_LPLoopCfgS(&lp_loop); + + + dsp_cfg.ADCBaseCfg.ADCMuxN = ADCMUXN_VZERO0; + dsp_cfg.ADCBaseCfg.ADCMuxP = ADCMUXP_AIN4; + dsp_cfg.ADCBaseCfg.ADCPga = AppAMPCfg.ADCPgaGain; + + memset(&dsp_cfg.ADCDigCompCfg, 0, sizeof(dsp_cfg.ADCDigCompCfg)); + memset(&dsp_cfg.DftCfg, 0, sizeof(dsp_cfg.DftCfg)); + dsp_cfg.ADCFilterCfg.ADCAvgNum = ADCAVGNUM_16; /* Don't care because it's disabled */ + dsp_cfg.ADCFilterCfg.ADCRate = ADCRATE_800KHZ; /* Tell filter block clock rate of ADC*/ + dsp_cfg.ADCFilterCfg.ADCSinc2Osr = AppAMPCfg.ADCSinc2Osr; + dsp_cfg.ADCFilterCfg.ADCSinc3Osr = AppAMPCfg.ADCSinc3Osr; + dsp_cfg.ADCFilterCfg.BpSinc3 = bFALSE; + dsp_cfg.ADCFilterCfg.BpNotch = bFALSE; + dsp_cfg.ADCFilterCfg.Sinc2NotchEnable = bTRUE; + + memset(&dsp_cfg.StatCfg, 0, sizeof(dsp_cfg.StatCfg)); /* Don't care about Statistic */ + AD5940_DSPCfgS(&dsp_cfg); + + sw_cfg.Dswitch = 0; + sw_cfg.Pswitch = 0; + sw_cfg.Nswitch = 0; + sw_cfg.Tswitch = 0; + AD5940_SWMatrixCfgS(&sw_cfg); + + /* Enable all of them. They are automatically turned off during hibernate mode to save power */ + AD5940_AFECtrlS(AFECTRL_HPREFPWR|AFECTRL_SINC2NOTCH, bTRUE); + AD5940_AFECtrlS(AFECTRL_SINC2NOTCH, bFALSE); + AD5940_SEQGpioCtrlS(0/*AGPIO_Pin6|AGPIO_Pin5|AGPIO_Pin1*/); //GP6->endSeq, GP5 -> AD8233=OFF, GP1->RLD=OFF . + + /* Sequence end. */ + AD5940_SEQGenInsert(SEQ_STOP()); /* Add one extra command to disable sequencer for initialization sequence because we only want it to run one time. */ + + /* Stop here */ + error = AD5940_SEQGenFetchSeq(&pSeqCmd, &SeqLen); + AD5940_SEQGenCtrl(bFALSE); /* Stop sequencer generator */ + if(error == AD5940ERR_OK) + { + AppAMPCfg.InitSeqInfo.SeqId = SEQID_1; + AppAMPCfg.InitSeqInfo.SeqRamAddr = AppAMPCfg.SeqStartAddr; + AppAMPCfg.InitSeqInfo.pSeqCmd = pSeqCmd; + AppAMPCfg.InitSeqInfo.SeqLen = SeqLen; + /* Write command to SRAM */ + AD5940_SEQCmdWrite(AppAMPCfg.InitSeqInfo.SeqRamAddr, pSeqCmd, SeqLen); + } + else + return error; /* Error */ + return AD5940ERR_OK; +} + +static AD5940Err AppAMPSeqMeasureGen(void) +{ + AD5940Err error = AD5940ERR_OK; + uint32_t const *pSeqCmd; + uint32_t SeqLen; + + uint32_t WaitClks; + ClksCalInfo_Type clks_cal; + + clks_cal.DataType = DATATYPE_SINC2; + clks_cal.DataCount = 1; + clks_cal.ADCSinc2Osr = AppAMPCfg.ADCSinc2Osr; + clks_cal.ADCSinc3Osr = AppAMPCfg.ADCSinc3Osr; + clks_cal.ADCAvgNum = 0; + clks_cal.RatioSys2AdcClk = AppAMPCfg.SysClkFreq/AppAMPCfg.AdcClkFreq; + AD5940_ClksCalculate(&clks_cal, &WaitClks); + WaitClks += 15; + AD5940_SEQGenCtrl(bTRUE); + AD5940_SEQGpioCtrlS(AGPIO_Pin2); + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_SINC2NOTCH, bTRUE); + AD5940_SEQGenInsert(SEQ_WAIT(16*250)); /* wait 250us */ + AD5940_AFECtrlS(AFECTRL_ADCCNV, bTRUE); /* Start ADC convert*/ + AD5940_SEQGenInsert(SEQ_WAIT(WaitClks)); /* wait for first data ready */ + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_ADCCNV|AFECTRL_SINC2NOTCH, bFALSE); /* Stop ADC */ + AD5940_SEQGpioCtrlS(0); + AD5940_EnterSleepS();/* Goto hibernate */ + /* Sequence end. */ + error = AD5940_SEQGenFetchSeq(&pSeqCmd, &SeqLen); + AD5940_SEQGenCtrl(bFALSE); /* Stop sequencer generator */ + + if(error == AD5940ERR_OK) + { + AppAMPCfg.MeasureSeqInfo.SeqId = SEQID_0; + AppAMPCfg.MeasureSeqInfo.SeqRamAddr = AppAMPCfg.InitSeqInfo.SeqRamAddr + AppAMPCfg.InitSeqInfo.SeqLen ; + AppAMPCfg.MeasureSeqInfo.pSeqCmd = pSeqCmd; + AppAMPCfg.MeasureSeqInfo.SeqLen = SeqLen; + /* Write command to SRAM */ + AD5940_SEQCmdWrite(AppAMPCfg.MeasureSeqInfo.SeqRamAddr, pSeqCmd, SeqLen); + } + else + return error; /* Error */ + return AD5940ERR_OK; +} +static AD5940Err AppAMPRtiaCal(void) +{ +fImpPol_Type RtiaCalValue; /* Calibration result */ + LPRTIACal_Type lprtia_cal; + AD5940_StructInit(&lprtia_cal, sizeof(lprtia_cal)); + + lprtia_cal.bPolarResult = bTRUE; /* Magnitude + Phase */ + lprtia_cal.AdcClkFreq = AppAMPCfg.AdcClkFreq; + lprtia_cal.SysClkFreq = AppAMPCfg.SysClkFreq; + lprtia_cal.ADCSinc3Osr = ADCSINC3OSR_4; + lprtia_cal.ADCSinc2Osr = ADCSINC2OSR_22; /* Use SINC2 data as DFT data source */ + lprtia_cal.DftCfg.DftNum = DFTNUM_2048; /* Maximum DFT number */ + lprtia_cal.DftCfg.DftSrc = DFTSRC_SINC2NOTCH; /* For frequency under 12Hz, need to optimize DFT source. Use SINC3 data as DFT source */ + lprtia_cal.DftCfg.HanWinEn = bTRUE; + lprtia_cal.fFreq = AppAMPCfg.AdcClkFreq/4/22/2048*3; /* Sample 3 period of signal, 13.317Hz here. Do not use DC method, because it needs ADC/PGA calibrated firstly(but it's faster) */ + lprtia_cal.fRcal = AppAMPCfg.RcalVal; + lprtia_cal.LpTiaRtia = AppAMPCfg.LptiaRtiaSel; + lprtia_cal.LpAmpPwrMod = LPAMPPWR_NORM; + lprtia_cal.bWithCtia = bFALSE; + AD5940_LPRtiaCal(&lprtia_cal, &RtiaCalValue); + AppAMPCfg.RtiaCalValue = RtiaCalValue; + + return AD5940ERR_OK; +} +/* This function provide application initialize. */ +AD5940Err AppAMPInit(uint32_t *pBuffer, uint32_t BufferSize) +{ + AD5940Err error = AD5940ERR_OK; + SEQCfg_Type seq_cfg; + FIFOCfg_Type fifo_cfg; + + if(AD5940_WakeUp(10) > 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + + /* Configure sequencer and stop it */ + seq_cfg.SeqMemSize = SEQMEMSIZE_2KB; /* 2kB SRAM is used for sequencer, others for data FIFO */ + seq_cfg.SeqBreakEn = bFALSE; + seq_cfg.SeqIgnoreEn = bFALSE; + seq_cfg.SeqCntCRCClr = bTRUE; + seq_cfg.SeqEnable = bFALSE; + seq_cfg.SeqWrTimer = 0; + AD5940_SEQCfg(&seq_cfg); + + /* Do RTIA calibration */ + if(((AppAMPCfg.ReDoRtiaCal == bTRUE) || \ + AppAMPCfg.AMPInited == bFALSE) && AppAMPCfg.ExtRtia == bFALSE) /* Do calibration on the first initializaion */ + { + AppAMPRtiaCal(); + AppAMPCfg.ReDoRtiaCal = bFALSE; + }else + AppAMPCfg.RtiaCalValue.Magnitude = AppAMPCfg.ExtRtiaVal; + + /* Reconfigure FIFO */ + AD5940_FIFOCtrlS(DFTSRC_SINC3, bFALSE); /* Disable FIFO firstly */ + fifo_cfg.FIFOEn = bTRUE; + fifo_cfg.FIFOMode = FIFOMODE_FIFO; + fifo_cfg.FIFOSize = FIFOSIZE_4KB; /* 4kB for FIFO, The reset 2kB for sequencer */ + fifo_cfg.FIFOSrc = AppAMPCfg.DataFifoSrc; + fifo_cfg.FIFOThresh = AppAMPCfg.FifoThresh; + AD5940_FIFOCfg(&fifo_cfg); + + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + + /* Start sequence generator */ + /* Initialize sequencer generator */ + if((AppAMPCfg.AMPInited == bFALSE)||\ + (AppAMPCfg.bParaChanged == bTRUE)) + { + if(pBuffer == 0) return AD5940ERR_PARA; + if(BufferSize == 0) return AD5940ERR_PARA; + AD5940_SEQGenInit(pBuffer, BufferSize); + + /* Generate initialize sequence */ + error = AppAMPSeqCfgGen(); /* Application initialization sequence using either MCU or sequencer */ + if(error != AD5940ERR_OK) return error; + + /* Generate measurement sequence */ + error = AppAMPSeqMeasureGen(); + if(error != AD5940ERR_OK) return error; + + AppAMPCfg.bParaChanged = bFALSE; /* Clear this flag as we already implemented the new configuration */ + } + /* Initialization sequencer */ + AppAMPCfg.InitSeqInfo.WriteSRAM = bFALSE; + AD5940_SEQInfoCfg(&AppAMPCfg.InitSeqInfo); + seq_cfg.SeqEnable = bTRUE; + AD5940_SEQCfg(&seq_cfg); /* Enable sequencer */ + AD5940_SEQMmrTrig(AppAMPCfg.InitSeqInfo.SeqId); + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_ENDSEQ) == bFALSE); + + /* Measurement sequence */ + AppAMPCfg.MeasureSeqInfo.WriteSRAM = bFALSE; + AD5940_SEQInfoCfg(&AppAMPCfg.MeasureSeqInfo); + +// seq_cfg.SeqEnable = bTRUE; +// AD5940_SEQCfg(&seq_cfg); /* Enable sequencer, and wait for trigger */ + AD5940_SEQCtrlS(bTRUE); /* Enable sequencer, and wait for trigger. It's disabled in initialization sequence */ + AD5940_ClrMCUIntFlag(); /* Clear interrupt flag generated before */ + + AD5940_AFEPwrBW(AppAMPCfg.PwrMod, AFEBW_250KHZ); + AppAMPCfg.AMPInited = bTRUE; /* AMP application has been initialized. */ + return AD5940ERR_OK; +} + +/* Modify registers when AFE wakeup */ +static AD5940Err AppAMPRegModify(int32_t * const pData, uint32_t *pDataCount) +{ + if(AppAMPCfg.NumOfData > 0) + { + AppAMPCfg.FifoDataCount += *pDataCount/4; + if(AppAMPCfg.FifoDataCount >= AppAMPCfg.NumOfData) + { + AD5940_WUPTCtrl(bFALSE); + return AD5940ERR_STOP; // Return STOP code + } + } + if(AppAMPCfg.StopRequired == bTRUE) + { + AD5940_WUPTCtrl(bFALSE); + return AD5940ERR_OK; + } + + return AD5940ERR_OK; +} + +/* Depending on the data type, do appropriate data pre-process before return back to controller */ +static AD5940Err AppAMPDataProcess(int32_t * const pData, uint32_t *pDataCount) +{ + uint32_t i, datacount; + datacount = *pDataCount; + float *pOut = (float *)pData; + for(i=0;i 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + AD5940_SleepKeyCtrlS(SLPKEY_LOCK); + + *pCount = 0; + if(AD5940_INTCTestFlag(AFEINTC_0, AFEINTSRC_DATAFIFOTHRESH) == bTRUE) + { + FifoCnt = AD5940_FIFOGetCnt(); + AD5940_FIFORd((uint32_t *)pBuff, FifoCnt); + AD5940_INTCClrFlag(AFEINTSRC_DATAFIFOTHRESH); + + AD5940Err status = AppAMPRegModify(pBuff, &FifoCnt); /* If there is need to do AFE re-configure, do it here when AFE is in active state */ + AD5940_SleepKeyCtrlS(SLPKEY_UNLOCK); + //AD5940_EnterSleepS(); /* Manually put AFE back to hibernate mode. This operation only takes effect when register value is ACTIVE previously */ + + /* Process data */ + AppAMPDataProcess((int32_t*)pBuff,&FifoCnt); + *pCount = FifoCnt; + + if (status == AD5940ERR_STOP) return AD5940ERR_STOP; + return 0; + } + + return 0; +} + +/* Calculate voltage */ +float AppAMPCalcVoltage(uint32_t ADCcode) +{ + float kFactor = 1.835/1.82; + float fVolt = 0.0; + int32_t tmp = 0; + tmp = ADCcode - 32768; + switch(AppAMPCfg.ADCPgaGain) + { + case ADCPGA_1: + fVolt = ((float)(tmp)/32768)*(AppAMPCfg.ADCRefVolt/1)*kFactor; + break; + case ADCPGA_1P5: + fVolt = ((float)(tmp)/32768)*(AppAMPCfg.ADCRefVolt/1.5f)*kFactor; + break; + case ADCPGA_2: + fVolt = ((float)(tmp)/32768)*(AppAMPCfg.ADCRefVolt/2)*kFactor; + break; + case ADCPGA_4: + fVolt = ((float)(tmp)/32768)*(AppAMPCfg.ADCRefVolt/4)*kFactor; + break; + case ADCPGA_9: + fVolt = ((float)(tmp)/32768)*(AppAMPCfg.ADCRefVolt/9)*kFactor; + break; + } + return fVolt; +} +/* Calculate current in uA */ +float AppAMPCalcCurrent(uint32_t ADCcode) +{ + float fCurrent, fVoltage = 0.0; + fVoltage = AppAMPCalcVoltage(ADCcode); + fCurrent = fVoltage/AppAMPCfg.RtiaCalValue.Magnitude; + + return -fCurrent*1000000; +} \ No newline at end of file diff --git a/examples/rp2040_port/Amperometric.h b/examples/rp2040_port/Amperometric.h new file mode 100644 index 0000000..f6e908c --- /dev/null +++ b/examples/rp2040_port/Amperometric.h @@ -0,0 +1,74 @@ +// File: Amperometric.h +#ifndef _AMPEROMETRIC_H_ +#define _AMPEROMETRIC_H_ +#include "ad5940.h" +#include "stdio.h" +#include "string.h" +#include "math.h" + +#define DAC12BITVOLT_1LSB (2200.0f/4095) //mV +#define DAC6BITVOLT_1LSB (DAC12BITVOLT_1LSB*64) //mV + +typedef struct +{ +/* Common configurations for all kinds of Application. */ + BoolFlag bParaChanged; /* Indicate to generate sequence again. It's auto cleared by AppAMPInit */ + uint32_t SeqStartAddr; /* Initialaztion sequence start address in SRAM of AD5940 */ + uint32_t MaxSeqLen; /* Limit the maximum sequence. */ + uint32_t SeqStartAddrCal; /* Measurement sequence start address in SRAM of AD5940 */ + uint32_t MaxSeqLenCal; + +/* Application related parameters */ + BoolFlag ReDoRtiaCal; /* Set this flag to bTRUE when there is need to do calibration. */ + float SysClkFreq; /* The real frequency of system clock */ + float WuptClkFreq; /* The clock frequency of Wakeup Timer in Hz. Typically it's 32kHz. Leave it here in case we calibrate clock in software method */ + float AdcClkFreq; /* The real frequency of ADC clock */ + uint32_t FifoThresh; /* FIFO threshold. Should be N*4 */ + float AmpODR; /* in Hz. ODR decides the period of WakeupTimer who will trigger sequencer periodically.*/ + int32_t NumOfData; /* By default it's '-1'. If you want the engine stops after get NumofData, then set the value here. Otherwise, set it to '-1' which means never stop. */ + float RcalVal; /* Rcal value in Ohm */ + float ADCRefVolt; /* Measured 1.82 V reference*/ + uint32_t PwrMod; /* Control Chip power mode(LP/HP) */ + uint32_t ADCPgaGain; /* PGA Gain select from GNPGA_1, GNPGA_1_5, GNPGA_2, GNPGA_4, GNPGA_9 !!! We must ensure signal is in range of +-1.5V which is limited by ADC input stage */ + uint8_t ADCSinc3Osr; /* SINC3 OSR selection. ADCSINC3OSR_2, ADCSINC3OSR_4 */ + uint8_t ADCSinc2Osr; /* SINC2 OSR selection. ADCSINC2OSR_22...ADCSINC2OSR_1333 */ + uint32_t DataFifoSrc; /* DataFIFO source. FIFOSRC_SINC3, FIFOSRC_DFT, FIFOSRC_SINC2NOTCH, FIFOSRC_VAR, FIFOSRC_MEAN*/ + uint32_t LptiaRtiaSel; /* Use internal RTIA, select from RTIA_INT_200, RTIA_INT_1K, RTIA_INT_5K, RTIA_INT_10K, RTIA_INT_20K, RTIA_INT_40K, RTIA_INT_80K, RTIA_INT_160K */ + uint32_t LpTiaRf; /* Rfilter select */ + uint32_t LpTiaRl; /* SE0 Rload select */ + fImpPol_Type RtiaCalValue; /* Calibrated Rtia value */ + float Vzero; /* Voltage on SE0 pin and Vzero, optimumly 1100mV*/ + float SensorBias; /* Sensor bias voltage = VRE0 - VSE0 */ + BoolFlag ExtRtia; /* Use internal or external Rtia */ + float ExtRtiaVal; /* External Rtia value if using one */ + BoolFlag AMPInited; /* If the program run firstly, generated sequence commands */ + SEQInfo_Type InitSeqInfo; + SEQInfo_Type MeasureSeqInfo; + BoolFlag StopRequired; /* After FIFO is ready, stop the measurement sequence */ + uint32_t FifoDataCount; /* Count how many times impedance have been measured */ + BoolFlag ShortRe0Se0; /* Short RE0 to SE0 */ +/* End */ +}AppAMPCfg_Type; + +/** + * int32_t type Impedance result in Cartesian coordinate +*/ +typedef struct +{ + float Current; + float Voltage; +}fAmpRes_Type; + +#define AMPCTRL_START 0 +#define AMPCTRL_STOPNOW 1 +#define AMPCTRL_STOPSYNC 2 +#define AMPCTRL_SHUTDOWN 4 /* Note: shutdown here means turn off everything and put AFE to hibernate mode. The word 'SHUT DOWN' is only used here. */ + +AD5940Err AppAMPGetCfg(void *pCfg); +AD5940Err AppAMPInit(uint32_t *pBuffer, uint32_t BufferSize); +AD5940Err AppAMPISR(void *pBuff, uint32_t *pCount); +AD5940Err AppAMPCtrl(int32_t AmpCtrl, void *pPara); +float AppAMPCalcVoltage(uint32_t ADCcode); +float AppAMPCalcCurrent(uint32_t ADCcode); + +#endif \ No newline at end of file diff --git a/examples/rp2040_port/App_Common.h b/examples/rp2040_port/App_Common.h new file mode 100644 index 0000000..abfbc13 --- /dev/null +++ b/examples/rp2040_port/App_Common.h @@ -0,0 +1,87 @@ +// File: App_Common.h +#ifndef _APP_COMMON_H_ +#define _APP_COMMON_H_ + +#include "Amperometric.h" +#include "Impedance.h" +#include "RampTest.h" +#include "ad5940.h" +#include "pico/stdlib.h" +#include "rp2040port.h" +#include +#include +#include +#include + +// --- Hardware Definitions --- +#define PIN_MISO 0 +#define PIN_CS 1 +#define PIN_SCK 2 +#define PIN_MOSI 3 +#define PIN_RST 9 +#define PIN_INT 29 + +#define APPBUFF_SIZE 512 +#define AD5940ERR_STOP 10 + +#ifndef LPTIARF_BYPASS +#define LPTIARF_BYPASS 0x2000 +#endif + +// --- Application State Enums --- +typedef enum { + MODE_IDLE, + MODE_IMPEDANCE, + MODE_AMPEROMETRIC, + MODE_RAMP +} AppMode; + +// --- Global Variables --- +extern uint32_t AppBuff[APPBUFF_SIZE]; +extern AppMode CurrentMode; +extern float LFOSCFreq; +extern uint32_t g_AmpIndex; +extern uint32_t g_RampIndex; + +// Configuration Globals +extern uint32_t ConfigLptiaVal; +extern uint32_t ConfigHstiaVal; +extern uint32_t CurrentLpTiaRf; +extern uint32_t ConfigRLoad; +extern float CalibratedLptiaVal; +extern float CalibratedHstiaVal; +extern float CalibratedHstiaPhase; // Added for single-point phase correction +extern BoolFlag GlobalShortRe0Se0; + +// --- Function Prototypes --- + +// From AD5940_Platform.c +void setup_pins(void); +int32_t AD5940PlatformCfg(void); +void SystemReset(void); +uint32_t GetHSTIARtia(uint32_t val); +uint32_t GetLPTIARtia(uint32_t val); +uint32_t GetLPTIARload(uint32_t val); +void ImpedanceShowResult(uint32_t *pData, uint32_t DataCount); +void AmperometricShowResult(float *pData, uint32_t DataCount); +void RampShowResult(float *pData, uint32_t DataCount); + +// From Measurement_Core.c +void AD5940ImpedanceStructInit(void); +void AD5940AMPStructInit(void); +void AD5940RampStructInit(void); +void Config_LPLOOP(float bias_mv); +void Calibrate_HSDAC(float freq); +void Configure_Filters(float freq); +void Do_WaveGen(float freq); +void AD5941_InitAll(void); + +// From Measurement_Routines.c +void Routine_CalibrateLFO(void); +void Routine_Measure(float freq, float bias_mv); +void Routine_Sweep(float start, float end, int steps, float bias_mv); +void Routine_Amperometric(float bias_mv); +void Routine_LSV(float start_mv, float end_mv, int steps, int duration_ms); +void Routine_CalibrateSystem(void); + +#endif \ No newline at end of file diff --git a/examples/rp2040_port/CMakeLists.txt b/examples/rp2040_port/CMakeLists.txt new file mode 100644 index 0000000..e5fd956 --- /dev/null +++ b/examples/rp2040_port/CMakeLists.txt @@ -0,0 +1,45 @@ +# File: CMakeLists.txt +cmake_minimum_required(VERSION 3.13) + +include(pico_sdk_import.cmake) + +project(EIS C CXX ASM) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) + +pico_sdk_init() + +# Changed main.cpp to main.c +add_executable(EIS + main.c + ad5940.c + Impedance.c + Amperometric.c + RampTest.c + Reset.c + Measurement_Core.c + Measurement_Routines.c + AD5940_Platform.c + rp2040port.c +) + +target_compile_definitions(EIS PRIVATE CHIPSEL_594X) + +target_include_directories(EIS PRIVATE ${CMAKE_CURRENT_LIST_DIR}) + +target_link_libraries(EIS + pico_stdlib + hardware_spi + hardware_gpio + hardware_dma + hardware_irq + hardware_vreg + hardware_clocks + m +) + +pico_enable_stdio_usb(EIS 1) +pico_enable_stdio_uart(EIS 0) + +pico_add_extra_outputs(EIS) \ No newline at end of file diff --git a/examples/rp2040_port/Impedance.c b/examples/rp2040_port/Impedance.c new file mode 100644 index 0000000..d543245 --- /dev/null +++ b/examples/rp2040_port/Impedance.c @@ -0,0 +1,650 @@ +/*! + ***************************************************************************** + @file: Impedance.c + @author: Neo Xu + @brief: standard 4-wire or 2-wire impedance measurement sequences. + ----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*****************************************************************************/ +#include "Impedance.h" +#include "ad5940.h" +#include "math.h" +#include "string.h" +#include + +/* Default LPDAC resolution(2.5V internal reference). */ +#define DAC12BITVOLT_1LSB (2200.0f / 4095) // mV +#define DAC6BITVOLT_1LSB (DAC12BITVOLT_1LSB * 64) // mV + +static uint32_t const HpRtiaTable[] = {200, 1000, 5000, 10000, 20000, + 40000, 80000, 160000, 0}; +static float ResRtiaCal = 0.0f; + +/* + Application configuration structure. Specified by user from template. + The variables are usable in this whole application. + It includes basic configuration for sequencer generator and application + related parameters +*/ +AppIMPCfg_Type AppIMPCfg = { + .bParaChanged = bFALSE, + .SeqStartAddr = 0, + .MaxSeqLen = 0, + + .SeqStartAddrCal = 0, + .MaxSeqLenCal = 0, + + .ImpODR = 20.0, /* 20.0 Hz*/ + .NumOfData = -1, + .SysClkFreq = 16000000.0, + .WuptClkFreq = 32000.0, + .AdcClkFreq = 16000000.0, + .RcalVal = 10000.0, + .RtiaVal = 1000.0, + .ShortRe0Se0 = bFALSE, + + .DswitchSel = SWD_CE0, + .PswitchSel = SWP_CE0, + .NswitchSel = SWN_AIN1, + .TswitchSel = SWT_AIN1, + + .PwrMod = AFEPWR_HP, + + .HstiaRtiaSel = HSTIARTIA_200, + .ExcitBufGain = EXCITBUFGAIN_2, + .HsDacGain = HSDACGAIN_1, + .HsDacUpdateRate = 7, + .DacVoltPP = 800.0, + .BiasVolt = 0.0f, + + .SinFreq = 100000.0, /* 1000Hz */ + + .DftNum = DFTNUM_16384, + .DftSrc = DFTSRC_SINC3, + .HanWinEn = bTRUE, + + .AdcPgaGain = ADCPGA_1, + .ADCSinc3Osr = ADCSINC3OSR_2, + .ADCSinc2Osr = ADCSINC2OSR_22, + + .ADCAvgNum = ADCAVGNUM_16, + + .SweepCfg.SweepEn = bTRUE, + .SweepCfg.SweepStart = 1000.0, + .SweepCfg.SweepStop = 200000.0, + .SweepCfg.SweepPoints = 101, + .SweepCfg.SweepLog = bFALSE, + .SweepCfg.SweepIndex = 0, + + .FifoThresh = 4, + .IMPInited = bFALSE, + .StopRequired = bFALSE, +}; + +/** + This function is provided for upper controllers that want to change + application parameters specially for user defined parameters. +*/ +int32_t AppIMPGetCfg(void *pCfg) { + if (pCfg) { + *(AppIMPCfg_Type **)pCfg = &AppIMPCfg; + return AD5940ERR_OK; + } + return AD5940ERR_PARA; +} + +int32_t AppIMPCtrl(uint32_t Command, void *pPara) { + + switch (Command) { + case IMPCTRL_START: { + WUPTCfg_Type wupt_cfg; + + if (AD5940_WakeUp(10) > + 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + if (AppIMPCfg.IMPInited == bFALSE) + return AD5940ERR_APPERROR; + /* Start it */ + wupt_cfg.WuptEn = bTRUE; + wupt_cfg.WuptEndSeq = WUPTENDSEQ_A; + wupt_cfg.WuptOrder[0] = SEQID_0; + wupt_cfg.SeqxSleepTime[SEQID_0] = 4; + wupt_cfg.SeqxWakeupTime[SEQID_0] = + (uint32_t)(AppIMPCfg.WuptClkFreq / AppIMPCfg.ImpODR) - 4; + AD5940_WUPTCfg(&wupt_cfg); + + AppIMPCfg.FifoDataCount = 0; /* restart */ + break; + } + case IMPCTRL_STOPNOW: { + if (AD5940_WakeUp(10) > + 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + /* Start Wupt right now */ + AD5940_WUPTCtrl(bFALSE); + /* There is chance this operation will fail because sequencer could put AFE + back to hibernate mode just after waking up. Use STOPSYNC is better. */ + AD5940_WUPTCtrl(bFALSE); + break; + } + case IMPCTRL_STOPSYNC: { + AppIMPCfg.StopRequired = bTRUE; + break; + } + case IMPCTRL_GETFREQ: { + if (pPara == 0) + return AD5940ERR_PARA; + if (AppIMPCfg.SweepCfg.SweepEn == bTRUE) + *(float *)pPara = AppIMPCfg.FreqofData; + else + *(float *)pPara = AppIMPCfg.SinFreq; + } break; + case IMPCTRL_SHUTDOWN: { + AppIMPCtrl(IMPCTRL_STOPNOW, 0); /* Stop the measurement if it's running. */ + /* Turn off LPloop related blocks which are not controlled automatically by + * hibernate operation */ + AFERefCfg_Type aferef_cfg; + LPLoopCfg_Type lp_loop; + memset(&aferef_cfg, 0, sizeof(aferef_cfg)); + AD5940_REFCfgS(&aferef_cfg); + memset(&lp_loop, 0, sizeof(lp_loop)); + AD5940_LPLoopCfgS(&lp_loop); + AD5940_EnterSleepS(); /* Enter Hibernate */ + } break; + default: + break; + } + return AD5940ERR_OK; +} + +/* generated code snnipet */ +float AppIMPGetCurrFreq(void) { + if (AppIMPCfg.SweepCfg.SweepEn == bTRUE) + return AppIMPCfg.FreqofData; + else + return AppIMPCfg.SinFreq; +} + +/* Application initialization */ +static AD5940Err AppIMPSeqCfgGen(void) { + AD5940Err error = AD5940ERR_OK; + const uint32_t *pSeqCmd; + uint32_t SeqLen; + AFERefCfg_Type aferef_cfg; + HSLoopCfg_Type HsLoopCfg; + DSPCfg_Type dsp_cfg; + float sin_freq; + + /* Start sequence generator here */ + AD5940_SEQGenCtrl(bTRUE); + + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Init all to disable state */ + + aferef_cfg.HpBandgapEn = bTRUE; + aferef_cfg.Hp1V1BuffEn = bTRUE; + aferef_cfg.Hp1V8BuffEn = bTRUE; + aferef_cfg.Disc1V1Cap = bFALSE; + aferef_cfg.Disc1V8Cap = bFALSE; + aferef_cfg.Hp1V8ThemBuff = bFALSE; + aferef_cfg.Hp1V8Ilimit = bFALSE; + aferef_cfg.Lp1V1BuffEn = bFALSE; + aferef_cfg.Lp1V8BuffEn = bFALSE; + /* LP reference control - turn off them to save power*/ + aferef_cfg.LpBandgapEn = bFALSE; + aferef_cfg.LpRefBufEn = bFALSE; + aferef_cfg.LpRefBoostEn = bFALSE; + AD5940_REFCfgS(&aferef_cfg); + HsLoopCfg.HsDacCfg.ExcitBufGain = AppIMPCfg.ExcitBufGain; + HsLoopCfg.HsDacCfg.HsDacGain = AppIMPCfg.HsDacGain; + HsLoopCfg.HsDacCfg.HsDacUpdateRate = AppIMPCfg.HsDacUpdateRate; + + HsLoopCfg.HsTiaCfg.DiodeClose = bFALSE; + HsLoopCfg.HsTiaCfg.HstiaBias = HSTIABIAS_1P1; + HsLoopCfg.HsTiaCfg.HstiaCtia = 31; /* 31pF + 2pF */ + HsLoopCfg.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_OPEN; + HsLoopCfg.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_OPEN; + HsLoopCfg.HsTiaCfg.HstiaRtiaSel = AppIMPCfg.HstiaRtiaSel; + + HsLoopCfg.SWMatCfg.Dswitch = AppIMPCfg.DswitchSel; + HsLoopCfg.SWMatCfg.Pswitch = AppIMPCfg.PswitchSel; + HsLoopCfg.SWMatCfg.Nswitch = AppIMPCfg.NswitchSel; + HsLoopCfg.SWMatCfg.Tswitch = SWT_TRTIA | AppIMPCfg.TswitchSel; + + HsLoopCfg.WgCfg.WgType = WGTYPE_SIN; + HsLoopCfg.WgCfg.GainCalEn = bTRUE; + HsLoopCfg.WgCfg.OffsetCalEn = bTRUE; + if (AppIMPCfg.SweepCfg.SweepEn == bTRUE) { + AppIMPCfg.FreqofData = AppIMPCfg.SweepCfg.SweepStart; + AppIMPCfg.SweepCurrFreq = AppIMPCfg.SweepCfg.SweepStart; + AD5940_SweepNext(&AppIMPCfg.SweepCfg, &AppIMPCfg.SweepNextFreq); + sin_freq = AppIMPCfg.SweepCurrFreq; + } else { + sin_freq = AppIMPCfg.SinFreq; + AppIMPCfg.FreqofData = sin_freq; + } + HsLoopCfg.WgCfg.SinCfg.SinFreqWord = + AD5940_WGFreqWordCal(sin_freq, AppIMPCfg.SysClkFreq); + HsLoopCfg.WgCfg.SinCfg.SinAmplitudeWord = + (uint32_t)(AppIMPCfg.DacVoltPP / 800.0f * 2047 + 0.5f); + HsLoopCfg.WgCfg.SinCfg.SinOffsetWord = 0; + HsLoopCfg.WgCfg.SinCfg.SinPhaseWord = 0; + AD5940_HSLoopCfgS(&HsLoopCfg); + /* LPDAC configuration removed - using HSTIA internal bias */ + dsp_cfg.ADCBaseCfg.ADCMuxN = ADCMUXN_HSTIA_N; + dsp_cfg.ADCBaseCfg.ADCMuxP = ADCMUXP_HSTIA_P; + dsp_cfg.ADCBaseCfg.ADCPga = AppIMPCfg.AdcPgaGain; + + memset(&dsp_cfg.ADCDigCompCfg, 0, sizeof(dsp_cfg.ADCDigCompCfg)); + + dsp_cfg.ADCFilterCfg.ADCAvgNum = AppIMPCfg.ADCAvgNum; + dsp_cfg.ADCFilterCfg.ADCRate = + ADCRATE_800KHZ; /* Tell filter block clock rate of ADC*/ + dsp_cfg.ADCFilterCfg.ADCSinc2Osr = AppIMPCfg.ADCSinc2Osr; + dsp_cfg.ADCFilterCfg.ADCSinc3Osr = AppIMPCfg.ADCSinc3Osr; + dsp_cfg.ADCFilterCfg.BpNotch = bTRUE; + dsp_cfg.ADCFilterCfg.BpSinc3 = bFALSE; + dsp_cfg.ADCFilterCfg.Sinc2NotchEnable = bTRUE; + dsp_cfg.DftCfg.DftNum = AppIMPCfg.DftNum; + dsp_cfg.DftCfg.DftSrc = AppIMPCfg.DftSrc; + dsp_cfg.DftCfg.HanWinEn = AppIMPCfg.HanWinEn; + + memset(&dsp_cfg.StatCfg, 0, sizeof(dsp_cfg.StatCfg)); + AD5940_DSPCfgS(&dsp_cfg); + + /* Enable all of them. They are automatically turned off during hibernate mode + * to save power */ + /* Enable all of them. They are automatically turned off during hibernate mode + * to save power */ + AD5940_AFECtrlS(AFECTRL_HSTIAPWR | AFECTRL_INAMPPWR | AFECTRL_EXTBUFPWR | + AFECTRL_WG | AFECTRL_DACREFPWR | AFECTRL_HSDACPWR | + AFECTRL_SINC2NOTCH, + bTRUE); + /* Sequence end. */ + AD5940_SEQGenInsert(SEQ_STOP()); /* Add one extra command to disable sequencer + for initialization sequence because we + only want it to run one time. */ + + /* Stop here */ + error = AD5940_SEQGenFetchSeq(&pSeqCmd, &SeqLen); + AD5940_SEQGenCtrl(bFALSE); /* Stop sequencer generator */ + if (error == AD5940ERR_OK) { + AppIMPCfg.InitSeqInfo.SeqId = SEQID_1; + AppIMPCfg.InitSeqInfo.SeqRamAddr = AppIMPCfg.SeqStartAddr; + AppIMPCfg.InitSeqInfo.pSeqCmd = pSeqCmd; + AppIMPCfg.InitSeqInfo.SeqLen = SeqLen; + /* Write command to SRAM */ + AD5940_SEQCmdWrite(AppIMPCfg.InitSeqInfo.SeqRamAddr, pSeqCmd, SeqLen); + } else + return error; /* Error */ + return AD5940ERR_OK; +} + +static AD5940Err AppIMPSeqMeasureGen(void) { + AD5940Err error = AD5940ERR_OK; + const uint32_t *pSeqCmd; + uint32_t SeqLen; + + uint32_t WaitClks; + SWMatrixCfg_Type sw_cfg; + ClksCalInfo_Type clks_cal; + + clks_cal.DataType = DATATYPE_DFT; + clks_cal.DftSrc = AppIMPCfg.DftSrc; + clks_cal.DataCount = 1L << (AppIMPCfg.DftNum + 2); /* 2^(DFTNUMBER+2) */ + clks_cal.ADCSinc2Osr = AppIMPCfg.ADCSinc2Osr; + clks_cal.ADCSinc3Osr = AppIMPCfg.ADCSinc3Osr; + clks_cal.ADCAvgNum = AppIMPCfg.ADCAvgNum; + clks_cal.RatioSys2AdcClk = AppIMPCfg.SysClkFreq / AppIMPCfg.AdcClkFreq; + AD5940_ClksCalculate(&clks_cal, &WaitClks); + + AD5940_SEQGenCtrl(bTRUE); + AD5940_SEQGpioCtrlS( + AGPIO_Pin2); /* Set GPIO1, clear others that under control */ + AD5940_SEQGenInsert(SEQ_WAIT(16 * 250)); /* @todo wait 250us? */ + + /* Configure matrix for RCAL measurement */ + sw_cfg.Dswitch = SWD_RCAL0; + sw_cfg.Pswitch = SWP_RCAL0; + sw_cfg.Nswitch = SWN_RCAL1; + sw_cfg.Tswitch = SWT_RCAL1 | SWT_TRTIA; + AD5940_SWMatrixCfgS(&sw_cfg); + + // Turn on Excitation/ADC + AD5940_AFECtrlS(AFECTRL_HSTIAPWR | AFECTRL_INAMPPWR | AFECTRL_EXTBUFPWR | + AFECTRL_DACREFPWR | AFECTRL_HSDACPWR | AFECTRL_SINC2NOTCH, + bTRUE); + AD5940_AFECtrlS(AFECTRL_ADCPWR | AFECTRL_WG, bTRUE); + AD5940_SEQGenInsert(SEQ_WAIT(16 * 10)); // Settling + AD5940_AFECtrlS(AFECTRL_ADCCNV | AFECTRL_DFT, bTRUE); + AD5940_SEQGenInsert(SEQ_WAIT(WaitClks)); + AD5940_AFECtrlS(AFECTRL_ADCCNV | AFECTRL_DFT | AFECTRL_WG | AFECTRL_ADCPWR, + bFALSE); + + /* Configure matrix for external Rz (Sensor) */ + sw_cfg.Dswitch = AppIMPCfg.DswitchSel; + sw_cfg.Pswitch = AppIMPCfg.PswitchSel; + sw_cfg.Nswitch = AppIMPCfg.NswitchSel; + sw_cfg.Tswitch = SWT_TRTIA | AppIMPCfg.TswitchSel; + AD5940_SWMatrixCfgS(&sw_cfg); + + AD5940_AFECtrlS(AFECTRL_ADCPWR | AFECTRL_WG, bTRUE); + /* Enable Waveform generator */ + AD5940_SEQGenInsert(SEQ_WAIT(16 * 10)); // Settling + AD5940_AFECtrlS(AFECTRL_ADCCNV | AFECTRL_DFT, + bTRUE); /* Start ADC convert and DFT */ + AD5940_SEQGenInsert(SEQ_WAIT(WaitClks)); /* wait for first data ready */ + AD5940_AFECtrlS(AFECTRL_ADCCNV | AFECTRL_DFT | AFECTRL_WG | AFECTRL_ADCPWR, + bFALSE); /* Stop ADC convert and DFT */ + + AD5940_AFECtrlS(AFECTRL_HSTIAPWR | AFECTRL_INAMPPWR | AFECTRL_EXTBUFPWR | + AFECTRL_WG | AFECTRL_DACREFPWR | AFECTRL_HSDACPWR | + AFECTRL_SINC2NOTCH, + bFALSE); + AD5940_SEQGpioCtrlS(0); /* Clr GPIO1 */ + + AD5940_EnterSleepS(); /* Goto hibernate */ + + /* Sequence end. */ + error = AD5940_SEQGenFetchSeq(&pSeqCmd, &SeqLen); + AD5940_SEQGenCtrl(bFALSE); /* Stop sequencer generator */ + + if (error == AD5940ERR_OK) { + AppIMPCfg.MeasureSeqInfo.SeqId = SEQID_0; + AppIMPCfg.MeasureSeqInfo.SeqRamAddr = + AppIMPCfg.InitSeqInfo.SeqRamAddr + AppIMPCfg.InitSeqInfo.SeqLen; + AppIMPCfg.MeasureSeqInfo.pSeqCmd = pSeqCmd; + AppIMPCfg.MeasureSeqInfo.SeqLen = SeqLen; + /* Write command to SRAM */ + AD5940_SEQCmdWrite(AppIMPCfg.MeasureSeqInfo.SeqRamAddr, pSeqCmd, SeqLen); + } else + return error; /* Error */ + return AD5940ERR_OK; +} + +/* This function provide application initialize. It can also enable Wupt that + * will automatically trigger sequence. Or it can configure */ +int32_t AppIMPInit(uint32_t *pBuffer, uint32_t BufferSize) { + AD5940Err error = AD5940ERR_OK; + SEQCfg_Type seq_cfg; + FIFOCfg_Type fifo_cfg; + + if (AD5940_WakeUp(10) > + 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + + /* Configure sequencer and stop it */ + seq_cfg.SeqMemSize = + SEQMEMSIZE_2KB; /* 2kB SRAM is used for sequencer, others for data FIFO */ + seq_cfg.SeqBreakEn = bFALSE; + seq_cfg.SeqIgnoreEn = bTRUE; + seq_cfg.SeqCntCRCClr = bTRUE; + seq_cfg.SeqEnable = bFALSE; + seq_cfg.SeqWrTimer = 0; + AD5940_SEQCfg(&seq_cfg); + + /* Reconfigure FIFO */ + AD5940_FIFOCtrlS(FIFOSRC_DFT, bFALSE); /* Disable FIFO firstly */ + fifo_cfg.FIFOEn = bTRUE; + fifo_cfg.FIFOMode = FIFOMODE_FIFO; + fifo_cfg.FIFOSize = + FIFOSIZE_4KB; /* 4kB for FIFO, The reset 2kB for sequencer */ + fifo_cfg.FIFOSrc = FIFOSRC_DFT; + fifo_cfg.FIFOThresh = AppIMPCfg.FifoThresh; + AD5940_FIFOCfg(&fifo_cfg); + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + + /* Start sequence generator */ + /* Initialize sequencer generator */ + if ((AppIMPCfg.IMPInited == bFALSE) || (AppIMPCfg.bParaChanged == bTRUE)) { + if (pBuffer == 0) + return AD5940ERR_PARA; + if (BufferSize == 0) + return AD5940ERR_PARA; + AD5940_SEQGenInit(pBuffer, BufferSize); + + /* Generate initialize sequence */ + error = AppIMPSeqCfgGen(); /* Application initialization sequence using + either MCU or sequencer */ + if (error != AD5940ERR_OK) + return error; + + /* Generate measurement sequence */ + error = AppIMPSeqMeasureGen(); + if (error != AD5940ERR_OK) + return error; + + AppIMPCfg.bParaChanged = bFALSE; /* Clear this flag as we already + implemented the new configuration */ + } + + /* Initialization sequencer */ + AppIMPCfg.InitSeqInfo.WriteSRAM = bFALSE; + AD5940_SEQInfoCfg(&AppIMPCfg.InitSeqInfo); + seq_cfg.SeqEnable = bTRUE; + AD5940_SEQCfg(&seq_cfg); /* Enable sequencer */ + AD5940_SEQMmrTrig(AppIMPCfg.InitSeqInfo.SeqId); + while (AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_ENDSEQ) == bFALSE) + ; + + /* Measurement sequence */ + AppIMPCfg.MeasureSeqInfo.WriteSRAM = bFALSE; + AD5940_SEQInfoCfg(&AppIMPCfg.MeasureSeqInfo); + + seq_cfg.SeqEnable = bTRUE; + AD5940_SEQCfg(&seq_cfg); /* Enable sequencer, and wait for trigger */ + AD5940_ClrMCUIntFlag(); /* Clear interrupt flag generated before */ + + AD5940_AFEPwrBW(AppIMPCfg.PwrMod, AFEBW_250KHZ); + + AppIMPCfg.IMPInited = bTRUE; /* IMP application has been initialized. */ + return AD5940ERR_OK; +} + +/* Modify registers when AFE wakeup */ +int32_t AppIMPRegModify(int32_t *const pData, uint32_t *pDataCount) { + if (AppIMPCfg.NumOfData > 0) { + AppIMPCfg.FifoDataCount += *pDataCount / 4; // Changed from /2 to /4 + if (AppIMPCfg.FifoDataCount >= AppIMPCfg.NumOfData) { + AD5940_WUPTCtrl(bFALSE); + return AD5940ERR_OK; + } + } + if (AppIMPCfg.StopRequired == bTRUE) { + AD5940_WUPTCtrl(bFALSE); + return AD5940ERR_OK; + } + if (AppIMPCfg.SweepCfg + .SweepEn) /* Need to set new frequency and set power mode */ + { + AD5940_WGFreqCtrlS(AppIMPCfg.SweepNextFreq, AppIMPCfg.SysClkFreq); + } + return AD5940ERR_OK; +} + +/* Depending on the data type, do appropriate data pre-process before return + * back to controller */ +int32_t AppIMPDataProcess(int32_t *const pData, uint32_t *pDataCount) { + uint32_t DataCount = *pDataCount; + uint32_t ImpResCount = DataCount / 4; + + fImpPol_Type *const pOut = (fImpPol_Type *)pData; + iImpCar_Type *pSrcData = (iImpCar_Type *)pData; + + *pDataCount = 0; + + DataCount = (DataCount / 4) * 4; // Align 4 + + /* Convert DFT result to int32_t type */ + for (uint32_t i = 0; i < DataCount; i++) { + pData[i] &= 0x3ffff; /* @todo option to check ECC */ + if (pData[i] & (1L << 17)) /* Bit17 is sign bit */ + { + pData[i] |= 0xfffc0000; /* Data is 18bit in two's complement, bit17 is the + sign bit */ + } + } + for (uint32_t i = 0; i < ImpResCount; i++) { + iImpCar_Type *pDftRcal, *pDftRz; + pDftRcal = pSrcData++; + pDftRz = pSrcData++; + + float RzMag, RzPhase; + float RcalMag, RcalPhase; + + // Calculate RCAL (Reference) + RcalMag = sqrt((float)pDftRcal->Real * pDftRcal->Real + + (float)pDftRcal->Image * pDftRcal->Image); + RcalPhase = atan2(-pDftRcal->Image, pDftRcal->Real); + + // Calculate Sensor + RzMag = sqrt((float)pDftRz->Real * pDftRz->Real + + (float)pDftRz->Image * pDftRz->Image); + RzPhase = atan2(-pDftRz->Image, pDftRz->Real); + + // Determines Gain Factor for Calibration logic (though mostly ratiometric + // acts via ratio) + // Formula: Rz = Rcal * (V_rz_out / V_rcal_out) ? No. + // Formula: Rz = (V_excite / I) + // I = V_rcal_out / Rcal_gain_resistor ?? No. + // Standard Ratiometric: Rz = Rcal_val * (Mag_Rcal_Meas / Mag_Rz_Meas) + // (Assuming constant current or ratio of voltages). + // Let's use the standard formula from original code which accounts for + // everything via Ratio. + + // Note: This relies on Gain being CONSTANT between RCAL measure and Sensor + // measure. Since we don't change Gain settings in the sequence (only MUX), + // this holds true. + + RzMag = (RcalMag / RzMag) * AppIMPCfg.RcalVal; + RzPhase = RcalPhase - RzPhase; + + pOut[i].Magnitude = RzMag; + pOut[i].Phase = RzPhase; // Phase drift should cancel out via Ratiometric? + // Original code did RcalPhase - RzPhase. + } + *pDataCount = ImpResCount; + AppIMPCfg.FreqofData = AppIMPCfg.SweepCurrFreq; + /* Calculate next frequency point */ + if (AppIMPCfg.SweepCfg.SweepEn == bTRUE) { + AppIMPCfg.FreqofData = AppIMPCfg.SweepCurrFreq; + AppIMPCfg.SweepCurrFreq = AppIMPCfg.SweepNextFreq; + AD5940_SweepNext(&AppIMPCfg.SweepCfg, &AppIMPCfg.SweepNextFreq); + } + + return 0; +} + +/** + +*/ +int32_t AppIMPISR(void *pBuff, uint32_t *pCount) { + uint32_t BuffCount; + uint32_t FifoCnt; + BuffCount = *pCount; + + *pCount = 0; + + if (AD5940_WakeUp(10) > + 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + AD5940_SleepKeyCtrlS(SLPKEY_LOCK); /* Prohibit AFE to enter sleep mode. */ + + if (AD5940_INTCTestFlag(AFEINTC_0, AFEINTSRC_DATAFIFOTHRESH) == bTRUE) { + /* Now there should be 4 data in FIFO */ + FifoCnt = (AD5940_FIFOGetCnt() / 4) * 4; + + if (FifoCnt > BuffCount) { + ///@todo buffer is limited. + } + AD5940_FIFORd((uint32_t *)pBuff, FifoCnt); + AD5940_INTCClrFlag(AFEINTSRC_DATAFIFOTHRESH); + AppIMPRegModify(pBuff, + &FifoCnt); /* If there is need to do AFE re-configure, do it + here when AFE is in active state */ + // AD5940_EnterSleepS(); /* Manually put AFE back to hibernate mode. This + // operation only takes effect when register value is ACTIVE previously */ + AD5940_SleepKeyCtrlS(SLPKEY_UNLOCK); /* Allow AFE to enter sleep mode. */ + /* Process data */ + AppIMPDataProcess((int32_t *)pBuff, &FifoCnt); + *pCount = FifoCnt; + return 0; + } + + return 0; +} + +// Added for compatibility with Measurement_Routines.c +void AppIMPCleanup(void) { + // Ensure chip is awake before sending commands + if (AD5940_WakeUp(10) > 10) + return; + + // Stop Sequencer and Wakeup Timer + AD5940_WUPTCtrl(bFALSE); + AD5940_SEQCtrlS(bFALSE); + + // Stop active conversions and Waveform Generator, keep Reference/LDOs on + AD5940_AFECtrlS(AFECTRL_ADCCNV | AFECTRL_DFT | AFECTRL_WG, bFALSE); + + // Reset FIFO configuration + FIFOCfg_Type fifo_cfg; + fifo_cfg.FIFOEn = bFALSE; + AD5940_FIFOCfg(&fifo_cfg); + + fifo_cfg.FIFOEn = bTRUE; + fifo_cfg.FIFOMode = FIFOMODE_FIFO; + fifo_cfg.FIFOSize = FIFOSIZE_4KB; + fifo_cfg.FIFOSrc = FIFOSRC_DFT; + fifo_cfg.FIFOThresh = 4; // Match the new threshold + AD5940_FIFOCfg(&fifo_cfg); + + // Clear all interrupt flags + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); +} + +// Added for compatibility with Measurement_Routines.c +AD5940Err AppIMPRtiaCal(void) { + HSRTIACal_Type hs_cal; + fImpPol_Type res; + AD5940Err error; + + hs_cal.fFreq = AppIMPCfg.SinFreq; + hs_cal.fRcal = AppIMPCfg.RcalVal; + hs_cal.SysClkFreq = AppIMPCfg.SysClkFreq; + hs_cal.AdcClkFreq = AppIMPCfg.AdcClkFreq; + + hs_cal.HsTiaCfg.DiodeClose = bFALSE; + hs_cal.HsTiaCfg.HstiaBias = HSTIABIAS_1P1; + + hs_cal.HsTiaCfg.HstiaCtia = 31; + hs_cal.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_OPEN; + hs_cal.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_OPEN; + hs_cal.HsTiaCfg.HstiaRtiaSel = AppIMPCfg.HstiaRtiaSel; + + hs_cal.ADCSinc3Osr = AppIMPCfg.ADCSinc3Osr; + hs_cal.ADCSinc2Osr = AppIMPCfg.ADCSinc2Osr; + + hs_cal.DftCfg.DftNum = AppIMPCfg.DftNum; + hs_cal.DftCfg.DftSrc = AppIMPCfg.DftSrc; + hs_cal.DftCfg.HanWinEn = AppIMPCfg.HanWinEn; + + hs_cal.bPolarResult = bTRUE; + + hs_cal.bPolarResult = bTRUE; + + error = AD5940_HSRtiaCal(&hs_cal, &res); + if (error == AD5940ERR_OK) { + ResRtiaCal = res.Magnitude; + // AppIMPCfg.RtiaVal = ResRtiaCal; // Removed as it was custom addition + printf("Calibrated RTIA: %f Ohm, Phase: %f\n", res.Magnitude, res.Phase); + } else + printf("RTIA Calibration Failed: %d\n", error); + + return error; +} \ No newline at end of file diff --git a/examples/rp2040_port/Impedance.h b/examples/rp2040_port/Impedance.h new file mode 100644 index 0000000..2d43a4f --- /dev/null +++ b/examples/rp2040_port/Impedance.h @@ -0,0 +1,109 @@ +/*! + ***************************************************************************** + @file: Impedance.h + @author: Neo XU + @brief: 4-wire/2-wire impedance measurement header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*****************************************************************************/ +#ifndef _IMPEDANCESEQUENCES_H_ +#define _IMPEDANCESEQUENCES_H_ +#include "ad5940.h" +#include "math.h" +#include "string.h" +#include + +typedef struct { + /* Common configurations for all kinds of Application. */ + BoolFlag bParaChanged; /* Indicate to generate sequence again. It's auto + cleared by AppBIAInit */ + uint32_t + SeqStartAddr; /* Initialaztion sequence start address in SRAM of AD5940 */ + uint32_t MaxSeqLen; /* Limit the maximum sequence. */ + uint32_t SeqStartAddrCal; /* Measurement sequence start address in SRAM of + AD5940 */ + uint32_t SeqWaitAddr[2]; + uint32_t MaxSeqLenCal; + /* Application related parameters */ + float ImpODR; /* */ + int32_t NumOfData; /* By default it's '-1'. If you want the engine stops after + get NumofData, then set the value here. Otherwise, set + it to '-1' which means never stop. */ + float WuptClkFreq; /* The clock frequency of Wakeup Timer in Hz. Typically + it's 32kHz. Leave it here in case we calibrate clock in + software method */ + float SysClkFreq; /* The real frequency of system clock */ + float AdcClkFreq; /* The real frequency of ADC clock */ + float RcalVal; /* Rcal value in Ohm */ + float RtiaVal; /* Calibrated Rtia value in Ohm */ + float AdcPhaseOffset; /* Calibrated ADC Phase Offset */ + BoolFlag ShortRe0Se0; /* Short RE0 to SE0 */ + /* Switch Configuration */ + uint32_t DswitchSel; + uint32_t PswitchSel; + uint32_t NswitchSel; + uint32_t TswitchSel; + uint32_t PwrMod; /* Control Chip power mode(LP/HP) */ + uint32_t + HstiaRtiaSel; /* Use internal RTIA, select from RTIA_INT_200, RTIA_INT_1K, + RTIA_INT_5K, RTIA_INT_10K, RTIA_INT_20K, RTIA_INT_40K, + RTIA_INT_80K, RTIA_INT_160K */ + uint32_t ExcitBufGain; /* Select from EXCTBUFGAIN_2, EXCTBUFGAIN_0P25 */ + uint32_t HsDacGain; /* Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + uint32_t HsDacUpdateRate; + float DacVoltPP; /* DAC output voltage in mV peak to peak. Maximum value is + 800mVpp. Peak to peak voltage */ + float BiasVolt; /* The excitation signal is DC+AC. This parameter decides the + DC value in mV unit. 0.0mV means no DC bias.*/ + float SinFreq; /* Frequency of excitation signal */ + uint32_t DftNum; /* DFT number */ + uint32_t DftSrc; /* DFT Source */ + BoolFlag HanWinEn; /* Enable Hanning window */ + uint32_t AdcPgaGain; /* PGA Gain select from GNPGA_1, GNPGA_1_5, GNPGA_2, + GNPGA_4, GNPGA_9 !!! We must ensure signal is in range + of +-1.5V which is limited by ADC input stage */ + uint8_t ADCSinc3Osr; + uint8_t ADCSinc2Osr; + uint8_t ADCAvgNum; + /* Sweep Function Control */ + SoftSweepCfg_Type SweepCfg; + uint32_t FifoThresh; /* FIFO threshold. Should be N*4 */ + /* Private variables for internal usage */ + /* Private variables for internal usage */ + float SweepCurrFreq; + float SweepNextFreq; + float FreqofData; /* The frequency of latest data sampled */ + BoolFlag + IMPInited; /* If the program run firstly, generated sequence commands */ + SEQInfo_Type InitSeqInfo; + SEQInfo_Type MeasureSeqInfo; + BoolFlag + StopRequired; /* After FIFO is ready, stop the measurement sequence */ + uint32_t + FifoDataCount; /* Count how many times impedance have been measured */ +} AppIMPCfg_Type; + +#define IMPCTRL_START 0 +#define IMPCTRL_STOPNOW 1 +#define IMPCTRL_STOPSYNC 2 +#define IMPCTRL_GETFREQ \ + 3 /* Get Current frequency of returned data from ISR \ + */ +#define IMPCTRL_SHUTDOWN \ + 4 /* Note: shutdown here means turn off everything and put AFE to hibernate \ + mode. The word 'SHUT DOWN' is only used here. */ + +int32_t AppIMPInit(uint32_t *pBuffer, uint32_t BufferSize); +int32_t AppIMPGetCfg(void *pCfg); +int32_t AppIMPISR(void *pBuff, uint32_t *pCount); +int32_t AppIMPCtrl(uint32_t Command, void *pPara); +void AppIMPCleanup(void); +AD5940Err AppIMPRtiaCal(void); + +#endif \ No newline at end of file diff --git a/examples/rp2040_port/Makefile b/examples/rp2040_port/Makefile new file mode 100644 index 0000000..a591a17 --- /dev/null +++ b/examples/rp2040_port/Makefile @@ -0,0 +1,28 @@ +# Name of your build directory +BUILD_DIR = build + +# Name of the output file (Must match what is in CMakeLists.txt) +TARGET = EIS + +# Default target: Build the project +all: $(BUILD_DIR)/Makefile + @$(MAKE) -C $(BUILD_DIR) + +# Ensure the build directory exists and run CMake if needed +$(BUILD_DIR)/Makefile: CMakeLists.txt + @mkdir -p $(BUILD_DIR) + @cd $(BUILD_DIR) && cmake .. + +# Clean up the build directory +clean: + @rm -rf $(BUILD_DIR) + +# Helper to automatically flash (Mac specific path) +flash: all + @echo "Waiting for RPI-RP2 volume..." + @while [ ! -d /Volumes/RPI-RP2 ]; do sleep 0.1; done + @echo "Flashing..." + @cp $(BUILD_DIR)/$(TARGET).uf2 /Volumes/RPI-RP2/ + @echo "Done." + +.PHONY: all clean flash diff --git a/examples/rp2040_port/Measurement_Core.c b/examples/rp2040_port/Measurement_Core.c new file mode 100644 index 0000000..1efab57 --- /dev/null +++ b/examples/rp2040_port/Measurement_Core.c @@ -0,0 +1,368 @@ +// File: Measurement_Core.c +#include "App_Common.h" + +void AD5941_InitAll(void) { + AD5940_HWReset(); + AD5940_MCUResourceInit(0); + AD5940_Initialize(); + // CRITICAL: Re-enable Platform Interrupts/GPIOs after HW Reset + AD5940PlatformCfg(); +} + +void AD5940ImpedanceStructInit(void) { + AppIMPCfg_Type *pImpedanceCfg; + AppIMPGetCfg(&pImpedanceCfg); + + pImpedanceCfg->IMPInited = bFALSE; + pImpedanceCfg->SeqStartAddr = 0; + pImpedanceCfg->MaxSeqLen = 512; + pImpedanceCfg->RcalVal = 100.0; + pImpedanceCfg->RtiaVal = CalibratedHstiaVal; + pImpedanceCfg->SinFreq = 1000.0; + pImpedanceCfg->FifoThresh = 4; + pImpedanceCfg->DacVoltPP = 800.0; + pImpedanceCfg->ExcitBufGain = EXCITBUFGAIN_2; + pImpedanceCfg->HsDacGain = HSDACGAIN_1; + pImpedanceCfg->HsDacUpdateRate = 7; + + // --- Switch Matrix Configuration --- + // D-Switch: Connect DAC to CE0 (Force +) + pImpedanceCfg->DswitchSel = SWD_CE0; + + // P-Switch: Connect CE0 to P-Bus (Optional, but standard) + pImpedanceCfg->PswitchSel = SWP_CE0; + + // N-Switch: Connect SE0 to N-Bus (Force - / Current Input) + pImpedanceCfg->NswitchSel = SWN_SE0; + + // T-Switch: Connect SE0LOAD to T-Node (Effectively SE0 with RLOAD=0) + pImpedanceCfg->TswitchSel = SWT_SE0LOAD; + + pImpedanceCfg->HstiaRtiaSel = GetHSTIARtia(ConfigHstiaVal); + pImpedanceCfg->BiasVolt = 0.0; + pImpedanceCfg->SweepCfg.SweepEn = bFALSE; + pImpedanceCfg->SweepCfg.SweepStart = 100.0f; + pImpedanceCfg->SweepCfg.SweepStop = 100000.0f; + pImpedanceCfg->SweepCfg.SweepPoints = 50; + pImpedanceCfg->SweepCfg.SweepLog = bTRUE; + pImpedanceCfg->PwrMod = AFEPWR_LP; + pImpedanceCfg->ADCSinc3Osr = ADCSINC3OSR_4; + pImpedanceCfg->DftNum = DFTNUM_16384; + pImpedanceCfg->DftSrc = DFTSRC_SINC3; + pImpedanceCfg->ShortRe0Se0 = GlobalShortRe0Se0; +} + +void AD5940AMPStructInit(void) { + AppAMPCfg_Type *pAMPCfg; + AppAMPGetCfg(&pAMPCfg); + + pAMPCfg->AMPInited = bFALSE; + pAMPCfg->WuptClkFreq = LFOSCFreq; + pAMPCfg->SeqStartAddr = 0; + pAMPCfg->MaxSeqLen = 512; + pAMPCfg->RcalVal = 100.0; + pAMPCfg->NumOfData = -1; + pAMPCfg->AmpODR = 1.0; + pAMPCfg->FifoThresh = 4; + pAMPCfg->SensorBias = 0; + pAMPCfg->LptiaRtiaSel = GetLPTIARtia(ConfigLptiaVal); + pAMPCfg->LptiaRtiaSel = GetLPTIARtia(ConfigLptiaVal); + pAMPCfg->LpTiaRl = LPTIARLOAD_SHORT; + pAMPCfg->LpTiaRf = CurrentLpTiaRf; + pAMPCfg->Vzero = 1100; + pAMPCfg->ADCRefVolt = 1.82; + pAMPCfg->RtiaCalValue.Magnitude = CalibratedLptiaVal; + pAMPCfg->ShortRe0Se0 = GlobalShortRe0Se0; +} + +void AD5940RampStructInit(void) { + AppRAMPCfg_Type *pRampCfg; + AppRAMPGetCfg(&pRampCfg); + + pRampCfg->RAMPInited = bFALSE; + pRampCfg->SeqStartAddr = 0; + pRampCfg->MaxSeqLen = 1024; + pRampCfg->RcalVal = 100.0; + pRampCfg->ADCRefVolt = 1820.0f; + pRampCfg->FifoThresh = 4; + pRampCfg->SysClkFreq = 16000000.0f; + pRampCfg->LFOSCClkFreq = LFOSCFreq; + + pRampCfg->RampStartVolt = -500.0f; + pRampCfg->RampPeakVolt = +500.0f; + pRampCfg->VzeroStart = 1100.0f; + pRampCfg->VzeroPeak = 1100.0f; + pRampCfg->StepNumber = 100; + pRampCfg->RampDuration = 10000; + pRampCfg->SampleDelay = 1.0f; + + pRampCfg->LPTIARtiaSel = GetLPTIARtia(ConfigLptiaVal); + pRampCfg->LPTIARtiaSel = GetLPTIARtia(ConfigLptiaVal); + pRampCfg->LPTIARloadSel = LPTIARLOAD_SHORT; + pRampCfg->LpTiaRf = CurrentLpTiaRf; + pRampCfg->AdcPgaGain = ADCPGA_1P5; + pRampCfg->RtiaValue.Magnitude = CalibratedLptiaVal; + pRampCfg->ShortRe0Se0 = GlobalShortRe0Se0; +} + +void Config_LPLOOP(float bias_mv) { + uint32_t vzero_code = 32; + float vzero_volts = vzero_code * (2200.0f / 64.0f); + float vbias_volts = vzero_volts + bias_mv; + uint32_t vbias_code = (uint32_t)(vbias_volts / (2200.0f / 4095.0f)); + if (vbias_code > 4095) + vbias_code = 4095; + + LPDACCfg_Type lpdac_cfg; + lpdac_cfg.LpdacSel = LPDAC0; + lpdac_cfg.LpDacVbiasMux = LPDACVBIAS_12BIT; + lpdac_cfg.LpDacVzeroMux = LPDACVZERO_6BIT; + lpdac_cfg.DacData6Bit = vzero_code; + lpdac_cfg.DacData12Bit = vbias_code; + lpdac_cfg.DataRst = bFALSE; + lpdac_cfg.LpDacSW = LPDACSW_VBIAS2LPPA | LPDACSW_VBIAS2PIN | + LPDACSW_VZERO2LPTIA | LPDACSW_VZERO2PIN; + lpdac_cfg.LpDacRef = LPDACREF_2P5; + lpdac_cfg.LpDacSrc = LPDACSRC_MMR; + lpdac_cfg.PowerEn = bTRUE; + AD5940_LPDACCfgS(&lpdac_cfg); + + LPLoopCfg_Type lp_loop; + lp_loop.LpAmpCfg.LpAmpSel = LPAMP0; + lp_loop.LpAmpCfg.LpAmpPwrMod = LPAMPPWR_NORM; + lp_loop.LpAmpCfg.LpPaPwrEn = bTRUE; + lp_loop.LpAmpCfg.LpTiaPwrEn = bTRUE; + lp_loop.LpAmpCfg.LpTiaRf = CurrentLpTiaRf; + lp_loop.LpAmpCfg.LpTiaRf = CurrentLpTiaRf; + lp_loop.LpAmpCfg.LpTiaRload = LPTIARLOAD_SHORT; + lp_loop.LpAmpCfg.LpTiaRtia = GetLPTIARtia(ConfigLptiaVal); + + // Base Switches + lp_loop.LpAmpCfg.LpTiaSW = + LPTIASW(5) | LPTIASW(2) | LPTIASW(4) | LPTIASW(12) | LPTIASW(13); + + // Apply Short Option + if (GlobalShortRe0Se0) { + lp_loop.LpAmpCfg.LpTiaSW |= LPTIASW(11); + } + + AD5940_LPLoopCfgS(&lp_loop); +} + +void Calibrate_HSDAC(float freq) { + HSDACCal_Type hsdac_cal; + ADCPGACal_Type adcpga_cal; + CLKCfg_Type clk_cfg; + + // Configure Clock based on frequency (matches Do_WaveGen logic) + clk_cfg.ADCClkDiv = ADCCLKDIV_1; + clk_cfg.ADCCLkSrc = ADCCLKSRC_HFOSC; + clk_cfg.SysClkDiv = SYSCLKDIV_1; + clk_cfg.SysClkSrc = SYSCLKSRC_HFOSC; + clk_cfg.HFXTALEn = bFALSE; + clk_cfg.LFOSCEn = bTRUE; + + if (freq > 80000) { + clk_cfg.HfOSC32MHzMode = bTRUE; + clk_cfg.HFOSCEn = bTRUE; + AD5940_CLKCfg(&clk_cfg); + AD5940_HPModeEn(bTRUE); + } else { + clk_cfg.HfOSC32MHzMode = bFALSE; + clk_cfg.HFOSCEn = bTRUE; + AD5940_CLKCfg(&clk_cfg); + AD5940_HPModeEn(bFALSE); + } + + AD5940_AFEPwrBW(AFEPWR_LP, AFEBW_250KHZ); + + adcpga_cal.AdcClkFreq = 16000000; + adcpga_cal.ADCPga = ADCPGA_1P5; + adcpga_cal.ADCSinc2Osr = ADCSINC2OSR_1333; + adcpga_cal.ADCSinc3Osr = ADCSINC3OSR_4; + adcpga_cal.PGACalType = PGACALTYPE_OFFSET; + adcpga_cal.TimeOut10us = 1000; + adcpga_cal.VRef1p11 = 1.11; + adcpga_cal.VRef1p82 = 1.82; + AD5940_ADCPGACal(&adcpga_cal); + + hsdac_cal.ExcitBufGain = EXCITBUFGAIN_2; + hsdac_cal.HsDacGain = HSDACGAIN_1; + hsdac_cal.AfePwrMode = AFEPWR_LP; + hsdac_cal.ADCSinc2Osr = ADCSINC2OSR_1333; + hsdac_cal.ADCSinc3Osr = ADCSINC3OSR_4; + AD5940_HSDACCal(&hsdac_cal); + + hsdac_cal.ExcitBufGain = EXCITBUFGAIN_2; + hsdac_cal.HsDacGain = HSDACGAIN_0P2; + AD5940_HSDACCal(&hsdac_cal); + + hsdac_cal.ExcitBufGain = EXCITBUFGAIN_0P25; + hsdac_cal.HsDacGain = HSDACGAIN_1; + AD5940_HSDACCal(&hsdac_cal); + + hsdac_cal.ExcitBufGain = EXCITBUFGAIN_0P25; + hsdac_cal.HsDacGain = HSDACGAIN_0P2; + AD5940_HSDACCal(&hsdac_cal); +} + +void Configure_Filters(float freq) { + ADCFilterCfg_Type adc_filter; + DFTCfg_Type dft_cfg; + FIFOCfg_Type fifo_cfg; + + fifo_cfg.FIFOEn = bFALSE; + fifo_cfg.FIFOMode = FIFOMODE_FIFO; + fifo_cfg.FIFOSize = FIFOSIZE_4KB; + fifo_cfg.FIFOSrc = FIFOSRC_DFT; + fifo_cfg.FIFOThresh = 2; + AD5940_FIFOCfg(&fifo_cfg); + fifo_cfg.FIFOEn = bTRUE; + AD5940_FIFOCfg(&fifo_cfg); + + AD5940_ADCMuxCfgS(ADCMUXP_HSTIA_P, ADCMUXN_HSTIA_N); + AD5940_StructInit(&adc_filter, sizeof(adc_filter)); + AD5940_StructInit(&dft_cfg, sizeof(dft_cfg)); + + if (freq < 0.51f) { + adc_filter.ADCAvgNum = ADCAVGNUM_16; + adc_filter.ADCSinc2Osr = ADCSINC2OSR_267; + adc_filter.ADCSinc3Osr = ADCSINC3OSR_5; + adc_filter.BpNotch = bTRUE; + adc_filter.BpSinc3 = bFALSE; + adc_filter.Sinc2NotchEnable = bTRUE; + adc_filter.ADCRate = ADCRATE_800KHZ; + dft_cfg.DftNum = DFTNUM_8192; + dft_cfg.DftSrc = DFTSRC_SINC2NOTCH; + } else if (freq < 5.0f) { + adc_filter.ADCAvgNum = ADCAVGNUM_16; + adc_filter.ADCSinc2Osr = ADCSINC2OSR_178; + adc_filter.ADCSinc3Osr = ADCSINC3OSR_4; + adc_filter.BpNotch = bTRUE; + adc_filter.BpSinc3 = bFALSE; + adc_filter.Sinc2NotchEnable = bTRUE; + adc_filter.ADCRate = ADCRATE_800KHZ; + dft_cfg.DftNum = DFTNUM_8192; + dft_cfg.DftSrc = DFTSRC_SINC2NOTCH; + } else if (freq < 450.0f) { + adc_filter.ADCAvgNum = ADCAVGNUM_16; + adc_filter.ADCSinc2Osr = ADCSINC2OSR_44; + adc_filter.ADCSinc3Osr = ADCSINC3OSR_4; + adc_filter.BpNotch = bTRUE; + adc_filter.BpSinc3 = bFALSE; + adc_filter.Sinc2NotchEnable = bTRUE; + adc_filter.ADCRate = ADCRATE_800KHZ; + dft_cfg.DftNum = DFTNUM_4096; + dft_cfg.DftSrc = DFTSRC_SINC2NOTCH; + } else if (freq < 80000.0f) { + adc_filter.ADCAvgNum = ADCAVGNUM_16; + adc_filter.ADCSinc2Osr = ADCSINC2OSR_178; + adc_filter.ADCSinc3Osr = ADCSINC3OSR_4; + adc_filter.BpNotch = bTRUE; + adc_filter.BpSinc3 = bFALSE; + adc_filter.Sinc2NotchEnable = bFALSE; + adc_filter.ADCRate = ADCRATE_800KHZ; + dft_cfg.DftNum = DFTNUM_16384; + dft_cfg.DftSrc = DFTSRC_SINC3; + } else { + adc_filter.ADCAvgNum = ADCAVGNUM_16; + adc_filter.ADCSinc2Osr = ADCSINC2OSR_178; + adc_filter.ADCSinc3Osr = ADCSINC3OSR_2; + adc_filter.BpNotch = bTRUE; + adc_filter.BpSinc3 = bFALSE; + adc_filter.Sinc2NotchEnable = bFALSE; + adc_filter.ADCRate = ADCRATE_1P6MHZ; + dft_cfg.DftNum = DFTNUM_16384; + dft_cfg.DftSrc = DFTSRC_SINC3; + } + dft_cfg.HanWinEn = bTRUE; + + AD5940_ADCFilterCfgS(&adc_filter); + AD5940_DFTCfgS(&dft_cfg); +} + +void Do_WaveGen(float freq) { + CLKCfg_Type clk_cfg; + AFERefCfg_Type aferef_cfg; + HSLoopCfg_Type HpLoopCfg; + ADCBaseCfg_Type adc_base; + + clk_cfg.ADCClkDiv = ADCCLKDIV_1; + clk_cfg.ADCCLkSrc = ADCCLKSRC_HFOSC; + clk_cfg.SysClkDiv = SYSCLKDIV_1; + clk_cfg.SysClkSrc = SYSCLKSRC_HFOSC; + clk_cfg.HFXTALEn = bFALSE; + clk_cfg.LFOSCEn = bTRUE; + + if (freq > 80000) { + clk_cfg.HfOSC32MHzMode = bTRUE; + clk_cfg.HFOSCEn = bTRUE; + AD5940_CLKCfg(&clk_cfg); + AD5940_HPModeEn(bTRUE); + } else { + clk_cfg.HfOSC32MHzMode = bFALSE; + clk_cfg.HFOSCEn = bTRUE; + AD5940_CLKCfg(&clk_cfg); + AD5940_HPModeEn(bFALSE); + } + + aferef_cfg.HpBandgapEn = bTRUE; + aferef_cfg.Hp1V1BuffEn = bTRUE; + aferef_cfg.Hp1V8BuffEn = bTRUE; + aferef_cfg.Disc1V1Cap = bFALSE; + aferef_cfg.Disc1V8Cap = bFALSE; + aferef_cfg.Hp1V8ThemBuff = bFALSE; + aferef_cfg.Hp1V8Ilimit = bFALSE; + aferef_cfg.Lp1V1BuffEn = bFALSE; + aferef_cfg.Lp1V8BuffEn = bFALSE; + aferef_cfg.LpBandgapEn = bTRUE; + aferef_cfg.LpRefBufEn = bTRUE; + aferef_cfg.LpRefBoostEn = bFALSE; + AD5940_REFCfgS(&aferef_cfg); + + HpLoopCfg.HsDacCfg.ExcitBufGain = EXCITBUFGAIN_2; + HpLoopCfg.HsDacCfg.HsDacGain = HSDACGAIN_1; + HpLoopCfg.HsDacCfg.HsDacUpdateRate = (freq > 80000) ? 0x07 : 0x1B; + + HpLoopCfg.HsTiaCfg.DiodeClose = bFALSE; + HpLoopCfg.HsTiaCfg.HstiaBias = HSTIABIAS_1P1; + HpLoopCfg.HsTiaCfg.HstiaCtia = 16; + HpLoopCfg.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_0R; + HpLoopCfg.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_TODE; + HpLoopCfg.HsTiaCfg.HstiaRtiaSel = GetHSTIARtia(ConfigHstiaVal); + + adc_base.ADCPga = ADCPGA_1P5; + AD5940_ADCBaseCfgS(&adc_base); + + // --- Switch Matrix Configuration (Manual Sweep) --- + HpLoopCfg.SWMatCfg.Dswitch = SWD_CE0; + HpLoopCfg.SWMatCfg.Pswitch = SWP_CE0; + HpLoopCfg.SWMatCfg.Nswitch = SWN_SE0; + // T-Switch: Connect SE0LOAD to T-Node + HpLoopCfg.SWMatCfg.Tswitch = SWT_SE0LOAD; + + AD5940_AFECtrlS(AFECTRL_WG, bFALSE); + + HpLoopCfg.WgCfg.WgType = WGTYPE_SIN; + HpLoopCfg.WgCfg.GainCalEn = bFALSE; + HpLoopCfg.WgCfg.OffsetCalEn = bFALSE; + HpLoopCfg.WgCfg.SinCfg.SinFreqWord = + AD5940_WGFreqWordCal(freq, (freq > 80000) ? 32000000.0 : 16000000.0); + + // Reduced Amplitude: 50mV peak (100mV pp) to prevent saturation + // Range is +/- 607mV with Gain 2/1. + // 50 / 607 * 2047 = ~168 + HpLoopCfg.WgCfg.SinCfg.SinAmplitudeWord = + (uint32_t)(50.0f / 607.0f * 2047 + 0.5f); + HpLoopCfg.WgCfg.SinCfg.SinOffsetWord = 0; + HpLoopCfg.WgCfg.SinCfg.SinPhaseWord = 0; + AD5940_HSLoopCfgS(&HpLoopCfg); + + AD5940_AFECtrlS(AFECTRL_DACREFPWR, bTRUE); + AD5940_AFECtrlS(AFECTRL_EXTBUFPWR | AFECTRL_INAMPPWR | AFECTRL_HSTIAPWR | + AFECTRL_HSDACPWR, + bTRUE); + AD5940_AFECtrlS(AFECTRL_WG, bTRUE); + AD5940_AFECtrlS(AFECTRL_DCBUFPWR, bTRUE); + AD5940_AFEPwrBW(AFEPWR_LP, AFEBW_250KHZ); +} \ No newline at end of file diff --git a/examples/rp2040_port/Measurement_Routines.c b/examples/rp2040_port/Measurement_Routines.c new file mode 100644 index 0000000..b966ce7 --- /dev/null +++ b/examples/rp2040_port/Measurement_Routines.c @@ -0,0 +1,573 @@ +// File: Measurement_Routines.c +#include "App_Common.h" +#include "Impedance.h" + +// Forward declaration if not in header +// int32_t ImpedanceShowResult(uint32_t *pData, uint32_t DataCount); + +void Routine_CalibrateLFO(void) { + printf(">> Calibrating LFOSC...\n"); + if (CurrentMode == MODE_IMPEDANCE) + AppIMPCleanup(); + else if (CurrentMode == MODE_AMPEROMETRIC) + AppAMPCtrl(AMPCTRL_SHUTDOWN, 0); + else if (CurrentMode == MODE_RAMP) + AppRAMPCtrl(APPCTRL_SHUTDOWN, 0); + + LFOSCMeasure_Type cal_cfg; + cal_cfg.CalDuration = 1000.0; + cal_cfg.CalSeqAddr = 0; + cal_cfg.SystemClkFreq = 16000000.0; + + if (AD5940_LFOSCMeasure(&cal_cfg, &LFOSCFreq) == AD5940ERR_OK) { + printf(">> LFOSC Calibrated: %.2f Hz\n", LFOSCFreq); + } else { + printf(">> LFOSC Calibration Failed.\n"); + } +} + +// Helper to show results (adapted from test/AD5940Main.c) +void ImpedanceShowResult(uint32_t *pData, uint32_t DataCount) { + float freq; + + fImpPol_Type *pImp = (fImpPol_Type *)pData; + AppIMPCtrl(IMPCTRL_GETFREQ, &freq); + + /*Process data*/ + for (int i = 0; i < DataCount; i++) { + printf("DATA,%.2f,0,0,%.6f,%.6f\n", freq, pImp[i].Magnitude, pImp[i].Phase); + } +} + +void Routine_Measure(float freq, float bias_mv) { + if (CurrentMode == MODE_AMPEROMETRIC) + AppAMPCtrl(AMPCTRL_SHUTDOWN, 0); + else if (CurrentMode == MODE_RAMP) + AppRAMPCtrl(APPCTRL_SHUTDOWN, 0); + CurrentMode = MODE_IMPEDANCE; + + // Cleanup any previous run + AppIMPCleanup(); + + // Initialize Structure + AD5940ImpedanceStructInit(); + + AppIMPCfg_Type *pCfg; + AppIMPGetCfg(&pCfg); + + pCfg->WuptClkFreq = LFOSCFreq; + pCfg->SweepCfg.SweepEn = bFALSE; + pCfg->SinFreq = freq; + pCfg->NumOfData = -1; // Changes based on new logic? Test uses -1 for single + // point? No, test creates sequence. + + // Apply Global Settings + pCfg->ShortRe0Se0 = GlobalShortRe0Se0; + pCfg->HstiaRtiaSel = GetHSTIARtia(ConfigHstiaVal); + // Apply Calibration Values + pCfg->RtiaVal = CalibratedHstiaVal; + pCfg->AdcPhaseOffset = CalibratedHstiaPhase; + pCfg->BiasVolt = bias_mv; + + pCfg->bParaChanged = bTRUE; + + // Initialize App + if (AppIMPInit(AppBuff, APPBUFF_SIZE) != AD5940ERR_OK) { + printf("ERROR: Init Failed\n"); + return; + } + + // Calibrate RTIA (New implementation requires this) + AppIMPRtiaCal(); + + // Start Measurement + AppIMPCtrl(IMPCTRL_START, 0); + + // Poll for result (Blocking, similar to sweep) - or rely on Interrupt? + // The test code uses polling for sweep. For single measure, we can use the + // ISR method currently in main.c, BUT we need to make sure AppIMPInit didn't + // break anything. Actually, let's keep it consistent with the Sweep logic for + // now to ensure it works. + + while (1) { + if (AD5940_GetMCUIntFlag()) { + AD5940_ClrMCUIntFlag(); + uint32_t temp = APPBUFF_SIZE; + AppIMPISR(AppBuff, &temp); + ImpedanceShowResult(AppBuff, temp); + break; + } + // Timeout check? + } +} + +// Sweep Implementation matching test/AD5940Main.c +void Routine_Sweep(float start, float end, int steps, float bias_mv) { + if (CurrentMode == MODE_AMPEROMETRIC) + AppAMPCtrl(AMPCTRL_SHUTDOWN, 0); + else if (CurrentMode == MODE_RAMP) + AppRAMPCtrl(APPCTRL_SHUTDOWN, 0); + CurrentMode = MODE_IMPEDANCE; + + AppIMPCfg_Type *pCfg; + AppIMPGetCfg(&pCfg); + + // Initial Setup + AD5940ImpedanceStructInit(); + pCfg->WuptClkFreq = LFOSCFreq; + pCfg->ShortRe0Se0 = GlobalShortRe0Se0; + pCfg->HstiaRtiaSel = GetHSTIARtia(ConfigHstiaVal); + pCfg->BiasVolt = bias_mv; + + // Apply Calibration Values + pCfg->RtiaVal = CalibratedHstiaVal; + pCfg->AdcPhaseOffset = CalibratedHstiaPhase; + + // Calculate Sweep Points + float log_step = pow(end / start, 1.0 / (steps - 1)); + float curr_freq = start; + + printf("Starting Software Sweep: %.2f Hz to %.2f Hz, %d points\n", start, end, + steps); + + for (int i = 0; i < steps; i++) { + // Check for Abort from UART (User wants to stop) + int c = getchar_timeout_us(0); + if (c == 'x') { + printf("Sweep Aborted by User.\n"); + AppIMPCleanup(); + break; + } + + uint32_t temp; + /* Update Frequency */ + pCfg->SinFreq = curr_freq; + pCfg->bParaChanged = bTRUE; // Force sequence regeneration + + /* Re-Initialize App to apply new frequency (this regenerates sequences) */ + printf("DEBUG: Before Init for %.2f\n", curr_freq); + if (AppIMPInit(AppBuff, APPBUFF_SIZE) != AD5940ERR_OK) { + printf("ERROR: Init failed at %.2f\n", curr_freq); + break; + } + printf("DEBUG: After Init\n"); + + /* Calibrate RTIA at this frequency (Already done in AppIMPInit) */ + // AppIMPRtiaCal(); + + /* Measure Impedance */ + printf("DEBUG: Starting Measurement\n"); + AppIMPCtrl(IMPCTRL_START, 0); + + /* Wait for result */ + int timeout = 100000; // 1s timeout approx + while (timeout > 0) { + if (AD5940_GetMCUIntFlag()) { + // printf("DEBUG: Interrupt Triggered\n"); + AD5940_ClrMCUIntFlag(); + temp = APPBUFF_SIZE; + AppIMPISR(AppBuff, &temp); + + if (temp > 0) { + // printf("DEBUG: ISR processed %d items\n", temp); + ImpedanceShowResult(AppBuff, temp); + break; // Done with this point only if we got data + } else { + // Spurious interrupt or not enough data yet + // printf("DEBUG: Spurious INT, 0 items. Continue waiting.\n"); + } + } + AD5940_Delay10us(1); + timeout--; + } + + if (timeout <= 0) { + printf("timeout at freq: %.2f\n", curr_freq); + } + + /* Next Frequency */ + curr_freq *= log_step; + } + AppIMPCleanup(); // Stop hardware + printf("Sweep Completed.\n"); +} + +void Routine_Amperometric(float bias_mv) { + if (CurrentMode == MODE_IMPEDANCE) + AppIMPCleanup(); + else if (CurrentMode == MODE_RAMP) + AppRAMPCtrl(APPCTRL_SHUTDOWN, 0); + CurrentMode = MODE_AMPEROMETRIC; + + printf(">> Starting Amperometry (Bias: %.1f mV, LP Range: %d)...\n", bias_mv, + ConfigLptiaVal); + + AppAMPCfg_Type *pCfg; + AppAMPGetCfg(&pCfg); + AD5940AMPStructInit(); // Reload config with current LP settings + pCfg->SensorBias = bias_mv; + pCfg->ReDoRtiaCal = bFALSE; // Use pre-calibrated value + + if (AppAMPInit(AppBuff, APPBUFF_SIZE) == AD5940ERR_OK) { + AppAMPCtrl(AMPCTRL_START, 0); + } else { + printf("ERROR: AMP Init Failed\n"); + } +} + +void Routine_LSV(float start_mv, float end_mv, int steps, int duration_ms) { + if (CurrentMode == MODE_IMPEDANCE) + AppIMPCleanup(); + else if (CurrentMode == MODE_AMPEROMETRIC) + AppAMPCtrl(AMPCTRL_SHUTDOWN, 0); + CurrentMode = MODE_RAMP; + + printf( + ">> Starting LSV (%.1f to %.1f mV, %d steps, %d ms, LP Range: %d)...\n", + start_mv, end_mv, steps, duration_ms, ConfigLptiaVal); + + AppRAMPCfg_Type *pCfg; + AppRAMPGetCfg(&pCfg); + AD5940RampStructInit(); // Reload config with current LP settings + + pCfg->RampStartVolt = start_mv; + pCfg->RampPeakVolt = end_mv; + pCfg->StepNumber = steps; + pCfg->RampDuration = duration_ms; + pCfg->bRampOneDir = bTRUE; + pCfg->bParaChanged = bTRUE; + + if (AppRAMPInit(AppBuff, APPBUFF_SIZE) == AD5940ERR_OK) { + AppRAMPCtrl(APPCTRL_START, 0); + } else { + printf("ERROR: RAMP Init Failed\n"); + } +} + +extern void __AD5940_ReferenceON(void); + +// Custom LPTIA Calibration using Internal HSTIA as Reference +// Routing: Excitation -> RE0/CE0, Short SE0 +// This allows using HSTIA internal RTIA (e.g. 1k, 5k, etc) as the reference +// Rcal instead of the fixed external 100 Ohm Rcal which causes saturation. +AD5940Err AD5940_LPRtiaCal_UserCustom(LPRTIACal_Type *pCalCfg, void *pResult) { + HSLoopCfg_Type hs_loop; + LPLoopCfg_Type lp_loop; + DSPCfg_Type dsp_cfg; + ADCBaseCfg_Type *pADCBaseCfg; + SWMatrixCfg_Type *pSWCfg; + uint32_t INTCCfg; + BoolFlag bADCClk32MHzMode = bFALSE; + + float ExcitVolt; + uint32_t RtiaVal; + uint32_t const LpRtiaTable[] = { + 0, 110, 1000, 2000, 3000, 4000, 6000, 8000, 10000, + 12000, 16000, 20000, 24000, 30000, 32000, 40000, 48000, 64000, + 85000, 96000, 100000, 120000, 128000, 160000, 196000, 256000, 512000}; + float const ADCPGAGainTable[] = {1, 1.5, 2, 4, 9}; + uint32_t WgAmpWord; + uint32_t ADCPgaGainRtia, ADCPgaGainRcal; + float GainRatio; + iImpCar_Type DftRcal, DftRtia; + + if (pCalCfg == NULL) + return AD5940ERR_NULLP; + if (pResult == NULL) + return AD5940ERR_NULLP; + + if (pCalCfg->AdcClkFreq > (32000000 * 0.8)) + bADCClk32MHzMode = bTRUE; + + // Initialize Pointers + pSWCfg = &hs_loop.SWMatCfg; + pADCBaseCfg = &dsp_cfg.ADCBaseCfg; + + RtiaVal = LpRtiaTable[pCalCfg->LpTiaRtia]; + + // Calculate Excitation Voltage + // Note: We are using HSTIA as Reference (Rcal). + // Let's assume we use 1k Internal HSTIA RTIA as Rcal for this calculation to + // aim for 800mVpp + float RcalEffective = 1000.0f; // Approximate + ExcitVolt = 2000 * 0.8 * RcalEffective / RtiaVal; + WgAmpWord = ((uint32_t)(ExcitVolt / 2200 * 2047 * 2) + 1) >> 1; + if (WgAmpWord > 0x7FF) + WgAmpWord = 0x7FF; + + // Store original AFECON + // uint32_t reg_afecon = AD5940_ReadReg(REG_AFE_AFECON); // Unused in this + // snippet but good practice to restore if needed + + // INTC Config + INTCCfg = AD5940_INTCGetCfg(AFEINTC_1); + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_DFTRDY | AFEINTSRC_SINC2RDY, bTRUE); + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); + /* Helper to turn on reference - adapted from AD5940_ReferenceON */ + AFERefCfg_Type aferef_cfg; + aferef_cfg.HpBandgapEn = bTRUE; + aferef_cfg.Hp1V1BuffEn = bTRUE; + aferef_cfg.Hp1V8BuffEn = bTRUE; + aferef_cfg.Disc1V1Cap = bFALSE; + aferef_cfg.Disc1V8Cap = bFALSE; + aferef_cfg.Hp1V8ThemBuff = bFALSE; + aferef_cfg.Hp1V8Ilimit = bFALSE; + aferef_cfg.Lp1V1BuffEn = bFALSE; + aferef_cfg.Lp1V8BuffEn = bFALSE; + aferef_cfg.LpBandgapEn = bTRUE; + aferef_cfg.LpRefBufEn = bTRUE; + aferef_cfg.LpRefBoostEn = bFALSE; + AD5940_REFCfgS(&aferef_cfg); + + // __AD5940_ReferenceON(); + + // DSP Config + AD5940_StructInit(&dsp_cfg, sizeof(dsp_cfg)); + dsp_cfg.ADCFilterCfg.ADCAvgNum = ADCAVGNUM_16; + dsp_cfg.ADCFilterCfg.ADCRate = + bADCClk32MHzMode ? ADCRATE_1P6MHZ : ADCRATE_800KHZ; + dsp_cfg.ADCFilterCfg.ADCSinc2Osr = pCalCfg->ADCSinc2Osr; + dsp_cfg.ADCFilterCfg.ADCSinc3Osr = pCalCfg->ADCSinc3Osr; + dsp_cfg.ADCFilterCfg.BpNotch = bTRUE; + dsp_cfg.ADCFilterCfg.BpSinc3 = bFALSE; + dsp_cfg.ADCFilterCfg.Sinc2NotchEnable = bTRUE; + memcpy(&dsp_cfg.DftCfg, &pCalCfg->DftCfg, sizeof(pCalCfg->DftCfg)); + AD5940_DSPCfgS(&dsp_cfg); + + // LP Loop Config + AD5940_StructInit(&lp_loop, sizeof(lp_loop)); + lp_loop.LpDacCfg.LpdacSel = LPDAC0; + lp_loop.LpDacCfg.DacData12Bit = 0x800; + lp_loop.LpDacCfg.DacData6Bit = 32; + lp_loop.LpDacCfg.DataRst = bFALSE; + lp_loop.LpDacCfg.LpDacSW = + LPDACSW_VBIAS2LPPA | LPDACSW_VZERO2HSTIA; // Vzero to HSTIA + lp_loop.LpDacCfg.LpDacRef = LPDACREF_2P5; + lp_loop.LpDacCfg.LpDacSrc = LPDACSRC_WG; + lp_loop.LpDacCfg.LpDacVbiasMux = LPDACVBIAS_6BIT; + lp_loop.LpDacCfg.LpDacVzeroMux = LPDACVZERO_12BIT; + lp_loop.LpDacCfg.PowerEn = bTRUE; + + lp_loop.LpAmpCfg.LpAmpSel = pCalCfg->LpAmpSel; + lp_loop.LpAmpCfg.LpAmpPwrMod = pCalCfg->LpAmpPwrMod; + lp_loop.LpAmpCfg.LpPaPwrEn = bTRUE; + lp_loop.LpAmpCfg.LpTiaPwrEn = bTRUE; + lp_loop.LpAmpCfg.LpTiaRload = LPTIARLOAD_100R; + lp_loop.LpAmpCfg.LpTiaRtia = pCalCfg->LpTiaRtia; + lp_loop.LpAmpCfg.LpTiaRf = LPTIARF_OPEN; + // Use User Routing for LPTIA Switches if needed, but standard should work for + // TIA part + lp_loop.LpAmpCfg.LpTiaSW = + LPTIASW(6) | LPTIASW(8) | (pCalCfg->bWithCtia == bTRUE ? LPTIASW(5) : 0); + AD5940_LPLoopCfgS(&lp_loop); + + // HS Loop Config + AD5940_StructInit(&hs_loop, sizeof(hs_loop)); + hs_loop.HsTiaCfg.DiodeClose = bFALSE; + hs_loop.HsTiaCfg.HstiaBias = HSTIABIAS_VZERO0; // Bias from LPDAC Vzero + hs_loop.HsTiaCfg.HstiaCtia = 31; + hs_loop.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_OPEN; + hs_loop.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_OPEN; + hs_loop.HsTiaCfg.HstiaDe1Rload = HSTIADERLOAD_OPEN; + hs_loop.HsTiaCfg.HstiaDe1Rtia = HSTIADERTIA_OPEN; + // Use 1k Internal RTIA as Reference (or match approximate LPTIA range if + // possible, but 1k is a safe start) + hs_loop.HsTiaCfg.HstiaRtiaSel = HSTIARTIA_1K; + + hs_loop.HsDacCfg.ExcitBufGain = 0; + hs_loop.HsDacCfg.HsDacGain = 0; + hs_loop.HsDacCfg.HsDacUpdateRate = 255; + + // USER ROUTING: RE0, CE0, SE0(Short) + // Dswitch: Connect SE0 + // Pswitch: Connect RE0 + // Nswitch: Connect SE0LOAD? Or use SE0 as N? + // User said "utilizing reo and setting it to re0 and ce0 then shorting se0" + // -> SE0 is shorted to RE0? Let's try standard Ladder Routing logic: + // Excitation via CE0/RE0 (P/N switches?) or High Power loop? + // Actually, for LPTIA Cal, we use LPDAC/WG. + // We need to route the current through LPTIA and the Reference. + // Standard Cal uses RCAL0/RCAL1. + // We want to use HSTIA. + // Connect HSTIA to SE0? + + // Implementation based on interpretation: + // SWP = RE0 (Excitation P side) + // SWN = SE0 (Excitation N side?) No, SE0 is usually sense. + // SWT = TRTIA (Connects HSTIA to T-Matrix) + + hs_loop.SWMatCfg.Dswitch = SWD_SE0; + hs_loop.SWMatCfg.Pswitch = SWP_RE0 | SWP_CE0; // "setting it to re0 and ce0" + hs_loop.SWMatCfg.Nswitch = + SWN_SE0; // "shorting se0" - maybe use SE0 as return? + hs_loop.SWMatCfg.Tswitch = + SWT_TRTIA | SWT_SE0LOAD; // Connect HSTIA and SE0LOAD? + + AD5940_HSLoopCfgS(&hs_loop); + + // Waveform Generator + hs_loop.WgCfg.WgType = WGTYPE_SIN; + hs_loop.WgCfg.GainCalEn = bTRUE; + hs_loop.WgCfg.OffsetCalEn = bTRUE; + hs_loop.WgCfg.SinCfg.SinFreqWord = + AD5940_WGFreqWordCal(pCalCfg->fFreq, pCalCfg->SysClkFreq); + hs_loop.WgCfg.SinCfg.SinAmplitudeWord = WgAmpWord; + hs_loop.WgCfg.SinCfg.SinOffsetWord = 0; + hs_loop.WgCfg.SinCfg.SinPhaseWord = 0; + AD5940_HSLoopCfgS(&hs_loop); + + AD5940_AFECtrlS(AFECTRL_HSTIAPWR | AFECTRL_INAMPPWR | AFECTRL_EXTBUFPWR | + AFECTRL_SINC2NOTCH, + bTRUE); + + // 1. Measure Reference (HSTIA Internal RTIA) + // We need to measure voltage across HSTIA. + // Mux P = HSTIA_P, Mux N = HSTIA_N + AD5940_ADCMuxCfgS(ADCMUXP_HSTIA_P, ADCMUXN_HSTIA_N); + AD5940_AFECtrlS(AFECTRL_WG | AFECTRL_ADCPWR, bTRUE); + AD5940_Delay10us(25); + AD5940_AFECtrlS(AFECTRL_ADCCNV | AFECTRL_DFT, bTRUE); + while (AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_DFTRDY) == bFALSE) + ; + AD5940_AFECtrlS(AFECTRL_ADCCNV | AFECTRL_DFT | AFECTRL_WG | AFECTRL_ADCPWR, + bFALSE); + AD5940_INTCClrFlag(AFEINTSRC_DFTRDY); + + DftRcal.Real = AD5940_ReadAfeResult(AFERESULT_DFTREAL); + DftRcal.Image = AD5940_ReadAfeResult(AFERESULT_DFTIMAGE); + + // 2. Measure LPTIA + // Mux P = LPTIA_P, Mux N = LPTIA_N + AD5940_ADCMuxCfgS(ADCMUXP_LPTIA0_P, ADCMUXN_LPTIA0_N); + AD5940_AFECtrlS(AFECTRL_WG | AFECTRL_ADCPWR, bTRUE); + AD5940_Delay10us(25); + AD5940_AFECtrlS(AFECTRL_ADCCNV | AFECTRL_DFT, bTRUE); + while (AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_DFTRDY) == bFALSE) + ; + AD5940_AFECtrlS(AFECTRL_ADCCNV | AFECTRL_DFT | AFECTRL_WG | AFECTRL_ADCPWR, + bFALSE); + AD5940_INTCClrFlag(AFEINTSRC_DFTRDY); + + DftRtia.Real = AD5940_ReadAfeResult(AFERESULT_DFTREAL); + DftRtia.Image = AD5940_ReadAfeResult(AFERESULT_DFTIMAGE); + + // Calculation: Rtia = (V_Rtia / V_Rcal) * Rcal_Value + // Here Rcal_Value is 1000 Ohm (HSTIA 1k) + fImpCar_Type temp; + temp = AD5940_ComplexDivInt(&DftRtia, &DftRcal); + temp.Real *= 1000.0f; + temp.Image *= 1000.0f; + + if (pCalCfg->bPolarResult == bFALSE) { + *(fImpCar_Type *)pResult = temp; + } else { + ((fImpPol_Type *)pResult)->Magnitude = AD5940_ComplexMag(&temp); + ((fImpPol_Type *)pResult)->Phase = AD5940_ComplexPhase(&temp); + } + + // Restore INTC + if (INTCCfg & AFEINTSRC_DFTRDY) + ; + else + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_DFTRDY, bFALSE); + + return AD5940ERR_OK; +} + +void Routine_CalibrateSystem(void) { + if (CurrentMode == MODE_AMPEROMETRIC) + AppAMPCtrl(AMPCTRL_SHUTDOWN, 0); + else if (CurrentMode == MODE_RAMP) + AppRAMPCtrl(APPCTRL_SHUTDOWN, 0); + CurrentMode = MODE_IMPEDANCE; + + AppIMPCfg_Type *pCfg; + AppIMPGetCfg(&pCfg); + AppIMPCleanup(); + + ADCPGACal_Type adcpga_cal; + adcpga_cal.AdcClkFreq = 16000000.0; + adcpga_cal.SysClkFreq = 16000000.0; + adcpga_cal.ADCSinc3Osr = ADCSINC3OSR_4; + adcpga_cal.ADCSinc2Osr = ADCSINC2OSR_22; + adcpga_cal.ADCPga = ADCPGA_1P5; + adcpga_cal.PGACalType = PGACALTYPE_OFFSET; + adcpga_cal.TimeOut10us = 1000; + adcpga_cal.VRef1p11 = 1.11; + adcpga_cal.VRef1p82 = 1.82; + printf(">> Calibrating ADC Offset...\n"); + AD5940_ADCPGACal(&adcpga_cal); + + /* LPTIA Calibration Removed for HSTIA-Only Mode */ + // --- 1. Calibrate LPTIA (Low Power Loop) --- + /* + LPRTIACal_Type lprtia_cal; + fImpPol_Type LpRes; + memset(&lprtia_cal, 0, sizeof(lprtia_cal)); + lprtia_cal.AdcClkFreq = 16000000.0; + lprtia_cal.SysClkFreq = 16000000.0; + lprtia_cal.ADCSinc3Osr = ADCSINC3OSR_4; + lprtia_cal.ADCSinc2Osr = ADCSINC2OSR_22; + lprtia_cal.bPolarResult = bTRUE; + lprtia_cal.fRcal = pCfg->RcalVal; + lprtia_cal.LpTiaRtia = GetLPTIARtia(ConfigLptiaVal); + lprtia_cal.LpAmpPwrMod = LPAMPPWR_NORM; + lprtia_cal.bWithCtia = bFALSE; + lprtia_cal.fFreq = 100.0f; + lprtia_cal.DftCfg.DftNum = DFTNUM_2048; + lprtia_cal.DftCfg.DftSrc = DFTSRC_SINC3; + lprtia_cal.DftCfg.HanWinEn = bTRUE; + + printf(">> Calibrating LPTIA %d Ohm using Custom Routing (HSTIA Ref)...\n", + ConfigLptiaVal); + + // CALL CUSTOM CALIBRATION FUNCTION + if (AD5940_LPRtiaCal_UserCustom(&lprtia_cal, &LpRes) == AD5940ERR_OK) { + printf("RCAL,LPTIA,%f,%f\n", LpRes.Magnitude, LpRes.Phase); + CalibratedLptiaVal = LpRes.Magnitude; + } else { + printf("RCAL,LPTIA,FAIL\n"); + } + */ + + // --- 2. Calibrate HSTIA (High Speed Loop) --- + HSDACCfg_Type hsdac_cfg; + hsdac_cfg.ExcitBufGain = EXCITBUFGAIN_0P25; + hsdac_cfg.HsDacGain = HSDACGAIN_0P2; + hsdac_cfg.HsDacUpdateRate = 7; + AD5940_HSDacCfgS(&hsdac_cfg); + + HSRTIACal_Type hsrtia_cal; + fImpPol_Type HsRes; + memset(&hsrtia_cal, 0, sizeof(hsrtia_cal)); + hsrtia_cal.fFreq = 1000.0f; + hsrtia_cal.AdcClkFreq = 16000000.0; + hsrtia_cal.SysClkFreq = 16000000.0; // Orig was 16M + hsrtia_cal.ADCSinc3Osr = ADCSINC3OSR_4; + hsrtia_cal.ADCSinc2Osr = ADCSINC2OSR_22; + hsrtia_cal.bPolarResult = bTRUE; + hsrtia_cal.fRcal = 100.0; + hsrtia_cal.HsTiaCfg.DiodeClose = bFALSE; + hsrtia_cal.HsTiaCfg.HstiaBias = HSTIABIAS_1P1; + hsrtia_cal.HsTiaCfg.HstiaCtia = 31; + hsrtia_cal.HsTiaCfg.HstiaRtiaSel = GetHSTIARtia(ConfigHstiaVal); + hsrtia_cal.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_OPEN; + hsrtia_cal.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_OPEN; + hsrtia_cal.DftCfg.DftNum = DFTNUM_16384; + hsrtia_cal.DftCfg.DftSrc = DFTSRC_SINC3; + + printf(">> Calibrating HSTIA %d Ohm...\n", ConfigHstiaVal); + if (AD5940_HSRtiaCal(&hsrtia_cal, &HsRes) == AD5940ERR_OK) { + printf("RCAL,HSTIA,%f,%f\n", HsRes.Magnitude, HsRes.Phase); + CalibratedHstiaVal = HsRes.Magnitude; + CalibratedHstiaPhase = HsRes.Phase; // Store Phase for correction + } else { + printf("RCAL,HSTIA,FAIL\n"); + } + + // Cleanup to prevent spurious interrupts in main loop + AppIMPCleanup(); + CurrentMode = MODE_IDLE; +} \ No newline at end of file diff --git a/examples/rp2040_port/RampTest.c b/examples/rp2040_port/RampTest.c new file mode 100644 index 0000000..7df5e75 --- /dev/null +++ b/examples/rp2040_port/RampTest.c @@ -0,0 +1,596 @@ +// File: RampTest.c +#include "ad5940.h" +#include +#include "string.h" +#include "math.h" +#include "RampTest.h" + +#define AD5940ERR_STOP 10 + +AppRAMPCfg_Type AppRAMPCfg = +{ + .bParaChanged = bFALSE, + .SeqStartAddr = 0, + .MaxSeqLen = 0, + .SeqStartAddrCal = 0, + .MaxSeqLenCal = 0, + + .LFOSCClkFreq = 32000.0, + .SysClkFreq = 16000000.0, + .AdcClkFreq = 16000000.0, + .RcalVal = 100.0, + .ADCRefVolt = 1820.0f, + .bTestFinished = bFALSE, + + .RampStartVolt = -500.0f, + .RampPeakVolt = +500.0f, + .VzeroStart = 1100.0f, + .VzeroPeak = 1100.0f, + .StepNumber = 100, + .RampDuration = 10000, + + .SampleDelay = 1.0f, + .LPTIARtiaSel = LPTIARTIA_4K, + .LpTiaRf = LPTIARF_20K, /* Default LPF */ + .ExternalRtiaValue = 20000.0f, + .AdcPgaGain = ADCPGA_1P5, + .ADCSinc3Osr = ADCSINC3OSR_2, + .FifoThresh = 4, + + .RAMPInited = bFALSE, + .StopRequired = bFALSE, + .RampState = RAMP_STATE0, + .bFirstDACSeq = bTRUE, + .bRampOneDir = bFALSE, + .ShortRe0Se0 = bFALSE, +}; + +AD5940Err AppRAMPGetCfg(void *pCfg) +{ + if(pCfg) + { + *(AppRAMPCfg_Type **)pCfg = &AppRAMPCfg; + return AD5940ERR_OK; + } + return AD5940ERR_PARA; +} + +AD5940Err AppRAMPCtrl(uint32_t Command, void *pPara) +{ + switch (Command) + { + case APPCTRL_START: + { + WUPTCfg_Type wupt_cfg; + + if(AD5940_WakeUp(10) > 10) return AD5940ERR_WAKEUP; + if(AppRAMPCfg.RAMPInited == bFALSE) return AD5940ERR_APPERROR; + + // --- CRITICAL FIX: Reset State on Start --- + AppRAMPCfg.RampState = RAMP_STATE0; + AppRAMPCfg.CurrStepPos = 0; + AppRAMPCfg.bFirstDACSeq = bTRUE; + AppRAMPCfg.StopRequired = bFALSE; + AppRAMPCfg.FifoThresh = 4; + // ------------------------------------------ + + wupt_cfg.WuptEn = bTRUE; + wupt_cfg.WuptEndSeq = WUPTENDSEQ_D; + wupt_cfg.WuptOrder[0] = SEQID_0; + wupt_cfg.WuptOrder[1] = SEQID_2; + wupt_cfg.WuptOrder[2] = SEQID_1; + wupt_cfg.WuptOrder[3] = SEQID_2; + wupt_cfg.SeqxSleepTime[SEQID_2] = 4; + wupt_cfg.SeqxWakeupTime[SEQID_2] = (uint32_t)(AppRAMPCfg.LFOSCClkFreq * AppRAMPCfg.SampleDelay / 1000.0f) - 4 - 2; + wupt_cfg.SeqxSleepTime[SEQID_0] = 4; + wupt_cfg.SeqxWakeupTime[SEQID_0] = (uint32_t)(AppRAMPCfg.LFOSCClkFreq * (AppRAMPCfg.RampDuration / AppRAMPCfg.StepNumber - AppRAMPCfg.SampleDelay) / 1000.0f) - 4 - 2; + wupt_cfg.SeqxSleepTime[SEQID_1] = wupt_cfg.SeqxSleepTime[SEQID_0]; + wupt_cfg.SeqxWakeupTime[SEQID_1] = wupt_cfg.SeqxWakeupTime[SEQID_0]; + AD5940_WUPTCfg(&wupt_cfg); + break; + } + case APPCTRL_STOPNOW: + { + if(AD5940_WakeUp(10) > 10) return AD5940ERR_WAKEUP; + AD5940_WUPTCtrl(bFALSE); + AD5940_WUPTCtrl(bFALSE); + break; + } + case APPCTRL_STOPSYNC: + { + AppRAMPCfg.StopRequired = bTRUE; + break; + } + case APPCTRL_SHUTDOWN: + { + AppRAMPCtrl(APPCTRL_STOPNOW, 0); + AD5940_ShutDownS(); + break; + } + default: + break; + } + return AD5940ERR_OK; +} + +static AD5940Err AppRAMPSeqInitGen(void) +{ + AD5940Err error = AD5940ERR_OK; + const uint32_t *pSeqCmd; + uint32_t SeqLen; + AFERefCfg_Type aferef_cfg; + LPLoopCfg_Type lploop_cfg; + DSPCfg_Type dsp_cfg; + + AD5940_SEQGenCtrl(bTRUE); + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); + + aferef_cfg.HpBandgapEn = bTRUE; + aferef_cfg.Hp1V1BuffEn = bTRUE; + aferef_cfg.Hp1V8BuffEn = bTRUE; + aferef_cfg.Disc1V1Cap = bFALSE; + aferef_cfg.Disc1V8Cap = bFALSE; + aferef_cfg.Hp1V8ThemBuff = bFALSE; + aferef_cfg.Hp1V8Ilimit = bFALSE; + aferef_cfg.Lp1V1BuffEn = bTRUE; + aferef_cfg.Lp1V8BuffEn = bTRUE; + aferef_cfg.LpBandgapEn = bTRUE; + aferef_cfg.LpRefBufEn = bTRUE; + aferef_cfg.LpRefBoostEn = bFALSE; + AD5940_REFCfgS(&aferef_cfg); + + lploop_cfg.LpAmpCfg.LpAmpSel = LPAMP0; + lploop_cfg.LpAmpCfg.LpAmpPwrMod = LPAMPPWR_NORM; + lploop_cfg.LpAmpCfg.LpPaPwrEn = bTRUE; + lploop_cfg.LpAmpCfg.LpTiaPwrEn = bTRUE; + lploop_cfg.LpAmpCfg.LpTiaRf = AppRAMPCfg.LpTiaRf; // Use Configured LPF + lploop_cfg.LpAmpCfg.LpTiaRload = LPTIARLOAD_10R; + lploop_cfg.LpAmpCfg.LpTiaRtia = AppRAMPCfg.LPTIARtiaSel; + + lploop_cfg.LpAmpCfg.LpTiaSW = LPTIASW(5)|LPTIASW(2)|LPTIASW(4)|LPTIASW(12)|LPTIASW(13); + + // Apply Short Option + if(AppRAMPCfg.ShortRe0Se0) { + lploop_cfg.LpAmpCfg.LpTiaSW |= LPTIASW(11); + } + + lploop_cfg.LpDacCfg.LpdacSel = LPDAC0; + lploop_cfg.LpDacCfg.DacData12Bit = 0x800; + lploop_cfg.LpDacCfg.DacData6Bit = 0; + lploop_cfg.LpDacCfg.DataRst = bFALSE; + lploop_cfg.LpDacCfg.LpDacSW = LPDACSW_VBIAS2LPPA|LPDACSW_VBIAS2PIN|LPDACSW_VZERO2LPTIA|LPDACSW_VZERO2PIN; + lploop_cfg.LpDacCfg.LpDacRef = LPDACREF_2P5; + lploop_cfg.LpDacCfg.LpDacSrc = LPDACSRC_MMR; + lploop_cfg.LpDacCfg.LpDacVbiasMux = LPDACVBIAS_12BIT; + lploop_cfg.LpDacCfg.LpDacVzeroMux = LPDACVZERO_6BIT; + lploop_cfg.LpDacCfg.PowerEn = bTRUE; + AD5940_LPLoopCfgS(&lploop_cfg); + + AD5940_StructInit(&dsp_cfg, sizeof(dsp_cfg)); + dsp_cfg.ADCBaseCfg.ADCMuxN = ADCMUXN_LPTIA0_N; + dsp_cfg.ADCBaseCfg.ADCMuxP = ADCMUXP_LPTIA0_P; + dsp_cfg.ADCBaseCfg.ADCPga = AppRAMPCfg.AdcPgaGain; + + dsp_cfg.ADCFilterCfg.ADCSinc3Osr = AppRAMPCfg.ADCSinc3Osr; + dsp_cfg.ADCFilterCfg.ADCRate = ADCRATE_800KHZ; + dsp_cfg.ADCFilterCfg.BpSinc3 = bFALSE; + dsp_cfg.ADCFilterCfg.Sinc2NotchEnable = bTRUE; + dsp_cfg.ADCFilterCfg.BpNotch = bTRUE; + dsp_cfg.ADCFilterCfg.ADCSinc2Osr = ADCSINC2OSR_1067; + dsp_cfg.ADCFilterCfg.ADCAvgNum = ADCAVGNUM_2; + AD5940_DSPCfgS(&dsp_cfg); + + AD5940_SEQGenInsert(SEQ_STOP()); + + AD5940_SEQGenCtrl(bFALSE); + error = AD5940_SEQGenFetchSeq(&pSeqCmd, &SeqLen); + if(error == AD5940ERR_OK) + { + AD5940_StructInit(&AppRAMPCfg.InitSeqInfo, sizeof(AppRAMPCfg.InitSeqInfo)); + if(SeqLen >= AppRAMPCfg.MaxSeqLen) return AD5940ERR_SEQLEN; + + AppRAMPCfg.InitSeqInfo.SeqId = SEQID_3; + AppRAMPCfg.InitSeqInfo.SeqRamAddr = AppRAMPCfg.SeqStartAddr; + AppRAMPCfg.InitSeqInfo.pSeqCmd = pSeqCmd; + AppRAMPCfg.InitSeqInfo.SeqLen = SeqLen; + AppRAMPCfg.InitSeqInfo.WriteSRAM = bTRUE; + AD5940_SEQInfoCfg(&AppRAMPCfg.InitSeqInfo); + } + else + return error; + return AD5940ERR_OK; +} + +static AD5940Err AppRAMPSeqADCCtrlGen(void) +{ + AD5940Err error = AD5940ERR_OK; + const uint32_t *pSeqCmd; + uint32_t SeqLen; + uint32_t WaitClks; + ClksCalInfo_Type clks_cal; + + clks_cal.DataCount = 1; + clks_cal.DataType = DATATYPE_SINC3; + clks_cal.ADCSinc3Osr = AppRAMPCfg.ADCSinc3Osr; + clks_cal.ADCSinc2Osr = ADCSINC2OSR_1067; + clks_cal.ADCAvgNum = ADCAVGNUM_2; + clks_cal.RatioSys2AdcClk = AppRAMPCfg.SysClkFreq / AppRAMPCfg.AdcClkFreq; + AD5940_ClksCalculate(&clks_cal, &WaitClks); + + AD5940_SEQGenCtrl(bTRUE); + AD5940_SEQGpioCtrlS(AGPIO_Pin2); + AD5940_AFECtrlS(AFECTRL_ADCPWR, bTRUE); + AD5940_SEQGenInsert(SEQ_WAIT(16 * 250)); + AD5940_AFECtrlS(AFECTRL_ADCCNV, bTRUE); + AD5940_SEQGenInsert(SEQ_WAIT(WaitClks)); + AD5940_AFECtrlS(AFECTRL_ADCPWR | AFECTRL_ADCCNV, bFALSE); + AD5940_SEQGpioCtrlS(0); + AD5940_EnterSleepS(); + + error = AD5940_SEQGenFetchSeq(&pSeqCmd, &SeqLen); + AD5940_SEQGenCtrl(bFALSE); + + if(error == AD5940ERR_OK) + { + AD5940_StructInit(&AppRAMPCfg.ADCSeqInfo, sizeof(AppRAMPCfg.ADCSeqInfo)); + if((SeqLen + AppRAMPCfg.InitSeqInfo.SeqLen) >= AppRAMPCfg.MaxSeqLen) + return AD5940ERR_SEQLEN; + AppRAMPCfg.ADCSeqInfo.SeqId = SEQID_2; + AppRAMPCfg.ADCSeqInfo.SeqRamAddr = AppRAMPCfg.InitSeqInfo.SeqRamAddr + AppRAMPCfg.InitSeqInfo.SeqLen ; + AppRAMPCfg.ADCSeqInfo.pSeqCmd = pSeqCmd; + AppRAMPCfg.ADCSeqInfo.SeqLen = SeqLen; + AppRAMPCfg.ADCSeqInfo.WriteSRAM = bTRUE; + AD5940_SEQInfoCfg(&AppRAMPCfg.ADCSeqInfo); + } + else + return error; + return AD5940ERR_OK; +} + +static AD5940Err RampDacRegUpdate(uint32_t *pDACData) +{ + uint32_t VbiasCode, VzeroCode; + + if (AppRAMPCfg.bRampOneDir) + { + switch(AppRAMPCfg.RampState) + { + case RAMP_STATE0: + AppRAMPCfg.CurrVzeroCode = (uint32_t)((AppRAMPCfg.VzeroStart - 200.0f) / DAC6BITVOLT_1LSB); + AppRAMPCfg.RampState = RAMP_STATE1; + break; + case RAMP_STATE1: + if(AppRAMPCfg.CurrStepPos >= AppRAMPCfg.StepNumber / 2) + { + AppRAMPCfg.RampState = RAMP_STATE4; + AppRAMPCfg.CurrVzeroCode = (uint32_t)((AppRAMPCfg.VzeroPeak - 200.0f) / DAC6BITVOLT_1LSB); + } + break; + case RAMP_STATE4: + if(AppRAMPCfg.CurrStepPos >= AppRAMPCfg.StepNumber) + AppRAMPCfg.RampState = RAMP_STOP; + break; + case RAMP_STOP: + break; + } + } + else + { + switch(AppRAMPCfg.RampState) + { + case RAMP_STATE0: + AppRAMPCfg.CurrVzeroCode = (uint32_t)((AppRAMPCfg.VzeroStart - 200.0f) / DAC6BITVOLT_1LSB); + AppRAMPCfg.RampState = RAMP_STATE1; + break; + case RAMP_STATE1: + if(AppRAMPCfg.CurrStepPos >= AppRAMPCfg.StepNumber / 4) + { + AppRAMPCfg.RampState = RAMP_STATE2; + AppRAMPCfg.CurrVzeroCode = (uint32_t)((AppRAMPCfg.VzeroPeak - 200.0f) / DAC6BITVOLT_1LSB); + } + break; + case RAMP_STATE2: + if(AppRAMPCfg.CurrStepPos >= (AppRAMPCfg.StepNumber * 2) / 4) + { + AppRAMPCfg.RampState = RAMP_STATE3; + AppRAMPCfg.bDACCodeInc = AppRAMPCfg.bDACCodeInc ? bFALSE : bTRUE; + } + break; + case RAMP_STATE3: + if(AppRAMPCfg.CurrStepPos >= (AppRAMPCfg.StepNumber * 3) / 4) + { + AppRAMPCfg.RampState = RAMP_STATE4; + AppRAMPCfg.CurrVzeroCode = (uint32_t)((AppRAMPCfg.VzeroStart - 200.0f) / DAC6BITVOLT_1LSB); + } + break; + case RAMP_STATE4: + if(AppRAMPCfg.CurrStepPos >= AppRAMPCfg.StepNumber) + AppRAMPCfg.RampState = RAMP_STOP; + break; + case RAMP_STOP: + break; + } + } + + AppRAMPCfg.CurrStepPos ++; + if(AppRAMPCfg.bDACCodeInc) + AppRAMPCfg.CurrRampCode += AppRAMPCfg.DACCodePerStep; + else + AppRAMPCfg.CurrRampCode -= AppRAMPCfg.DACCodePerStep; + VzeroCode = AppRAMPCfg.CurrVzeroCode; + VbiasCode = (uint32_t)(VzeroCode * 64 + AppRAMPCfg.CurrRampCode); + if(VbiasCode < (VzeroCode * 64)) + VbiasCode --; + + if(VbiasCode > 4095) VbiasCode = 4095; + if(VzeroCode > 63) VzeroCode = 63; + *pDACData = (VzeroCode << 12) | VbiasCode; + return AD5940ERR_OK; +} + +static AD5940Err AppRAMPSeqDACCtrlGen(void) +{ +#define SEQLEN_ONESTEP 4L +#define CURRBLK_BLK0 0 +#define CURRBLK_BLK1 1 + AD5940Err error = AD5940ERR_OK; + uint32_t BlockStartSRAMAddr; + uint32_t DACData, SRAMAddr; + uint32_t i; + uint32_t StepsThisBlock; + BoolFlag bIsFinalBlk; + uint32_t SeqCmdBuff[SEQLEN_ONESTEP]; + + static BoolFlag bCmdForSeq0 = bTRUE; + static uint32_t DACSeqBlk0Addr, DACSeqBlk1Addr; + static uint32_t StepsRemainning, StepsPerBlock, DACSeqCurrBlk; + + if(AppRAMPCfg.bFirstDACSeq == bTRUE) + { + int32_t DACSeqLenMax; + StepsRemainning = AppRAMPCfg.StepNumber; + DACSeqLenMax = (int32_t)AppRAMPCfg.MaxSeqLen - (int32_t)AppRAMPCfg.InitSeqInfo.SeqLen - (int32_t)AppRAMPCfg.ADCSeqInfo.SeqLen; + if(DACSeqLenMax < SEQLEN_ONESTEP * 4) return AD5940ERR_SEQLEN; + DACSeqLenMax -= SEQLEN_ONESTEP * 2; + StepsPerBlock = DACSeqLenMax / SEQLEN_ONESTEP / 2; + DACSeqBlk0Addr = AppRAMPCfg.ADCSeqInfo.SeqRamAddr + AppRAMPCfg.ADCSeqInfo.SeqLen; + DACSeqBlk1Addr = DACSeqBlk0Addr + StepsPerBlock * SEQLEN_ONESTEP; + DACSeqCurrBlk = CURRBLK_BLK0; + + if (AppRAMPCfg.bRampOneDir) + { + AppRAMPCfg.DACCodePerStep = ((AppRAMPCfg.RampPeakVolt - AppRAMPCfg.RampStartVolt) / AppRAMPCfg.StepNumber) / DAC12BITVOLT_1LSB; + } + else + { + AppRAMPCfg.DACCodePerStep = ((AppRAMPCfg.RampPeakVolt - AppRAMPCfg.RampStartVolt) / AppRAMPCfg.StepNumber * 2) / DAC12BITVOLT_1LSB; + } + + if(AppRAMPCfg.DACCodePerStep > 0) + AppRAMPCfg.bDACCodeInc = bTRUE; + else + { + AppRAMPCfg.DACCodePerStep = -AppRAMPCfg.DACCodePerStep; + AppRAMPCfg.bDACCodeInc = bFALSE; + } + AppRAMPCfg.CurrRampCode = AppRAMPCfg.RampStartVolt / DAC12BITVOLT_1LSB; + + AppRAMPCfg.RampState = RAMP_STATE0; + AppRAMPCfg.CurrStepPos = 0; + + bCmdForSeq0 = bTRUE; + } + + if(StepsRemainning == 0) return AD5940ERR_OK; + bIsFinalBlk = StepsRemainning <= StepsPerBlock ? bTRUE : bFALSE; + if(bIsFinalBlk) + StepsThisBlock = StepsRemainning; + else + StepsThisBlock = StepsPerBlock; + StepsRemainning -= StepsThisBlock; + + BlockStartSRAMAddr = (DACSeqCurrBlk == CURRBLK_BLK0) ? DACSeqBlk0Addr : DACSeqBlk1Addr; + SRAMAddr = BlockStartSRAMAddr; + + for(i = 0; i < StepsThisBlock - 1; i++) + { + uint32_t CurrAddr = SRAMAddr; + SRAMAddr += SEQLEN_ONESTEP; + RampDacRegUpdate(&DACData); + SeqCmdBuff[0] = SEQ_WR(REG_AFE_LPDACDAT0, DACData); + SeqCmdBuff[1] = SEQ_WAIT(10); + SeqCmdBuff[2] = SEQ_WR(bCmdForSeq0 ? REG_AFE_SEQ1INFO : REG_AFE_SEQ0INFO, (SRAMAddr << BITP_AFE_SEQ1INFO_ADDR) | (SEQLEN_ONESTEP << BITP_AFE_SEQ1INFO_LEN)); + SeqCmdBuff[3] = SEQ_SLP(); + AD5940_SEQCmdWrite(CurrAddr, SeqCmdBuff, SEQLEN_ONESTEP); + bCmdForSeq0 = bCmdForSeq0 ? bFALSE : bTRUE; + } + + if(bIsFinalBlk) + { + uint32_t CurrAddr = SRAMAddr; + SRAMAddr += SEQLEN_ONESTEP; + RampDacRegUpdate(&DACData); + SeqCmdBuff[0] = SEQ_WR(REG_AFE_LPDACDAT0, DACData); + SeqCmdBuff[1] = SEQ_WAIT(10); + SeqCmdBuff[2] = SEQ_WR(bCmdForSeq0 ? REG_AFE_SEQ1INFO : REG_AFE_SEQ0INFO, (SRAMAddr << BITP_AFE_SEQ1INFO_ADDR) | (SEQLEN_ONESTEP << BITP_AFE_SEQ1INFO_LEN)); + SeqCmdBuff[3] = SEQ_SLP(); + AD5940_SEQCmdWrite(CurrAddr, SeqCmdBuff, SEQLEN_ONESTEP); + CurrAddr += SEQLEN_ONESTEP; + + SeqCmdBuff[0] = SEQ_NOP(); + SeqCmdBuff[1] = SEQ_NOP(); + SeqCmdBuff[2] = SEQ_NOP(); + SeqCmdBuff[3] = SEQ_STOP(); + AD5940_SEQCmdWrite(CurrAddr, SeqCmdBuff, SEQLEN_ONESTEP); + } + else + { + uint32_t CurrAddr = SRAMAddr; + SRAMAddr = (DACSeqCurrBlk == CURRBLK_BLK0) ? DACSeqBlk1Addr : DACSeqBlk0Addr; + RampDacRegUpdate(&DACData); + SeqCmdBuff[0] = SEQ_WR(REG_AFE_LPDACDAT0, DACData); + SeqCmdBuff[1] = SEQ_WAIT(10); + SeqCmdBuff[2] = SEQ_WR(bCmdForSeq0 ? REG_AFE_SEQ1INFO : REG_AFE_SEQ0INFO, (SRAMAddr << BITP_AFE_SEQ1INFO_ADDR) | (SEQLEN_ONESTEP << BITP_AFE_SEQ1INFO_LEN)); + SeqCmdBuff[3] = SEQ_INT0(); + AD5940_SEQCmdWrite(CurrAddr, SeqCmdBuff, SEQLEN_ONESTEP); + bCmdForSeq0 = bCmdForSeq0 ? bFALSE : bTRUE; + } + + DACSeqCurrBlk = (DACSeqCurrBlk == CURRBLK_BLK0) ? CURRBLK_BLK1 : CURRBLK_BLK0; + if(AppRAMPCfg.bFirstDACSeq) + { + AppRAMPCfg.bFirstDACSeq = bFALSE; + if(bIsFinalBlk == bFALSE) + { + error = AppRAMPSeqDACCtrlGen(); + if(error != AD5940ERR_OK) return error; + } + AppRAMPCfg.DACSeqInfo.SeqId = SEQID_0; + AppRAMPCfg.DACSeqInfo.SeqLen = SEQLEN_ONESTEP; + AppRAMPCfg.DACSeqInfo.SeqRamAddr = BlockStartSRAMAddr; + AppRAMPCfg.DACSeqInfo.WriteSRAM = bFALSE; + AD5940_SEQInfoCfg(&AppRAMPCfg.DACSeqInfo); + } + return AD5940ERR_OK; +} + +AD5940Err AppRAMPInit(uint32_t *pBuffer, uint32_t BufferSize) +{ + AD5940Err error = AD5940ERR_OK; + FIFOCfg_Type fifo_cfg; + SEQCfg_Type seq_cfg; + + if(AD5940_WakeUp(10) > 10) return AD5940ERR_WAKEUP; + + seq_cfg.SeqMemSize = SEQMEMSIZE_4KB; + seq_cfg.SeqBreakEn = bFALSE; + seq_cfg.SeqIgnoreEn = bFALSE; + seq_cfg.SeqCntCRCClr = bTRUE; + seq_cfg.SeqEnable = bFALSE; + seq_cfg.SeqWrTimer = 0; + AD5940_SEQCfg(&seq_cfg); + + if((AppRAMPCfg.RAMPInited == bFALSE) || (AppRAMPCfg.bParaChanged == bTRUE)) + { + if(pBuffer == 0) return AD5940ERR_PARA; + if(BufferSize == 0) return AD5940ERR_PARA; + + AppRAMPCfg.RAMPInited = bFALSE; + AD5940_SEQGenInit(pBuffer, BufferSize); + + error = AppRAMPSeqInitGen(); + if(error != AD5940ERR_OK) return error; + error = AppRAMPSeqADCCtrlGen(); + if(error != AD5940ERR_OK) return error; + AppRAMPCfg.bParaChanged = bFALSE; + } + + AD5940_FIFOCtrlS(FIFOSRC_SINC3, bFALSE); + fifo_cfg.FIFOEn = bTRUE; + fifo_cfg.FIFOSrc = FIFOSRC_SINC3; + fifo_cfg.FIFOThresh = AppRAMPCfg.FifoThresh; + fifo_cfg.FIFOMode = FIFOMODE_FIFO; + fifo_cfg.FIFOSize = FIFOSIZE_2KB; + AD5940_FIFOCfg(&fifo_cfg); + + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + + AppRAMPCfg.bFirstDACSeq = bTRUE; + error = AppRAMPSeqDACCtrlGen(); + if(error != AD5940ERR_OK) return error; + + AppRAMPCfg.InitSeqInfo.WriteSRAM = bFALSE; + AD5940_SEQInfoCfg(&AppRAMPCfg.InitSeqInfo); + + AD5940_SEQCtrlS(bTRUE); + AD5940_SEQMmrTrig(AppRAMPCfg.InitSeqInfo.SeqId); + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_ENDSEQ) == bFALSE); + AD5940_INTCClrFlag(AFEINTSRC_ENDSEQ); + + AppRAMPCfg.ADCSeqInfo.WriteSRAM = bFALSE; + AD5940_SEQInfoCfg(&AppRAMPCfg.ADCSeqInfo); + + AppRAMPCfg.DACSeqInfo.WriteSRAM = bFALSE; + AD5940_SEQInfoCfg(&AppRAMPCfg.DACSeqInfo); + + AD5940_SEQCtrlS(bFALSE); + AD5940_WriteReg(REG_AFE_SEQCNT, 0); + AD5940_SEQCtrlS(bTRUE); + AD5940_ClrMCUIntFlag(); + + AD5940_AFEPwrBW(AFEPWR_LP, AFEBW_250KHZ); + + AppRAMPCfg.RAMPInited = bTRUE; + return AD5940ERR_OK; +} + +static int32_t AppRAMPRegModify(int32_t *const pData, uint32_t *pDataCount) +{ + if(AppRAMPCfg.StopRequired == bTRUE) + { + AD5940_WUPTCtrl(bFALSE); + return AD5940ERR_OK; + } + return AD5940ERR_OK; +} + +static int32_t AppRAMPDataProcess(int32_t *const pData, uint32_t *pDataCount) +{ + uint32_t i, datacount; + datacount = *pDataCount; + float *pOut = (float *)pData; + float temp; + for(i = 0; i < datacount; i++) + { + pData[i] &= 0xffff; + temp = -AD5940_ADCCode2Volt(pData[i], AppRAMPCfg.AdcPgaGain, AppRAMPCfg.ADCRefVolt); + pOut[i] = temp / AppRAMPCfg.RtiaValue.Magnitude * 1e3f; /* Result unit is uA. */ + } + return 0; +} + +AD5940Err AppRAMPISR(void *pBuff, uint32_t *pCount) +{ + uint32_t BuffCount; + uint32_t FifoCnt; + BuffCount = *pCount; + uint32_t IntFlag; + + if(AD5940_WakeUp(10) > 10) return AD5940ERR_WAKEUP; + AD5940_SleepKeyCtrlS(SLPKEY_LOCK); + *pCount = 0; + IntFlag = AD5940_INTCGetFlag(AFEINTC_0); + + if(IntFlag & AFEINTSRC_CUSTOMINT0) + { + AD5940Err error; + AD5940_INTCClrFlag(AFEINTSRC_CUSTOMINT0); + error = AppRAMPSeqDACCtrlGen(); + if(error != AD5940ERR_OK) return error; + AD5940_SleepKeyCtrlS(SLPKEY_UNLOCK); + } + if(IntFlag & AFEINTSRC_DATAFIFOTHRESH) + { + FifoCnt = AD5940_FIFOGetCnt(); + AD5940_FIFORd((uint32_t *)pBuff, FifoCnt); + AD5940_INTCClrFlag(AFEINTSRC_DATAFIFOTHRESH); + AppRAMPRegModify((int32_t*)pBuff, &FifoCnt); + AD5940_SleepKeyCtrlS(SLPKEY_UNLOCK); + AppRAMPDataProcess((int32_t *)pBuff, &FifoCnt); + *pCount = FifoCnt; + return 0; + } + if(IntFlag & AFEINTSRC_ENDSEQ) + { + FifoCnt = AD5940_FIFOGetCnt(); + AD5940_INTCClrFlag(AFEINTSRC_ENDSEQ); + AD5940_FIFORd((uint32_t *)pBuff, FifoCnt); + AppRAMPDataProcess((int32_t *)pBuff, &FifoCnt); + *pCount = FifoCnt; + AppRAMPCtrl(APPCTRL_STOPNOW, 0); + + // Signal that we are done + return AD5940ERR_STOP; + } + return 0; +} \ No newline at end of file diff --git a/examples/rp2040_port/RampTest.h b/examples/rp2040_port/RampTest.h new file mode 100644 index 0000000..36a924f --- /dev/null +++ b/examples/rp2040_port/RampTest.h @@ -0,0 +1,67 @@ +// File: RampTest.h +#ifndef _RAMPTEST_H_ +#define _RAMPTEST_H_ +#include "ad5940.h" +#include +#include "string.h" +#include "math.h" + +#define ALIGIN_VOLT2LSB 0 +#define DAC12BITVOLT_1LSB (2200.0f/4095) //mV +#define DAC6BITVOLT_1LSB (DAC12BITVOLT_1LSB*64) //mV + +typedef struct +{ + BoolFlag bParaChanged; + uint32_t SeqStartAddr; + uint32_t MaxSeqLen; + uint32_t SeqStartAddrCal; + uint32_t MaxSeqLenCal; + float LFOSCClkFreq; + float SysClkFreq; + float AdcClkFreq; + float RcalVal; + float ADCRefVolt; + BoolFlag bTestFinished; + float RampStartVolt; + float RampPeakVolt; + float VzeroStart; + float VzeroPeak; + uint32_t StepNumber; + uint32_t RampDuration; + float SampleDelay; + uint32_t LPTIARtiaSel; + uint32_t LPTIARloadSel; + uint32_t LpTiaRf; /* Added LPF Resistor Configuration */ + float ExternalRtiaValue; + uint32_t AdcPgaGain; + uint8_t ADCSinc3Osr; + uint32_t FifoThresh; + BoolFlag RAMPInited; + fImpPol_Type RtiaValue; + SEQInfo_Type InitSeqInfo; + SEQInfo_Type ADCSeqInfo; + BoolFlag bFirstDACSeq; + SEQInfo_Type DACSeqInfo; + uint32_t CurrStepPos; + float DACCodePerStep; + float CurrRampCode; + uint32_t CurrVzeroCode; + BoolFlag bDACCodeInc; + BoolFlag StopRequired; + enum _RampState{RAMP_STATE0 = 0, RAMP_STATE1, RAMP_STATE2, RAMP_STATE3, RAMP_STATE4, RAMP_STOP} RampState; + BoolFlag bRampOneDir; + BoolFlag ShortRe0Se0; /* Short RE0 to SE0 */ +}AppRAMPCfg_Type; + +#define APPCTRL_START 0 +#define APPCTRL_STOPNOW 1 +#define APPCTRL_STOPSYNC 2 +#define APPCTRL_SHUTDOWN 3 + +AD5940Err AppRAMPInit(uint32_t *pBuffer, uint32_t BufferSize); +AD5940Err AppRAMPGetCfg(void *pCfg); +AD5940Err AppRAMPISR(void *pBuff, uint32_t *pCount); +AD5940Err AppRAMPCtrl(uint32_t Command, void *pPara); + +#endif \ No newline at end of file diff --git a/examples/rp2040_port/Reset.c b/examples/rp2040_port/Reset.c new file mode 100644 index 0000000..4a25b24 --- /dev/null +++ b/examples/rp2040_port/Reset.c @@ -0,0 +1,48 @@ +// File: Reset.c +#include "Reset.h" +#include "ad5940.h" +#include + +/** + * @brief Checks and prints the cause of the last reset. + * @note The RSTSTA register is sticky. It must be cleared manually. + */ +void AD5940_CheckResetStatus(void) +{ + uint32_t rststa = AD5940_ReadReg(REG_ALLON_RSTSTA); + + // printf(">> Reset Status (0x%04X): ", rststa); + + if(rststa & 0x01) printf("POR "); + if(rststa & 0x02) printf("EXT "); + if(rststa & 0x04) printf("WDT "); + if(rststa & 0x08) printf("MMR "); + if(rststa == 0) printf("None"); + + // printf("\n"); + + // Clear the reset status (Write 1 to clear) + AD5940_WriteReg(REG_ALLON_RSTSTA, 0xF); +} + +/** + * @brief Performs a Software Reset (MMR Reset). + * @return AD5940Err + */ +AD5940Err AD5940_SoftReset(void) +{ + // Trigger Software Reset + AD5940_SoftRst(); + + // Wait for the chip to reboot (essential) + AD5940_Delay10us(100); // 1ms wait + + // Re-initialize the AD5940 driver internal state (SPI, etc.) + // This function is required after any reset. + AD5940_Initialize(); + + // Check and clear the reset flag (Should show MMR) + AD5940_CheckResetStatus(); + + return AD5940ERR_OK; +} \ No newline at end of file diff --git a/examples/rp2040_port/Reset.h b/examples/rp2040_port/Reset.h new file mode 100644 index 0000000..5ca4b40 --- /dev/null +++ b/examples/rp2040_port/Reset.h @@ -0,0 +1,10 @@ +// File: Reset.h +#ifndef _RESET_H_ +#define _RESET_H_ + +#include "ad5940.h" + +void AD5940_CheckResetStatus(void); +AD5940Err AD5940_SoftReset(void); + +#endif \ No newline at end of file diff --git a/examples/rp2040_port/ad5940.h b/examples/rp2040_port/ad5940.h new file mode 100644 index 0000000..9ff35a3 --- /dev/null +++ b/examples/rp2040_port/ad5940.h @@ -0,0 +1,4950 @@ +/** + * @file ad5940.h + * @brief AD5940 library. This file contains all AD5940 library functions. + * @author ADI + * @date March 2019 + * @par Revision History: + * + * Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + * + * This software is proprietary to Analog Devices, Inc. and its licensors. + * By using this software you agree to the terms of the associated + * Analog Devices Software License Agreement. +**/ + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifndef _AD5940_H_ +#define _AD5940_H_ +#include "math.h" +#include "string.h" +#include "stdio.h" +/** @addtogroup AD5940_Library + * @{ + */ + +/** + * Select the correct chip. + * Recommend to define this in your compiler. + * */ +//#define CHIPSEL_M355 /**< ADuCM355 */ +//#define CHIPSEL_594X /**< AD5940 or AD5941 */ + +/* library version number */ +#define AD5940LIB_VER_MAJOR 0 /**< Major number */ +#define AD5940LIB_VER_MINOR 2 /**< Minor number */ +#define AD5940LIB_VER_PATCH 1 /**< Path number */ +#define AD5940LIB_VER (AD5940LIB_VER_MAJOR<<16)|(AD5940LIB_VER_MINOR<<8)|(AD5940LIB_VER_PATCH) + +#define ADI_DEBUG /**< Comment this line to remove debug info. */ + +#ifdef ADI_DEBUG +#define ADI_Print printf /**< Select the method to print out debug message */ +#endif + +#if defined(CHIPSEL_M355) && defined(CHIPSEL_594X) +#error Please select the correct chip by define CHIPSEL_M355 or CHIPSEL_594X. +#endif + +#if !defined(CHIPSEL_M355) && !defined(CHIPSEL_594X) +#error Please select the correct chip by define CHIPSEL_M355 or CHIPSEL_594X. +#endif + +/** + * @cond + * @defgroup AD5940RegistersBitfields + * @brief All AD5940 registers and bitfields definition. + * @{ +*/ +//#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +//#endif /* _LANGUAGE_C */ + +#ifndef __ADI_GENERATED_DEF_HEADERS__ +#define __ADI_GENERATED_DEF_HEADERS__ 1 +#endif + +#define __ADI_HAS_AGPIO__ 1 +#define __ADI_HAS_ALLON__ 1 +#define __ADI_HAS_INTC__ 1 +#define __ADI_HAS_AFECON__ 1 +#define __ADI_HAS_WUPTMR__ 1 +#define __ADI_HAS_AFE__ 1 + +/* ============================================================================================================================ + GPIO + ============================================================================================================================ */ + +/* ============================================================================================================================ + AGPIO + ============================================================================================================================ */ +#define REG_AGPIO_GP0CON_RESET 0x00000000 /* Reset Value for GP0CON */ +#define REG_AGPIO_GP0CON 0x00000000 /* AGPIO GPIO Port 0 Configuration */ +#define REG_AGPIO_GP0OEN_RESET 0x00000000 /* Reset Value for GP0OEN */ +#define REG_AGPIO_GP0OEN 0x00000004 /* AGPIO GPIO Port 0 Output Enable */ +#define REG_AGPIO_GP0PE_RESET 0x00000000 /* Reset Value for GP0PE */ +#define REG_AGPIO_GP0PE 0x00000008 /* AGPIO GPIO Port 0 Pullup/Pulldown Enable */ +#define REG_AGPIO_GP0IEN_RESET 0x00000000 /* Reset Value for GP0IEN */ +#define REG_AGPIO_GP0IEN 0x0000000C /* AGPIO GPIO Port 0 Input Path Enable */ +#define REG_AGPIO_GP0IN_RESET 0x00000000 /* Reset Value for GP0IN */ +#define REG_AGPIO_GP0IN 0x00000010 /* AGPIO GPIO Port 0 Registered Data Input */ +#define REG_AGPIO_GP0OUT_RESET 0x00000000 /* Reset Value for GP0OUT */ +#define REG_AGPIO_GP0OUT 0x00000014 /* AGPIO GPIO Port 0 Data Output */ +#define REG_AGPIO_GP0SET_RESET 0x00000000 /* Reset Value for GP0SET */ +#define REG_AGPIO_GP0SET 0x00000018 /* AGPIO GPIO Port 0 Data Out Set */ +#define REG_AGPIO_GP0CLR_RESET 0x00000000 /* Reset Value for GP0CLR */ +#define REG_AGPIO_GP0CLR 0x0000001C /* AGPIO GPIO Port 0 Data Out Clear */ +#define REG_AGPIO_GP0TGL_RESET 0x00000000 /* Reset Value for GP0TGL */ +#define REG_AGPIO_GP0TGL 0x00000020 /* AGPIO GPIO Port 0 Pin Toggle */ + +/* ============================================================================================================================ + AGPIO Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0CON_PIN7CFG 14 /* P0.7 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN6CFG 12 /* P0.6 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN5CFG 10 /* P0.5 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN4CFG 8 /* P0.4 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN3CFG 6 /* P0.3 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN2CFG 4 /* P0.2 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN1CFG 2 /* P0.1 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN0CFG 0 /* P0.0 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN7CFG 0x0000C000 /* P0.7 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN6CFG 0x00003000 /* P0.6 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN5CFG 0x00000C00 /* P0.5 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN4CFG 0x00000300 /* P0.4 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN3CFG 0x000000C0 /* P0.3 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN2CFG 0x00000030 /* P0.2 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN1CFG 0x0000000C /* P0.1 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN0CFG 0x00000003 /* P0.0 Configuration Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0OEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0OEN_OEN 0 /* Pin Output Drive Enable */ +#define BITM_AGPIO_GP0OEN_OEN 0x000000FF /* Pin Output Drive Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0PE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0PE_PE 0 /* Pin Pull Enable */ +#define BITM_AGPIO_GP0PE_PE 0x000000FF /* Pin Pull Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0IEN_IEN 0 /* Input Path Enable */ +#define BITM_AGPIO_GP0IEN_IEN 0x000000FF /* Input Path Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0IN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0IN_IN 0 /* Registered Data Input */ +#define BITM_AGPIO_GP0IN_IN 0x000000FF /* Registered Data Input */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0OUT_OUT 0 /* Data Out */ +#define BITM_AGPIO_GP0OUT_OUT 0x000000FF /* Data Out */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0SET_SET 0 /* Set the Output HIGH */ +#define BITM_AGPIO_GP0SET_SET 0x000000FF /* Set the Output HIGH */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0CLR_CLR 0 /* Set the Output LOW */ +#define BITM_AGPIO_GP0CLR_CLR 0x000000FF /* Set the Output LOW */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0TGL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPIO_GP0TGL_TGL 0 /* Toggle the Output */ +#define BITM_AGPIO_GP0TGL_TGL 0x000000FF /* Toggle the Output */ + + +/* ============================================================================================================================ + + ============================================================================================================================ */ + +/* ============================================================================================================================ + AFECON + ============================================================================================================================ */ +#define REG_AFECON_ADIID_RESET 0x00000000 /* Reset Value for ADIID */ +#define REG_AFECON_ADIID 0x00000400 /* AFECON ADI Identification */ +#define REG_AFECON_CHIPID_RESET 0x00000000 /* Reset Value for CHIPID */ +#define REG_AFECON_CHIPID 0x00000404 /* AFECON Chip Identification */ +#define REG_AFECON_CLKCON0_RESET 0x00000441 /* Reset Value for CLKCON0 */ +#define REG_AFECON_CLKCON0 0x00000408 /* AFECON Clock Divider Configuration */ +#define REG_AFECON_CLKEN1_RESET 0x000002C0 /* Reset Value for CLKEN1 */ +#define REG_AFECON_CLKEN1 0x00000410 /* AFECON Clock Gate Enable */ +#define REG_AFECON_CLKSEL_RESET 0x00000000 /* Reset Value for CLKSEL */ +#define REG_AFECON_CLKSEL 0x00000414 /* AFECON Clock Select */ +#define REG_AFECON_CLKCON0KEY_RESET 0x00000000 /* Reset Value for CLKCON0KEY */ +#define REG_AFECON_CLKCON0KEY 0x00000420 /* AFECON Enable Clock Division to 8Mhz,4Mhz and 2Mhz */ +#define REG_AFECON_SWRSTCON_RESET 0x00000001 /* Reset Value for SWRSTCON */ +#define REG_AFECON_SWRSTCON 0x00000424 /* AFECON Software Reset */ +#define REG_AFECON_TRIGSEQ_RESET 0x00000000 /* Reset Value for TRIGSEQ */ +#define REG_AFECON_TRIGSEQ 0x00000430 /* AFECON Trigger Sequence */ + +/* ============================================================================================================================ + AFECON Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_ADIID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_ADIID_ADIID 0 /* ADI Identifier. */ +#define BITM_AFECON_ADIID_ADIID 0x0000FFFF /* ADI Identifier. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CHIPID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_CHIPID_PARTID 4 /* Part Identifier */ +#define BITP_AFECON_CHIPID_REVISION 0 /* Silicon Revision Number */ +#define BITM_AFECON_CHIPID_PARTID 0x0000FFF0 /* Part Identifier */ +#define BITM_AFECON_CHIPID_REVISION 0x0000000F /* Silicon Revision Number */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKCON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_CLKCON0_SFFTCLKDIVCNT 10 /* SFFT Clock Divider Configuration */ +#define BITP_AFECON_CLKCON0_ADCCLKDIV 6 /* ADC Clock Divider Configuration */ +#define BITP_AFECON_CLKCON0_SYSCLKDIV 0 /* System Clock Divider Configuration */ +#define BITM_AFECON_CLKCON0_SFFTCLKDIVCNT 0x0000FC00 /* SFFT Clock Divider Configuration */ +#define BITM_AFECON_CLKCON0_ADCCLKDIV 0x000003C0 /* ADC Clock Divider Configuration */ +#define BITM_AFECON_CLKCON0_SYSCLKDIV 0x0000003F /* System Clock Divider Configuration */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKEN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_CLKEN1_GPT1DIS 7 /* GPT1 Clock Enable */ +#define BITP_AFECON_CLKEN1_GPT0DIS 6 /* GPT0 Clock Enable */ +#define BITP_AFECON_CLKEN1_ACLKDIS 5 /* ACLK Clock Enable */ +#define BITM_AFECON_CLKEN1_GPT1DIS 0x00000080 /* GPT1 Clock Enable */ +#define BITM_AFECON_CLKEN1_GPT0DIS 0x00000040 /* GPT0 Clock Enable */ +#define BITM_AFECON_CLKEN1_ACLKDIS 0x00000020 /* ACLK Clock Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKSEL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_CLKSEL_ADCCLKSEL 2 /* Select ADC Clock Source */ +#define BITP_AFECON_CLKSEL_SYSCLKSEL 0 /* Select System Clock Source */ +#define BITM_AFECON_CLKSEL_ADCCLKSEL 0x0000000C /* Select ADC Clock Source */ +#define BITM_AFECON_CLKSEL_SYSCLKSEL 0x00000003 /* Select System Clock Source */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKCON0KEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_CLKCON0KEY_DIVSYSCLK_ULP_EN 0 /* Enable Clock Division to 8Mhz,4Mhz and 2Mhz */ +#define BITM_AFECON_CLKCON0KEY_DIVSYSCLK_ULP_EN 0x0000FFFF /* Enable Clock Division to 8Mhz,4Mhz and 2Mhz */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_SWRSTCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_SWRSTCON_SWRSTL 0 /* Software Reset */ +#define BITM_AFECON_SWRSTCON_SWRSTL 0x0000FFFF /* Software Reset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_TRIGSEQ Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECON_TRIGSEQ_TRIG3 3 /* Trigger Sequence 3 */ +#define BITP_AFECON_TRIGSEQ_TRIG2 2 /* Trigger Sequence 2 */ +#define BITP_AFECON_TRIGSEQ_TRIG1 1 /* Trigger Sequence 1 */ +#define BITP_AFECON_TRIGSEQ_TRIG0 0 /* Trigger Sequence 0 */ +#define BITM_AFECON_TRIGSEQ_TRIG3 0x00000008 /* Trigger Sequence 3 */ +#define BITM_AFECON_TRIGSEQ_TRIG2 0x00000004 /* Trigger Sequence 2 */ +#define BITM_AFECON_TRIGSEQ_TRIG1 0x00000002 /* Trigger Sequence 1 */ +#define BITM_AFECON_TRIGSEQ_TRIG0 0x00000001 /* Trigger Sequence 0 */ + +/* ============================================================================================================================ + AFEWDT + ============================================================================================================================ */ +#define REG_AFEWDT_WDTLD 0x00000900 /* AFEWDT Watchdog Timer Load Value */ +#define REG_AFEWDT_WDTVALS 0x00000904 /* AFEWDT Current Count Value */ +#define REG_AFEWDT_WDTCON 0x00000908 /* AFEWDT Watchdog Timer Control Register */ +#define REG_AFEWDT_WDTCLRI 0x0000090C /* AFEWDT Refresh Watchdog Register */ +#define REG_AFEWDT_WDTSTA 0x00000918 /* AFEWDT Timer Status */ +#define REG_AFEWDT_WDTMINLD 0x0000091C /* AFEWDT Minimum Load Value */ + +/* ============================================================================================================================ + AFEWDT Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTLD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFEWDT_WDTLD_LOAD 0 /* WDT Load Value */ +#define BITM_AFEWDT_WDTLD_LOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* WDT Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTVALS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFEWDT_WDTVALS_CCOUNT 0 /* Current WDT Count Value. */ +#define BITM_AFEWDT_WDTVALS_CCOUNT (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Current WDT Count Value. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFEWDT_WDTCON_RESERVED_15_11 11 /* RESERVED */ +#define BITP_AFEWDT_WDTCON_WDTIRQEN 10 /* WDT Interrupt Enable */ +#define BITP_AFEWDT_WDTCON_MINLOAD_EN 9 /* Timer Window Control */ +#define BITP_AFEWDT_WDTCON_CLKDIV2 8 /* Clock Source */ +#define BITP_AFEWDT_WDTCON_RESERVED1_7 7 /* Reserved */ +#define BITP_AFEWDT_WDTCON_MDE 6 /* Timer Mode Select */ +#define BITP_AFEWDT_WDTCON_EN 5 /* Timer Enable */ +#define BITP_AFEWDT_WDTCON_PRE 2 /* Prescaler. */ +#define BITP_AFEWDT_WDTCON_IRQ 1 /* WDT Interrupt Enable */ +#define BITP_AFEWDT_WDTCON_PDSTOP 0 /* Power Down Stop Enable */ +#define BITM_AFEWDT_WDTCON_RESERVED_15_11 (_ADI_MSK_3(0x0000F800,0x0000F800U, uint16_t )) /* RESERVED */ +#define BITM_AFEWDT_WDTCON_WDTIRQEN (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* WDT Interrupt Enable */ +#define BITM_AFEWDT_WDTCON_MINLOAD_EN (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Timer Window Control */ +#define BITM_AFEWDT_WDTCON_CLKDIV2 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Clock Source */ +#define BITM_AFEWDT_WDTCON_RESERVED1_7 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Reserved */ +#define BITM_AFEWDT_WDTCON_MDE (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Mode Select */ +#define BITM_AFEWDT_WDTCON_EN (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Timer Enable */ +#define BITM_AFEWDT_WDTCON_PRE (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* Prescaler. */ +#define BITM_AFEWDT_WDTCON_IRQ (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* WDT Interrupt Enable */ +#define BITM_AFEWDT_WDTCON_PDSTOP (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Power Down Stop Enable */ +#define ENUM_AFEWDT_WDTCON_RESET (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* IRQ: Watchdog Timer timeout creates a reset. */ +#define ENUM_AFEWDT_WDTCON_INTERRUPT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* IRQ: Watchdog Timer timeout creates an interrupt instead of reset. */ +#define ENUM_AFEWDT_WDTCON_CONTINUE (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* PDSTOP: Continue Counting When In Hibernate */ +#define ENUM_AFEWDT_WDTCON_STOP (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PDSTOP: Stop Counter When In Hibernate. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTCLRI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFEWDT_WDTCLRI_CLRWDG 0 /* Refresh Register */ +#define BITM_AFEWDT_WDTCLRI_CLRWDG (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Refresh Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFEWDT_WDTSTA_RESERVED_15_7 7 /* RESERVED */ +#define BITP_AFEWDT_WDTSTA_TMINLD 6 /* WDTMINLD Write Status */ +#define BITP_AFEWDT_WDTSTA_OTPWRDONE 5 /* Reset Type Status */ +#define BITP_AFEWDT_WDTSTA_LOCK 4 /* Lock Status */ +#define BITP_AFEWDT_WDTSTA_CON 3 /* WDTCON Write Status */ +#define BITP_AFEWDT_WDTSTA_TLD 2 /* WDTVAL Write Status */ +#define BITP_AFEWDT_WDTSTA_CLRI 1 /* WDTCLRI Write Status */ +#define BITP_AFEWDT_WDTSTA_IRQ 0 /* WDT Interrupt */ +#define BITM_AFEWDT_WDTSTA_RESERVED_15_7 (_ADI_MSK_3(0x0000FF80,0x0000FF80U, uint16_t )) /* RESERVED */ +#define BITM_AFEWDT_WDTSTA_TMINLD (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* WDTMINLD Write Status */ +#define BITM_AFEWDT_WDTSTA_OTPWRDONE (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Reset Type Status */ +#define BITM_AFEWDT_WDTSTA_LOCK (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Lock Status */ +#define BITM_AFEWDT_WDTSTA_CON (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* WDTCON Write Status */ +#define BITM_AFEWDT_WDTSTA_TLD (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* WDTVAL Write Status */ +#define BITM_AFEWDT_WDTSTA_CLRI (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* WDTCLRI Write Status */ +#define BITM_AFEWDT_WDTSTA_IRQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* WDT Interrupt */ +#define ENUM_AFEWDT_WDTSTA_OPEN (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* LOCK: Timer Operation Not Locked */ +#define ENUM_AFEWDT_WDTSTA_LOCKED (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* LOCK: Timer Enabled and Locked */ +#define ENUM_AFEWDT_WDTSTA_SYNC_COMPLETE (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* TLD: Arm and AFE Watchdog Clock Domains WDTLD values match */ +#define ENUM_AFEWDT_WDTSTA_SYNC_IN_PROGRESS (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* TLD: Synchronize In Progress */ +#define ENUM_AFEWDT_WDTSTA_CLEARED (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* IRQ: Watchdog Timer Interrupt Not Pending */ +#define ENUM_AFEWDT_WDTSTA_PENDING (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* IRQ: Watchdog Timer Interrupt Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTMINLD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFEWDT_WDTMINLD_MIN_LOAD 0 /* WDT Min Load Value */ +#define BITM_AFEWDT_WDTMINLD_MIN_LOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* WDT Min Load Value */ + +/* ============================================================================================================================ + Wakeup Timer + ============================================================================================================================ */ + +/* ============================================================================================================================ + WUPTMR + ============================================================================================================================ */ +#define REG_WUPTMR_CON_RESET 0x00000000 /* Reset Value for CON */ +#define REG_WUPTMR_CON 0x00000800 /* WUPTMR Timer Control */ +#define REG_WUPTMR_SEQORDER_RESET 0x00000000 /* Reset Value for SEQORDER */ +#define REG_WUPTMR_SEQORDER 0x00000804 /* WUPTMR Order Control */ +#define REG_WUPTMR_SEQ0WUPL_RESET 0x0000FFFF /* Reset Value for SEQ0WUPL */ +#define REG_WUPTMR_SEQ0WUPL 0x00000808 /* WUPTMR SEQ0 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ0WUPH_RESET 0x0000000F /* Reset Value for SEQ0WUPH */ +#define REG_WUPTMR_SEQ0WUPH 0x0000080C /* WUPTMR SEQ0 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ0SLEEPL_RESET 0x0000FFFF /* Reset Value for SEQ0SLEEPL */ +#define REG_WUPTMR_SEQ0SLEEPL 0x00000810 /* WUPTMR SEQ0 STimeL (LSB) */ +#define REG_WUPTMR_SEQ0SLEEPH_RESET 0x0000000F /* Reset Value for SEQ0SLEEPH */ +#define REG_WUPTMR_SEQ0SLEEPH 0x00000814 /* WUPTMR SEQ0 STimeH (MSB) */ +#define REG_WUPTMR_SEQ1WUPL_RESET 0x0000FFFF /* Reset Value for SEQ1WUPL */ +#define REG_WUPTMR_SEQ1WUPL 0x00000818 /* WUPTMR SEQ1 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ1WUPH_RESET 0x0000000F /* Reset Value for SEQ1WUPH */ +#define REG_WUPTMR_SEQ1WUPH 0x0000081C /* WUPTMR SEQ1 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ1SLEEPL_RESET 0x0000FFFF /* Reset Value for SEQ1SLEEPL */ +#define REG_WUPTMR_SEQ1SLEEPL 0x00000820 /* WUPTMR SEQ1 STimeL (LSB) */ +#define REG_WUPTMR_SEQ1SLEEPH_RESET 0x0000000F /* Reset Value for SEQ1SLEEPH */ +#define REG_WUPTMR_SEQ1SLEEPH 0x00000824 /* WUPTMR SEQ1 STimeH (MSB) */ +#define REG_WUPTMR_SEQ2WUPL_RESET 0x0000FFFF /* Reset Value for SEQ2WUPL */ +#define REG_WUPTMR_SEQ2WUPL 0x00000828 /* WUPTMR SEQ2 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ2WUPH_RESET 0x0000000F /* Reset Value for SEQ2WUPH */ +#define REG_WUPTMR_SEQ2WUPH 0x0000082C /* WUPTMR SEQ2 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ2SLEEPL_RESET 0x0000FFFF /* Reset Value for SEQ2SLEEPL */ +#define REG_WUPTMR_SEQ2SLEEPL 0x00000830 /* WUPTMR SEQ2 STimeL (LSB) */ +#define REG_WUPTMR_SEQ2SLEEPH_RESET 0x0000000F /* Reset Value for SEQ2SLEEPH */ +#define REG_WUPTMR_SEQ2SLEEPH 0x00000834 /* WUPTMR SEQ2 STimeH (MSB) */ +#define REG_WUPTMR_SEQ3WUPL_RESET 0x0000FFFF /* Reset Value for SEQ3WUPL */ +#define REG_WUPTMR_SEQ3WUPL 0x00000838 /* WUPTMR SEQ3 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ3WUPH_RESET 0x0000000F /* Reset Value for SEQ3WUPH */ +#define REG_WUPTMR_SEQ3WUPH 0x0000083C /* WUPTMR SEQ3 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ3SLEEPL_RESET 0x0000FFFF /* Reset Value for SEQ3SLEEPL */ +#define REG_WUPTMR_SEQ3SLEEPL 0x00000840 /* WUPTMR SEQ3 STimeL (LSB) */ +#define REG_WUPTMR_SEQ3SLEEPH_RESET 0x0000000F /* Reset Value for SEQ3SLEEPH */ +#define REG_WUPTMR_SEQ3SLEEPH 0x00000844 /* WUPTMR SEQ3 STimeH (MSB) */ + +/* ============================================================================================================================ + WUPTMR Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_CON_MSKTRG 6 /* Mark Sequence Trigger from Sleep Wakeup Timer */ +#define BITP_WUPTMR_CON_CLKSEL 4 /* Clock Selection */ +#define BITP_WUPTMR_CON_ENDSEQ 1 /* End Sequence */ +#define BITP_WUPTMR_CON_EN 0 /* Sleep Wake Timer Enable Bit */ +#define BITM_WUPTMR_CON_MSKTRG 0x00000040 /* Mark Sequence Trigger from Sleep Wakeup Timer */ +#define BITM_WUPTMR_CON_CLKSEL 0x00000030 /* Clock Selection */ +#define BITM_WUPTMR_CON_ENDSEQ 0x0000000E /* End Sequence */ +#define BITM_WUPTMR_CON_EN 0x00000001 /* Sleep Wake Timer Enable Bit */ +#define ENUM_WUPTMR_CON_SWT32K0 0x00000000 /* CLKSEL: Internal 32kHz OSC */ +#define ENUM_WUPTMR_CON_SWTEXT0 0x00000010 /* CLKSEL: External Clock */ +#define ENUM_WUPTMR_CON_SWT32K 0x00000020 /* CLKSEL: Internal 32kHz OSC */ +#define ENUM_WUPTMR_CON_SWTEXT 0x00000030 /* CLKSEL: External Clock */ +#define ENUM_WUPTMR_CON_ENDSEQA 0x00000000 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqA And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQB 0x00000002 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqB And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQC 0x00000004 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqC And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQD 0x00000006 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqD And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQE 0x00000008 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqE And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQF 0x0000000A /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqF And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQG 0x0000000C /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqG And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQH 0x0000000E /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqH And Then Go Back To SeqA */ +#define ENUM_WUPTMR_CON_SWTEN 0x00000000 /* EN: Enable Sleep Wakeup Timer */ +#define ENUM_WUPTMR_CON_SWTDIS 0x00000001 /* EN: Disable Sleep Wakeup Timer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQORDER Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQORDER_SEQH 14 /* SEQH Config */ +#define BITP_WUPTMR_SEQORDER_SEQG 12 /* SEQG Config */ +#define BITP_WUPTMR_SEQORDER_SEQF 10 /* SEQF Config */ +#define BITP_WUPTMR_SEQORDER_SEQE 8 /* SEQE Config */ +#define BITP_WUPTMR_SEQORDER_SEQD 6 /* SEQD Config */ +#define BITP_WUPTMR_SEQORDER_SEQC 4 /* SEQC Config */ +#define BITP_WUPTMR_SEQORDER_SEQB 2 /* SEQB Config */ +#define BITP_WUPTMR_SEQORDER_SEQA 0 /* SEQA Config */ +#define BITM_WUPTMR_SEQORDER_SEQH 0x0000C000 /* SEQH Config */ +#define BITM_WUPTMR_SEQORDER_SEQG 0x00003000 /* SEQG Config */ +#define BITM_WUPTMR_SEQORDER_SEQF 0x00000C00 /* SEQF Config */ +#define BITM_WUPTMR_SEQORDER_SEQE 0x00000300 /* SEQE Config */ +#define BITM_WUPTMR_SEQORDER_SEQD 0x000000C0 /* SEQD Config */ +#define BITM_WUPTMR_SEQORDER_SEQC 0x00000030 /* SEQC Config */ +#define BITM_WUPTMR_SEQORDER_SEQB 0x0000000C /* SEQB Config */ +#define BITM_WUPTMR_SEQORDER_SEQA 0x00000003 /* SEQA Config */ +#define ENUM_WUPTMR_SEQORDER_SEQH0 0x00000000 /* SEQH: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQH1 0x00004000 /* SEQH: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQH2 0x00008000 /* SEQH: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQH3 0x0000C000 /* SEQH: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG0 0x00000000 /* SEQG: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG1 0x00001000 /* SEQG: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG2 0x00002000 /* SEQG: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG3 0x00003000 /* SEQG: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF0 0x00000000 /* SEQF: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF1 0x00000400 /* SEQF: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF2 0x00000800 /* SEQF: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF3 0x00000C00 /* SEQF: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE0 0x00000000 /* SEQE: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE1 0x00000100 /* SEQE: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE2 0x00000200 /* SEQE: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE3 0x00000300 /* SEQE: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD0 0x00000000 /* SEQD: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD1 0x00000040 /* SEQD: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD2 0x00000080 /* SEQD: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD3 0x000000C0 /* SEQD: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC0 0x00000000 /* SEQC: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC1 0x00000010 /* SEQC: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC2 0x00000020 /* SEQC: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC3 0x00000030 /* SEQC: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB0 0x00000000 /* SEQB: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB1 0x00000004 /* SEQB: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB2 0x00000008 /* SEQB: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB3 0x0000000C /* SEQB: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA0 0x00000000 /* SEQA: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA1 0x00000001 /* SEQA: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA2 0x00000002 /* SEQA: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA3 0x00000003 /* SEQA: Fill SEQ3 In */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ0WUPL_WAKEUPTIME0 0 /* Sequence 0 Sleep Period */ +#define BITM_WUPTMR_SEQ0WUPL_WAKEUPTIME0 0x0000FFFF /* Sequence 0 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ0WUPH_WAKEUPTIME0 0 /* Sequence 0 Sleep Period */ +#define BITM_WUPTMR_SEQ0WUPH_WAKEUPTIME0 0x0000000F /* Sequence 0 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ0SLEEPL_SLEEPTIME0 0 /* Sequence 0 Active Period */ +#define BITM_WUPTMR_SEQ0SLEEPL_SLEEPTIME0 0x0000FFFF /* Sequence 0 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ0SLEEPH_SLEEPTIME0 0 /* Sequence 0 Active Period */ +#define BITM_WUPTMR_SEQ0SLEEPH_SLEEPTIME0 0x0000000F /* Sequence 0 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ1WUPL_WAKEUPTIME 0 /* Sequence 1 Sleep Period */ +#define BITM_WUPTMR_SEQ1WUPL_WAKEUPTIME 0x0000FFFF /* Sequence 1 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ1WUPH_WAKEUPTIME 0 /* Sequence 1 Sleep Period */ +#define BITM_WUPTMR_SEQ1WUPH_WAKEUPTIME 0x0000000F /* Sequence 1 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ1SLEEPL_SLEEPTIME1 0 /* Sequence 1 Active Period */ +#define BITM_WUPTMR_SEQ1SLEEPL_SLEEPTIME1 0x0000FFFF /* Sequence 1 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ1SLEEPH_SLEEPTIME1 0 /* Sequence 1 Active Period */ +#define BITM_WUPTMR_SEQ1SLEEPH_SLEEPTIME1 0x0000000F /* Sequence 1 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ2WUPL_WAKEUPTIME2 0 /* Sequence 2 Sleep Period */ +#define BITM_WUPTMR_SEQ2WUPL_WAKEUPTIME2 0x0000FFFF /* Sequence 2 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ2WUPH_WAKEUPTIME2 0 /* Sequence 2 Sleep Period */ +#define BITM_WUPTMR_SEQ2WUPH_WAKEUPTIME2 0x0000000F /* Sequence 2 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ2SLEEPL_SLEEPTIME2 0 /* Sequence 2 Active Period */ +#define BITM_WUPTMR_SEQ2SLEEPL_SLEEPTIME2 0x0000FFFF /* Sequence 2 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ2SLEEPH_SLEEPTIME2 0 /* Sequence 2 Active Period */ +#define BITM_WUPTMR_SEQ2SLEEPH_SLEEPTIME2 0x0000000F /* Sequence 2 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ3WUPL_WAKEUPTIME3 0 /* Sequence 3 Sleep Period */ +#define BITM_WUPTMR_SEQ3WUPL_WAKEUPTIME3 0x0000FFFF /* Sequence 3 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ3WUPH_WAKEUPTIME3 0 /* Sequence 3 Sleep Period */ +#define BITM_WUPTMR_SEQ3WUPH_WAKEUPTIME3 0x0000000F /* Sequence 3 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ3SLEEPL_SLEEPTIME3 0 /* Sequence 3 Active Period */ +#define BITM_WUPTMR_SEQ3SLEEPL_SLEEPTIME3 0x0000FFFF /* Sequence 3 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WUPTMR_SEQ3SLEEPH_SLEEPTIME3 0 /* Sequence 3 Active Period */ +#define BITM_WUPTMR_SEQ3SLEEPH_SLEEPTIME3 0x0000000F /* Sequence 3 Active Period */ + + +/* ============================================================================================================================ + Always On Register + ============================================================================================================================ */ + +/* ============================================================================================================================ + ALLON + ============================================================================================================================ */ +#define REG_ALLON_PWRMOD_RESET 0x00000001 /* Reset Value for PWRMOD */ +#define REG_ALLON_PWRMOD 0x00000A00 /* ALLON Power Modes */ +#define REG_ALLON_PWRKEY_RESET 0x00000000 /* Reset Value for PWRKEY */ +#define REG_ALLON_PWRKEY 0x00000A04 /* ALLON Key Protection for PWRMOD */ +#define REG_ALLON_OSCKEY_RESET 0x00000000 /* Reset Value for OSCKEY */ +#define REG_ALLON_OSCKEY 0x00000A0C /* ALLON Key Protection for OSCCON */ +#define REG_ALLON_OSCCON_RESET 0x00000003 /* Reset Value for OSCCON */ +#define REG_ALLON_OSCCON 0x00000A10 /* ALLON Oscillator Control */ +#define REG_ALLON_TMRCON_RESET 0x00000000 /* Reset Value for TMRCON */ +#define REG_ALLON_TMRCON 0x00000A1C /* ALLON Timer Wakeup Configuration */ +#define REG_ALLON_EI0CON_RESET 0x00000000 /* Reset Value for EI0CON */ +#define REG_ALLON_EI0CON 0x00000A20 /* ALLON External Interrupt Configuration 0 */ +#define REG_ALLON_EI1CON_RESET 0x00000000 /* Reset Value for EI1CON */ +#define REG_ALLON_EI1CON 0x00000A24 /* ALLON External Interrupt Configuration 1 */ +#define REG_ALLON_EI2CON_RESET 0x00000000 /* Reset Value for EI2CON */ +#define REG_ALLON_EI2CON 0x00000A28 /* ALLON External Interrupt Configuration 2 */ +#define REG_ALLON_EICLR_RESET 0x0000C000 /* Reset Value for EICLR */ +#define REG_ALLON_EICLR 0x00000A30 /* ALLON External Interrupt Clear */ +#define REG_ALLON_RSTSTA_RESET 0x00000000 /* Reset Value for RSTSTA */ +#define REG_ALLON_RSTSTA 0x00000A40 /* ALLON Reset Status */ +#define REG_ALLON_RSTCONKEY_RESET 0x00000000 /* Reset Value for RSTCONKEY */ +#define REG_ALLON_RSTCONKEY 0x00000A5C /* ALLON Key Protection for RSTCON Register */ +#define REG_ALLON_LOSCTST_RESET 0x0000008F /* Reset Value for LOSCTST */ +#define REG_ALLON_LOSCTST 0x00000A6C /* ALLON Internal LF Oscillator Test */ +#define REG_ALLON_CLKEN0_RESET 0x00000004 /* Reset Value for CLKEN0 */ +#define REG_ALLON_CLKEN0 0x00000A70 /* ALLON 32KHz Peripheral Clock Enable */ + +/* ============================================================================================================================ + ALLON Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_PWRMOD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_PWRMOD_RAMRETEN 15 /* Retention for RAM */ +#define BITP_ALLON_PWRMOD_ADCRETEN 14 /* Keep ADC Power Switch on in Hibernate */ +#define BITP_ALLON_PWRMOD_SEQSLPEN 3 /* Auto Sleep by Sequencer Command */ +#define BITP_ALLON_PWRMOD_TMRSLPEN 2 /* Auto Sleep by Sleep Wakeup Timer */ +#define BITP_ALLON_PWRMOD_PWRMOD 0 /* Power Mode Control Bits */ +#define BITM_ALLON_PWRMOD_RAMRETEN 0x00008000 /* Retention for RAM */ +#define BITM_ALLON_PWRMOD_ADCRETEN 0x00004000 /* Keep ADC Power Switch on in Hibernate */ +#define BITM_ALLON_PWRMOD_SEQSLPEN 0x00000008 /* Auto Sleep by Sequencer Command */ +#define BITM_ALLON_PWRMOD_TMRSLPEN 0x00000004 /* Auto Sleep by Sleep Wakeup Timer */ +#define BITM_ALLON_PWRMOD_PWRMOD 0x00000003 /* Power Mode Control Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_PWRKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_PWRKEY_PWRKEY 0 /* PWRMOD Key Register */ +#define BITM_ALLON_PWRKEY_PWRKEY 0x0000FFFF /* PWRMOD Key Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_OSCKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_OSCKEY_OSCKEY 0 /* Oscillator Control Key Register. */ +#define BITM_ALLON_OSCKEY_OSCKEY 0x0000FFFF /* Oscillator Control Key Register. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_OSCCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_OSCCON_HFXTALOK 10 /* Status of HFXTAL Oscillator */ +#define BITP_ALLON_OSCCON_HFOSCOK 9 /* Status of HFOSC Oscillator */ +#define BITP_ALLON_OSCCON_LFOSCOK 8 /* Status of LFOSC Oscillator */ +#define BITP_ALLON_OSCCON_HFXTALEN 2 /* High Frequency Crystal Oscillator Enable */ +#define BITP_ALLON_OSCCON_HFOSCEN 1 /* High Frequency Internal Oscillator Enable */ +#define BITP_ALLON_OSCCON_LFOSCEN 0 /* Low Frequency Internal Oscillator Enable */ +#define BITM_ALLON_OSCCON_HFXTALOK 0x00000400 /* Status of HFXTAL Oscillator */ +#define BITM_ALLON_OSCCON_HFOSCOK 0x00000200 /* Status of HFOSC Oscillator */ +#define BITM_ALLON_OSCCON_LFOSCOK 0x00000100 /* Status of LFOSC Oscillator */ +#define BITM_ALLON_OSCCON_HFXTALEN 0x00000004 /* High Frequency Crystal Oscillator Enable */ +#define BITM_ALLON_OSCCON_HFOSCEN 0x00000002 /* High Frequency Internal Oscillator Enable */ +#define BITM_ALLON_OSCCON_LFOSCEN 0x00000001 /* Low Frequency Internal Oscillator Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_TMRCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_TMRCON_TMRINTEN 0 /* Enable Wakeup Timer */ +#define BITM_ALLON_TMRCON_TMRINTEN 0x00000001 /* Enable Wakeup Timer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EI0CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_EI0CON_IRQ3EN 15 /* External Interrupt 3 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ3MDE 12 /* External Interrupt 3 Mode Registers */ +#define BITP_ALLON_EI0CON_IRQ2EN 11 /* External Interrupt 2 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ2MDE 8 /* External Interrupt 2 Mode Registers */ +#define BITP_ALLON_EI0CON_IRQ1EN 7 /* External Interrupt 1 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ1MDE 4 /* External Interrupt 1 Mode Registers */ +#define BITP_ALLON_EI0CON_IRQ0EN 3 /* External Interrupt 0 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ0MDE 0 /* External Interrupt 0 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ3EN 0x00008000 /* External Interrupt 3 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ3MDE 0x00007000 /* External Interrupt 3 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ2EN 0x00000800 /* External Interrupt 2 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ2MDE 0x00000700 /* External Interrupt 2 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ1EN 0x00000080 /* External Interrupt 1 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ1MDE 0x00000070 /* External Interrupt 1 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ0EN 0x00000008 /* External Interrupt 0 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ0MDE 0x00000007 /* External Interrupt 0 Mode Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EI1CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_EI1CON_IRQ7EN 15 /* External Interrupt 7 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ7MDE 12 /* External Interrupt 7 Mode Registers */ +#define BITP_ALLON_EI1CON_IRQ6EN 11 /* External Interrupt 6 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ6MDE 8 /* External Interrupt 6 Mode Registers */ +#define BITP_ALLON_EI1CON_IRQ5EN 7 /* External Interrupt 5 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ5MDE 4 /* External Interrupt 5 Mode Registers */ +#define BITP_ALLON_EI1CON_IRQ4EN 3 /* External Interrupt 4 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ4MDE 0 /* External Interrupt 4 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ7EN 0x00008000 /* External Interrupt 7 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ7MDE 0x00007000 /* External Interrupt 7 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ6EN 0x00000800 /* External Interrupt 6 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ6MDE 0x00000700 /* External Interrupt 6 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ5EN 0x00000080 /* External Interrupt 5 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ5MDE 0x00000070 /* External Interrupt 5 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ4EN 0x00000008 /* External Interrupt 4 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ4MDE 0x00000007 /* External Interrupt 4 Mode Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EI2CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_EI2CON_BUSINTEN 3 /* BUS Interrupt Detection Enable Bit */ +#define BITP_ALLON_EI2CON_BUSINTMDE 0 /* BUS Interrupt Detection Mode Registers */ +#define BITM_ALLON_EI2CON_BUSINTEN 0x00000008 /* BUS Interrupt Detection Enable Bit */ +#define BITM_ALLON_EI2CON_BUSINTMDE 0x00000007 /* BUS Interrupt Detection Mode Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EICLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_EICLR_AUTCLRBUSEN 15 /* Enable Auto Clear of Bus Interrupt */ +#define BITP_ALLON_EICLR_BUSINT 8 /* BUS Interrupt */ +#define BITM_ALLON_EICLR_AUTCLRBUSEN 0x00008000 /* Enable Auto Clear of Bus Interrupt */ +#define BITM_ALLON_EICLR_BUSINT 0x00000100 /* BUS Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_RSTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_RSTSTA_PINSWRST 4 /* Software Reset Pin */ +#define BITP_ALLON_RSTSTA_MMRSWRST 3 /* MMR Software Reset */ +#define BITP_ALLON_RSTSTA_WDRST 2 /* Watchdog Timeout */ +#define BITP_ALLON_RSTSTA_EXTRST 1 /* External Reset */ +#define BITP_ALLON_RSTSTA_POR 0 /* Power-on Reset */ +#define BITM_ALLON_RSTSTA_PINSWRST 0x00000010 /* Software Reset Pin */ +#define BITM_ALLON_RSTSTA_MMRSWRST 0x00000008 /* MMR Software Reset */ +#define BITM_ALLON_RSTSTA_WDRST 0x00000004 /* Watchdog Timeout */ +#define BITM_ALLON_RSTSTA_EXTRST 0x00000002 /* External Reset */ +#define BITM_ALLON_RSTSTA_POR 0x00000001 /* Power-on Reset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_RSTCONKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_RSTCONKEY_KEY 0 /* Reset Control Key Register */ +#define BITM_ALLON_RSTCONKEY_KEY 0x0000FFFF /* Reset Control Key Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_LOSCTST Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_LOSCTST_TRIM 0 /* Trim Caps to Adjust Frequency. */ +#define BITM_ALLON_LOSCTST_TRIM 0x0000000F /* Trim Caps to Adjust Frequency. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_CLKEN0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ALLON_CLKEN0_TIACHPDIS 2 /* TIA Chop Clock Disable */ +#define BITP_ALLON_CLKEN0_SLPWUTDIS 1 /* Sleep/Wakeup Timer Clock Disable */ +#define BITP_ALLON_CLKEN0_WDTDIS 0 /* Watch Dog Timer Clock Disable */ +#define BITM_ALLON_CLKEN0_TIACHPDIS 0x00000004 /* TIA Chop Clock Disable */ +#define BITM_ALLON_CLKEN0_SLPWUTDIS 0x00000002 /* Sleep/Wakeup Timer Clock Disable */ +#define BITM_ALLON_CLKEN0_WDTDIS 0x00000001 /* Watch Dog Timer Clock Disable */ + +/* ============================================================================================================================ + General Purpose Timer + ============================================================================================================================ */ + +/* ============================================================================================================================ + AGPT0 + ============================================================================================================================ */ +#define REG_AGPT0_LD0 0x00000D00 /* AGPT0 16-bit Load Value Register. */ +#define REG_AGPT0_VAL0 0x00000D04 /* AGPT0 16-Bit Timer Value Register. */ +#define REG_AGPT0_CON0 0x00000D08 /* AGPT0 Control Register. */ +#define REG_AGPT0_CLRI0 0x00000D0C /* AGPT0 Clear Interrupt Register. */ +#define REG_AGPT0_CAP0 0x00000D10 /* AGPT0 Capture Register. */ +#define REG_AGPT0_ALD0 0x00000D14 /* AGPT0 16-Bit Load Value, Asynchronous. */ +#define REG_AGPT0_AVAL0 0x00000D18 /* AGPT0 16-Bit Timer Value, Asynchronous Register. */ +#define REG_AGPT0_STA0 0x00000D1C /* AGPT0 Status Register. */ +#define REG_AGPT0_PWMCON0 0x00000D20 /* AGPT0 PWM Control Register. */ +#define REG_AGPT0_PWMMAT0 0x00000D24 /* AGPT0 PWM Match Value Register. */ +#define REG_AGPT0_INTEN 0x00000D28 /* AGPT0 Interrupt Enable */ + +/* ============================================================================================================================ + AGPT0 Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_LD0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_LD0_LOAD 0 /* Load Value */ +#define BITM_AGPT0_LD0_LOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_VAL0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_VAL0_VAL 0 /* Current Count */ +#define BITM_AGPT0_VAL0_VAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Current Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_CON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_CON0_SYNCBYP 15 /* Synchronization Bypass */ +#define BITP_AGPT0_CON0_RSTEN 14 /* Counter and Prescale Reset Enable */ +#define BITP_AGPT0_CON0_EVTEN 13 /* Event Select */ +#define BITP_AGPT0_CON0_EVENT 8 /* Event Select Range */ +#define BITP_AGPT0_CON0_RLD 7 /* Reload Control */ +#define BITP_AGPT0_CON0_CLK 5 /* Clock Select */ +#define BITP_AGPT0_CON0_ENABLE 4 /* Timer Enable */ +#define BITP_AGPT0_CON0_MOD 3 /* Timer Mode */ +#define BITP_AGPT0_CON0_UP 2 /* Count up */ +#define BITP_AGPT0_CON0_PRE 0 /* Prescaler */ +#define BITM_AGPT0_CON0_SYNCBYP (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization Bypass */ +#define BITM_AGPT0_CON0_RSTEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Counter and Prescale Reset Enable */ +#define BITM_AGPT0_CON0_EVTEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Event Select */ +#define BITM_AGPT0_CON0_EVENT (_ADI_MSK_3(0x00001F00,0x00001F00U, uint16_t )) /* Event Select Range */ +#define BITM_AGPT0_CON0_RLD (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Reload Control */ +#define BITM_AGPT0_CON0_CLK (_ADI_MSK_3(0x00000060,0x00000060U, uint16_t )) /* Clock Select */ +#define BITM_AGPT0_CON0_ENABLE (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Timer Enable */ +#define BITM_AGPT0_CON0_MOD (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Timer Mode */ +#define BITM_AGPT0_CON0_UP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Count up */ +#define BITM_AGPT0_CON0_PRE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Prescaler */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_CLRI0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_CLRI0_CAP 1 /* Clear Captured Event Interrupt */ +#define BITP_AGPT0_CLRI0_TMOUT 0 /* Clear Timeout Interrupt */ +#define BITM_AGPT0_CLRI0_CAP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear Captured Event Interrupt */ +#define BITM_AGPT0_CLRI0_TMOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Clear Timeout Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_CAP0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_CAP0_CAP 0 /* 16-bit Captured Value */ +#define BITM_AGPT0_CAP0_CAP (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* 16-bit Captured Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_ALD0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_ALD0_ALOAD 0 /* Load Value, Asynchronous */ +#define BITM_AGPT0_ALD0_ALOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Load Value, Asynchronous */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_AVAL0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_AVAL0_AVAL 0 /* Counter Value */ +#define BITM_AGPT0_AVAL0_AVAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Counter Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_STA0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_STA0_RSTCNT 8 /* Counter Reset Occurring */ +#define BITP_AGPT0_STA0_PDOK 7 /* Clear Interrupt Register Synchronization */ +#define BITP_AGPT0_STA0_BUSY 6 /* Timer Busy */ +#define BITP_AGPT0_STA0_CAP 1 /* Capture Event Pending */ +#define BITP_AGPT0_STA0_TMOUT 0 /* Timeout Event Occurred */ +#define BITM_AGPT0_STA0_RSTCNT (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Counter Reset Occurring */ +#define BITM_AGPT0_STA0_PDOK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Clear Interrupt Register Synchronization */ +#define BITM_AGPT0_STA0_BUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Busy */ +#define BITM_AGPT0_STA0_CAP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Capture Event Pending */ +#define BITM_AGPT0_STA0_TMOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Timeout Event Occurred */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_PWMCON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_PWMCON0_IDLE 1 /* PWM Idle State */ +#define BITP_AGPT0_PWMCON0_MATCHEN 0 /* PWM Match Enabled */ +#define BITM_AGPT0_PWMCON0_IDLE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* PWM Idle State */ +#define BITM_AGPT0_PWMCON0_MATCHEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PWM Match Enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_PWMMAT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_PWMMAT0_MATCHVAL 0 /* PWM Match Value */ +#define BITM_AGPT0_PWMMAT0_MATCHVAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* PWM Match Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_INTEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT0_INTEN_INTEN 0 /* Interrupt Enable */ +#define BITM_AGPT0_INTEN_INTEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Interrupt Enable */ + + +/* ============================================================================================================================ + General Purpose Timer + ============================================================================================================================ */ + +/* ============================================================================================================================ + AGPT1 + ============================================================================================================================ */ +#define REG_AGPT1_LD1 0x00000E00 /* AGPT1 16-bit Load Value Register */ +#define REG_AGPT1_VAL1 0x00000E04 /* AGPT1 16-bit Timer Value Register */ +#define REG_AGPT1_CON1 0x00000E08 /* AGPT1 Control Register */ +#define REG_AGPT1_CLRI1 0x00000E0C /* AGPT1 Clear Interrupt Register */ +#define REG_AGPT1_CAP1 0x00000E10 /* AGPT1 Capture Register */ +#define REG_AGPT1_ALD1 0x00000E14 /* AGPT1 16-bit Load Value, Asynchronous Register */ +#define REG_AGPT1_AVAL1 0x00000E18 /* AGPT1 16-bit Timer Value, Asynchronous Register */ +#define REG_AGPT1_STA1 0x00000E1C /* AGPT1 Status Register */ +#define REG_AGPT1_PWMCON1 0x00000E20 /* AGPT1 PWM Control Register */ +#define REG_AGPT1_PWMMAT1 0x00000E24 /* AGPT1 PWM Match Value Register */ +#define REG_AGPT1_INTEN1 0x00000E28 /* AGPT1 Interrupt Enable */ + +/* ============================================================================================================================ + AGPT1 Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_LD1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_LD1_LOAD 0 /* Load Value */ +#define BITM_AGPT1_LD1_LOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_VAL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_VAL1_VAL 0 /* Current Count */ +#define BITM_AGPT1_VAL1_VAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Current Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_CON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_CON1_SYNCBYP 15 /* Synchronization Bypass */ +#define BITP_AGPT1_CON1_RSTEN 14 /* Counter and Prescale Reset Enable */ +#define BITP_AGPT1_CON1_EVENTEN 13 /* Event Select */ +#define BITP_AGPT1_CON1_EVENT 8 /* Event Select Range */ +#define BITP_AGPT1_CON1_RLD 7 /* Reload Control */ +#define BITP_AGPT1_CON1_CLK 5 /* Clock Select */ +#define BITP_AGPT1_CON1_ENABLE 4 /* Timer Enable */ +#define BITP_AGPT1_CON1_MOD 3 /* Timer Mode */ +#define BITP_AGPT1_CON1_UP 2 /* Count up */ +#define BITP_AGPT1_CON1_PRE 0 /* Prescaler */ +#define BITM_AGPT1_CON1_SYNCBYP (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization Bypass */ +#define BITM_AGPT1_CON1_RSTEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Counter and Prescale Reset Enable */ +#define BITM_AGPT1_CON1_EVENTEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Event Select */ +#define BITM_AGPT1_CON1_EVENT (_ADI_MSK_3(0x00001F00,0x00001F00U, uint16_t )) /* Event Select Range */ +#define BITM_AGPT1_CON1_RLD (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Reload Control */ +#define BITM_AGPT1_CON1_CLK (_ADI_MSK_3(0x00000060,0x00000060U, uint16_t )) /* Clock Select */ +#define BITM_AGPT1_CON1_ENABLE (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Timer Enable */ +#define BITM_AGPT1_CON1_MOD (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Timer Mode */ +#define BITM_AGPT1_CON1_UP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Count up */ +#define BITM_AGPT1_CON1_PRE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Prescaler */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_CLRI1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_CLRI1_CAP 1 /* Clear Captured Event Interrupt */ +#define BITP_AGPT1_CLRI1_TMOUT 0 /* Clear Timeout Interrupt */ +#define BITM_AGPT1_CLRI1_CAP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear Captured Event Interrupt */ +#define BITM_AGPT1_CLRI1_TMOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Clear Timeout Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_CAP1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_CAP1_CAP 0 /* 16-bit Captured Value. */ +#define BITM_AGPT1_CAP1_CAP (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* 16-bit Captured Value. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_ALD1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_ALD1_ALOAD 0 /* Load Value, Asynchronous */ +#define BITM_AGPT1_ALD1_ALOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Load Value, Asynchronous */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_AVAL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_AVAL1_AVAL 0 /* Counter Value */ +#define BITM_AGPT1_AVAL1_AVAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Counter Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_STA1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_STA1_RSTCNT 8 /* Counter Reset Occurring */ +#define BITP_AGPT1_STA1_PDOK 7 /* Clear Interrupt Register Synchronization */ +#define BITP_AGPT1_STA1_BUSY 6 /* Timer Busy */ +#define BITP_AGPT1_STA1_CAP 1 /* Capture Event Pending */ +#define BITP_AGPT1_STA1_TMOUT 0 /* Timeout Event Occurred */ +#define BITM_AGPT1_STA1_RSTCNT (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Counter Reset Occurring */ +#define BITM_AGPT1_STA1_PDOK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Clear Interrupt Register Synchronization */ +#define BITM_AGPT1_STA1_BUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Busy */ +#define BITM_AGPT1_STA1_CAP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Capture Event Pending */ +#define BITM_AGPT1_STA1_TMOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Timeout Event Occurred */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_PWMCON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_PWMCON1_IDLE 1 /* PWM Idle State. */ +#define BITP_AGPT1_PWMCON1_MATCHEN 0 /* PWM Match Enabled. */ +#define BITM_AGPT1_PWMCON1_IDLE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* PWM Idle State. */ +#define BITM_AGPT1_PWMCON1_MATCHEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PWM Match Enabled. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_PWMMAT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_PWMMAT1_MATCHVAL 0 /* PWM Match Value */ +#define BITM_AGPT1_PWMMAT1_MATCHVAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* PWM Match Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_INTEN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AGPT1_INTEN1_INTEN 0 /* Interrupt Enable */ +#define BITM_AGPT1_INTEN1_INTEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Interrupt Enable */ + + +/* ============================================================================================================================ + CRC Accelerator + ============================================================================================================================ */ + +/* ============================================================================================================================ + AFECRC + ============================================================================================================================ */ +#define REG_AFECRC_CTL 0x00001000 /* AFECRC CRC Control Register */ +#define REG_AFECRC_IPDATA 0x00001004 /* AFECRC Data Input. */ +#define REG_AFECRC_RESULT 0x00001008 /* AFECRC CRC Residue */ +#define REG_AFECRC_POLY 0x0000100C /* AFECRC CRC Reduction Polynomial */ +#define REG_AFECRC_IPBITS 0x00001010 /* AFECRC Input Data Bits */ +#define REG_AFECRC_IPBYTE 0x00001014 /* AFECRC Input Data Byte */ +#define REG_AFECRC_CRC_SIG_COMP 0x00001020 /* AFECRC CRC Signature Compare Data Input. */ +#define REG_AFECRC_CRCINTEN 0x00001024 /* AFECRC CRC Error Interrupt Enable Bit */ +#define REG_AFECRC_INTSTA 0x00001028 /* AFECRC CRC Error Interrupt Status Bit */ + +/* ============================================================================================================================ + AFECRC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_CTL_REVID 28 /* Revision ID */ +#define BITP_AFECRC_CTL_MON_EN 9 /* Enable Apb32/Apb16 to Get Address/Data for CRC Calculation */ +#define BITP_AFECRC_CTL_W16SWP 4 /* Word16 Swap Enabled. */ +#define BITP_AFECRC_CTL_BYTMIRR 3 /* Byte Mirroring. */ +#define BITP_AFECRC_CTL_BITMIRR 2 /* Bit Mirroring. */ +#define BITP_AFECRC_CTL_LSBFIRST 1 /* LSB First Calculation Order */ +#define BITP_AFECRC_CTL_EN 0 /* CRC Peripheral Enable */ +#define BITM_AFECRC_CTL_REVID (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t )) /* Revision ID */ +#define BITM_AFECRC_CTL_MON_EN (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* Enable Apb32/Apb16 to Get Address/Data for CRC Calculation */ +#define BITM_AFECRC_CTL_W16SWP (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Word16 Swap Enabled. */ +#define BITM_AFECRC_CTL_BYTMIRR (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Byte Mirroring. */ +#define BITM_AFECRC_CTL_BITMIRR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Bit Mirroring. */ +#define BITM_AFECRC_CTL_LSBFIRST (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* LSB First Calculation Order */ +#define BITM_AFECRC_CTL_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* CRC Peripheral Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_IPDATA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_IPDATA_VALUE 0 /* Data Input. */ +#define BITM_AFECRC_IPDATA_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFF, int32_t )) /* Data Input. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_RESULT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_RESULT_VALUE 0 /* CRC Residue */ +#define BITM_AFECRC_RESULT_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFF, int32_t )) /* CRC Residue */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_POLY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_POLY_VALUE 0 /* CRC Reduction Polynomial */ +#define BITM_AFECRC_POLY_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* CRC Reduction Polynomial */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_IPBITS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_IPBITS_DATA_BITS 0 /* Input Data Bits. */ +#define BITM_AFECRC_IPBITS_DATA_BITS (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t )) /* Input Data Bits. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_IPBYTE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_IPBYTE_DATA_BYTE 0 /* Input Data Byte. */ +#define BITM_AFECRC_IPBYTE_DATA_BYTE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t )) /* Input Data Byte. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_CRC_SIG_COMP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_CRC_SIG_COMP_CRC_SIG 0 /* CRC Signature Compare Data Input. */ +#define BITM_AFECRC_CRC_SIG_COMP_CRC_SIG (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* CRC Signature Compare Data Input. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_CRCINTEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_CRCINTEN_RESERVED_31_1 1 /* Reserved */ +#define BITP_AFECRC_CRCINTEN_CRC_ERR_EN 0 /* CRC Error Interrupt Enable Bit */ +#define BITM_AFECRC_CRCINTEN_RESERVED_31_1 (_ADI_MSK_3(0xFFFFFFFE,0xFFFFFFFEUL, uint32_t )) /* Reserved */ +#define BITM_AFECRC_CRCINTEN_CRC_ERR_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* CRC Error Interrupt Enable Bit */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_INTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFECRC_INTSTA_CRC_ERR_ST 0 /* CRC Error Interrupt Status Bit */ +#define BITM_AFECRC_INTSTA_CRC_ERR_ST (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* CRC Error Interrupt Status Bit */ + + +/* ============================================================================================================================ + + ============================================================================================================================ */ + +/* ============================================================================================================================ + AFE + ============================================================================================================================ */ +#define REG_AFE_AFECON_RESET 0x00080000 /* Reset Value for AFECON */ +#define REG_AFE_AFECON 0x00002000 /* AFE AFE Configuration */ +#define REG_AFE_SEQCON_RESET 0x00000002 /* Reset Value for SEQCON */ +#define REG_AFE_SEQCON 0x00002004 /* AFE Sequencer Configuration */ +#define REG_AFE_FIFOCON_RESET 0x00001010 /* Reset Value for FIFOCON */ +#define REG_AFE_FIFOCON 0x00002008 /* AFE FIFOs Configuration */ +#define REG_AFE_SWCON_RESET 0x0000FFFF /* Reset Value for SWCON */ +#define REG_AFE_SWCON 0x0000200C /* AFE Switch Matrix Configuration */ +#define REG_AFE_HSDACCON_RESET 0x0000001E /* Reset Value for HSDACCON */ +#define REG_AFE_HSDACCON 0x00002010 /* AFE High Speed DAC Configuration */ +#define REG_AFE_WGCON_RESET 0x00000030 /* Reset Value for WGCON */ +#define REG_AFE_WGCON 0x00002014 /* AFE Waveform Generator Configuration */ +#define REG_AFE_WGDCLEVEL1_RESET 0x00000000 /* Reset Value for WGDCLEVEL1 */ +#define REG_AFE_WGDCLEVEL1 0x00002018 /* AFE Waveform Generator - Trapezoid DC Level 1 */ +#define REG_AFE_WGDCLEVEL2_RESET 0x00000000 /* Reset Value for WGDCLEVEL2 */ +#define REG_AFE_WGDCLEVEL2 0x0000201C /* AFE Waveform Generator - Trapezoid DC Level 2 */ +#define REG_AFE_WGDELAY1_RESET 0x00000000 /* Reset Value for WGDELAY1 */ +#define REG_AFE_WGDELAY1 0x00002020 /* AFE Waveform Generator - Trapezoid Delay 1 Time */ +#define REG_AFE_WGSLOPE1_RESET 0x00000000 /* Reset Value for WGSLOPE1 */ +#define REG_AFE_WGSLOPE1 0x00002024 /* AFE Waveform Generator - Trapezoid Slope 1 Time */ +#define REG_AFE_WGDELAY2_RESET 0x00000000 /* Reset Value for WGDELAY2 */ +#define REG_AFE_WGDELAY2 0x00002028 /* AFE Waveform Generator - Trapezoid Delay 2 Time */ +#define REG_AFE_WGSLOPE2_RESET 0x00000000 /* Reset Value for WGSLOPE2 */ +#define REG_AFE_WGSLOPE2 0x0000202C /* AFE Waveform Generator - Trapezoid Slope 2 Time */ +#define REG_AFE_WGFCW_RESET 0x00000000 /* Reset Value for WGFCW */ +#define REG_AFE_WGFCW 0x00002030 /* AFE Waveform Generator - Sinusoid Frequency Control Word */ +#define REG_AFE_WGPHASE_RESET 0x00000000 /* Reset Value for WGPHASE */ +#define REG_AFE_WGPHASE 0x00002034 /* AFE Waveform Generator - Sinusoid Phase Offset */ +#define REG_AFE_WGOFFSET_RESET 0x00000000 /* Reset Value for WGOFFSET */ +#define REG_AFE_WGOFFSET 0x00002038 /* AFE Waveform Generator - Sinusoid Offset */ +#define REG_AFE_WGAMPLITUDE_RESET 0x00000000 /* Reset Value for WGAMPLITUDE */ +#define REG_AFE_WGAMPLITUDE 0x0000203C /* AFE Waveform Generator - Sinusoid Amplitude */ +#define REG_AFE_ADCFILTERCON_RESET 0x00000301 /* Reset Value for ADCFILTERCON */ +#define REG_AFE_ADCFILTERCON 0x00002044 /* AFE ADC Output Filters Configuration */ +#define REG_AFE_HSDACDAT_RESET 0x00000800 /* Reset Value for HSDACDAT */ +#define REG_AFE_HSDACDAT 0x00002048 /* AFE HS DAC Code */ +#define REG_AFE_LPREFBUFCON_RESET 0x00000000 /* Reset Value for LPREFBUFCON */ +#define REG_AFE_LPREFBUFCON 0x00002050 /* AFE LPREF_BUF_CON */ +#define REG_AFE_SYNCEXTDEVICE_RESET 0x00000000 /* Reset Value for SYNCEXTDEVICE */ +#define REG_AFE_SYNCEXTDEVICE 0x00002054 /* AFE SYNC External Devices */ +#define REG_AFE_SEQCRC_RESET 0x00000001 /* Reset Value for SEQCRC */ +#define REG_AFE_SEQCRC 0x00002060 /* AFE Sequencer CRC Value */ +#define REG_AFE_SEQCNT_RESET 0x00000000 /* Reset Value for SEQCNT */ +#define REG_AFE_SEQCNT 0x00002064 /* AFE Sequencer Command Count */ +#define REG_AFE_SEQTIMEOUT_RESET 0x00000000 /* Reset Value for SEQTIMEOUT */ +#define REG_AFE_SEQTIMEOUT 0x00002068 /* AFE Sequencer Timeout Counter */ +#define REG_AFE_DATAFIFORD_RESET 0x00000000 /* Reset Value for DATAFIFORD */ +#define REG_AFE_DATAFIFORD 0x0000206C /* AFE Data FIFO Read */ +#define REG_AFE_CMDFIFOWRITE_RESET 0x00000000 /* Reset Value for CMDFIFOWRITE */ +#define REG_AFE_CMDFIFOWRITE 0x00002070 /* AFE Command FIFO Write */ +#define REG_AFE_ADCDAT_RESET 0x00000000 /* Reset Value for ADCDAT */ +#define REG_AFE_ADCDAT 0x00002074 /* AFE ADC Raw Result */ +#define REG_AFE_DFTREAL_RESET 0x00000000 /* Reset Value for DFTREAL */ +#define REG_AFE_DFTREAL 0x00002078 /* AFE DFT Result, Real Part */ +#define REG_AFE_DFTIMAG_RESET 0x00000000 /* Reset Value for DFTIMAG */ +#define REG_AFE_DFTIMAG 0x0000207C /* AFE DFT Result, Imaginary Part */ +#define REG_AFE_SINC2DAT_RESET 0x00000000 /* Reset Value for SINC2DAT */ +#define REG_AFE_SINC2DAT 0x00002080 /* AFE Supply Rejection Filter Result */ +#define REG_AFE_TEMPSENSDAT_RESET 0x00000000 /* Reset Value for TEMPSENSDAT */ +#define REG_AFE_TEMPSENSDAT 0x00002084 /* AFE Temperature Sensor Result */ +#define REG_AFE_AFEGENINTSTA_RESET 0x00000000 /* Reset Value for AFEGENINTSTA */ +#define REG_AFE_AFEGENINTSTA 0x0000209C /* AFE Analog Generation Interrupt */ +#define REG_AFE_ADCMIN_RESET 0x00000000 /* Reset Value for ADCMIN */ +#define REG_AFE_ADCMIN 0x000020A8 /* AFE ADC Minimum Value Check */ +#define REG_AFE_ADCMINSM_RESET 0x00000000 /* Reset Value for ADCMINSM */ +#define REG_AFE_ADCMINSM 0x000020AC /* AFE ADCMIN Hysteresis Value */ +#define REG_AFE_ADCMAX_RESET 0x00000000 /* Reset Value for ADCMAX */ +#define REG_AFE_ADCMAX 0x000020B0 /* AFE ADC Maximum Value Check */ +#define REG_AFE_ADCMAXSMEN_RESET 0x00000000 /* Reset Value for ADCMAXSMEN */ +#define REG_AFE_ADCMAXSMEN 0x000020B4 /* AFE ADCMAX Hysteresis Value */ +#define REG_AFE_ADCDELTA_RESET 0x00000000 /* Reset Value for ADCDELTA */ +#define REG_AFE_ADCDELTA 0x000020B8 /* AFE ADC Delta Value */ +#define REG_AFE_HPOSCCON_RESET 0x00000024 /* Reset Value for HPOSCCON */ +#define REG_AFE_HPOSCCON 0x000020BC /* AFE HPOSC Configuration */ +#define REG_AFE_DFTCON_RESET 0x00000090 /* Reset Value for DFTCON */ +#define REG_AFE_DFTCON 0x000020D0 /* AFE AFE DSP Configuration */ +#define REG_AFE_LPTIASW1 0x000020E0 /* AFE ULPTIA Switch Configuration for Channel 1 */ +#define REG_AFE_LPTIASW0_RESET 0x00000000 /* Reset Value for LPTIASW0 */ +#define REG_AFE_LPTIACON1 0x000020E8 /* AFE ULPTIA Control Bits Channel 1 */ +#define REG_AFE_LPTIASW0 0x000020E4 /* AFE ULPTIA Switch Configuration for Channel 0 */ +#define REG_AFE_LPTIACON0_RESET 0x00000003 /* Reset Value for LPTIACON0 */ +#define REG_AFE_LPTIACON0 0x000020EC /* AFE ULPTIA Control Bits Channel 0 */ +#define REG_AFE_HSRTIACON_RESET 0x0000000F /* Reset Value for HSRTIACON */ +#define REG_AFE_HSRTIACON 0x000020F0 /* AFE High Power RTIA Configuration */ +#define REG_AFE_DE1RESCON 0x000020F4 /* AFE DE1 HSTIA Resistors Configuration */ +#define REG_AFE_DE0RESCON_RESET 0x000000FF /* Reset Value for DE0RESCON */ +#define REG_AFE_DE0RESCON 0x000020F8 /* AFE DE0 HSTIA Resistors Configuration */ +#define REG_AFE_HSTIACON_RESET 0x00000000 /* Reset Value for HSTIACON */ +#define REG_AFE_HSTIACON 0x000020FC /* AFE HSTIA Amplifier Configuration */ +#define REG_AFE_LPMODEKEY_RESET 0x00000000 /* Reset Value for LPMODEKEY */ +#define REG_AFE_LPMODEKEY 0x0000210C /* AFE LP Mode AFE Control Lock */ +#define REG_AFE_LPMODECLKSEL_RESET 0x00000000 /* Reset Value for LPMODECLKSEL */ +#define REG_AFE_LPMODECLKSEL 0x00002110 /* AFE LFSYSCLKEN */ +#define REG_AFE_LPMODECON_RESET 0x00000102 /* Reset Value for LPMODECON */ +#define REG_AFE_LPMODECON 0x00002114 /* AFE LPMODECON */ +#define REG_AFE_SEQSLPLOCK_RESET 0x00000000 /* Reset Value for SEQSLPLOCK */ +#define REG_AFE_SEQSLPLOCK 0x00002118 /* AFE Sequencer Sleep Control Lock */ +#define REG_AFE_SEQTRGSLP_RESET 0x00000000 /* Reset Value for SEQTRGSLP */ +#define REG_AFE_SEQTRGSLP 0x0000211C /* AFE Sequencer Trigger Sleep */ +#define REG_AFE_LPDACDAT0_RESET 0x00000000 /* Reset Value for LPDACDAT0 */ +#define REG_AFE_LPDACDAT0 0x00002120 /* AFE LPDAC Data-out */ +#define REG_AFE_LPDACSW0_RESET 0x00000000 /* Reset Value for LPDACSW0 */ +#define REG_AFE_LPDACSW0 0x00002124 /* AFE LPDAC0 Switch Control */ +#define REG_AFE_LPDACCON0_RESET 0x00000002 /* Reset Value for LPDACCON0 */ +#define REG_AFE_LPDACCON0 0x00002128 /* AFE LPDAC Control Bits */ +#define REG_AFE_LPDACDAT1 0x0000212C /* AFE Low Power DAC1 data register */ +#define REG_AFE_LPDACSW1 0x00002130 /* AFE Control register for switches to LPDAC1 */ +#define REG_AFE_LPDACCON1 0x00002134 /* AFE ULP_DACCON1 */ +#define REG_AFE_DSWFULLCON_RESET 0x00000000 /* Reset Value for DSWFULLCON */ +#define REG_AFE_DSWFULLCON 0x00002150 /* AFE Switch Matrix Full Configuration (D) */ +#define REG_AFE_NSWFULLCON_RESET 0x00000000 /* Reset Value for NSWFULLCON */ +#define REG_AFE_NSWFULLCON 0x00002154 /* AFE Switch Matrix Full Configuration (N) */ +#define REG_AFE_PSWFULLCON_RESET 0x00000000 /* Reset Value for PSWFULLCON */ +#define REG_AFE_PSWFULLCON 0x00002158 /* AFE Switch Matrix Full Configuration (P) */ +#define REG_AFE_TSWFULLCON_RESET 0x00000000 /* Reset Value for TSWFULLCON */ +#define REG_AFE_TSWFULLCON 0x0000215C /* AFE Switch Matrix Full Configuration (T) */ +#define REG_AFE_TEMPSENS_RESET 0x00000000 /* Reset Value for TEMPSENS */ +#define REG_AFE_TEMPSENS 0x00002174 /* AFE Temp Sensor Configuration */ +#define REG_AFE_BUFSENCON_RESET 0x00000037 /* Reset Value for BUFSENCON */ +#define REG_AFE_BUFSENCON 0x00002180 /* AFE HP and LP Buffer Control */ +#define REG_AFE_ADCCON_RESET 0x00000000 /* Reset Value for ADCCON */ +#define REG_AFE_ADCCON 0x000021A8 /* AFE ADC Configuration */ +#define REG_AFE_DSWSTA_RESET 0x00000000 /* Reset Value for DSWSTA */ +#define REG_AFE_DSWSTA 0x000021B0 /* AFE Switch Matrix Status (D) */ +#define REG_AFE_PSWSTA_RESET 0x00006000 /* Reset Value for PSWSTA */ +#define REG_AFE_PSWSTA 0x000021B4 /* AFE Switch Matrix Status (P) */ +#define REG_AFE_NSWSTA_RESET 0x00000C00 /* Reset Value for NSWSTA */ +#define REG_AFE_NSWSTA 0x000021B8 /* AFE Switch Matrix Status (N) */ +#define REG_AFE_TSWSTA_RESET 0x00000000 /* Reset Value for TSWSTA */ +#define REG_AFE_TSWSTA 0x000021BC /* AFE Switch Matrix Status (T) */ +#define REG_AFE_STATSVAR_RESET 0x00000000 /* Reset Value for STATSVAR */ +#define REG_AFE_STATSVAR 0x000021C0 /* AFE Variance Output */ +#define REG_AFE_STATSCON_RESET 0x00000000 /* Reset Value for STATSCON */ +#define REG_AFE_STATSCON 0x000021C4 /* AFE Statistics Control */ +#define REG_AFE_STATSMEAN_RESET 0x00000000 /* Reset Value for STATSMEAN */ +#define REG_AFE_STATSMEAN 0x000021C8 /* AFE Statistics Mean Output */ +#define REG_AFE_SEQ0INFO_RESET 0x00000000 /* Reset Value for SEQ0INFO */ +#define REG_AFE_SEQ0INFO 0x000021CC /* AFE Sequence 0 Info */ +#define REG_AFE_SEQ2INFO_RESET 0x00000000 /* Reset Value for SEQ2INFO */ +#define REG_AFE_SEQ2INFO 0x000021D0 /* AFE Sequence 2 Info */ +#define REG_AFE_CMDFIFOWADDR_RESET 0x00000000 /* Reset Value for CMDFIFOWADDR */ +#define REG_AFE_CMDFIFOWADDR 0x000021D4 /* AFE Command FIFO Write Address */ +#define REG_AFE_CMDDATACON_RESET 0x00000410 /* Reset Value for CMDDATACON */ +#define REG_AFE_CMDDATACON 0x000021D8 /* AFE Command Data Control */ +#define REG_AFE_DATAFIFOTHRES_RESET 0x00000000 /* Reset Value for DATAFIFOTHRES */ +#define REG_AFE_DATAFIFOTHRES 0x000021E0 /* AFE Data FIFO Threshold */ +#define REG_AFE_SEQ3INFO_RESET 0x00000000 /* Reset Value for SEQ3INFO */ +#define REG_AFE_SEQ3INFO 0x000021E4 /* AFE Sequence 3 Info */ +#define REG_AFE_SEQ1INFO_RESET 0x00000000 /* Reset Value for SEQ1INFO */ +#define REG_AFE_SEQ1INFO 0x000021E8 /* AFE Sequence 1 Info */ +#define REG_AFE_REPEATADCCNV_RESET 0x00000160 /* Reset Value for REPEATADCCNV */ +#define REG_AFE_REPEATADCCNV 0x000021F0 /* AFE REPEAT ADC Conversions */ +#define REG_AFE_FIFOCNTSTA_RESET 0x00000000 /* Reset Value for FIFOCNTSTA */ +#define REG_AFE_FIFOCNTSTA 0x00002200 /* AFE CMD and DATA FIFO INTERNAL DATA COUNT */ +#define REG_AFE_CALDATLOCK_RESET 0x00000000 /* Reset Value for CALDATLOCK */ +#define REG_AFE_CALDATLOCK 0x00002230 /* AFE Calibration Data Lock */ +#define REG_AFE_ADCOFFSETHSTIA_RESET 0x00000000 /* Reset Value for ADCOFFSETHSTIA */ +#define REG_AFE_ADCOFFSETHSTIA 0x00002234 /* AFE ADC Offset Calibration High Speed TIA Channel */ +#define REG_AFE_ADCGAINTEMPSENS0_RESET 0x00004000 /* Reset Value for ADCGAINTEMPSENS0 */ +#define REG_AFE_ADCGAINTEMPSENS0 0x00002238 /* AFE ADC Gain Calibration Temp Sensor Channel */ +#define REG_AFE_ADCOFFSETTEMPSENS0_RESET 0x00000000 /* Reset Value for ADCOFFSETTEMPSENS0 */ +#define REG_AFE_ADCOFFSETTEMPSENS0 0x0000223C /* AFE ADC Offset Calibration Temp Sensor Channel 0 */ +#define REG_AFE_ADCGAINGN1_RESET 0x00004000 /* Reset Value for ADCGAINGN1 */ +#define REG_AFE_ADCGAINGN1 0x00002240 /* AFE ADCPGAGN1: ADC Gain Calibration Auxiliary Input Channel */ +#define REG_AFE_ADCOFFSETGN1_RESET 0x00000000 /* Reset Value for ADCOFFSETGN1 */ +#define REG_AFE_ADCOFFSETGN1 0x00002244 /* AFE ADC Offset Calibration Auxiliary Channel (PGA Gain=1) */ +#define REG_AFE_DACGAIN_RESET 0x00000800 /* Reset Value for DACGAIN */ +#define REG_AFE_DACGAIN 0x00002260 /* AFE DACGAIN */ +#define REG_AFE_DACOFFSETATTEN_RESET 0x00000000 /* Reset Value for DACOFFSETATTEN */ +#define REG_AFE_DACOFFSETATTEN 0x00002264 /* AFE DAC Offset with Attenuator Enabled (LP Mode) */ +#define REG_AFE_DACOFFSET_RESET 0x00000000 /* Reset Value for DACOFFSET */ +#define REG_AFE_DACOFFSET 0x00002268 /* AFE DAC Offset with Attenuator Disabled (LP Mode) */ +#define REG_AFE_ADCGAINGN1P5_RESET 0x00004000 /* Reset Value for ADCGAINGN1P5 */ +#define REG_AFE_ADCGAINGN1P5 0x00002270 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=1.5) */ +#define REG_AFE_ADCGAINGN2_RESET 0x00004000 /* Reset Value for ADCGAINGN2 */ +#define REG_AFE_ADCGAINGN2 0x00002274 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=2) */ +#define REG_AFE_ADCGAINGN4_RESET 0x00004000 /* Reset Value for ADCGAINGN4 */ +#define REG_AFE_ADCGAINGN4 0x00002278 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=4) */ +#define REG_AFE_ADCPGAOFFSETCANCEL_RESET 0x00000000 /* Reset Value for ADCPGAOFFSETCANCEL */ +#define REG_AFE_ADCPGAOFFSETCANCEL 0x00002280 /* AFE ADC Offset Cancellation (Optional) */ +#define REG_AFE_ADCGNHSTIA_RESET 0x00004000 /* Reset Value for ADCGNHSTIA */ +#define REG_AFE_ADCGNHSTIA 0x00002284 /* AFE ADC Gain Calibration for HS TIA Channel */ +#define REG_AFE_ADCOFFSETLPTIA0_RESET 0x00000000 /* Reset Value for ADCOFFSETLPTIA0 */ +#define REG_AFE_ADCOFFSETLPTIA0 0x00002288 /* AFE ADC Offset Calibration ULP-TIA0 Channel */ +#define REG_AFE_ADCGNLPTIA0_RESET 0x00004000 /* Reset Value for ADCGNLPTIA0 */ +#define REG_AFE_ADCGNLPTIA0 0x0000228C /* AFE ADC GAIN Calibration for LP TIA0 Channel */ +#define REG_AFE_ADCPGAGN4OFCAL_RESET 0x00004000 /* Reset Value for ADCPGAGN4OFCAL */ +#define REG_AFE_ADCPGAGN4OFCAL 0x00002294 /* AFE ADC Gain Calibration with DC Cancellation(PGA G=4) */ +#define REG_AFE_ADCGAINGN9_RESET 0x00004000 /* Reset Value for ADCGAINGN9 */ +#define REG_AFE_ADCGAINGN9 0x00002298 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=9) */ +#define REG_AFE_ADCOFFSETEMPSENS1_RESET 0x00000000 /* Reset Value for ADCOFFSETEMPSENS1 */ +#define REG_AFE_ADCOFFSETEMPSENS1 0x000022A8 /* AFE ADC Offset Calibration Temp Sensor Channel 1 */ +#define REG_AFE_ADCGAINDIOTEMPSENS_RESET 0x00004000 /* Reset Value for ADCGAINDIOTEMPSENS */ +#define REG_AFE_ADCGAINDIOTEMPSENS 0x000022AC /* AFE ADC Gain Calibration Diode Temperature Sensor Channel */ +#define REG_AFE_DACOFFSETATTENHP_RESET 0x00000000 /* Reset Value for DACOFFSETATTENHP */ +#define REG_AFE_DACOFFSETATTENHP 0x000022B8 /* AFE DAC Offset with Attenuator Enabled (HP Mode) */ +#define REG_AFE_DACOFFSETHP_RESET 0x00000000 /* Reset Value for DACOFFSETHP */ +#define REG_AFE_DACOFFSETHP 0x000022BC /* AFE DAC Offset with Attenuator Disabled (HP Mode) */ +#define REG_AFE_ADCGNLPTIA1_RESET 0x00004000 /* Reset Value for ADCGNLPTIA1 */ +#define REG_AFE_ADCOFFSETLPTIA1 0x000022C0 /* AFE ADC Offset Calibration ULP-TIA0 Channel */ +#define REG_AFE_ADCGNLPTIA1 0x000022C4 /* AFE ADC GAIN Calibration for LP TIA1 Channel */ +#define REG_AFE_ADCOFFSETGN2_RESET 0x00000000 /* Reset Value for ADCOFFSETGN2 */ +#define REG_AFE_ADCOFFSETGN2 0x000022C8 /* AFE Offset Calibration Auxiliary Channel (PGA Gain =2) */ +#define REG_AFE_ADCOFFSETGN1P5_RESET 0x00000000 /* Reset Value for ADCOFFSETGN1P5 */ +#define REG_AFE_ADCOFFSETGN1P5 0x000022CC /* AFE Offset Calibration Auxiliary Channel (PGA Gain =1.5) */ +#define REG_AFE_ADCOFFSETGN9_RESET 0x00000000 /* Reset Value for ADCOFFSETGN9 */ +#define REG_AFE_ADCOFFSETGN9 0x000022D0 /* AFE Offset Calibration Auxiliary Channel (PGA Gain =9) */ +#define REG_AFE_ADCOFFSETGN4_RESET 0x00000000 /* Reset Value for ADCOFFSETGN4 */ +#define REG_AFE_ADCOFFSETGN4 0x000022D4 /* AFE Offset Calibration Auxiliary Channel (PGA Gain =4) */ +#define REG_AFE_PMBW_RESET 0x00088800 /* Reset Value for PMBW */ +#define REG_AFE_PMBW 0x000022F0 /* AFE Power Mode Configuration */ +#define REG_AFE_SWMUX_RESET 0x00000000 /* Reset Value for SWMUX */ +#define REG_AFE_SWMUX 0x0000235C /* AFE Switch Mux for ECG */ +#define REG_AFE_AFE_TEMPSEN_DIO_RESET 0x00020000 /* Reset Value for AFE_TEMPSEN_DIO */ +#define REG_AFE_AFE_TEMPSEN_DIO 0x00002374 /* AFE AFE_TEMPSEN_DIO */ +#define REG_AFE_ADCBUFCON_RESET 0x005F3D00 /* Reset Value for ADCBUFCON */ +#define REG_AFE_ADCBUFCON 0x0000238C /* AFE Configure ADC Input Buffer */ + +/* ============================================================================================================================ + AFE Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_AFECON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_AFECON_DACBUFEN 21 /* Enable DC DAC Buffer */ +#define BITP_AFE_AFECON_DACREFEN 20 /* High Speed DAC Reference Enable */ +#define BITP_AFE_AFECON_ALDOILIMITEN 19 /* Analog LDO Current Limiting Enable */ +#define BITP_AFE_AFECON_SINC2EN 16 /* ADC Output 50/60Hz Filter Enable */ +#define BITP_AFE_AFECON_DFTEN 15 /* DFT Hardware Accelerator Enable */ +#define BITP_AFE_AFECON_WAVEGENEN 14 /* Waveform Generator Enable */ +#define BITP_AFE_AFECON_TEMPCONVEN 13 /* ADC Temp Sensor Convert Enable */ +#define BITP_AFE_AFECON_TEMPSENSEN 12 /* ADC Temperature Sensor Channel Enable */ +#define BITP_AFE_AFECON_TIAEN 11 /* High Power TIA Enable */ +#define BITP_AFE_AFECON_INAMPEN 10 /* Enable Excitation Amplifier */ +#define BITP_AFE_AFECON_EXBUFEN 9 /* Enable Excitation Buffer */ +#define BITP_AFE_AFECON_ADCCONVEN 8 /* ADC Conversion Start Enable */ +#define BITP_AFE_AFECON_ADCEN 7 /* ADC Power Enable */ +#define BITP_AFE_AFECON_DACEN 6 /* High Power DAC Enable */ +#define BITP_AFE_AFECON_HPREFDIS 5 /* Disable High Power Reference */ +#define BITM_AFE_AFECON_DACBUFEN 0x00200000 /* Enable DC DAC Buffer */ +#define BITM_AFE_AFECON_DACREFEN 0x00100000 /* High Speed DAC Reference Enable */ +#define BITM_AFE_AFECON_ALDOILIMITEN 0x00080000 /* Analog LDO Current Limiting Enable */ +#define BITM_AFE_AFECON_SINC2EN 0x00010000 /* ADC Output 50/60Hz Filter Enable */ +#define BITM_AFE_AFECON_DFTEN 0x00008000 /* DFT Hardware Accelerator Enable */ +#define BITM_AFE_AFECON_WAVEGENEN 0x00004000 /* Waveform Generator Enable */ +#define BITM_AFE_AFECON_TEMPCONVEN 0x00002000 /* ADC Temp Sensor Convert Enable */ +#define BITM_AFE_AFECON_TEMPSENSEN 0x00001000 /* ADC Temperature Sensor Channel Enable */ +#define BITM_AFE_AFECON_TIAEN 0x00000800 /* High Power TIA Enable */ +#define BITM_AFE_AFECON_INAMPEN 0x00000400 /* Enable Excitation Amplifier */ +#define BITM_AFE_AFECON_EXBUFEN 0x00000200 /* Enable Excitation Buffer */ +#define BITM_AFE_AFECON_ADCCONVEN 0x00000100 /* ADC Conversion Start Enable */ +#define BITM_AFE_AFECON_ADCEN 0x00000080 /* ADC Power Enable */ +#define BITM_AFE_AFECON_DACEN 0x00000040 /* High Power DAC Enable */ +#define BITM_AFE_AFECON_HPREFDIS 0x00000020 /* Disable High Power Reference */ +#define ENUM_AFE_AFECON_OFF 0x00000000 /* DACEN: High Power DAC Disabled */ +#define ENUM_AFE_AFECON_ON 0x00000040 /* DACEN: High Power DAC Enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQCON_SEQWRTMR 8 /* Timer for Sequencer Write Commands */ +#define BITP_AFE_SEQCON_SEQHALT 4 /* Halt Seq */ +#define BITP_AFE_SEQCON_SEQHALTFIFOEMPTY 1 /* Halt Sequencer If Empty */ +#define BITP_AFE_SEQCON_SEQEN 0 /* Enable Sequencer */ +#define BITM_AFE_SEQCON_SEQWRTMR 0x0000FF00 /* Timer for Sequencer Write Commands */ +#define BITM_AFE_SEQCON_SEQHALT 0x00000010 /* Halt Seq */ +#define BITM_AFE_SEQCON_SEQHALTFIFOEMPTY 0x00000002 /* Halt Sequencer If Empty */ +#define BITM_AFE_SEQCON_SEQEN 0x00000001 /* Enable Sequencer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_FIFOCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_FIFOCON_DATAFIFOSRCSEL 13 /* Selects the Source for the Data FIFO. */ +#define BITP_AFE_FIFOCON_DATAFIFOEN 11 /* Data FIFO Enable. */ +#define BITM_AFE_FIFOCON_DATAFIFOSRCSEL 0x0000E000 /* Selects the Source for the Data FIFO. */ +#define BITM_AFE_FIFOCON_DATAFIFOEN 0x00000800 /* Data FIFO Enable. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SWCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SWCON_T11CON 19 /* Control of T[11] */ +#define BITP_AFE_SWCON_T10CON 18 /* Control of T[10] */ +#define BITP_AFE_SWCON_T9CON 17 /* Control of T[9] */ +#define BITP_AFE_SWCON_SWSOURCESEL 16 /* Switch Control Select */ +#define BITP_AFE_SWCON_TMUXCON 12 /* Control of T Switch MUX. */ +#define BITP_AFE_SWCON_NMUXCON 8 /* Control of N Switch MUX */ +#define BITP_AFE_SWCON_PMUXCON 4 /* Control of P Switch MUX */ +#define BITP_AFE_SWCON_DMUXCON 0 /* Control of D Switch MUX */ +#define BITM_AFE_SWCON_T11CON 0x00080000 /* Control of T[11] */ +#define BITM_AFE_SWCON_T10CON 0x00040000 /* Control of T[10] */ +#define BITM_AFE_SWCON_T9CON 0x00020000 /* Control of T[9] */ +#define BITM_AFE_SWCON_SWSOURCESEL 0x00010000 /* Switch Control Select */ +#define BITM_AFE_SWCON_TMUXCON 0x0000F000 /* Control of T Switch MUX. */ +#define BITM_AFE_SWCON_NMUXCON 0x00000F00 /* Control of N Switch MUX */ +#define BITM_AFE_SWCON_PMUXCON 0x000000F0 /* Control of P Switch MUX */ +#define BITM_AFE_SWCON_DMUXCON 0x0000000F /* Control of D Switch MUX */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSDACCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_HSDACCON_INAMPGNMDE 12 /* Excitation Amplifier Gain Control */ +#define BITP_AFE_HSDACCON_RATE 1 /* DAC Update Rate */ +#define BITP_AFE_HSDACCON_ATTENEN 0 /* PGA Stage Gain Attenuation */ +#define BITM_AFE_HSDACCON_INAMPGNMDE 0x00001000 /* Excitation Amplifier Gain Control */ +#define BITM_AFE_HSDACCON_RATE 0x000001FE /* DAC Update Rate */ +#define BITM_AFE_HSDACCON_ATTENEN 0x00000001 /* PGA Stage Gain Attenuation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGCON_DACGAINCAL 5 /* Bypass DAC Gain */ +#define BITP_AFE_WGCON_DACOFFSETCAL 4 /* Bypass DAC Offset */ +#define BITP_AFE_WGCON_TYPESEL 1 /* Selects the Type of Waveform */ +#define BITP_AFE_WGCON_TRAPRSTEN 0 /* Resets the Trapezoid Waveform Generator */ +#define BITM_AFE_WGCON_DACGAINCAL 0x00000020 /* Bypass DAC Gain */ +#define BITM_AFE_WGCON_DACOFFSETCAL 0x00000010 /* Bypass DAC Offset */ +#define BITM_AFE_WGCON_TYPESEL 0x00000006 /* Selects the Type of Waveform */ +#define BITM_AFE_WGCON_TRAPRSTEN 0x00000001 /* Resets the Trapezoid Waveform Generator */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDCLEVEL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGDCLEVEL1_TRAPDCLEVEL1 0 /* DC Level 1 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDCLEVEL1_TRAPDCLEVEL1 0x00000FFF /* DC Level 1 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDCLEVEL2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGDCLEVEL2_TRAPDCLEVEL2 0 /* DC Level 2 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDCLEVEL2_TRAPDCLEVEL2 0x00000FFF /* DC Level 2 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDELAY1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGDELAY1_DELAY1 0 /* Delay 1 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDELAY1_DELAY1 0x000FFFFF /* Delay 1 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGSLOPE1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGSLOPE1_SLOPE1 0 /* Slope 1 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGSLOPE1_SLOPE1 0x000FFFFF /* Slope 1 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDELAY2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGDELAY2_DELAY2 0 /* Delay 2 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDELAY2_DELAY2 0x000FFFFF /* Delay 2 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGSLOPE2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGSLOPE2_SLOPE2 0 /* Slope 2 Value for Trapezoid Waveform Generation. */ +#define BITM_AFE_WGSLOPE2_SLOPE2 0x000FFFFF /* Slope 2 Value for Trapezoid Waveform Generation. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGFCW Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGFCW_SINEFCW 0 /* Sinusoid Generator Frequency Control Word */ +#define BITM_AFE_WGFCW_SINEFCW 0x00FFFFFF /* Sinusoid Generator Frequency Control Word */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGPHASE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGPHASE_SINEOFFSET 0 /* Sinusoid Phase Offset */ +#define BITM_AFE_WGPHASE_SINEOFFSET 0x000FFFFF /* Sinusoid Phase Offset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGOFFSET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGOFFSET_SINEOFFSET 0 /* Sinusoid Offset */ +#define BITM_AFE_WGOFFSET_SINEOFFSET 0x00000FFF /* Sinusoid Offset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGAMPLITUDE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_WGAMPLITUDE_SINEAMPLITUDE 0 /* Sinusoid Amplitude */ +#define BITM_AFE_WGAMPLITUDE_SINEAMPLITUDE 0x000007FF /* Sinusoid Amplitude */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCFILTERCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCFILTERCON_AVRGNUM 14 /* Number of Samples Averaged */ +#define BITP_AFE_ADCFILTERCON_SINC3OSR 12 /* SINC3 OSR */ +#define BITP_AFE_ADCFILTERCON_SINC2OSR 8 /* SINC2 OSR */ +#define BITP_AFE_ADCFILTERCON_AVRGEN 7 /* Average Function Enable */ +#define BITP_AFE_ADCFILTERCON_SINC3BYP 6 /* SINC3 Filter Bypass */ +#define BITP_AFE_ADCFILTERCON_LPFBYPEN 4 /* 50/60Hz Low Pass Filter */ +#define BITP_AFE_ADCFILTERCON_ADCCLK 0 /* ADC Data Rate */ +#define BITM_AFE_ADCFILTERCON_AVRGNUM 0x0000C000 /* Number of Samples Averaged */ +#define BITM_AFE_ADCFILTERCON_SINC3OSR 0x00003000 /* SINC3 OSR */ +#define BITM_AFE_ADCFILTERCON_SINC2OSR 0x00000F00 /* SINC2 OSR */ +#define BITM_AFE_ADCFILTERCON_AVRGEN 0x00000080 /* Average Function Enable */ +#define BITM_AFE_ADCFILTERCON_SINC3BYP 0x00000040 /* SINC3 Filter Bypass */ +#define BITM_AFE_ADCFILTERCON_LPFBYPEN 0x00000010 /* 50/60Hz Low Pass Filter */ +#define BITM_AFE_ADCFILTERCON_ADCCLK 0x00000001 /* ADC Data Rate */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSDACDAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_HSDACDAT_DACDAT 0 /* DAC Code */ +#define BITM_AFE_HSDACDAT_DACDAT 0x00000FFF /* DAC Code */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPREFBUFCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPREFBUFCON_BOOSTCURRENT 2 /* Set: Drive 2 Dac ;Unset Drive 1 Dac, and Save Power */ +#define BITP_AFE_LPREFBUFCON_LPBUF2P5DIS 1 /* Low Power Bandgap's Output Buffer */ +#define BITP_AFE_LPREFBUFCON_LPREFDIS 0 /* Set This Bit Will Power Down Low Power Bandgap */ +#define BITM_AFE_LPREFBUFCON_BOOSTCURRENT 0x00000004 /* Set: Drive 2 Dac ;Unset Drive 1 Dac, and Save Power */ +#define BITM_AFE_LPREFBUFCON_LPBUF2P5DIS 0x00000002 /* Low Power Bandgap's Output Buffer */ +#define BITM_AFE_LPREFBUFCON_LPREFDIS 0x00000001 /* Set This Bit Will Power Down Low Power Bandgap */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SYNCEXTDEVICE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SYNCEXTDEVICE_SYNC 0 /* As Output Data of GPIO */ +#define BITM_AFE_SYNCEXTDEVICE_SYNC 0x000000FF /* As Output Data of GPIO */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQCRC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQCRC_CRC 0 /* Sequencer Command CRC Value. */ +#define BITM_AFE_SEQCRC_CRC 0x000000FF /* Sequencer Command CRC Value. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQCNT_COUNT 0 /* Sequencer Command Count */ +#define BITM_AFE_SEQCNT_COUNT 0x0000FFFF /* Sequencer Command Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQTIMEOUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQTIMEOUT_TIMEOUT 0 /* Current Value of the Sequencer Timeout Counter. */ +#define BITM_AFE_SEQTIMEOUT_TIMEOUT 0x3FFFFFFF /* Current Value of the Sequencer Timeout Counter. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DATAFIFORD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DATAFIFORD_DATAFIFOOUT 0 /* Data FIFO Read */ +#define BITM_AFE_DATAFIFORD_DATAFIFOOUT 0x0000FFFF /* Data FIFO Read */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CMDFIFOWRITE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_CMDFIFOWRITE_CMDFIFOIN 0 /* Command FIFO Write. */ +#define BITM_AFE_CMDFIFOWRITE_CMDFIFOIN 0xFFFFFFFF /* Command FIFO Write. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCDAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCDAT_DATA 0 /* ADC Result */ +#define BITM_AFE_ADCDAT_DATA 0x0000FFFF /* ADC Result */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DFTREAL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DFTREAL_DATA 0 /* DFT Real */ +#define BITM_AFE_DFTREAL_DATA 0x0003FFFF /* DFT Real */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DFTIMAG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DFTIMAG_DATA 0 /* DFT Imaginary */ +#define BITM_AFE_DFTIMAG_DATA 0x0003FFFF /* DFT Imaginary */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SINC2DAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SINC2DAT_DATA 0 /* LPF Result */ +#define BITM_AFE_SINC2DAT_DATA 0x0000FFFF /* LPF Result */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TEMPSENSDAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_TEMPSENSDAT_DATA 0 /* Temp Sensor */ +#define BITM_AFE_TEMPSENSDAT_DATA 0x0000FFFF /* Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_AFEGENINTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ3 3 /* Custom IRQ 3. */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ2 2 /* Custom IRQ 2 */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ1 1 /* Custom IRQ 1. */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ0 0 /* Custom IRQ 0 */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ3 0x00000008 /* Custom IRQ 3. */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ2 0x00000004 /* Custom IRQ 2 */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ1 0x00000002 /* Custom IRQ 1. */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ0 0x00000001 /* Custom IRQ 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMIN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCMIN_MINVAL 0 /* ADC Minimum Value Threshold */ +#define BITM_AFE_ADCMIN_MINVAL 0x0000FFFF /* ADC Minimum Value Threshold */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMINSM Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCMINSM_MINCLRVAL 0 /* ADCMIN Hysteresis Value */ +#define BITM_AFE_ADCMINSM_MINCLRVAL 0x0000FFFF /* ADCMIN Hysteresis Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMAX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCMAX_MAXVAL 0 /* ADC Max Threshold */ +#define BITM_AFE_ADCMAX_MAXVAL 0x0000FFFF /* ADC Max Threshold */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMAXSMEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCMAXSMEN_MAXSWEN 0 /* ADCMAX Hysteresis Value */ +#define BITM_AFE_ADCMAXSMEN_MAXSWEN 0x0000FFFF /* ADCMAX Hysteresis Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCDELTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCDELTA_DELTAVAL 0 /* ADCDAT Code Differences Limit Option */ +#define BITM_AFE_ADCDELTA_DELTAVAL 0x0000FFFF /* ADCDAT Code Differences Limit Option */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HPOSCCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_HPOSCCON_CLK32MHZEN 2 /* 16M/32M Output Selector Signal. */ +#define BITM_AFE_HPOSCCON_CLK32MHZEN 0x00000004 /* 16M/32M Output Selector Signal. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DFTCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DFTCON_DFTINSEL 20 /* DFT Input Select */ +#define BITP_AFE_DFTCON_DFTNUM 4 /* ADC Samples Used */ +#define BITP_AFE_DFTCON_HANNINGEN 0 /* Hanning Window Enable */ +#define BITM_AFE_DFTCON_DFTINSEL 0x00300000 /* DFT Input Select */ +#define BITM_AFE_DFTCON_DFTNUM 0x000000F0 /* ADC Samples Used */ +#define BITM_AFE_DFTCON_HANNINGEN 0x00000001 /* Hanning Window Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIASW1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPTIASW1_TIABIASSEL 13 /* TIA SW13 Control. Active High */ +#define BITP_AFE_LPTIASW1_PABIASSEL 12 /* TIA SW12 Control. Active High */ +#define BITP_AFE_LPTIASW1_TIASWCON 0 /* TIA SW[11:0] Control */ +#define BITM_AFE_LPTIASW1_TIABIASSEL (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* TIA SW13 Control. Active High */ +#define BITM_AFE_LPTIASW1_PABIASSEL (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* TIA SW12 Control. Active High */ +#define BITM_AFE_LPTIASW1_TIASWCON (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t )) /* TIA SW[11:0] Control */ +#define ENUM_AFE_LPTIASW1_CAPA_LP (_ADI_MSK_3(0x00000014,0x00000014UL, uint32_t )) /* TIASWCON: CAPA test with LP TIA */ +#define ENUM_AFE_LPTIASW1_NORM (_ADI_MSK_3(0x0000002C,0x0000002CUL, uint32_t )) /* TIASWCON: Normal work mode */ +#define ENUM_AFE_LPTIASW1_DIO (_ADI_MSK_3(0x0000002D,0x0000002DUL, uint32_t )) /* TIASWCON: Normal work mode with back-back diode enabled. */ +#define ENUM_AFE_LPTIASW1_SHORTSW (_ADI_MSK_3(0x0000002E,0x0000002EUL, uint32_t )) /* TIASWCON: Work mode with short switch protection */ +#define ENUM_AFE_LPTIASW1_LOWNOISE (_ADI_MSK_3(0x0000006C,0x0000006CUL, uint32_t )) /* TIASWCON: Work mode, vzero-vbias=0. */ +#define ENUM_AFE_LPTIASW1_CAPA_RAMP_H (_ADI_MSK_3(0x00000094,0x00000094UL, uint32_t )) /* TIASWCON: CAPA test or Ramp test with HP TIA */ +#define ENUM_AFE_LPTIASW1_BUFDIS (_ADI_MSK_3(0x00000180,0x00000180UL, uint32_t )) /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW1_BUFEN (_ADI_MSK_3(0x000001A4,0x000001A4UL, uint32_t )) /* TIASWCON: Set PA/TIA as unity gain buffer. Connect amp's output to CE1 & RC11. */ +#define ENUM_AFE_LPTIASW1_TWOLEAD (_ADI_MSK_3(0x0000042C,0x0000042CUL, uint32_t )) /* TIASWCON: Two lead sensor, set PA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW1_BUFEN2 (_ADI_MSK_3(0x000004A4,0x000004A4UL, uint32_t )) /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW1_SESHORTRE (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* TIASWCON: Close SW11 - Short SE1 to RE1, */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIASW0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPTIASW0_RECAL 15 /* TIA SW15 Control. Active High */ +#define BITP_AFE_LPTIASW0_VZEROSHARE 14 /* TIA SW14 Control. Active High */ +#define BITP_AFE_LPTIASW0_TIABIASSEL 13 /* TIA SW13 Control. Active High */ +#define BITP_AFE_LPTIASW0_PABIASSEL 12 /* TIA SW12 Control. Active High */ +#define BITP_AFE_LPTIASW0_TIASWCON 0 /* TIA SW[11:0] Control */ +#define BITM_AFE_LPTIASW0_RECAL 0x00008000 /* TIA SW15 Control. Active High */ +#define BITM_AFE_LPTIASW0_VZEROSHARE 0x00004000 /* TIA SW14 Control. Active High */ +#define BITM_AFE_LPTIASW0_TIABIASSEL 0x00002000 /* TIA SW13 Control. Active High */ +#define BITM_AFE_LPTIASW0_PABIASSEL 0x00001000 /* TIA SW12 Control. Active High */ +#define BITM_AFE_LPTIASW0_TIASWCON 0x00000FFF /* TIA SW[11:0] Control */ +#define ENUM_AFE_LPTIASW0_11 0x00000014 /* TIASWCON: CAPA test with LP TIA */ +#define ENUM_AFE_LPTIASW0_NORM 0x0000002C /* TIASWCON: Normal work mode */ +#define ENUM_AFE_LPTIASW0_DIO 0x0000002D /* TIASWCON: Normal work mode with back-back diode enabled. */ +#define ENUM_AFE_LPTIASW0_SHORTSW 0x0000002E /* TIASWCON: Work mode with short switch protection */ +#define ENUM_AFE_LPTIASW0_LOWNOISE 0x0000006C /* TIASWCON: Work mode, vzero-vbias=0. */ +#define ENUM_AFE_LPTIASW0_1 0x00000094 /* TIASWCON: CAPA test or Ramp test with HP TIA */ +#define ENUM_AFE_LPTIASW0_BUFDIS 0x00000180 /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW0_BUFEN 0x000001A4 /* TIASWCON: Set PA/TIA as unity gain buffer. Connect amp's output to CE0 & RC01. */ +#define ENUM_AFE_LPTIASW0_TWOLEAD 0x0000042C /* TIASWCON: Two lead sensor, set PA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW0_BUFEN2 0x000004A4 /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW0_SESHORTRE 0x00000800 /* TIASWCON: Close SW11 - Short SE0 to RE0. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIACON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPTIACON1_CHOPEN 16 /* Chopping Enable */ +#define BITP_AFE_LPTIACON1_TIARF 13 /* Set LPF Resistor */ +#define BITP_AFE_LPTIACON1_TIARL 10 /* Set RLOAD */ +#define BITP_AFE_LPTIACON1_TIAGAIN 5 /* Set RTIA Gain Resistor */ +#define BITP_AFE_LPTIACON1_IBOOST 3 /* Current Boost Control */ +#define BITP_AFE_LPTIACON1_HALFPWR 2 /* Half Power Mode Select */ +#define BITP_AFE_LPTIACON1_PAPDEN 1 /* PA Power Down */ +#define BITP_AFE_LPTIACON1_TIAPDEN 0 /* TIA Power Down */ +#define BITM_AFE_LPTIACON1_CHOPEN (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t )) /* Chopping Enable */ +#define BITM_AFE_LPTIACON1_TIARF (_ADI_MSK_3(0x0000E000,0x0000E000UL, uint32_t )) /* Set LPF Resistor */ +#define BITM_AFE_LPTIACON1_TIARL (_ADI_MSK_3(0x00001C00,0x00001C00UL, uint32_t )) /* Set RLOAD */ +#define BITM_AFE_LPTIACON1_TIAGAIN (_ADI_MSK_3(0x000003E0,0x000003E0UL, uint32_t )) /* Set RTIA Gain Resistor */ +#define BITM_AFE_LPTIACON1_IBOOST (_ADI_MSK_3(0x00000018,0x00000018UL, uint32_t )) /* Current Boost Control */ +#define BITM_AFE_LPTIACON1_HALFPWR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Half Power Mode Select */ +#define BITM_AFE_LPTIACON1_PAPDEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* PA Power Down */ +#define BITM_AFE_LPTIACON1_TIAPDEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* TIA Power Down */ +#define ENUM_AFE_LPTIACON1_DISCONRF (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* TIARF: Disconnect TIA output from LPF pin */ +#define ENUM_AFE_LPTIACON1_BYPRF (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* TIARF: Bypass resistor */ +#define ENUM_AFE_LPTIACON1_RF20K (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* TIARF: 20k Ohm */ +#define ENUM_AFE_LPTIACON1_RF100K (_ADI_MSK_3(0x00006000,0x00006000UL, uint32_t )) /* TIARF: 100k Ohm */ +#define ENUM_AFE_LPTIACON1_RF200K (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* TIARF: 200k Ohm */ +#define ENUM_AFE_LPTIACON1_RF400K (_ADI_MSK_3(0x0000A000,0x0000A000UL, uint32_t )) /* TIARF: 400k Ohm */ +#define ENUM_AFE_LPTIACON1_RF600K (_ADI_MSK_3(0x0000C000,0x0000C000UL, uint32_t )) /* TIARF: 600k Ohm */ +#define ENUM_AFE_LPTIACON1_RF1MOHM (_ADI_MSK_3(0x0000E000,0x0000E000UL, uint32_t )) /* TIARF: 1Meg Ohm */ +#define ENUM_AFE_LPTIACON1_RL0 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* TIARL: 0 ohm */ +#define ENUM_AFE_LPTIACON1_RL10 (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* TIARL: 10 ohm */ +#define ENUM_AFE_LPTIACON1_RL30 (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* TIARL: 30 ohm */ +#define ENUM_AFE_LPTIACON1_RL50 (_ADI_MSK_3(0x00000C00,0x00000C00UL, uint32_t )) /* TIARL: 50 ohm */ +#define ENUM_AFE_LPTIACON1_RL100 (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* TIARL: 100 ohm */ +#define ENUM_AFE_LPTIACON1_RL1P6K (_ADI_MSK_3(0x00001400,0x00001400UL, uint32_t )) /* TIARL: 1.6kohm */ +#define ENUM_AFE_LPTIACON1_RL3P1K (_ADI_MSK_3(0x00001800,0x00001800UL, uint32_t )) /* TIARL: 3.1kohm */ +#define ENUM_AFE_LPTIACON1_RL3P5K (_ADI_MSK_3(0x00001C00,0x00001C00UL, uint32_t )) /* TIARL: 3.6kohm */ +#define ENUM_AFE_LPTIACON1_DISCONTIA (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* TIAGAIN: Disconnect TIA Gain resistor */ +#define ENUM_AFE_LPTIACON1_TIAGAIN200 (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* TIAGAIN: 200 Ohm */ +#define ENUM_AFE_LPTIACON1_TIAGAIN1K (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* TIAGAIN: 1k ohm */ +#define ENUM_AFE_LPTIACON1_TIAGAIN2K (_ADI_MSK_3(0x00000060,0x00000060UL, uint32_t )) /* TIAGAIN: 2k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN3K (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* TIAGAIN: 3k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN4K (_ADI_MSK_3(0x000000A0,0x000000A0UL, uint32_t )) /* TIAGAIN: 4k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN6K (_ADI_MSK_3(0x000000C0,0x000000C0UL, uint32_t )) /* TIAGAIN: 6k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN8K (_ADI_MSK_3(0x000000E0,0x000000E0UL, uint32_t )) /* TIAGAIN: 8k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN10K (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* TIAGAIN: 10k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN12K (_ADI_MSK_3(0x00000120,0x00000120UL, uint32_t )) /* TIAGAIN: 12k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN16K (_ADI_MSK_3(0x00000140,0x00000140UL, uint32_t )) /* TIAGAIN: 16k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN20K (_ADI_MSK_3(0x00000160,0x00000160UL, uint32_t )) /* TIAGAIN: 20k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN24K (_ADI_MSK_3(0x00000180,0x00000180UL, uint32_t )) /* TIAGAIN: 24k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN30K (_ADI_MSK_3(0x000001A0,0x000001A0UL, uint32_t )) /* TIAGAIN: 30k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN32K (_ADI_MSK_3(0x000001C0,0x000001C0UL, uint32_t )) /* TIAGAIN: 32k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN40K (_ADI_MSK_3(0x000001E0,0x000001E0UL, uint32_t )) /* TIAGAIN: 40k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN48K (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* TIAGAIN: 48k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN64K (_ADI_MSK_3(0x00000220,0x00000220UL, uint32_t )) /* TIAGAIN: 64k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN85K (_ADI_MSK_3(0x00000240,0x00000240UL, uint32_t )) /* TIAGAIN: 85k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN96K (_ADI_MSK_3(0x00000260,0x00000260UL, uint32_t )) /* TIAGAIN: 96k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN100K (_ADI_MSK_3(0x00000280,0x00000280UL, uint32_t )) /* TIAGAIN: 100k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN120K (_ADI_MSK_3(0x000002A0,0x000002A0UL, uint32_t )) /* TIAGAIN: 120k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN128K (_ADI_MSK_3(0x000002C0,0x000002C0UL, uint32_t )) /* TIAGAIN: 128k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN160K (_ADI_MSK_3(0x000002E0,0x000002E0UL, uint32_t )) /* TIAGAIN: 160k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN196K (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* TIAGAIN: 196k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN256K (_ADI_MSK_3(0x00000320,0x00000320UL, uint32_t )) /* TIAGAIN: 256k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN512K (_ADI_MSK_3(0x00000340,0x00000340UL, uint32_t )) /* TIAGAIN: 512k */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIACON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPTIACON0_CHOPEN 16 /* Chopping Enable */ +#define BITP_AFE_LPTIACON0_TIARF 13 /* Set LPF Resistor */ +#define BITP_AFE_LPTIACON0_TIARL 10 /* Set RLOAD */ +#define BITP_AFE_LPTIACON0_TIAGAIN 5 /* Set RTIA */ +#define BITP_AFE_LPTIACON0_IBOOST 3 /* Current Boost Control */ +#define BITP_AFE_LPTIACON0_HALFPWR 2 /* Half Power Mode Select */ +#define BITP_AFE_LPTIACON0_PAPDEN 1 /* PA Power Down */ +#define BITP_AFE_LPTIACON0_TIAPDEN 0 /* TIA Power Down */ +#define BITM_AFE_LPTIACON0_CHOPEN 0x00030000 /* Chopping Enable */ +#define BITM_AFE_LPTIACON0_TIARF 0x0000E000 /* Set LPF Resistor */ +#define BITM_AFE_LPTIACON0_TIARL 0x00001C00 /* Set RLOAD */ +#define BITM_AFE_LPTIACON0_TIAGAIN 0x000003E0 /* Set RTIA */ +#define BITM_AFE_LPTIACON0_IBOOST 0x00000018 /* Current Boost Control */ +#define BITM_AFE_LPTIACON0_HALFPWR 0x00000004 /* Half Power Mode Select */ +#define BITM_AFE_LPTIACON0_PAPDEN 0x00000002 /* PA Power Down */ +#define BITM_AFE_LPTIACON0_TIAPDEN 0x00000001 /* TIA Power Down */ +#define ENUM_AFE_LPTIACON0_DISCONRF 0x00000000 /* TIARF: Disconnect TIA output from LPF pin */ +#define ENUM_AFE_LPTIACON0_BYPRF 0x00002000 /* TIARF: Bypass resistor */ +#define ENUM_AFE_LPTIACON0_RF20K 0x00004000 /* TIARF: 20k Ohm */ +#define ENUM_AFE_LPTIACON0_RF100K 0x00006000 /* TIARF: 100k Ohm */ +#define ENUM_AFE_LPTIACON0_RF200K 0x00008000 /* TIARF: 200k Ohm */ +#define ENUM_AFE_LPTIACON0_RF400K 0x0000A000 /* TIARF: 400k Ohm */ +#define ENUM_AFE_LPTIACON0_RF600K 0x0000C000 /* TIARF: 600k Ohm */ +#define ENUM_AFE_LPTIACON0_RF1MOHM 0x0000E000 /* TIARF: 1Meg Ohm */ +#define ENUM_AFE_LPTIACON0_RL0 0x00000000 /* TIARL: 0 ohm */ +#define ENUM_AFE_LPTIACON0_RL10 0x00000400 /* TIARL: 10 ohm */ +#define ENUM_AFE_LPTIACON0_RL30 0x00000800 /* TIARL: 30 ohm */ +#define ENUM_AFE_LPTIACON0_RL50 0x00000C00 /* TIARL: 50 ohm */ +#define ENUM_AFE_LPTIACON0_RL100 0x00001000 /* TIARL: 100 ohm */ +#define ENUM_AFE_LPTIACON0_RL1P6K 0x00001400 /* TIARL: 1.6kohm */ +#define ENUM_AFE_LPTIACON0_RL3P1K 0x00001800 /* TIARL: 3.1kohm */ +#define ENUM_AFE_LPTIACON0_RL3P5K 0x00001C00 /* TIARL: 3.6kohm */ +#define ENUM_AFE_LPTIACON0_DISCONTIA 0x00000000 /* TIAGAIN: Disconnect TIA Gain resistor */ +#define ENUM_AFE_LPTIACON0_TIAGAIN200 0x00000020 /* TIAGAIN: 200 Ohm */ +#define ENUM_AFE_LPTIACON0_TIAGAIN1K 0x00000040 /* TIAGAIN: 1k ohm */ +#define ENUM_AFE_LPTIACON0_TIAGAIN2K 0x00000060 /* TIAGAIN: 2k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN3K 0x00000080 /* TIAGAIN: 3k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN4K 0x000000A0 /* TIAGAIN: 4k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN6K 0x000000C0 /* TIAGAIN: 6k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN8K 0x000000E0 /* TIAGAIN: 8k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN10K 0x00000100 /* TIAGAIN: 10k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN12K 0x00000120 /* TIAGAIN: 12k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN16K 0x00000140 /* TIAGAIN: 16k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN20K 0x00000160 /* TIAGAIN: 20k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN24K 0x00000180 /* TIAGAIN: 24k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN30K 0x000001A0 /* TIAGAIN: 30k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN32K 0x000001C0 /* TIAGAIN: 32k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN40K 0x000001E0 /* TIAGAIN: 40k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN48K 0x00000200 /* TIAGAIN: 48k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN64K 0x00000220 /* TIAGAIN: 64k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN85K 0x00000240 /* TIAGAIN: 85k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN96K 0x00000260 /* TIAGAIN: 96k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN100K 0x00000280 /* TIAGAIN: 100k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN120K 0x000002A0 /* TIAGAIN: 120k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN128K 0x000002C0 /* TIAGAIN: 128k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN160K 0x000002E0 /* TIAGAIN: 160k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN196K 0x00000300 /* TIAGAIN: 196k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN256K 0x00000320 /* TIAGAIN: 256k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN512K 0x00000340 /* TIAGAIN: 512k */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSRTIACON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_HSRTIACON_CTIACON 5 /* Configure Capacitor in Parallel with RTIA */ +#define BITP_AFE_HSRTIACON_TIASW6CON 4 /* SW6 Control */ +#define BITP_AFE_HSRTIACON_RTIACON 0 /* Configure General RTIA Value */ +#define BITM_AFE_HSRTIACON_CTIACON 0x00001FE0 /* Configure Capacitor in Parallel with RTIA */ +#define BITM_AFE_HSRTIACON_TIASW6CON 0x00000010 /* SW6 Control */ +#define BITM_AFE_HSRTIACON_RTIACON 0x0000000F /* Configure General RTIA Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DE1RESCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DE1RESCON_DE1RCON 0 /* DE1 RLOAD RTIA Setting */ +#define BITM_AFE_DE1RESCON_DE1RCON (_ADI_MSK_3(0x000000FF,0x000000FFUL, uint32_t )) /* DE1 RLOAD RTIA Setting */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DE0RESCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DE0RESCON_DE0RCON 0 /* DE0 RLOAD RTIA Setting */ +#define BITM_AFE_DE0RESCON_DE0RCON 0x000000FF /* DE0 RLOAD RTIA Setting */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSTIACON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_HSTIACON_VBIASSEL 0 /* Select HSTIA Positive Input */ +#define BITM_AFE_HSTIACON_VBIASSEL 0x00000003 /* Select HSTIA Positive Input */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACDCBUFCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DACDCBUFCON_CHANSEL 1 /* DAC DC Channel Selection */ +#define BITP_AFE_DACDCBUFCON_RESERVED_0 0 /* Reserved */ +#define BITM_AFE_DACDCBUFCON_CHANSEL (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* DAC DC Channel Selection */ +#define BITM_AFE_DACDCBUFCON_RESERVED_0 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Reserved */ +#define ENUM_AFE_DACDCBUFCON_CHAN0 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* CHANSEL: ULPDAC0 Sets DC level */ +#define ENUM_AFE_DACDCBUFCON_CHAN1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* CHANSEL: ULPDAC1 Sets DC level */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPMODEKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPMODEKEY_KEY 0 /* LP Key */ +#define BITM_AFE_LPMODEKEY_KEY 0x000FFFFF /* LP Key */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPMODECLKSEL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPMODECLKSEL_LFSYSCLKEN 0 /* Enable Switching System Clock to 32KHz by Sequencer */ +#define BITM_AFE_LPMODECLKSEL_LFSYSCLKEN 0x00000001 /* Enable Switching System Clock to 32KHz by Sequencer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPMODECON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPMODECON_ALDOEN 8 /* Set High to Power Down of Analog LDO */ +#define BITP_AFE_LPMODECON_V1P1HPADCEN 7 /* Set High to Enable 1.1V HP CM Buffer */ +#define BITP_AFE_LPMODECON_V1P8HPADCEN 6 /* Set High to Enable HP 1.8V Reference Buffer */ +#define BITP_AFE_LPMODECON_PTATEN 5 /* Set to High to Generate Ptat Current Bias */ +#define BITP_AFE_LPMODECON_ZTATEN 4 /* Set High to Generate Ztat Current Bias */ +#define BITP_AFE_LPMODECON_REPEATADCCNVEN_P 3 /* Set High to Enable Repeat ADC Conversion */ +#define BITP_AFE_LPMODECON_ADCCONVEN 2 /* Set High to Enable ADC Conversion */ +#define BITP_AFE_LPMODECON_HPREFDIS 1 /* Set High to Power Down HP Reference */ +#define BITP_AFE_LPMODECON_HFOSCPD 0 /* Set High to Power Down HP Power Oscillator */ +#define BITM_AFE_LPMODECON_ALDOEN 0x00000100 /* Set High to Power Down of Analog LDO */ +#define BITM_AFE_LPMODECON_V1P1HPADCEN 0x00000080 /* Set High to Enable 1.1V HP CM Buffer */ +#define BITM_AFE_LPMODECON_V1P8HPADCEN 0x00000040 /* Set High to Enable HP 1.8V Reference Buffer */ +#define BITM_AFE_LPMODECON_PTATEN 0x00000020 /* Set to High to Generate Ptat Current Bias */ +#define BITM_AFE_LPMODECON_ZTATEN 0x00000010 /* Set High to Generate Ztat Current Bias */ +#define BITM_AFE_LPMODECON_REPEATADCCNVEN_P 0x00000008 /* Set High to Enable Repeat ADC Conversion */ +#define BITM_AFE_LPMODECON_ADCCONVEN 0x00000004 /* Set High to Enable ADC Conversion */ +#define BITM_AFE_LPMODECON_HPREFDIS 0x00000002 /* Set High to Power Down HP Reference */ +#define BITM_AFE_LPMODECON_HFOSCPD 0x00000001 /* Set High to Power Down HP Power Oscillator */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQSLPLOCK Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQSLPLOCK_SEQ_SLP_PW 0 /* Password for SLPBYSEQ Register */ +#define BITM_AFE_SEQSLPLOCK_SEQ_SLP_PW 0x000FFFFF /* Password for SLPBYSEQ Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQTRGSLP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQTRGSLP_TRGSLP 0 /* Trigger Sleep by Sequencer */ +#define BITM_AFE_SEQTRGSLP_TRGSLP 0x00000001 /* Trigger Sleep by Sequencer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACDAT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPDACDAT0_DACIN6 12 /* 6BITVAL, 1LSB=34.375mV */ +#define BITP_AFE_LPDACDAT0_DACIN12 0 /* 12BITVAL, 1LSB=537uV */ +#define BITM_AFE_LPDACDAT0_DACIN6 0x0003F000 /* 6BITVAL, 1LSB=34.375mV */ +#define BITM_AFE_LPDACDAT0_DACIN12 0x00000FFF /* 12BITVAL, 1LSB=537uV */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACSW0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPDACSW0_LPMODEDIS 5 /* Switch Control */ +#define BITP_AFE_LPDACSW0_LPDACSW 0 /* LPDAC0 Switches Matrix */ +#define BITM_AFE_LPDACSW0_LPMODEDIS 0x00000020 /* Switch Control */ +#define BITM_AFE_LPDACSW0_LPDACSW 0x0000001F /* LPDAC0 Switches Matrix */ +#define ENUM_AFE_LPDACSW0_DACCONBIT5 0x00000000 /* LPMODEDIS: REG_AFE_LPDACDAT0 Switch controlled by REG_AFE_LPDACDAT0CON0 bit 5 */ +#define ENUM_AFE_LPDACSW0_OVRRIDE 0x00000020 /* LPMODEDIS: REG_AFE_LPDACDAT0 Switches override */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACCON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPDACCON0_WAVETYPE 6 /* LPDAC Data Source */ +#define BITP_AFE_LPDACCON0_DACMDE 5 /* LPDAC0 Switch Settings */ +#define BITP_AFE_LPDACCON0_VZEROMUX 4 /* VZERO MUX Select */ +#define BITP_AFE_LPDACCON0_VBIASMUX 3 /* VBIAS MUX Select */ +#define BITP_AFE_LPDACCON0_REFSEL 2 /* Reference Select Bit */ +#define BITP_AFE_LPDACCON0_PWDEN 1 /* LPDAC0 Power Down */ +#define BITP_AFE_LPDACCON0_RSTEN 0 /* Enable Writes to REG_AFE_LPDACDAT00 */ +#define BITM_AFE_LPDACCON0_WAVETYPE 0x00000040 /* LPDAC Data Source */ +#define BITM_AFE_LPDACCON0_DACMDE 0x00000020 /* LPDAC0 Switch Settings */ +#define BITM_AFE_LPDACCON0_VZEROMUX 0x00000010 /* VZERO MUX Select */ +#define BITM_AFE_LPDACCON0_VBIASMUX 0x00000008 /* VBIAS MUX Select */ +#define BITM_AFE_LPDACCON0_REFSEL 0x00000004 /* Reference Select Bit */ +#define BITM_AFE_LPDACCON0_PWDEN 0x00000002 /* LPDAC0 Power Down */ +#define BITM_AFE_LPDACCON0_RSTEN 0x00000001 /* Enable Writes to REG_AFE_LPDACDAT00 */ +#define ENUM_AFE_LPDACCON0_MMR 0x00000000 /* WAVETYPE: Direct from REG_AFE_LPDACDAT0DAT0 */ +#define ENUM_AFE_LPDACCON0_WAVEGEN 0x00000040 /* WAVETYPE: Waveform generator */ +#define ENUM_AFE_LPDACCON0_NORM 0x00000000 /* DACMDE: REG_AFE_LPDACDAT00 switches set for normal mode */ +#define ENUM_AFE_LPDACCON0_DIAG 0x00000020 /* DACMDE: REG_AFE_LPDACDAT00 switches set for Diagnostic mode */ +#define ENUM_AFE_LPDACCON0_BITS6 0x00000000 /* VZEROMUX: VZERO 6BIT */ +#define ENUM_AFE_LPDACCON0_BITS12 0x00000010 /* VZEROMUX: VZERO 12BIT */ +#define ENUM_AFE_LPDACCON0_12BIT 0x00000000 /* VBIASMUX: Output 12Bit */ +#define ENUM_AFE_LPDACCON0_EN 0x00000008 /* VBIASMUX: output 6Bit */ +#define ENUM_AFE_LPDACCON0_ULPREF 0x00000000 /* REFSEL: ULP2P5V Ref */ +#define ENUM_AFE_LPDACCON0_AVDD 0x00000004 /* REFSEL: AVDD Reference */ +#define ENUM_AFE_LPDACCON0_PWREN 0x00000000 /* PWDEN: REG_AFE_LPDACDAT00 Powered On */ +#define ENUM_AFE_LPDACCON0_PWRDIS 0x00000002 /* PWDEN: REG_AFE_LPDACDAT00 Powered Off */ +#define ENUM_AFE_LPDACCON0_WRITEDIS 0x00000000 /* RSTEN: Disable REG_AFE_LPDACDAT00 Writes */ +#define ENUM_AFE_LPDACCON0_WRITEEN 0x00000001 /* RSTEN: Enable REG_AFE_LPDACDAT00 Writes */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACDAT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPDACDAT1_DACIN6 12 /* 6BITVAL, 1LSB=34.375mV */ +#define BITP_AFE_LPDACDAT1_DACIN12 0 /* 12BITVAL, 1LSB=537uV */ +#define BITM_AFE_LPDACDAT1_DACIN6 (_ADI_MSK_3(0x0003F000,0x0003F000UL, uint32_t )) /* 6BITVAL, 1LSB=34.375mV */ +#define BITM_AFE_LPDACDAT1_DACIN12 (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t )) /* 12BITVAL, 1LSB=537uV */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACSW1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPDACSW1_LPMODEDIS 5 /* Switch Control */ +#define BITP_AFE_LPDACSW1_LPDACSW 0 /* ULPDAC0 Switches Matrix */ +#define BITM_AFE_LPDACSW1_LPMODEDIS (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Switch Control */ +#define BITM_AFE_LPDACSW1_LPDACSW (_ADI_MSK_3(0x0000001F,0x0000001FUL, uint32_t )) /* ULPDAC0 Switches Matrix */ +#define ENUM_AFE_LPDACSW1_DACCONBIT5 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LPMODEDIS: ULPDAC Switch controlled by ULPDACCON1 bit 5 */ +#define ENUM_AFE_LPDACSW1_OVRRIDE (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* LPMODEDIS: ULPDAC Switches override */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACCON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_LPDACCON1_WAVETYPE 6 /* DAC Input Source */ +#define BITP_AFE_LPDACCON1_DACMDE 5 /* LPDAC1 Switch Settings */ +#define BITP_AFE_LPDACCON1_VZEROMUX 4 /* VZEROOUT */ +#define BITP_AFE_LPDACCON1_VBIASMUX 3 /* BITSEL */ +#define BITP_AFE_LPDACCON1_REFSEL 2 /* REFSEL */ +#define BITP_AFE_LPDACCON1_PWDEN 1 /* ULPDAC0 Power */ +#define BITP_AFE_LPDACCON1_RSTEN 0 /* Enable Writes to ULPDAC1 */ +#define BITM_AFE_LPDACCON1_WAVETYPE (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* DAC Input Source */ +#define BITM_AFE_LPDACCON1_DACMDE (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* LPDAC1 Switch Settings */ +#define BITM_AFE_LPDACCON1_VZEROMUX (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* VZEROOUT */ +#define BITM_AFE_LPDACCON1_VBIASMUX (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* BITSEL */ +#define BITM_AFE_LPDACCON1_REFSEL (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* REFSEL */ +#define BITM_AFE_LPDACCON1_PWDEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* ULPDAC0 Power */ +#define BITM_AFE_LPDACCON1_RSTEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Writes to ULPDAC1 */ +#define ENUM_AFE_LPDACCON1_NORM (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* DACMDE: ULPDAC1 switches set for normal mode */ +#define ENUM_AFE_LPDACCON1_DIAG (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* DACMDE: ULPDAC1 switches set for Diagnostic mode */ +#define ENUM_AFE_LPDACCON1_BITS6 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* VZEROMUX: VZERO 6BIT */ +#define ENUM_AFE_LPDACCON1_BITS12 (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* VZEROMUX: VZERO 12BIT */ +#define ENUM_AFE_LPDACCON1_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* VBIASMUX: 12BIT Output */ +#define ENUM_AFE_LPDACCON1_EN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* VBIASMUX: 6BIT Output */ +#define ENUM_AFE_LPDACCON1_ULPREF (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) +#define ENUM_AFE_LPDACCON1_AVDD (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) +#define ENUM_AFE_LPDACCON1_PWREN (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* PWDEN: ULPDAC1 Powered On */ +#define ENUM_AFE_LPDACCON1_PWRDIS (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* PWDEN: ULPDAC1 Powered Off */ +#define ENUM_AFE_LPDACCON1_WRITEDIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* RSTEN: Disable ULPDAC1 Writes */ +#define ENUM_AFE_LPDACCON1_WRITEEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* RSTEN: Enable ULPDAC1 Writes */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DSWFULLCON_D8 7 /* Control of D8 Switch. */ +#define BITP_AFE_DSWFULLCON_D7 6 /* Control of D7 Switch. */ +#define BITP_AFE_DSWFULLCON_D6 5 /* Control of D6 Switch. */ +#define BITP_AFE_DSWFULLCON_D5 4 /* Control of D5 Switch. */ +#define BITP_AFE_DSWFULLCON_D4 3 /* Control of D4 Switch. */ +#define BITP_AFE_DSWFULLCON_D3 2 /* Control of D3 Switch. */ +#define BITP_AFE_DSWFULLCON_D2 1 /* Control of D2 Switch. */ +#define BITP_AFE_DSWFULLCON_DR0 0 /* Control of Dr0 Switch. */ +#define BITM_AFE_DSWFULLCON_D8 0x00000080 /* Control of D8 Switch. */ +#define BITM_AFE_DSWFULLCON_D7 0x00000040 /* Control of D7 Switch. */ +#define BITM_AFE_DSWFULLCON_D6 0x00000020 /* Control of D6 Switch. */ +#define BITM_AFE_DSWFULLCON_D5 0x00000010 /* Control of D5 Switch. */ +#define BITM_AFE_DSWFULLCON_D4 0x00000008 /* Control of D4 Switch. */ +#define BITM_AFE_DSWFULLCON_D3 0x00000004 /* Control of D3 Switch. */ +#define BITM_AFE_DSWFULLCON_D2 0x00000002 /* Control of D2 Switch. */ +#define BITM_AFE_DSWFULLCON_DR0 0x00000001 /* Control of Dr0 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_NSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_NSWFULLCON_NL2 11 /* Control of NL2 Switch. */ +#define BITP_AFE_NSWFULLCON_NL 10 /* Control of NL Switch. */ +#define BITP_AFE_NSWFULLCON_NR1 9 /* Control of Nr1 Switch. Set Will Close Nr1, Unset Open */ +#define BITP_AFE_NSWFULLCON_N9 8 /* Control of N9 Switch. Set Will Close N9, Unset Open */ +#define BITP_AFE_NSWFULLCON_N8 7 /* Control of N8 Switch. Set Will Close N8, Unset Open */ +#define BITP_AFE_NSWFULLCON_N7 6 /* Control of N7 Switch. Set Will Close N7, Unset Open */ +#define BITP_AFE_NSWFULLCON_N6 5 /* Control of N6 Switch. Set Will Close N6, Unset Open */ +#define BITP_AFE_NSWFULLCON_N5 4 /* Control of N5 Switch. Set Will Close N5, Unset Open */ +#define BITP_AFE_NSWFULLCON_N4 3 /* Control of N4 Switch. Set Will Close N4, Unset Open */ +#define BITP_AFE_NSWFULLCON_N3 2 /* Control of N3 Switch. Set Will Close N3, Unset Open */ +#define BITP_AFE_NSWFULLCON_N2 1 /* Control of N2 Switch. Set Will Close N2, Unset Open */ +#define BITP_AFE_NSWFULLCON_N1 0 /* Control of N1 Switch. Set Will Close N1, Unset Open */ +#define BITM_AFE_NSWFULLCON_NL2 0x00000800 /* Control of NL2 Switch. */ +#define BITM_AFE_NSWFULLCON_NL 0x00000400 /* Control of NL Switch. */ +#define BITM_AFE_NSWFULLCON_NR1 0x00000200 /* Control of Nr1 Switch. Set Will Close Nr1, Unset Open */ +#define BITM_AFE_NSWFULLCON_N9 0x00000100 /* Control of N9 Switch. Set Will Close N9, Unset Open */ +#define BITM_AFE_NSWFULLCON_N8 0x00000080 /* Control of N8 Switch. Set Will Close N8, Unset Open */ +#define BITM_AFE_NSWFULLCON_N7 0x00000040 /* Control of N7 Switch. Set Will Close N7, Unset Open */ +#define BITM_AFE_NSWFULLCON_N6 0x00000020 /* Control of N6 Switch. Set Will Close N6, Unset Open */ +#define BITM_AFE_NSWFULLCON_N5 0x00000010 /* Control of N5 Switch. Set Will Close N5, Unset Open */ +#define BITM_AFE_NSWFULLCON_N4 0x00000008 /* Control of N4 Switch. Set Will Close N4, Unset Open */ +#define BITM_AFE_NSWFULLCON_N3 0x00000004 /* Control of N3 Switch. Set Will Close N3, Unset Open */ +#define BITM_AFE_NSWFULLCON_N2 0x00000002 /* Control of N2 Switch. Set Will Close N2, Unset Open */ +#define BITM_AFE_NSWFULLCON_N1 0x00000001 /* Control of N1 Switch. Set Will Close N1, Unset Open */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_PSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_PSWFULLCON_PL2 14 /* PL2 Switch Control */ +#define BITP_AFE_PSWFULLCON_PL 13 /* PL Switch Control */ +#define BITP_AFE_PSWFULLCON_P12 11 /* Control of P12 Switch. Set Will Close P12, Unset Open */ +#define BITP_AFE_PSWFULLCON_P11 10 /* Control of P11 Switch. Set Will Close P11, Unset Open */ +#define BITP_AFE_PSWFULLCON_P10 9 /* P10 Switch Control */ +#define BITP_AFE_PSWFULLCON_P9 8 /* Control of P9 Switch. Set Will Close P9, Unset Open */ +#define BITP_AFE_PSWFULLCON_P8 7 /* Control of P8 Switch. Set Will Close P8, Unset Open */ +#define BITP_AFE_PSWFULLCON_P7 6 /* Control of P7 Switch. Set Will Close P7, Unset Open */ +#define BITP_AFE_PSWFULLCON_P6 5 /* Control of P6 Switch. Set Will Close P6, Unset Open */ +#define BITP_AFE_PSWFULLCON_P5 4 /* Control of P5 Switch. Set Will Close P5, Unset Open */ +#define BITP_AFE_PSWFULLCON_P4 3 /* Control of P4 Switch. Set Will Close P4, Unset Open */ +#define BITP_AFE_PSWFULLCON_P3 2 /* Control of P3 Switch. Set Will Close P3, Unset Open */ +#define BITP_AFE_PSWFULLCON_P2 1 /* Control of P2 Switch. Set Will Close P2, Unset Open */ +#define BITP_AFE_PSWFULLCON_PR0 0 /* PR0 Switch Control */ +#define BITM_AFE_PSWFULLCON_PL2 0x00004000 /* PL2 Switch Control */ +#define BITM_AFE_PSWFULLCON_PL 0x00002000 /* PL Switch Control */ +#define BITM_AFE_PSWFULLCON_P12 0x00000800 /* Control of P12 Switch. Set Will Close P12, Unset Open */ +#define BITM_AFE_PSWFULLCON_P11 0x00000400 /* Control of P11 Switch. Set Will Close P11, Unset Open */ +#define BITM_AFE_PSWFULLCON_P10 0x00000200 /* P10 Switch Control */ +#define BITM_AFE_PSWFULLCON_P9 0x00000100 /* Control of P9 Switch. Set Will Close P9, Unset Open */ +#define BITM_AFE_PSWFULLCON_P8 0x00000080 /* Control of P8 Switch. Set Will Close P8, Unset Open */ +#define BITM_AFE_PSWFULLCON_P7 0x00000040 /* Control of P7 Switch. Set Will Close P7, Unset Open */ +#define BITM_AFE_PSWFULLCON_P6 0x00000020 /* Control of P6 Switch. Set Will Close P6, Unset Open */ +#define BITM_AFE_PSWFULLCON_P5 0x00000010 /* Control of P5 Switch. Set Will Close P5, Unset Open */ +#define BITM_AFE_PSWFULLCON_P4 0x00000008 /* Control of P4 Switch. Set Will Close P4, Unset Open */ +#define BITM_AFE_PSWFULLCON_P3 0x00000004 /* Control of P3 Switch. Set Will Close P3, Unset Open */ +#define BITM_AFE_PSWFULLCON_P2 0x00000002 /* Control of P2 Switch. Set Will Close P2, Unset Open */ +#define BITM_AFE_PSWFULLCON_PR0 0x00000001 /* PR0 Switch Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_TSWFULLCON_TR1 11 /* Control of Tr1 Switch. Set Will Close Tr1, Unset Open */ +#define BITP_AFE_TSWFULLCON_T11 10 /* Control of T11 Switch. Set Will Close T11, Unset Open */ +#define BITP_AFE_TSWFULLCON_T10 9 /* Control of T10 Switch. Set Will Close T10, Unset Open */ +#define BITP_AFE_TSWFULLCON_T9 8 /* Control of T9 Switch. Set Will Close T9, Unset Open */ +#define BITP_AFE_TSWFULLCON_T7 6 /* Control of T7 Switch. Set Will Close T7, Unset Open */ +#define BITP_AFE_TSWFULLCON_T5 4 /* Control of T5 Switch. Set Will Close T5, Unset Open */ +#define BITP_AFE_TSWFULLCON_T4 3 /* Control of T4 Switch. Set Will Close T4, Unset Open */ +#define BITP_AFE_TSWFULLCON_T3 2 /* Control of T3 Switch. Set Will Close T3, Unset Open */ +#define BITP_AFE_TSWFULLCON_T2 1 /* Control of T2 Switch. Set Will Close T2, Unset Open */ +#define BITP_AFE_TSWFULLCON_T1 0 /* Control of T1 Switch. Set Will Close T1, Unset Open */ +#define BITM_AFE_TSWFULLCON_TR1 0x00000800 /* Control of Tr1 Switch. Set Will Close Tr1, Unset Open */ +#define BITM_AFE_TSWFULLCON_T11 0x00000400 /* Control of T11 Switch. Set Will Close T11, Unset Open */ +#define BITM_AFE_TSWFULLCON_T10 0x00000200 /* Control of T10 Switch. Set Will Close T10, Unset Open */ +#define BITM_AFE_TSWFULLCON_T9 0x00000100 /* Control of T9 Switch. Set Will Close T9, Unset Open */ +#define BITM_AFE_TSWFULLCON_T7 0x00000040 /* Control of T7 Switch. Set Will Close T7, Unset Open */ +#define BITM_AFE_TSWFULLCON_T5 0x00000010 /* Control of T5 Switch. Set Will Close T5, Unset Open */ +#define BITM_AFE_TSWFULLCON_T4 0x00000008 /* Control of T4 Switch. Set Will Close T4, Unset Open */ +#define BITM_AFE_TSWFULLCON_T3 0x00000004 /* Control of T3 Switch. Set Will Close T3, Unset Open */ +#define BITM_AFE_TSWFULLCON_T2 0x00000002 /* Control of T2 Switch. Set Will Close T2, Unset Open */ +#define BITM_AFE_TSWFULLCON_T1 0x00000001 /* Control of T1 Switch. Set Will Close T1, Unset Open */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TEMPSENS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_TEMPSENS_CHOPFRESEL 2 /* Chop Mode Frequency Setting */ +#define BITP_AFE_TEMPSENS_CHOPCON 1 /* Temp Sensor Chop Mode */ +#define BITP_AFE_TEMPSENS_ENABLE 0 /* Unused */ +#define BITM_AFE_TEMPSENS_CHOPFRESEL 0x0000000C /* Chop Mode Frequency Setting */ +#define BITM_AFE_TEMPSENS_CHOPCON 0x00000002 /* Temp Sensor Chop Mode */ +#define BITM_AFE_TEMPSENS_ENABLE 0x00000001 /* Unused */ +#define ENUM_AFE_TEMPSENS_DIS 0x00000000 /* CHOPCON: Disable chop */ +#define ENUM_AFE_TEMPSENS_EN 0x00000002 /* CHOPCON: Enable chop */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_BUFSENCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_BUFSENCON_V1P8THERMSTEN 8 /* Buffered Reference Output */ +#define BITP_AFE_BUFSENCON_V1P1LPADCCHGDIS 6 /* Controls Decoupling Cap Discharge Switch */ +#define BITP_AFE_BUFSENCON_V1P1LPADCEN 5 /* ADC 1.1V LP Buffer */ +#define BITP_AFE_BUFSENCON_V1P1HPADCEN 4 /* Enable 1.1V HP CM Buffer */ +#define BITP_AFE_BUFSENCON_V1P8HPADCCHGDIS 3 /* Controls Decoupling Cap Discharge Switch */ +#define BITP_AFE_BUFSENCON_V1P8LPADCEN 2 /* ADC 1.8V LP Reference Buffer */ +#define BITP_AFE_BUFSENCON_V1P8HPADCILIMITEN 1 /* HP ADC Input Current Limit */ +#define BITP_AFE_BUFSENCON_V1P8HPADCEN 0 /* HP 1.8V Reference Buffer */ +#define BITM_AFE_BUFSENCON_V1P8THERMSTEN 0x00000100 /* Buffered Reference Output */ +#define BITM_AFE_BUFSENCON_V1P1LPADCCHGDIS 0x00000040 /* Controls Decoupling Cap Discharge Switch */ +#define BITM_AFE_BUFSENCON_V1P1LPADCEN 0x00000020 /* ADC 1.1V LP Buffer */ +#define BITM_AFE_BUFSENCON_V1P1HPADCEN 0x00000010 /* Enable 1.1V HP CM Buffer */ +#define BITM_AFE_BUFSENCON_V1P8HPADCCHGDIS 0x00000008 /* Controls Decoupling Cap Discharge Switch */ +#define BITM_AFE_BUFSENCON_V1P8LPADCEN 0x00000004 /* ADC 1.8V LP Reference Buffer */ +#define BITM_AFE_BUFSENCON_V1P8HPADCILIMITEN 0x00000002 /* HP ADC Input Current Limit */ +#define BITM_AFE_BUFSENCON_V1P8HPADCEN 0x00000001 /* HP 1.8V Reference Buffer */ +#define ENUM_AFE_BUFSENCON_DIS 0x00000000 /* V1P8THERMSTEN: Disable 1.8V Buffered Reference output */ +#define ENUM_AFE_BUFSENCON_EN 0x00000100 /* V1P8THERMSTEN: Enable 1.8V Buffered Reference output */ +#define ENUM_AFE_BUFSENCON_ENCHRG 0x00000000 /* V1P1LPADCCHGDIS: Open switch */ +#define ENUM_AFE_BUFSENCON_DISCHRG 0x00000040 /* V1P1LPADCCHGDIS: Close Switch */ +#define ENUM_AFE_BUFSENCON_DISABLE 0x00000000 /* V1P1LPADCEN: Disable ADC 1.8V LP Reference Buffer */ +#define ENUM_AFE_BUFSENCON_ENABLE 0x00000020 /* V1P1LPADCEN: Enable ADC 1.8V LP Reference Buffer */ +#define ENUM_AFE_BUFSENCON_OFF 0x00000000 /* V1P1HPADCEN: Disable 1.1V HP Common Mode Buffer */ +#define ENUM_AFE_BUFSENCON_ON 0x00000010 /* V1P1HPADCEN: Enable 1.1V HP Common Mode Buffer */ +#define ENUM_AFE_BUFSENCON_OPEN 0x00000000 /* V1P8HPADCCHGDIS: Open switch */ +#define ENUM_AFE_BUFSENCON_CLOSED 0x00000008 /* V1P8HPADCCHGDIS: Close Switch */ +#define ENUM_AFE_BUFSENCON_LPADCREF_DIS 0x00000000 /* V1P8LPADCEN: Disable LP 1.8V Reference Buffer */ +#define ENUM_AFE_BUFSENCON_LPADCREF_EN 0x00000004 /* V1P8LPADCEN: Enable LP 1.8V Reference Buffer */ +#define ENUM_AFE_BUFSENCON_LIMIT_DIS 0x00000000 /* V1P8HPADCILIMITEN: Disable buffer Current Limit */ +#define ENUM_AFE_BUFSENCON_LIMIT_EN 0x00000002 /* V1P8HPADCILIMITEN: Enable buffer Current Limit */ +#define ENUM_AFE_BUFSENCON_HPBUF_DIS 0x00000000 /* V1P8HPADCEN: Disable 1.8V HP ADC Reference Buffer */ +#define ENUM_AFE_BUFSENCON_HPBUF_EN 0x00000001 /* V1P8HPADCEN: Enable 1.8V HP ADC Reference Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCCON_GNPGA 16 /* PGA Gain Setup */ +#define BITP_AFE_ADCCON_GNOFSELPGA 15 /* Internal Offset/Gain Cancellation */ +#define BITP_AFE_ADCCON_GNOFFSEL 13 /* Obsolete */ +#define BITP_AFE_ADCCON_MUXSELN 8 /* Select Negative Input */ +#define BITP_AFE_ADCCON_MUXSELP 0 /* Select Positive Input */ +#define BITM_AFE_ADCCON_GNPGA 0x00070000 /* PGA Gain Setup */ +#define BITM_AFE_ADCCON_GNOFSELPGA 0x00008000 /* Internal Offset/Gain Cancellation */ +#define BITM_AFE_ADCCON_GNOFFSEL 0x00006000 /* Obsolete */ +#define BITM_AFE_ADCCON_MUXSELN 0x00001F00 /* Select Negative Input */ +#define BITM_AFE_ADCCON_MUXSELP 0x0000003F /* Select Positive Input */ +#define ENUM_AFE_ADCCON_RESERVED 0x00000011 /* MUXSELP: Reserved */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DSWSTA_D8STA 7 /* Status of D8 Switch. */ +#define BITP_AFE_DSWSTA_D7STA 6 /* Status of D7 Switch. */ +#define BITP_AFE_DSWSTA_D6STA 5 /* Status of D6 Switch. */ +#define BITP_AFE_DSWSTA_D5STA 4 /* Status of D5 Switch. */ +#define BITP_AFE_DSWSTA_D4STA 3 /* Status of D4 Switch. */ +#define BITP_AFE_DSWSTA_D3STA 2 /* Status of D3 Switch. */ +#define BITP_AFE_DSWSTA_D2STA 1 /* Status of D2 Switch. */ +#define BITP_AFE_DSWSTA_D1STA 0 /* Status of Dr0 Switch. */ +#define BITM_AFE_DSWSTA_D8STA 0x00000080 /* Status of D8 Switch. */ +#define BITM_AFE_DSWSTA_D7STA 0x00000040 /* Status of D7 Switch. */ +#define BITM_AFE_DSWSTA_D6STA 0x00000020 /* Status of D6 Switch. */ +#define BITM_AFE_DSWSTA_D5STA 0x00000010 /* Status of D5 Switch. */ +#define BITM_AFE_DSWSTA_D4STA 0x00000008 /* Status of D4 Switch. */ +#define BITM_AFE_DSWSTA_D3STA 0x00000004 /* Status of D3 Switch. */ +#define BITM_AFE_DSWSTA_D2STA 0x00000002 /* Status of D2 Switch. */ +#define BITM_AFE_DSWSTA_D1STA 0x00000001 /* Status of Dr0 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_PSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_PSWSTA_PL2STA 14 /* PL Switch Control */ +#define BITP_AFE_PSWSTA_PLSTA 13 /* PL Switch Control */ +#define BITP_AFE_PSWSTA_P13STA 12 /* Status of P13 Switch. */ +#define BITP_AFE_PSWSTA_P12STA 11 /* Status of P12 Switch. */ +#define BITP_AFE_PSWSTA_P11STA 10 /* Status of P11 Switch. */ +#define BITP_AFE_PSWSTA_P10STA 9 /* Status of P10 Switch. */ +#define BITP_AFE_PSWSTA_P9STA 8 /* Status of P9 Switch. */ +#define BITP_AFE_PSWSTA_P8STA 7 /* Status of P8 Switch. */ +#define BITP_AFE_PSWSTA_P7STA 6 /* Status of P7 Switch. */ +#define BITP_AFE_PSWSTA_P6STA 5 /* Status of P6 Switch. */ +#define BITP_AFE_PSWSTA_P5STA 4 /* Status of P5 Switch. */ +#define BITP_AFE_PSWSTA_P4STA 3 /* Status of P4 Switch. */ +#define BITP_AFE_PSWSTA_P3STA 2 /* Status of P3 Switch. */ +#define BITP_AFE_PSWSTA_P2STA 1 /* Status of P2 Switch. */ +#define BITP_AFE_PSWSTA_PR0STA 0 /* PR0 Switch Control */ +#define BITM_AFE_PSWSTA_PL2STA 0x00004000 /* PL Switch Control */ +#define BITM_AFE_PSWSTA_PLSTA 0x00002000 /* PL Switch Control */ +#define BITM_AFE_PSWSTA_P13STA 0x00001000 /* Status of P13 Switch. */ +#define BITM_AFE_PSWSTA_P12STA 0x00000800 /* Status of P12 Switch. */ +#define BITM_AFE_PSWSTA_P11STA 0x00000400 /* Status of P11 Switch. */ +#define BITM_AFE_PSWSTA_P10STA 0x00000200 /* Status of P10 Switch. */ +#define BITM_AFE_PSWSTA_P9STA 0x00000100 /* Status of P9 Switch. */ +#define BITM_AFE_PSWSTA_P8STA 0x00000080 /* Status of P8 Switch. */ +#define BITM_AFE_PSWSTA_P7STA 0x00000040 /* Status of P7 Switch. */ +#define BITM_AFE_PSWSTA_P6STA 0x00000020 /* Status of P6 Switch. */ +#define BITM_AFE_PSWSTA_P5STA 0x00000010 /* Status of P5 Switch. */ +#define BITM_AFE_PSWSTA_P4STA 0x00000008 /* Status of P4 Switch. */ +#define BITM_AFE_PSWSTA_P3STA 0x00000004 /* Status of P3 Switch. */ +#define BITM_AFE_PSWSTA_P2STA 0x00000002 /* Status of P2 Switch. */ +#define BITM_AFE_PSWSTA_PR0STA 0x00000001 /* PR0 Switch Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_NSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_NSWSTA_NL2STA 11 /* Status of NL2 Switch. */ +#define BITP_AFE_NSWSTA_NLSTA 10 /* Status of NL Switch. */ +#define BITP_AFE_NSWSTA_NR1STA 9 /* Status of NR1 Switch. */ +#define BITP_AFE_NSWSTA_N9STA 8 /* Status of N9 Switch. */ +#define BITP_AFE_NSWSTA_N8STA 7 /* Status of N8 Switch. */ +#define BITP_AFE_NSWSTA_N7STA 6 /* Status of N7 Switch. */ +#define BITP_AFE_NSWSTA_N6STA 5 /* Status of N6 Switch. */ +#define BITP_AFE_NSWSTA_N5STA 4 /* Status of N5 Switch. */ +#define BITP_AFE_NSWSTA_N4STA 3 /* Status of N4 Switch. */ +#define BITP_AFE_NSWSTA_N3STA 2 /* Status of N3 Switch. */ +#define BITP_AFE_NSWSTA_N2STA 1 /* Status of N2 Switch. */ +#define BITP_AFE_NSWSTA_N1STA 0 /* Status of N1 Switch. */ +#define BITM_AFE_NSWSTA_NL2STA 0x00000800 /* Status of NL2 Switch. */ +#define BITM_AFE_NSWSTA_NLSTA 0x00000400 /* Status of NL Switch. */ +#define BITM_AFE_NSWSTA_NR1STA 0x00000200 /* Status of NR1 Switch. */ +#define BITM_AFE_NSWSTA_N9STA 0x00000100 /* Status of N9 Switch. */ +#define BITM_AFE_NSWSTA_N8STA 0x00000080 /* Status of N8 Switch. */ +#define BITM_AFE_NSWSTA_N7STA 0x00000040 /* Status of N7 Switch. */ +#define BITM_AFE_NSWSTA_N6STA 0x00000020 /* Status of N6 Switch. */ +#define BITM_AFE_NSWSTA_N5STA 0x00000010 /* Status of N5 Switch. */ +#define BITM_AFE_NSWSTA_N4STA 0x00000008 /* Status of N4 Switch. */ +#define BITM_AFE_NSWSTA_N3STA 0x00000004 /* Status of N3 Switch. */ +#define BITM_AFE_NSWSTA_N2STA 0x00000002 /* Status of N2 Switch. */ +#define BITM_AFE_NSWSTA_N1STA 0x00000001 /* Status of N1 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_TSWSTA_TR1STA 11 /* Status of TR1 Switch. */ +#define BITP_AFE_TSWSTA_T11STA 10 /* Status of T11 Switch. */ +#define BITP_AFE_TSWSTA_T10STA 9 /* Status of T10 Switch. */ +#define BITP_AFE_TSWSTA_T9STA 8 /* Status of T9 Switch. */ +#define BITP_AFE_TSWSTA_T8STA 7 /* Status of T8 Switch. */ +#define BITP_AFE_TSWSTA_T7STA 6 /* Status of T7 Switch. */ +#define BITP_AFE_TSWSTA_T6STA 5 /* Status of T6 Switch. */ +#define BITP_AFE_TSWSTA_T5STA 4 /* Status of T5 Switch. */ +#define BITP_AFE_TSWSTA_T4STA 3 /* Status of T4 Switch. */ +#define BITP_AFE_TSWSTA_T3STA 2 /* Status of T3 Switch. */ +#define BITP_AFE_TSWSTA_T2STA 1 /* Status of T2 Switch. */ +#define BITP_AFE_TSWSTA_T1STA 0 /* Status of T1 Switch. */ +#define BITM_AFE_TSWSTA_TR1STA 0x00000800 /* Status of TR1 Switch. */ +#define BITM_AFE_TSWSTA_T11STA 0x00000400 /* Status of T11 Switch. */ +#define BITM_AFE_TSWSTA_T10STA 0x00000200 /* Status of T10 Switch. */ +#define BITM_AFE_TSWSTA_T9STA 0x00000100 /* Status of T9 Switch. */ +#define BITM_AFE_TSWSTA_T8STA 0x00000080 /* Status of T8 Switch. */ +#define BITM_AFE_TSWSTA_T7STA 0x00000040 /* Status of T7 Switch. */ +#define BITM_AFE_TSWSTA_T6STA 0x00000020 /* Status of T6 Switch. */ +#define BITM_AFE_TSWSTA_T5STA 0x00000010 /* Status of T5 Switch. */ +#define BITM_AFE_TSWSTA_T4STA 0x00000008 /* Status of T4 Switch. */ +#define BITM_AFE_TSWSTA_T3STA 0x00000004 /* Status of T3 Switch. */ +#define BITM_AFE_TSWSTA_T2STA 0x00000002 /* Status of T2 Switch. */ +#define BITM_AFE_TSWSTA_T1STA 0x00000001 /* Status of T1 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_STATSVAR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_STATSVAR_VARIANCE 0 /* Statistical Variance Value */ +#define BITM_AFE_STATSVAR_VARIANCE 0x7FFFFFFF /* Statistical Variance Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_STATSCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_STATSCON_STDDEV 7 /* Standard Deviation Configuration */ +#define BITP_AFE_STATSCON_SAMPLENUM 4 /* Sample Size */ +#define BITP_AFE_STATSCON_RESRVED 1 /* Reserved */ +#define BITP_AFE_STATSCON_STATSEN 0 /* Statistics Enable */ +#define BITM_AFE_STATSCON_STDDEV 0x00000F80 /* Standard Deviation Configuration */ +#define BITM_AFE_STATSCON_SAMPLENUM 0x00000070 /* Sample Size */ +#define BITM_AFE_STATSCON_RESRVED 0x0000000E /* Reserved */ +#define BITM_AFE_STATSCON_STATSEN 0x00000001 /* Statistics Enable */ +#define ENUM_AFE_STATSCON_DIS 0x00000000 /* STATSEN: Disable Statistics */ +#define ENUM_AFE_STATSCON_EN 0x00000001 /* STATSEN: Enable Statistics */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_STATSMEAN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_STATSMEAN_MEAN 0 /* Mean Output */ +#define BITM_AFE_STATSMEAN_MEAN 0x0000FFFF /* Mean Output */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ0INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQ0INFO_LEN 16 /* SEQ0 Instruction Number */ +#define BITP_AFE_SEQ0INFO_ADDR 0 /* SEQ0 Start Address */ +#define BITM_AFE_SEQ0INFO_LEN 0x07FF0000 /* SEQ0 Instruction Number */ +#define BITM_AFE_SEQ0INFO_ADDR 0x000007FF /* SEQ0 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ2INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQ2INFO_LEN 16 /* SEQ2 Instruction Number */ +#define BITP_AFE_SEQ2INFO_ADDR 0 /* SEQ2 Start Address */ +#define BITM_AFE_SEQ2INFO_LEN 0x07FF0000 /* SEQ2 Instruction Number */ +#define BITM_AFE_SEQ2INFO_ADDR 0x000007FF /* SEQ2 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CMDFIFOWADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_CMDFIFOWADDR_WADDR 0 /* Write Address */ +#define BITM_AFE_CMDFIFOWADDR_WADDR 0x000007FF /* Write Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CMDDATACON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_CMDDATACON_DATAMEMMDE 9 /* Data FIFO Mode Select */ +#define BITP_AFE_CMDDATACON_DATA_MEM_SEL 6 /* Data FIFO Size Select */ +#define BITP_AFE_CMDDATACON_CMDMEMMDE 3 /* This is Command Fifo Mode Register */ +#define BITP_AFE_CMDDATACON_CMD_MEM_SEL 0 /* Command Memory Select */ +#define BITM_AFE_CMDDATACON_DATAMEMMDE 0x00000E00 /* Data FIFO Mode Select */ +#define BITM_AFE_CMDDATACON_DATA_MEM_SEL 0x000001C0 /* Data FIFO Size Select */ +#define BITM_AFE_CMDDATACON_CMDMEMMDE 0x00000038 /* This is Command Fifo Mode Register */ +#define BITM_AFE_CMDDATACON_CMD_MEM_SEL 0x00000007 /* Command Memory Select */ +#define ENUM_AFE_CMDDATACON_DFIFO 0x00000400 /* DATAMEMMDE: FIFO MODE */ +#define ENUM_AFE_CMDDATACON_DSTM 0x00000600 /* DATAMEMMDE: STREAM MODE */ +#define ENUM_AFE_CMDDATACON_DMEM32B 0x00000000 /* DATA_MEM_SEL: 32B_1 Local Memory */ +#define ENUM_AFE_CMDDATACON_DMEM2K 0x00000040 /* DATA_MEM_SEL: 2K_2 SRAM */ +#define ENUM_AFE_CMDDATACON_DMEM4K 0x00000080 /* DATA_MEM_SEL: 2K_2~1 SRAM */ +#define ENUM_AFE_CMDDATACON_DMEM6K 0x000000C0 /* DATA_MEM_SEL: 2K_2~0 SRAM */ +#define ENUM_AFE_CMDDATACON_CMEM 0x00000008 /* CMDMEMMDE: MEMORY MODE */ +#define ENUM_AFE_CMDDATACON_CFIFO 0x00000010 /* CMDMEMMDE: FIFO MODE */ +#define ENUM_AFE_CMDDATACON_CSTM 0x00000018 /* CMDMEMMDE: STREAM MODE */ +#define ENUM_AFE_CMDDATACON_CMEM32B 0x00000000 /* CMD_MEM_SEL: 32B_0 Local Memory */ +#define ENUM_AFE_CMDDATACON_CMEM2K 0x00000001 /* CMD_MEM_SEL: 2K_0 SRAM */ +#define ENUM_AFE_CMDDATACON_CMEM4K 0x00000002 /* CMD_MEM_SEL: 2K_0~1 SRAM */ +#define ENUM_AFE_CMDDATACON_CMEM6K 0x00000003 /* CMD_MEM_SEL: 2K_0~2 SRAM */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DATAFIFOTHRES Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DATAFIFOTHRES_HIGHTHRES 16 /* High Threshold */ +#define BITM_AFE_DATAFIFOTHRES_HIGHTHRES 0x07FF0000 /* High Threshold */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ3INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQ3INFO_LEN 16 /* SEQ3 Instruction Number */ +#define BITP_AFE_SEQ3INFO_ADDR 0 /* SEQ3 Start Address */ +#define BITM_AFE_SEQ3INFO_LEN 0x07FF0000 /* SEQ3 Instruction Number */ +#define BITM_AFE_SEQ3INFO_ADDR 0x000007FF /* SEQ3 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ1INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SEQ1INFO_LEN 16 /* SEQ1 Instruction Number */ +#define BITP_AFE_SEQ1INFO_ADDR 0 /* SEQ1 Start Address */ +#define BITM_AFE_SEQ1INFO_LEN 0x07FF0000 /* SEQ1 Instruction Number */ +#define BITM_AFE_SEQ1INFO_ADDR 0x000007FF /* SEQ1 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_REPEATADCCNV Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_REPEATADCCNV_NUM 4 /* Repeat Value */ +#define BITP_AFE_REPEATADCCNV_EN 0 /* Enable Repeat ADC Conversions */ +#define BITM_AFE_REPEATADCCNV_NUM 0x00000FF0 /* Repeat Value */ +#define BITM_AFE_REPEATADCCNV_EN 0x00000001 /* Enable Repeat ADC Conversions */ +#define ENUM_AFE_REPEATADCCNV_DIS 0x00000000 /* EN: Disable Repeat ADC Conversions */ +#define ENUM_AFE_REPEATADCCNV_EN 0x00000001 /* EN: Enable Repeat ADC Conversions */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_FIFOCNTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_FIFOCNTSTA_DATAFIFOCNTSTA 16 /* Current Number of Words in the Data FIFO */ +#define BITM_AFE_FIFOCNTSTA_DATAFIFOCNTSTA 0x07FF0000 /* Current Number of Words in the Data FIFO */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CALDATLOCK Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_CALDATLOCK_KEY 0 /* Password for Calibration Data Registers */ +#define BITM_AFE_CALDATLOCK_KEY 0xFFFFFFFF /* Password for Calibration Data Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETHSTIA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETHSTIA_VALUE 0 /* HSTIA Offset Calibration */ +#define BITM_AFE_ADCOFFSETHSTIA_VALUE 0x00007FFF /* HSTIA Offset Calibration */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINTEMPSENS0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGAINTEMPSENS0_VALUE 0 /* Gain Calibration Temp Sensor Channel */ +#define BITM_AFE_ADCGAINTEMPSENS0_VALUE 0x00007FFF /* Gain Calibration Temp Sensor Channel */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETTEMPSENS0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETTEMPSENS0_VALUE 0 /* Offset Calibration Temp Sensor */ +#define BITM_AFE_ADCOFFSETTEMPSENS0_VALUE 0x00007FFF /* Offset Calibration Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGAINGN1_VALUE 0 /* Gain Calibration PGA Gain 1x */ +#define BITM_AFE_ADCGAINGN1_VALUE 0x00007FFF /* Gain Calibration PGA Gain 1x */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETGN1_VALUE 0 /* Offset Calibration Gain1 */ +#define BITM_AFE_ADCOFFSETGN1_VALUE 0x00007FFF /* Offset Calibration Gain1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACGAIN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DACGAIN_VALUE 0 /* HS DAC Gain Correction Factor */ +#define BITM_AFE_DACGAIN_VALUE 0x00000FFF /* HS DAC Gain Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSETATTEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DACOFFSETATTEN_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSETATTEN_VALUE 0x00000FFF /* DAC Offset Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DACOFFSET_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSET_VALUE 0x00000FFF /* DAC Offset Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN1P5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGAINGN1P5_VALUE 0 /* Gain Calibration PGA Gain 1.5x */ +#define BITM_AFE_ADCGAINGN1P5_VALUE 0x00007FFF /* Gain Calibration PGA Gain 1.5x */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGAINGN2_VALUE 0 /* Gain Calibration PGA Gain 2x */ +#define BITM_AFE_ADCGAINGN2_VALUE 0x00007FFF /* Gain Calibration PGA Gain 2x */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGAINGN4_VALUE 0 /* Gain Calibration PGA Gain 4x */ +#define BITM_AFE_ADCGAINGN4_VALUE 0x00007FFF /* Gain Calibration PGA Gain 4x */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCPGAOFFSETCANCEL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCPGAOFFSETCANCEL_OFFSETCANCEL 0 /* Offset Cancellation */ +#define BITM_AFE_ADCPGAOFFSETCANCEL_OFFSETCANCEL 0x00007FFF /* Offset Cancellation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGNHSTIA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGNHSTIA_VALUE 0 /* Gain Error Calibration HS TIA Channel */ +#define BITM_AFE_ADCGNHSTIA_VALUE 0x00007FFF /* Gain Error Calibration HS TIA Channel */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETLPTIA0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETLPTIA0_VALUE 0 /* Offset Calibration for ULP-TIA0 */ +#define BITM_AFE_ADCOFFSETLPTIA0_VALUE 0x00007FFF /* Offset Calibration for ULP-TIA0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGNLPTIA0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGNLPTIA0_VALUE 0 /* Gain Error Calibration ULPTIA0 */ +#define BITM_AFE_ADCGNLPTIA0_VALUE 0x00007FFF /* Gain Error Calibration ULPTIA0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCPGAGN4OFCAL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCPGAGN4OFCAL_ADCGAINAUX 0 /* DC Calibration Gain=4 */ +#define BITM_AFE_ADCPGAGN4OFCAL_ADCGAINAUX 0x00007FFF /* DC Calibration Gain=4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN9 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGAINGN9_VALUE 0 /* Gain Calibration PGA Gain 9x */ +#define BITM_AFE_ADCGAINGN9_VALUE 0x00007FFF /* Gain Calibration PGA Gain 9x */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETEMPSENS1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETEMPSENS1_VALUE 0 /* Offset Calibration Temp Sensor */ +#define BITM_AFE_ADCOFFSETEMPSENS1_VALUE 0x00007FFF /* Offset Calibration Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINDIOTEMPSENS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGAINDIOTEMPSENS_VALUE 0 /* Gain Calibration for Diode Temp Sensor */ +#define BITM_AFE_ADCGAINDIOTEMPSENS_VALUE 0x00007FFF /* Gain Calibration for Diode Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSETATTENHP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DACOFFSETATTENHP_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSETATTENHP_VALUE 0x00000FFF /* DAC Offset Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSETHP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_DACOFFSETHP_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSETHP_VALUE 0x00000FFF /* DAC Offset Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETLPTIA1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETLPTIA1_VALUE 0 /* Offset Calibration for ULP-TIA1 */ +#define BITM_AFE_ADCOFFSETLPTIA1_VALUE (_ADI_MSK_3(0x00007FFF,0x00007FFFUL, uint32_t )) /* Offset Calibration for ULP-TIA1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGNLPTIA1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCGNLPTIA1_ULPTIA1GN 0 /* Gain Calibration ULP-TIA1 */ +#define BITM_AFE_ADCGNLPTIA1_ULPTIA1GN 0x00007FFF /* Gain Calibration ULP-TIA1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETGN2_VALUE 0 /* Offset Calibration Auxiliary Channel (PGA Gain =2) */ +#define BITM_AFE_ADCOFFSETGN2_VALUE 0x00007FFF /* Offset Calibration Auxiliary Channel (PGA Gain =2) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN1P5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETGN1P5_VALUE 0 /* Offset Calibration Gain1.5 */ +#define BITM_AFE_ADCOFFSETGN1P5_VALUE 0x00007FFF /* Offset Calibration Gain1.5 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN9 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETGN9_VALUE 0 /* Offset Calibration Gain9 */ +#define BITM_AFE_ADCOFFSETGN9_VALUE 0x00007FFF /* Offset Calibration Gain9 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCOFFSETGN4_VALUE 0 /* Offset Calibration Gain4 */ +#define BITM_AFE_ADCOFFSETGN4_VALUE 0x00007FFF /* Offset Calibration Gain4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_PMBW Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_PMBW_SYSBW 2 /* Configure System Bandwidth */ +#define BITP_AFE_PMBW_SYSHP 0 /* Set High Speed DAC and ADC in High Power Mode */ +#define BITM_AFE_PMBW_SYSBW 0x0000000C /* Configure System Bandwidth */ +#define BITM_AFE_PMBW_SYSHP 0x00000001 /* Set High Speed DAC and ADC in High Power Mode */ +#define ENUM_AFE_PMBW_BWNA 0x00000000 /* SYSBW: no action for system configuration */ +#define ENUM_AFE_PMBW_BW50 0x00000004 /* SYSBW: 50kHz -3dB bandwidth */ +#define ENUM_AFE_PMBW_BW100 0x00000008 /* SYSBW: 100kHz -3dB bandwidth */ +#define ENUM_AFE_PMBW_BW250 0x0000000C /* SYSBW: 250kHz -3dB bandwidth */ +#define ENUM_AFE_PMBW_LP 0x00000000 /* SYSHP: LP mode */ +#define ENUM_AFE_PMBW_HP 0x00000001 /* SYSHP: HP mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SWMUX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_SWMUX_CMMUX 3 /* CM Resistor Select for Ain2, Ain3 */ +#define BITM_AFE_SWMUX_CMMUX 0x00000008 /* CM Resistor Select for Ain2, Ain3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_AFE_TEMPSEN_DIO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_AFE_TEMPSEN_DIO_TSDIO_PD 17 /* Power Down Control */ +#define BITP_AFE_AFE_TEMPSEN_DIO_TSDIO_EN 16 /* Test Signal Enable */ +#define BITP_AFE_AFE_TEMPSEN_DIO_TSDIO_CON 0 /* Bias Current Selection */ +#define BITM_AFE_AFE_TEMPSEN_DIO_TSDIO_PD 0x00020000 /* Power Down Control */ +#define BITM_AFE_AFE_TEMPSEN_DIO_TSDIO_EN 0x00010000 /* Test Signal Enable */ +#define BITM_AFE_AFE_TEMPSEN_DIO_TSDIO_CON 0x0000FFFF /* Bias Current Selection */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCBUFCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_AFE_ADCBUFCON_AMPDIS 4 /* Disable OpAmp. */ +#define BITP_AFE_ADCBUFCON_CHOPDIS 0 /* Disable Chop */ +#define BITM_AFE_ADCBUFCON_AMPDIS 0x000001F0 /* Disable OpAmp. */ +#define BITM_AFE_ADCBUFCON_CHOPDIS 0x0000000F /* Disable Chop */ + + +/* ============================================================================================================================ + Interrupt Controller Register Map + ============================================================================================================================ */ + +/* ============================================================================================================================ + INTC + ============================================================================================================================ */ +#define REG_INTC_INTCPOL_RESET 0x00000000 /* Reset Value for INTCPOL */ +#define REG_INTC_INTCPOL 0x00003000 /* INTC Interrupt Polarity Register */ +#define REG_INTC_INTCCLR_RESET 0x00000000 /* Reset Value for INTCCLR */ +#define REG_INTC_INTCCLR 0x00003004 /* INTC Interrupt Clear Register */ +#define REG_INTC_INTCSEL0_RESET 0x00002000 /* Reset Value for INTCSEL0 */ +#define REG_INTC_INTCSEL0 0x00003008 /* INTC INT0 Select Register */ +#define REG_INTC_INTCSEL1_RESET 0x00000000 /* Reset Value for INTCSEL1 */ +#define REG_INTC_INTCSEL1 0x0000300C /* INTC INT1 Select Register */ +#define REG_INTC_INTCFLAG0_RESET 0x00000000 /* Reset Value for INTCFLAG0 */ +#define REG_INTC_INTCFLAG0 0x00003010 /* INTC INT0 FLAG Register */ +#define REG_INTC_INTCFLAG1_RESET 0x00000000 /* Reset Value for INTCFLAG1 */ +#define REG_INTC_INTCFLAG1 0x00003014 /* INTC INT1 FLAG Register */ + +/* ============================================================================================================================ + INTC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCPOL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_INTC_INTCPOL_INTPOL 0 +#define BITM_INTC_INTCPOL_INTPOL 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCCLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_INTC_INTCCLR_INTCLR31 31 +#define BITP_INTC_INTCCLR_INTCLR30 30 +#define BITP_INTC_INTCCLR_INTCLR29 29 +#define BITP_INTC_INTCCLR_INTCLR28 28 +#define BITP_INTC_INTCCLR_INTCLR27 27 +#define BITP_INTC_INTCCLR_INTCLR26 26 +#define BITP_INTC_INTCCLR_INTCLR25 25 +#define BITP_INTC_INTCCLR_INTCLR24 24 +#define BITP_INTC_INTCCLR_INTCLR23 23 +#define BITP_INTC_INTCCLR_INTCLR22 22 +#define BITP_INTC_INTCCLR_INTCLR21 21 +#define BITP_INTC_INTCCLR_INTCLR20 20 +#define BITP_INTC_INTCCLR_INTCLR19 19 +#define BITP_INTC_INTCCLR_INTCLR18 18 +#define BITP_INTC_INTCCLR_INTCLR17 17 +#define BITP_INTC_INTCCLR_INTCLR16 16 +#define BITP_INTC_INTCCLR_INTCLR15 15 +#define BITP_INTC_INTCCLR_INTCLR14 14 +#define BITP_INTC_INTCCLR_INTCLR13 13 +#define BITP_INTC_INTCCLR_INTCLR12 12 /* Custom IRQ 3. Write 1 to clear. */ +#define BITP_INTC_INTCCLR_INTCLR11 11 /* Custom IRQ 2. Write 1 to clear. */ +#define BITP_INTC_INTCCLR_INTCLR10 10 /* Custom IRQ 1. Write 1 to clear. */ +#define BITP_INTC_INTCCLR_INTCLR9 9 /* Custom IRQ 0. Write 1 to clear */ +#define BITP_INTC_INTCCLR_INTCLR8 8 +#define BITP_INTC_INTCCLR_INTCLR7 7 +#define BITP_INTC_INTCCLR_INTCLR6 6 +#define BITP_INTC_INTCCLR_INTCLR5 5 +#define BITP_INTC_INTCCLR_INTCLR4 4 +#define BITP_INTC_INTCCLR_INTCLR3 3 +#define BITP_INTC_INTCCLR_INTCLR2 2 +#define BITP_INTC_INTCCLR_INTCLR1 1 +#define BITP_INTC_INTCCLR_INTCLR0 0 +#define BITM_INTC_INTCCLR_INTCLR31 0x80000000 +#define BITM_INTC_INTCCLR_INTCLR30 0x40000000 +#define BITM_INTC_INTCCLR_INTCLR29 0x20000000 +#define BITM_INTC_INTCCLR_INTCLR28 0x10000000 +#define BITM_INTC_INTCCLR_INTCLR27 0x08000000 +#define BITM_INTC_INTCCLR_INTCLR26 0x04000000 +#define BITM_INTC_INTCCLR_INTCLR25 0x02000000 +#define BITM_INTC_INTCCLR_INTCLR24 0x01000000 +#define BITM_INTC_INTCCLR_INTCLR23 0x00800000 +#define BITM_INTC_INTCCLR_INTCLR22 0x00400000 +#define BITM_INTC_INTCCLR_INTCLR21 0x00200000 +#define BITM_INTC_INTCCLR_INTCLR20 0x00100000 +#define BITM_INTC_INTCCLR_INTCLR19 0x00080000 +#define BITM_INTC_INTCCLR_INTCLR18 0x00040000 +#define BITM_INTC_INTCCLR_INTCLR17 0x00020000 +#define BITM_INTC_INTCCLR_INTCLR16 0x00010000 +#define BITM_INTC_INTCCLR_INTCLR15 0x00008000 +#define BITM_INTC_INTCCLR_INTCLR14 0x00004000 +#define BITM_INTC_INTCCLR_INTCLR13 0x00002000 +#define BITM_INTC_INTCCLR_INTCLR12 0x00001000 /* Custom IRQ 3. Write 1 to clear. */ +#define BITM_INTC_INTCCLR_INTCLR11 0x00000800 /* Custom IRQ 2. Write 1 to clear. */ +#define BITM_INTC_INTCCLR_INTCLR10 0x00000400 /* Custom IRQ 1. Write 1 to clear. */ +#define BITM_INTC_INTCCLR_INTCLR9 0x00000200 /* Custom IRQ 0. Write 1 to clear */ +#define BITM_INTC_INTCCLR_INTCLR8 0x00000100 +#define BITM_INTC_INTCCLR_INTCLR7 0x00000080 +#define BITM_INTC_INTCCLR_INTCLR6 0x00000040 +#define BITM_INTC_INTCCLR_INTCLR5 0x00000020 +#define BITM_INTC_INTCCLR_INTCLR4 0x00000010 +#define BITM_INTC_INTCCLR_INTCLR3 0x00000008 +#define BITM_INTC_INTCCLR_INTCLR2 0x00000004 +#define BITM_INTC_INTCCLR_INTCLR1 0x00000002 +#define BITM_INTC_INTCCLR_INTCLR0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCSEL0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_INTC_INTCSEL0_INTSEL31 31 +#define BITP_INTC_INTCSEL0_INTSEL30 30 +#define BITP_INTC_INTCSEL0_INTSEL29 29 +#define BITP_INTC_INTCSEL0_INTSEL28 28 +#define BITP_INTC_INTCSEL0_INTSEL27 27 +#define BITP_INTC_INTCSEL0_INTSEL26 26 +#define BITP_INTC_INTCSEL0_INTSEL25 25 +#define BITP_INTC_INTCSEL0_INTSEL24 24 +#define BITP_INTC_INTCSEL0_INTSEL23 23 +#define BITP_INTC_INTCSEL0_INTSEL22 22 +#define BITP_INTC_INTCSEL0_INTSEL21 21 +#define BITP_INTC_INTCSEL0_INTSEL20 20 +#define BITP_INTC_INTCSEL0_INTSEL19 19 +#define BITP_INTC_INTCSEL0_INTSEL18 18 +#define BITP_INTC_INTCSEL0_INTSEL17 17 +#define BITP_INTC_INTCSEL0_INTSEL16 16 +#define BITP_INTC_INTCSEL0_INTSEL15 15 +#define BITP_INTC_INTCSEL0_INTSEL14 14 +#define BITP_INTC_INTCSEL0_INTSEL13 13 +#define BITP_INTC_INTCSEL0_INTSEL12 12 /* Custom IRQ 3 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL11 11 /* Custom IRQ 2 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL10 10 /* Custom IRQ 1 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL9 9 /* Custom IRQ 0 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL8 8 +#define BITP_INTC_INTCSEL0_INTSEL7 7 +#define BITP_INTC_INTCSEL0_INTSEL6 6 +#define BITP_INTC_INTCSEL0_INTSEL5 5 +#define BITP_INTC_INTCSEL0_INTSEL4 4 +#define BITP_INTC_INTCSEL0_INTSEL3 3 +#define BITP_INTC_INTCSEL0_INTSEL2 2 +#define BITP_INTC_INTCSEL0_INTSEL1 1 +#define BITP_INTC_INTCSEL0_INTSEL0 0 +#define BITM_INTC_INTCSEL0_INTSEL31 0x80000000 +#define BITM_INTC_INTCSEL0_INTSEL30 0x40000000 +#define BITM_INTC_INTCSEL0_INTSEL29 0x20000000 +#define BITM_INTC_INTCSEL0_INTSEL28 0x10000000 +#define BITM_INTC_INTCSEL0_INTSEL27 0x08000000 +#define BITM_INTC_INTCSEL0_INTSEL26 0x04000000 +#define BITM_INTC_INTCSEL0_INTSEL25 0x02000000 +#define BITM_INTC_INTCSEL0_INTSEL24 0x01000000 +#define BITM_INTC_INTCSEL0_INTSEL23 0x00800000 +#define BITM_INTC_INTCSEL0_INTSEL22 0x00400000 +#define BITM_INTC_INTCSEL0_INTSEL21 0x00200000 +#define BITM_INTC_INTCSEL0_INTSEL20 0x00100000 +#define BITM_INTC_INTCSEL0_INTSEL19 0x00080000 +#define BITM_INTC_INTCSEL0_INTSEL18 0x00040000 +#define BITM_INTC_INTCSEL0_INTSEL17 0x00020000 +#define BITM_INTC_INTCSEL0_INTSEL16 0x00010000 +#define BITM_INTC_INTCSEL0_INTSEL15 0x00008000 +#define BITM_INTC_INTCSEL0_INTSEL14 0x00004000 +#define BITM_INTC_INTCSEL0_INTSEL13 0x00002000 +#define BITM_INTC_INTCSEL0_INTSEL12 0x00001000 /* Custom IRQ 3 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL11 0x00000800 /* Custom IRQ 2 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL10 0x00000400 /* Custom IRQ 1 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL9 0x00000200 /* Custom IRQ 0 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL8 0x00000100 +#define BITM_INTC_INTCSEL0_INTSEL7 0x00000080 +#define BITM_INTC_INTCSEL0_INTSEL6 0x00000040 +#define BITM_INTC_INTCSEL0_INTSEL5 0x00000020 +#define BITM_INTC_INTCSEL0_INTSEL4 0x00000010 +#define BITM_INTC_INTCSEL0_INTSEL3 0x00000008 +#define BITM_INTC_INTCSEL0_INTSEL2 0x00000004 +#define BITM_INTC_INTCSEL0_INTSEL1 0x00000002 +#define BITM_INTC_INTCSEL0_INTSEL0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCSEL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_INTC_INTCSEL1_INTSEL31 31 +#define BITP_INTC_INTCSEL1_INTSEL30 30 +#define BITP_INTC_INTCSEL1_INTSEL29 29 +#define BITP_INTC_INTCSEL1_INTSEL28 28 +#define BITP_INTC_INTCSEL1_INTSEL27 27 +#define BITP_INTC_INTCSEL1_INTSEL26 26 +#define BITP_INTC_INTCSEL1_INTSEL25 25 +#define BITP_INTC_INTCSEL1_INTSEL24 24 +#define BITP_INTC_INTCSEL1_INTSEL23 23 +#define BITP_INTC_INTCSEL1_INTSEL22 22 +#define BITP_INTC_INTCSEL1_INTSEL21 21 +#define BITP_INTC_INTCSEL1_INTSEL20 20 +#define BITP_INTC_INTCSEL1_INTSEL19 19 +#define BITP_INTC_INTCSEL1_INTSEL18 18 +#define BITP_INTC_INTCSEL1_INTSEL17 17 +#define BITP_INTC_INTCSEL1_INTSEL16 16 +#define BITP_INTC_INTCSEL1_INTSEL15 15 +#define BITP_INTC_INTCSEL1_INTSEL14 14 +#define BITP_INTC_INTCSEL1_INTSEL13 13 +#define BITP_INTC_INTCSEL1_INTSEL12 12 /* Custom IRQ 3 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL11 11 /* Custom IRQ 2 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL10 10 /* Custom IRQ 1 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL9 9 /* Custom IRQ 0 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL8 8 +#define BITP_INTC_INTCSEL1_INTSEL7 7 +#define BITP_INTC_INTCSEL1_INTSEL6 6 +#define BITP_INTC_INTCSEL1_INTSEL5 5 +#define BITP_INTC_INTCSEL1_INTSEL4 4 +#define BITP_INTC_INTCSEL1_INTSEL3 3 +#define BITP_INTC_INTCSEL1_INTSEL2 2 +#define BITP_INTC_INTCSEL1_INTSEL1 1 +#define BITP_INTC_INTCSEL1_INTSEL0 0 +#define BITM_INTC_INTCSEL1_INTSEL31 0x80000000 +#define BITM_INTC_INTCSEL1_INTSEL30 0x40000000 +#define BITM_INTC_INTCSEL1_INTSEL29 0x20000000 +#define BITM_INTC_INTCSEL1_INTSEL28 0x10000000 +#define BITM_INTC_INTCSEL1_INTSEL27 0x08000000 +#define BITM_INTC_INTCSEL1_INTSEL26 0x04000000 +#define BITM_INTC_INTCSEL1_INTSEL25 0x02000000 +#define BITM_INTC_INTCSEL1_INTSEL24 0x01000000 +#define BITM_INTC_INTCSEL1_INTSEL23 0x00800000 +#define BITM_INTC_INTCSEL1_INTSEL22 0x00400000 +#define BITM_INTC_INTCSEL1_INTSEL21 0x00200000 +#define BITM_INTC_INTCSEL1_INTSEL20 0x00100000 +#define BITM_INTC_INTCSEL1_INTSEL19 0x00080000 +#define BITM_INTC_INTCSEL1_INTSEL18 0x00040000 +#define BITM_INTC_INTCSEL1_INTSEL17 0x00020000 +#define BITM_INTC_INTCSEL1_INTSEL16 0x00010000 +#define BITM_INTC_INTCSEL1_INTSEL15 0x00008000 +#define BITM_INTC_INTCSEL1_INTSEL14 0x00004000 +#define BITM_INTC_INTCSEL1_INTSEL13 0x00002000 +#define BITM_INTC_INTCSEL1_INTSEL12 0x00001000 /* Custom IRQ 3 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL11 0x00000800 /* Custom IRQ 2 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL10 0x00000400 /* Custom IRQ 1 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL9 0x00000200 /* Custom IRQ 0 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL8 0x00000100 +#define BITM_INTC_INTCSEL1_INTSEL7 0x00000080 +#define BITM_INTC_INTCSEL1_INTSEL6 0x00000040 +#define BITM_INTC_INTCSEL1_INTSEL5 0x00000020 +#define BITM_INTC_INTCSEL1_INTSEL4 0x00000010 +#define BITM_INTC_INTCSEL1_INTSEL3 0x00000008 +#define BITM_INTC_INTCSEL1_INTSEL2 0x00000004 +#define BITM_INTC_INTCSEL1_INTSEL1 0x00000002 +#define BITM_INTC_INTCSEL1_INTSEL0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCFLAG0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_INTC_INTCFLAG0_FLAG31 31 +#define BITP_INTC_INTCFLAG0_FLAG30 30 +#define BITP_INTC_INTCFLAG0_FLAG29 29 +#define BITP_INTC_INTCFLAG0_FLAG28 28 +#define BITP_INTC_INTCFLAG0_FLAG27 27 +#define BITP_INTC_INTCFLAG0_FLAG26 26 +#define BITP_INTC_INTCFLAG0_FLAG25 25 +#define BITP_INTC_INTCFLAG0_FLAG24 24 +#define BITP_INTC_INTCFLAG0_FLAG23 23 +#define BITP_INTC_INTCFLAG0_FLAG22 22 +#define BITP_INTC_INTCFLAG0_FLAG21 21 +#define BITP_INTC_INTCFLAG0_FLAG20 20 +#define BITP_INTC_INTCFLAG0_FLAG19 19 +#define BITP_INTC_INTCFLAG0_FLAG18 18 +#define BITP_INTC_INTCFLAG0_FLAG17 17 +#define BITP_INTC_INTCFLAG0_FLAG16 16 +#define BITP_INTC_INTCFLAG0_FLAG15 15 +#define BITP_INTC_INTCFLAG0_FLAG14 14 +#define BITP_INTC_INTCFLAG0_FLAG13 13 +#define BITP_INTC_INTCFLAG0_FLAG12 12 /* Custom IRQ 3 Status */ +#define BITP_INTC_INTCFLAG0_FLAG11 11 /* Custom IRQ 2 Status */ +#define BITP_INTC_INTCFLAG0_FLAG10 10 /* Custom IRQ 1 Status */ +#define BITP_INTC_INTCFLAG0_FLAG9 9 /* Custom IRQ 0 Status */ +#define BITP_INTC_INTCFLAG0_FLAG8 8 /* Variance IRQ status. */ +#define BITP_INTC_INTCFLAG0_FLAG7 7 +#define BITP_INTC_INTCFLAG0_FLAG6 6 +#define BITP_INTC_INTCFLAG0_FLAG5 5 +#define BITP_INTC_INTCFLAG0_FLAG4 4 +#define BITP_INTC_INTCFLAG0_FLAG3 3 +#define BITP_INTC_INTCFLAG0_FLAG2 2 +#define BITP_INTC_INTCFLAG0_FLAG1 1 +#define BITP_INTC_INTCFLAG0_FLAG0 0 +#define BITM_INTC_INTCFLAG0_FLAG31 0x80000000 +#define BITM_INTC_INTCFLAG0_FLAG30 0x40000000 +#define BITM_INTC_INTCFLAG0_FLAG29 0x20000000 +#define BITM_INTC_INTCFLAG0_FLAG28 0x10000000 +#define BITM_INTC_INTCFLAG0_FLAG27 0x08000000 +#define BITM_INTC_INTCFLAG0_FLAG26 0x04000000 +#define BITM_INTC_INTCFLAG0_FLAG25 0x02000000 +#define BITM_INTC_INTCFLAG0_FLAG24 0x01000000 +#define BITM_INTC_INTCFLAG0_FLAG23 0x00800000 +#define BITM_INTC_INTCFLAG0_FLAG22 0x00400000 +#define BITM_INTC_INTCFLAG0_FLAG21 0x00200000 +#define BITM_INTC_INTCFLAG0_FLAG20 0x00100000 +#define BITM_INTC_INTCFLAG0_FLAG19 0x00080000 +#define BITM_INTC_INTCFLAG0_FLAG18 0x00040000 +#define BITM_INTC_INTCFLAG0_FLAG17 0x00020000 +#define BITM_INTC_INTCFLAG0_FLAG16 0x00010000 +#define BITM_INTC_INTCFLAG0_FLAG15 0x00008000 +#define BITM_INTC_INTCFLAG0_FLAG14 0x00004000 +#define BITM_INTC_INTCFLAG0_FLAG13 0x00002000 +#define BITM_INTC_INTCFLAG0_FLAG12 0x00001000 /* Custom IRQ 3 Status */ +#define BITM_INTC_INTCFLAG0_FLAG11 0x00000800 /* Custom IRQ 2 Status */ +#define BITM_INTC_INTCFLAG0_FLAG10 0x00000400 /* Custom IRQ 1 Status */ +#define BITM_INTC_INTCFLAG0_FLAG9 0x00000200 /* Custom IRQ 0 Status */ +#define BITM_INTC_INTCFLAG0_FLAG8 0x00000100 /* Variance IRQ status. */ +#define BITM_INTC_INTCFLAG0_FLAG7 0x00000080 +#define BITM_INTC_INTCFLAG0_FLAG6 0x00000040 +#define BITM_INTC_INTCFLAG0_FLAG5 0x00000020 +#define BITM_INTC_INTCFLAG0_FLAG4 0x00000010 +#define BITM_INTC_INTCFLAG0_FLAG3 0x00000008 +#define BITM_INTC_INTCFLAG0_FLAG2 0x00000004 +#define BITM_INTC_INTCFLAG0_FLAG1 0x00000002 +#define BITM_INTC_INTCFLAG0_FLAG0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCFLAG1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_INTC_INTCFLAG1_FLAG31 31 +#define BITP_INTC_INTCFLAG1_FLAG30 30 +#define BITP_INTC_INTCFLAG1_FLAG29 29 +#define BITP_INTC_INTCFLAG1_FLAG28 28 +#define BITP_INTC_INTCFLAG1_FLAG27 27 +#define BITP_INTC_INTCFLAG1_FLAG26 26 +#define BITP_INTC_INTCFLAG1_FLAG25 25 +#define BITP_INTC_INTCFLAG1_FLAG24 24 +#define BITP_INTC_INTCFLAG1_FLAG23 23 +#define BITP_INTC_INTCFLAG1_FLAG22 22 +#define BITP_INTC_INTCFLAG1_FLAG21 21 +#define BITP_INTC_INTCFLAG1_FLAG20 20 +#define BITP_INTC_INTCFLAG1_FLAG19 19 +#define BITP_INTC_INTCFLAG1_FLAG18 18 +#define BITP_INTC_INTCFLAG1_FLAG17 17 +#define BITP_INTC_INTCFLAG1_FLAG16 16 +#define BITP_INTC_INTCFLAG1_FLAG15 15 +#define BITP_INTC_INTCFLAG1_FLAG14 14 +#define BITP_INTC_INTCFLAG1_FLAG13 13 +#define BITP_INTC_INTCFLAG1_FLAG12 12 /* Custom IRQ 3 Status */ +#define BITP_INTC_INTCFLAG1_FLAG11 11 /* Custom IRQ 2 Status */ +#define BITP_INTC_INTCFLAG1_FLAG10 10 /* Custom IRQ 1 Status */ +#define BITP_INTC_INTCFLAG1_FLAG9 9 /* Custom IRQ 0 Status */ +#define BITP_INTC_INTCFLAG1_FLAG8 8 /* Variance IRQ status. */ +#define BITP_INTC_INTCFLAG1_FLAG7 7 +#define BITP_INTC_INTCFLAG1_FLAG6 6 +#define BITP_INTC_INTCFLAG1_FLAG5 5 +#define BITP_INTC_INTCFLAG1_FLAG4 4 +#define BITP_INTC_INTCFLAG1_FLAG3 3 +#define BITP_INTC_INTCFLAG1_FLAG2 2 +#define BITP_INTC_INTCFLAG1_FLAG1 1 +#define BITP_INTC_INTCFLAG1_FLAG0 0 +#define BITM_INTC_INTCFLAG1_FLAG31 0x80000000 +#define BITM_INTC_INTCFLAG1_FLAG30 0x40000000 +#define BITM_INTC_INTCFLAG1_FLAG29 0x20000000 +#define BITM_INTC_INTCFLAG1_FLAG28 0x10000000 +#define BITM_INTC_INTCFLAG1_FLAG27 0x08000000 +#define BITM_INTC_INTCFLAG1_FLAG26 0x04000000 +#define BITM_INTC_INTCFLAG1_FLAG25 0x02000000 +#define BITM_INTC_INTCFLAG1_FLAG24 0x01000000 +#define BITM_INTC_INTCFLAG1_FLAG23 0x00800000 +#define BITM_INTC_INTCFLAG1_FLAG22 0x00400000 +#define BITM_INTC_INTCFLAG1_FLAG21 0x00200000 +#define BITM_INTC_INTCFLAG1_FLAG20 0x00100000 +#define BITM_INTC_INTCFLAG1_FLAG19 0x00080000 +#define BITM_INTC_INTCFLAG1_FLAG18 0x00040000 +#define BITM_INTC_INTCFLAG1_FLAG17 0x00020000 +#define BITM_INTC_INTCFLAG1_FLAG16 0x00010000 +#define BITM_INTC_INTCFLAG1_FLAG15 0x00008000 +#define BITM_INTC_INTCFLAG1_FLAG14 0x00004000 +#define BITM_INTC_INTCFLAG1_FLAG13 0x00002000 +#define BITM_INTC_INTCFLAG1_FLAG12 0x00001000 /* Custom IRQ 3 Status */ +#define BITM_INTC_INTCFLAG1_FLAG11 0x00000800 /* Custom IRQ 2 Status */ +#define BITM_INTC_INTCFLAG1_FLAG10 0x00000400 /* Custom IRQ 1 Status */ +#define BITM_INTC_INTCFLAG1_FLAG9 0x00000200 /* Custom IRQ 0 Status */ +#define BITM_INTC_INTCFLAG1_FLAG8 0x00000100 /* Variance IRQ status. */ +#define BITM_INTC_INTCFLAG1_FLAG7 0x00000080 +#define BITM_INTC_INTCFLAG1_FLAG6 0x00000040 +#define BITM_INTC_INTCFLAG1_FLAG5 0x00000020 +#define BITM_INTC_INTCFLAG1_FLAG4 0x00000010 +#define BITM_INTC_INTCFLAG1_FLAG3 0x00000008 +#define BITM_INTC_INTCFLAG1_FLAG2 0x00000004 +#define BITM_INTC_INTCFLAG1_FLAG1 0x00000002 +#define BITM_INTC_INTCFLAG1_FLAG0 0x00000001 +/** + * @} AD5940RegistersBitfields + * @endcond + * */ + +/** + * @addtogroup SPI_Block + * @{ + * @defgroup SPI_Block_Const + * @{ + * +*/ +#define SPICMD_SETADDR 0x20 /**< set the register address that is going to operate. */ +#define SPICMD_READREG 0x6d /**< command to read register */ +#define SPICMD_WRITEREG 0x2d /**< command to write register */ +#define SPICMD_READFIFO 0x5f /**< command to read FIFO */ +/** + * @} SPI_Block_Const + * @} SPI_Block +*/ + +/** + * @addtogroup AFE_Control + * @{ + * */ + +/** + * @defgroup AFE_Control_Const + * @{ + * */ + +/** + * @defgroup AFEINTC_Const + * @brief AD5940 has two interrupt controller INTC0 and INTC1. Both of them have ability to generate interrupt signal from GPIO. + * @{ + * */ +/* AFE Interrupt controller selection */ +#define AFEINTC_0 0 /**< Interrupt controller 0 */ +#define AFEINTC_1 1 /**< Interrupt controller 1 */ +/** @} */ + +/** + * @defgroup AFEINTC_SRC_Const + * @brief Interrupt source selection. These sources are defined as bit mask. They are available for register INTCCLR, INTCSEL0/1, INTCFLAG0/1 + * @{ + * */ +#define AFEINTSRC_ADCRDY 0x00000001 /**< Bit0, ADC Result Ready Status */ +#define AFEINTSRC_DFTRDY 0x00000002 /**< Bit1, DFT Result Ready Status */ +#define AFEINTSRC_SINC2RDY 0x00000004 /**< Bit2, SINC2/Low Pass Filter Result Status */ +#define AFEINTSRC_TEMPRDY 0x00000008 /**< Bit3, Temp Sensor Result Ready */ +#define AFEINTSRC_ADCMINERR 0x00000010 /**< Bit4, ADC Minimum Value */ +#define AFEINTSRC_ADCMAXERR 0x00000020 /**< Bit5, ADC Maximum Value */ +#define AFEINTSRC_ADCDIFFERR 0x00000040 /**< Bit6, ADC Delta Ready */ +#define AFEINTSRC_MEANRDY 0x00000080 /**< Bit7, Mean Result Ready */ +#define AFEINTSRC_VARRDY 0x00000100 /**< Bit8, Variance Result Ready */ +#define AFEINTSRC_CUSTOMINT0 0x00000200 /**< Bit9, Custom interrupt source 0. It happens when **sequencer** writes 1 to register AFEGENINTSTA.BIT0 */ +#define AFEINTSRC_CUSTOMINT1 0x00000400 /**< Bit10, Custom interrupt source 1. It happens when **sequencer** writes 1 to register AFEGENINTSTA.BIT1*/ +#define AFEINTSRC_CUSTOMINT2 0x00000800 /**< Bit11, Custom interrupt source 2. It happens when **sequencer** writes 1 to register AFEGENINTSTA.BIT2 */ +#define AFEINTSRC_CUSTOMINT3 0x00001000 /**< Bit12, Custom interrupt source 3. It happens when **sequencer** writes 1 to register AFEGENINTSTA.BIT3 */ +#define AFEINTSRC_BOOTLDDONE 0x00002000 /**< Bit13, OTP Boot Loading Done */ +#define AFEINTSRC_WAKEUP 0x00004000 /**< Bit14, AFE Woken up*/ +#define AFEINTSRC_ENDSEQ 0x00008000 /**< Bit15, End of Sequence Interrupt. */ +#define AFEINTSRC_SEQTIMEOUT 0x00010000 /**< Bit16, Sequencer Timeout Command Finished. */ +#define AFEINTSRC_SEQTIMEOUTERR 0x00020000 /**< Bit17, Sequencer Timeout Command Error. */ +#define AFEINTSRC_CMDFIFOFULL 0x00040000 /**< Bit18, Command FIFO Full Interrupt. */ +#define AFEINTSRC_CMDFIFOEMPTY 0x00080000 /**< Bit19, Command FIFO Empty */ +#define AFEINTSRC_CMDFIFOTHRESH 0x00100000 /**< Bit20, Command FIFO Threshold Interrupt. */ +#define AFEINTSRC_CMDFIFOOF 0x00200000 /**< Bit21, Command FIFO Overflow Interrupt. */ +#define AFEINTSRC_CMDFIFOUF 0x00400000 /**< Bit22, Command FIFO Underflow Interrupt. */ +#define AFEINTSRC_DATAFIFOFULL 0x00800000 /**< Bit23, Data FIFO Full Interrupt. */ +#define AFEINTSRC_DATAFIFOEMPTY 0x01000000 /**< Bit24, Data FIFO Empty */ +#define AFEINTSRC_DATAFIFOTHRESH 0x02000000 /**< Bit25, Data FIFO Threshold Interrupt. */ +#define AFEINTSRC_DATAFIFOOF 0x04000000 /**< Bit26, Data FIFO Overflow Interrupt. */ +#define AFEINTSRC_DATAFIFOUF 0x08000000 /**< Bit27, Data FIFO Underflow Interrupt. */ +#define AFEINTSRC_WDTIRQ 0x10000000 /**< Bit28, WDT Timeout Interrupt. */ +#define AFEINTSRC_CRC_OUTLIER 0x20000000 /**< Bit29, CRC interrupt for M355, Outlier Int for AD5940 */ +#define AFEINTSRC_GPT0INT_SLPWUT 0x40000000 /**< Bit30, Gneral Pupose Timer0 IRQ for M355. Sleep or Wakeup Tiemr timeout for AD5940*/ +#define AFEINTSRC_GPT1INT_TRYBRK 0x80000000 /**< Bit31, Gneral Pupose Timer1 IRQ for M355. Tried to Break IRQ for AD5940*/ +#define AFEINTSRC_ALLINT 0xffffffff /**< mask of all interrupt */ +/** @} */ + +/** + * @defgroup AFEPWR_Const + * @brief AFE power mode. + * @details It will set the whole analog system power mode include HSDAC, Excitation Buffer, HSTIA, ADC front-buffer etc. + * @{ +*/ +#define AFEPWR_LP 0 /**< Set AFE to Low Power mode. For signal <80kHz, use it. */ +#define AFEPWR_HP 1 /**< Set AFE to High Power mode. For signal >80kHz, use it. */ +/** + * @} +*/ + +/** + * @defgroup AFEBW_Const + * @brief AFE system bandwidth. + * @details It will set the whole analog bandwidth include HSDAC, Excitation Buffer, HSTIA, ADC front-buffer etc. + * @{ +*/ +#define AFEBW_AUTOSET 0 /**< Set the bandwidth automatically based on WGFCW frequency word. */ +#define AFEBW_50KHZ 1 /**< 50kHZ system bandwidth(DAC/ADC) */ +#define AFEBW_100KHZ 2 /**< 100kHZ system bandwidth(DAC/ADC) */ +#define AFEBW_250KHZ 3 /**< 250kHZ system bandwidth(DAC/ADC) */ +/** + * @} +*/ + +/** + * @defgroup AFECTRL_Const + * @brief AFE Control signal set. Bit masks for register AFECON. + * @details This is all the available control signal for function @ref AD5940_AFECtrlS + * @warning Bit field in register AFECON has some opposite meaning as below definitions. We use all positive word here + * like HPREF instead of HPREFDIS. This set is only used in function @ref AD5940_AFECtrlS, the second parameter + * decides whether enable it or disable it. + * @{ +*/ +#define AFECTRL_HPREFPWR (1L<<5) /**< High power reference on-off control */ +#define AFECTRL_HSDACPWR (1L<<6) /**< High speed DAC on-off control */ +#define AFECTRL_ADCPWR (1L<<7) /**< ADC power on-off control */ +#define AFECTRL_ADCCNV (1L<<8) /**< Start ADC convert enable */ +#define AFECTRL_EXTBUFPWR (1L<<9) /**< Excitation buffer power control */ +#define AFECTRL_INAMPPWR (1L<<10) /**< Excitation loop input amplifier before P/N node power control */ +#define AFECTRL_HSTIAPWR (1L<<11) /**< High speed TIA amplifier power control */ +#define AFECTRL_TEMPSPWR (1L<<12) /**< Temperature sensor power */ +#define AFECTRL_TEMPCNV (1L<<13) /**< Start Temperature sensor convert */ +#define AFECTRL_WG (1L<<14) /**< Waveform generator on-off control */ +#define AFECTRL_DFT (1L<<15) /**< DFT engine on-off control */ +#define AFECTRL_SINC2NOTCH (1L<<16) /**< SIN2+Notch block on-off control */ +#define AFECTRL_ALDOLIMIT (1L<<19) /**< ALDO current limit on-off control */ +#define AFECTRL_DACREFPWR (1L<<20) /**< DAC reference buffer power control */ +#define AFECTRL_DCBUFPWR (1L<<21) /**< Excitation loop DC offset buffer sourced from LPDAC power control */ +#define AFECTRL_ALL 0x39ffe0 /**< All control signals */ +/** + * @} +*/ + +/** + * @defgroup LPMODECTRL_Const + * @brief LP Control signal(bit mask) for register LPMODECON + * @details This is all the available control signal for function @ref AD5940_LPModeCtrlS + * @warning Bit field in register LPMODECON has some opposite meaning as below definitions. We use all positive word here + * like HPREFPWR instead of HPREFDIS. This set is only used in function @ref AD5940_AFECtrlS, the second parameter + * decides whether enable or disable selected block(s). + * @{ +*/ +#define LPMODECTRL_HFOSCEN (1<<0) /**< Enable internal HFOSC. Note: the register defination is set this bit to 1 to disable it. */ +#define LPMODECTRL_HPREFPWR (1<<1) /**< High power reference power EN. Note: the register defination is set this bit to 1 to disable it. */ +#define LPMODECTRL_ADCCNV (1<<2) /**< Start ADC convert enable */ +#define LPMODECTRL_REPEATEN (1<<3) /**< Enable repeat convert function. This will enable ADC power automatically */ +#define LPMODECTRL_GLBBIASZ (1<<4) /**< Enable Global ZTAT bias. Disable it to save more power */ +#define LPMODECTRL_GLBBIASP (1<<5) /**< Enable Global PTAT bias. Disable it to save more power */ +#define LPMODECTRL_BUFHP1P8V (1<<6) /**< High power 1.8V reference buffer */ +#define LPMODECTRL_BUFHP1P1V (1<<7) /**< High power 1.1V reference buffer */ +#define LPMODECTRL_ALDOPWR (1<<8) /**< Enable ALDO. Note: register defination is set this bit to 1 to disable ALDO. */ +#define LPMODECTRL_ALL 0x1ff /**< All Control signal Or'ed together*/ +#define LPMODECTRL_NONE 0 /**< No blocks selected */ +/** @} */ + +/** + * @defgroup AFERESULT_Const + * @brief The available AFE results type. Used for function @ref AD5940_ReadAfeResult + * @{ +*/ +#define AFERESULT_SINC3 0 /**< SINC3 result */ +#define AFERESULT_SINC2 1 /**< SINC2+NOTCH result */ +#define AFERESULT_TEMPSENSOR 2 /**< Temperature sensor result */ +#define AFERESULT_DFTREAL 3 /**< DFT Real result */ +#define AFERESULT_DFTIMAGE 4 /**< DFT Imaginary result */ +#define AFERESULT_STATSMEAN 5 /**< Statistic Mean result */ +#define AFERESULT_STATSVAR 6 /**< Statistic Variance result */ +/** @} */ + +/** + * @} AFE_Control_Const + * @} AFE_Control + * */ + +/** + * @addtogroup High_Speed_Loop + * @{ + * @defgroup High_Speed_Loop_Const + * @{ +*/ + +/** + * @defgroup Switch_Matrix_Block_Const + * @{ + * @defgroup SWD_Const + * @brief Switch D set. This is bit mask for register DSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type + * The bit masks can be OR'ed together. For example + * - `SWD_AIN1|SWD_RCAL0` means close SWD_AIN1 and SWD_RCAL0 in same time, and open all other D switches. + * - `SWD_AIN2` means close SWD_AIN2 and open all other D switches. + * @{ +*/ +#define SWD_OPEN (0<<0) /**< Open all D switch. */ +#define SWD_RCAL0 (1<<0) /**< pin RCAL0 */ +#define SWD_AIN1 (1<<1) /**< Pin AIN1 */ +#define SWD_AIN2 (1<<2) /**< Pin AIN2 */ +#define SWD_AIN3 (1<<3) /**< Pin AIN3 */ +#define SWD_CE0 (1<<4) /**< Pin CE0 */ +#define SWD_CE1 (1<<5) /**< CE1 in ADuCM355 */ +#define SWD_AFE1 (1<<5) /**< AFE1 in AD594x */ +#define SWD_SE0 (1<<6) /**< Pin SE0 */ +#define SWD_SE1 (1<<7) /**< SE1 in ADuCM355 */ +#define SWD_AFE3 (1<<7) /**< AFE3 in AD594x */ +/** @} */ + +/** + * @defgroup SWP_Const + * @brief Switch P set. This is bit mask for register PSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type. + * The bit masks can be OR'ed together. For example + * - `SWP_RCAL0|SWP_AIN1` means close SWP_RCAL0 and SWP_AIN1 in same time, and open all other P switches. + * - `SWP_SE0` means close SWP_SE0 and open all other P switches. + * @{ +*/ +#define SWP_OPEN 0 /**< Open all P switches */ +#define SWP_RCAL0 (1<<0) /**< Pin RCAL0 */ +#define SWP_AIN1 (1<<1) /**< Pin AIN1 */ +#define SWP_AIN2 (1<<2) /**< Pin AIN2 */ +#define SWP_AIN3 (1<<3) /**< Pin AIN3 */ +#define SWP_RE0 (1<<4) /**< Pin RE0 */ +#define SWP_RE1 (1<<5) /**< RE1 in ADuCM355 */ +#define SWP_AFE2 (1<<5) /**< AFE2 in AD5940 */ +#define SWP_SE0 (1<<6) /**< Pin SE0 */ +#define SWP_DE0 (1<<7) /**< Pin DE0 */ +#define SWP_SE1 (1<<8) /**< SE1 in ADuCM355 */ +#define SWP_AFE3 (1<<8) /**< AFE3 in AD5940 */ +#define SWP_DE1 (1<<9) /**< ADuCM355 Only. */ +#define SWP_CE0 (1<<10) /**< Pin CE0 */ +#define SWP_CE1 (1<<11) /**< CE1 in ADuCM355 */ +#define SWP_AFE1 (1<<11) /**< AFE1 in AD5940 */ +#define SWP_PL (1<<13) /**< Internal PL switch */ +#define SWP_PL2 (1<<14) /**< Internal PL2 switch */ +/** @} */ + +/** + * @defgroup SWN_Const + * @brief Switch N set. This is bit mask for register NSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type. + * The bit masks can be OR'ed together. For example + * - `SWN_RCAL0|SWN_AIN1` means close SWN_RCAL0 and SWN_AIN1 in same time, and open all other N switches. + * - `SWN_SE0` means close SWN_SE0 and open all other N switches. + * @{ +*/ +#define SWN_OPEN 0 /**< Open all N switches */ +#define SWN_RCAL1 (1<<9) /**< Pin RCAL1 */ +#define SWN_AIN0 (1<<0) /**< Pin AIN0 */ +#define SWN_AIN1 (1<<1) /**< Pin AIN1 */ +#define SWN_AIN2 (1<<2) /**< Pin AIN2 */ +#define SWN_AIN3 (1<<3) /**< Pin AIN3 */ +#define SWN_SE0LOAD (1<<4) /**< SE0_LOAD is different from PIN SE0. It's the point after 100Ohm load resistor */ +#define SWN_DE0LOAD (1<<5) /**< DE0_Load is after Rload resistor */ +#define SWN_SE1LOAD (1<<6) /**< SE1_LOAD in ADuCM355 */ +#define SWN_AFE3LOAD (1<<6) /**< AFE3LOAD in ADuCM355 */ +#define SWN_DE1LOAD (1<<7) /**< ADuCM355 Only*/ +#define SWN_SE0 (1<<8) /**< SE0 here means the PIN SE0. */ +#define SWN_NL (1<<10) /**< Internal NL switch */ +#define SWN_NL2 (1<<11) /**< Internal NL2 switch */ +/** @} */ + +/** + * @defgroup SWT_Const + * @brief Switch T set. This is bit mask for register TSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type. + * The bit masks can be OR'ed together. For example + * - SWT_RCAL0|SWT_AIN1 means close SWT_RCAL0 and SWT_AIN1 in same time, and open all other T switches. + * - SWT_SE0LOAD means close SWT_SE0LOAD and open all other T switches. + * @{ +*/ +#define SWT_OPEN 0 /**< Open all T switches */ +#define SWT_RCAL1 (1<<11) /**< Pin RCAL1 */ +#define SWT_AIN0 (1<<0) /**< Pin AIN0 */ +#define SWT_AIN1 (1<<1) /**< Pin AIN1 */ +#define SWT_AIN2 (1<<2) /**< Pin AIN2 */ +#define SWT_AIN3 (1<<3) /**< Pin AIN3 */ +#define SWT_SE0LOAD (1<<4) /**< SE0_LOAD is different from PIN SE0. It's the point after 100Ohm load resistor */ +#define SWT_DE0 (1<<5) /**< DE0 pin. */ +#define SWT_SE1LOAD (1<<6) /**< SE1_LOAD on ADuCM355*/ +#define SWT_AFE3LOAD (1<<6) /**< AFE3_LOAD on ADuCM355*/ +#define SWT_DE1 (1<<7) /**< ADuCM355 Only*/ +#define SWT_TRTIA (1<<8) /**< T9 switch. Connect RTIA to T matrix */ +#define SWT_DE0LOAD (1<<9) /**< DE0Load is the position after Rload Resisor */ +#define SWT_DE1LOAD (1<<10) /**< DE1Load is the position after Rload Resisor */ +/** @} */ + +/** @} Switch_Matrix_Block_Const */ + + +/** + * @defgroup Waveform_Generator_Block_Const + * @{ +*/ +/** + * @defgroup WGTYPE_Const + * @brief Waveform generator signal type + * @{ +*/ +#define WGTYPE_MMR 0 /**< Direct write to DAC using register */ +#define WGTYPE_SIN 2 /**< Sine wave generator */ +#define WGTYPE_TRAPZ 3 /**< Trapezoid generator */ +/** @} */ +/** @} Waveform_Generator_Block_Const */ + +/** + * @defgroup HSDAC_Block_Const + * @{ +*/ +/* Excitation buffer gain selection */ +/** + * @defgroup EXCITBUFGAIN_Const + * @{ +*/ +#define EXCITBUFGAIN_2 0 /**< Excitation buffer gain is x2 */ +#define EXCITBUFGAIN_0P25 1 /**< Excitation buffer gain is x1/4 */ +/** @} */ + +/** + * @defgroup HSDACGAIN_Const + * @{ +*/ +/* HSDAC PGA Gain selection(DACCON.BIT0) */ +#define HSDACGAIN_1 0 /**< Gain is x1 */ +#define HSDACGAIN_0P2 1 /**< Gain is x1/5 */ +/** @} */ +/** @} */ //HSDAC_Block_Const + +/** + * @defgroup HSTIA_Block_Const + * @{ + * */ +/* HSTIA Amplifier Positive Input selection */ + +/** + * @defgroup HSTIABIAS_Const + * @warning When select Vzero0 as bias, close LPDAC switch + * @{ +*/ +#define HSTIABIAS_1P1 0 /**< Internal 1.1V common voltage from internal 1.1V reference buffer */ +#define HSTIABIAS_VZERO0 1 /**< From LPDAC0 Vzero0 output */ +#define HSTIABIAS_VZERO1 2 /**< From LPDAC1 Vzero1 output. Only available on ADuCM355. */ +/** @} */ + + +/* HSTIA Internal RTIA selection */ + +/** + * @defgroup HSTIARTIA_Const + * @{ +*/ +#define HSTIARTIA_200 0 /**< HSTIA Internal RTIA resistor 200 */ +#define HSTIARTIA_1K 1 /**< HSTIA Internal RTIA resistor 1K */ +#define HSTIARTIA_5K 2 /**< HSTIA Internal RTIA resistor 5K */ +#define HSTIARTIA_10K 3 /**< HSTIA Internal RTIA resistor 10K */ +#define HSTIARTIA_20K 4 /**< HSTIA Internal RTIA resistor 20K */ +#define HSTIARTIA_40K 5 /**< HSTIA Internal RTIA resistor 40K */ +#define HSTIARTIA_80K 6 /**< HSTIA Internal RTIA resistor 80K */ +#define HSTIARTIA_160K 7 /**< HSTIA Internal RTIA resistor 160K */ +#define HSTIARTIA_OPEN 8 /**< Open internal resistor */ +/** @} */ + +/** + * @defgroup HSTIADERTIA_Const + * @{ +*/ +#define HSTIADERTIA_50 0 /**< 50Ohm Settings depends on RLOAD resistor. */ +#define HSTIADERTIA_100 1 /**< 100Ohm Settings depends on RLOAD resistor.*/ +#define HSTIADERTIA_200 2 /**< 200Ohm Settings depends on RLOAD resistor.*/ +#define HSTIADERTIA_1K 3 /**< set bit[7:3] to 0x0b(11) */ +#define HSTIADERTIA_5K 4 /**< set bit[7:3] to 0x0c(12) */ +#define HSTIADERTIA_10K 5 /**< set bit[7:3] to 0x0d(13) */ +#define HSTIADERTIA_20K 6 /**< set bit[7:3] to 0x0e(14) */ +#define HSTIADERTIA_40K 7 /**< set bit[7:3] to 0x0f(15) */ +#define HSTIADERTIA_80K 8 /**< set bit[7:3] to 0x10(16) */ +#define HSTIADERTIA_160K 9 /**< set bit[7:3] to 0x11(17) */ +#define HSTIADERTIA_TODE 10 /**< short HSTIA output to DE0 pin. set bit[7:3] to 0x12(18) */ +#define HSTIADERTIA_OPEN 11 /**< Default state is set to OPEN RTIA by setting bit[7:3] to 0x1f */ +/** @} */ + +/* HSTIA DE0 Terminal internal RLOAD selection */ +/** + * @defgroup HSTIADERLOAD_Const + * @{ +*/ +#define HSTIADERLOAD_0R 0 /**< set bit[2:0] to 0x00 */ +#define HSTIADERLOAD_10R 1 /**< set bit[2:0] to 0x01 */ +#define HSTIADERLOAD_30R 2 /**< set bit[2:0] to 0x02 */ +#define HSTIADERLOAD_50R 3 /**< set bit[2:0] to 0x03 */ +#define HSTIADERLOAD_100R 4 /**< set bit[2:0] to 0x04 */ +#define HSTIADERLOAD_OPEN 5 /**< RLOAD open means open switch between HSTIA negative input and Rload resistor().Default state is OPEN RLOAD by setting HSTIARES03CON[2:0] to 0x5, 0x6 or 0x7 */ +/** @} */ + +/** + * @defgroup HSTIAPWRMOE_Const + * @{ +*/ +#define HSTIAPWRMOE_LP 0 /**< HSTIA in LP mode */ +#define HSTIAPWRMOE_HP 1 /**< HSTIA in HP mode */ +/** @} */ + + +/** @} HSTIA_Block_Const */ +/** + * @} High_Speed_Loop_Const + * @} High_Speed_Loop +*/ + +/** + * @addtogroup Low_Power_Loop + * Low power includes low power DAC and two low power amplifiers(PA and TIA) + * @{ + * @defgroup Low_Power_Loop_Const + * The constant used in Low power loop. + * @{ +*/ + +/** + * @defgroup LPDAC_Block_Const + * @{ + * */ +/** + * @defgroup LPDAC_Const + * Select which LPDAC is accessing. + * @note This parameter must be configured correctly + * @{ +*/ +#define LPDAC0 0 /**< LPDAC0 */ +#define LPDAC1 1 /**< LPDAC1, ADuCM355 Only */ +/** @} */ +/** + * @defgroup LPDACSRC_Const + * LPDAC data source selection. Either from MMR or from waveform generator. + * @{ +*/ +#define LPDACSRC_MMR 0 /**< Get data from register REG_AFE_LPDACDAT0DATA0 */ +#define LPDACSRC_WG 1 /**< Get data from waveform generator */ +/** @} */ + +/** + * @defgroup LPDACSW_Const + * @brief LPDAC switch settings + * @{ +*/ +#define LPDACSW_VBIAS2LPPA 0x10 /**< switch between LPDAC Vbias output and LPPA(low power PA(Potential Amplifier)) */ +#define LPDACSW_VBIAS2PIN 0x08 /**< Switch between LPDAC Vbias output and Vbias pin */ +#define LPDACSW_VZERO2LPTIA 0x04 /**< Switch between LPDAC Vzero output and LPTIA positive input */ +#define LPDACSW_VZERO2PIN 0x02 /**< Switch between LPDAC Vzero output and Vzero pin */ +#define LPDACSW_VZERO2HSTIA 0x01 /**< Switch between LPDAC Vzero output and HSTIA positive input MUX */ +/** @} */ + +/** + * @defgroup LPDACVZERO_Const + * @brief Vzero MUX selection + * @{ +*/ +#define LPDACVZERO_6BIT 0 /**< Connect Vzero to 6bit LPDAC output */ +#define LPDACVZERO_12BIT 1 /**< Connect Vzero to 12bit LPDAC output */ +/** @} */ + +/** + * @defgroup LPDACVBIAS_Const + * @brief Vbias MUX selection + * @{ +*/ +#define LPDACVBIAS_6BIT 1 /**< Connect Vbias to 6bit LPDAC output */ +#define LPDACVBIAS_12BIT 0 /**< Connect Vbias to 12bit LPDAC output */ +/** @} */ + + +/** + * @defgroup LPDACREF_Const + * @brief LPDAC reference selection + * @{ +*/ +#define LPDACREF_2P5 0 /**< Internal 2.5V reference */ +#define LPDACREF_AVDD 1 /**< Use AVDD as reference */ +/** @} */ + +/** @} */ //LPDAC_Block_Const + +/** + * @defgroup LPAMP_Block_Const + * @brief Low power amplifies include potential-state amplifier(PA in short) and TIA. + * @{ + * */ + +/** + * @defgroup LPTIA_Const + * @brief LPTIA selecion + * @{ + * */ +#define LPTIA0 0 /**< LPTIA0 */ +#define LPTIA1 1 /**< LPTIA1, ADuCM355 Only */ +/** @} */ + +/** + * @defgroup LPTIARF_Const + * @brief LPTIA LPF Resistor selection + * @{ + * */ +#define LPTIARF_OPEN 0 /**< Disconnect Rf resistor */ +#define LPTIARF_SHORT 1 /**< Bypass Rf resistor */ +#define LPTIARF_20K 2 /**< 20kOhm Rf */ +#define LPTIARF_100K 3 /**< Rf resistor 100kOhm */ +#define LPTIARF_200K 4 /**< Rf resistor 200kOhm */ +#define LPTIARF_400K 5 /**< Rf resistor 400kOhm */ +#define LPTIARF_600K 6 /**< Rf resistor 600kOhm */ +#define LPTIARF_1M 7 /**< Rf resistor 1MOhm */ +/** @} */ + +/** + * @defgroup LPTIARLOAD_Const + * @brief LPTIA Rload Selection + * @{ +*/ +#define LPTIARLOAD_SHORT 0 /**< 0Ohm Rload */ +#define LPTIARLOAD_10R 1 /**< 10Ohm Rload */ +#define LPTIARLOAD_30R 2 /**< Rload resistor 30Ohm */ +#define LPTIARLOAD_50R 3 /**< Rload resistor 50Ohm */ +#define LPTIARLOAD_100R 4 /**< Rload resistor 100Ohm */ +#define LPTIARLOAD_1K6 5 /**< Only available when RTIA setting >= 2KOHM */ +#define LPTIARLOAD_3K1 6 /**< Only available when RTIA setting >= 4KOHM */ +#define LPTIARLOAD_3K6 7 /**< Only available when RTIA setting >= 4KOHM */ +/** @} */ + +/** + * @defgroup LPTIARTIA_Const + * @brief LPTIA RTIA Selection + * @note The real RTIA resistor value dependents on Rload settings. + * @{ +*/ +#define LPTIARTIA_OPEN 0 /**< Disconnect LPTIA Internal RTIA */ +#define LPTIARTIA_200R 1 /**< 200Ohm Internal RTIA */ +#define LPTIARTIA_1K 2 /**< 1KOHM */ +#define LPTIARTIA_2K 3 /**< 2KOHM */ +#define LPTIARTIA_3K 4 /**< 3KOHM */ +#define LPTIARTIA_4K 5 /**< 4KOHM */ +#define LPTIARTIA_6K 6 /**< 6KOHM */ +#define LPTIARTIA_8K 7 /**< 8KOHM */ +#define LPTIARTIA_10K 8 /**< 10KOHM */ +#define LPTIARTIA_12K 9 /**< 12KOHM */ +#define LPTIARTIA_16K 10 /**< 16KOHM */ +#define LPTIARTIA_20K 11 /**< 20KOHM */ +#define LPTIARTIA_24K 12 /**< 24KOHM */ +#define LPTIARTIA_30K 13 /**< 30KOHM */ +#define LPTIARTIA_32K 14 /**< 32KOHM */ +#define LPTIARTIA_40K 15 /**< 40KOHM */ +#define LPTIARTIA_48K 16 /**< 48KOHM */ +#define LPTIARTIA_64K 17 /**< 64KOHM */ +#define LPTIARTIA_85K 18 /**< 85KOHM */ +#define LPTIARTIA_96K 19 /**< 96KOHM */ +#define LPTIARTIA_100K 20 /**< 100KOHM */ +#define LPTIARTIA_120K 21 /**< 120KOHM */ +#define LPTIARTIA_128K 22 /**< 128KOHM */ +#define LPTIARTIA_160K 23 /**< 160KOHM */ +#define LPTIARTIA_196K 24 /**< 196KOHM */ +#define LPTIARTIA_256K 25 /**< 256KOHM */ +#define LPTIARTIA_512K 26 /**< 512KOHM */ +/** @} */ + +/** + * @defgroup LPAMP_Const + * LPAMP selecion. On AD594x, only LPAMP0 is available. + * @note This parameter must be configured correctly. + * @{ + * */ +#define LPAMP0 0 /**< LPAMP0, AMP include both LPTIA and Potentio-stat amplifiers */ +#define LPAMP1 1 /**< LPAMP1, ADuCM355 Only */ +/** @} */ + +/** + * @defgroup LPAMPPWR_Const + * @brief Low power amplifier(PA and TIA) power mode selection. + * @{ +*/ +#define LPAMPPWR_NORM 0 /**< Normal Power mode */ +#define LPAMPPWR_BOOST1 1 /**< Boost power to level 1 */ +#define LPAMPPWR_BOOST2 2 /**< Boost power to level 2 */ +#define LPAMPPWR_BOOST3 3 /**< Boost power to level 3 */ +#define LPAMPPWR_HALF 4 /**< Put PA and TIA in half power mode */ +/** @} */ + +#define LPTIASW(n) (1L<>2)&0x7f)<<24) \ + |(((uint32_t)(data))&0xffffff)) + +/* Some commands used frequently */ +#define SEQ_NOP() SEQ_WAIT(0) /**< SEQ_NOP is just a simple wait command that wait one system clock */ +#define SEQ_HALT() SEQ_WR(REG_AFE_SEQCON,0x12) /**< Can halt sequencer. Used for debug */ +#define SEQ_STOP() SEQ_WR(REG_AFE_SEQCON,0x00) /**< Disable sequencer, this will generate End of Sequence interrupt */ + +#define SEQ_SLP() SEQ_WR(REG_AFE_SEQTRGSLP, 1) /**< Trigger sleep. If sleep is allowed, AFE will go to sleep/hibernate mode */ + +#define SEQ_INT0() SEQ_WR(REG_AFE_AFEGENINTSTA, (1L<<0)) /**< Generate custom interrupt 0 */ +#define SEQ_INT1() SEQ_WR(REG_AFE_AFEGENINTSTA, (1L<<1)) /**< Generate custom interrupt 1 */ +#define SEQ_INT2() SEQ_WR(REG_AFE_AFEGENINTSTA, (1L<<2)) /**< Generate custom interrupt 2 */ +#define SEQ_INT3() SEQ_WR(REG_AFE_AFEGENINTSTA, (1L<<3)) /**< Generate custom interrupt 3 */ + +/* Helper to calculate sequence length in array */ +#define SEQ_LEN(n) (sizeof(n)/4) /**< Calculate how many commands are in sepecified array. */ +/** @} */ //Sequencer_Helper + +/* FIFO */ +/** + * @defgroup FIFOMODE_Const + * @{ +*/ +#define FIFOMODE_FIFO 2 /**< Standard FIFO mode. If FIFO is full, reject all comming data and put FIFO to fault state, report interrupt if enabled */ +#define FIFOMODE_STREAM 3 /**< Stream mode. If FIFO is full, discard older data. Report FIFO full interrupt if enabled */ +/** @} */ + +/** + * @defgroup FIFOSRC_Const + * @{ +*/ +#define FIFOSRC_SINC3 0 /**< SINC3 data */ +#define FIFOSRC_DFT 2 /**< DFT real and imaginary part */ +#define FIFOSRC_SINC2NOTCH 3 /**< SINC2+NOTCH block. Notch can be bypassed, so SINC2 data can be feed to FIFO */ +#define FIFOSRC_VAR 4 /**< Statistic variarance output */ +#define FIFOSRC_MEAN 5 /**< Statistic mean output */ +/** @} */ + +/** + * @defgroup FIFO_Helper + * @{ +*/ +/** + * Method to identify FIFO channel ID: + * [31:25][24:23][22:16][15:0] + * [ ECC ][SEQID][CH_ID][DATA] + * + * CH_ID: [22:16] 7bit in total: + * xxxxx_xx + * 11111_xx : DFT results + * 11110_xx : Mean of statistic block + * 11101_xx : Variance of statistic block + * 1xxxx_xx : Notch filter result, where xxx_xx is the ADC MUX P settings(6bits of reg ADCCON[5:0]). + * 0xxxx_xx : SINC3 filter result, where xxx_xx is the ADC MUX P settings(6bits of reg ADCCON[5:0]). +*/ +#define FIFO_SEQID(data) ((((uint32_t)data)>>23)&0x3) /**< Return seqid of this FIFO result */ +#define FIFO_ECC(data) ((((uint32_t)data)>>25)&0x7f) /**< Return ECC of this FIFO result */ +#define FIFO_CHANID(data) ((((uint32_t)data)>>16)&0x7f) /**< Return Channel ID */ +#define FIFOCHANID_MUXP(data) ((((uint32_t)data)>>16)&0x3f) /**< Return the ADC MUXP selection */ + +#define ISCHANID_DFT(data) ((((((uint32_t)data)>>18)&0x1f)==0x1f)?bTRUE:bFALSE) /**< If the channel id is DFT */ +#define ISCHANID_MEAN(data) ((((((uint32_t)data)>>18)&0x1f)==0x1e)?bTRUE:bFALSE) /**< If the channel id is MEAN */ +#define ISCHANID_VAR(data) ((((((uint32_t)data)>>18)&0x1f)==0x1d)?bTRUE:bFALSE) /**< If the channel id is Variance */ +#define ISCHANID_SINC3(data) ((((((uint32_t)data)>>18)&0x1f)< 0x10)?bTRUE:bFALSE) /**< If the channel id is SINC3 */ +#define ISCHANID_NOTCH(data) ((((((uint32_t)data)>>18)&0x1f)>=0x10)&&(((((uint32_t)data>>18)&0x1f) < 0x1d)?bTRUE:bFALSE)) /**< If the channel id is Notch */ +/** @} */ + +/** + * @defgroup FIFOSIZE_Const + * @brief Set FIFO size. + * @warning The total available SRAM is 6kB. It's shared by FIFO and sequencer. + * @{ +*/ +#define FIFOSIZE_32B 0 /**< The selfbuild in 32Byte for data FIFO. All 6kB SRAM for sequencer */ +#define FIFOSIZE_2KB 1 /**< DATA FIFO use 2kB. The reset 4kB is used for sequencer */ +#define FIFOSIZE_4KB 2 /**< 4kB for Data FIFO. 2kB for sequencer */ +#define FIFOSIZE_6KB 3 /**< All 6kB for Data FIFO. Build in 32Bytes memory for sequencer */ +/** @} */ + +/* Wake up timer */ +/** + * @defgroup WUPTENDSEQ_Const + * @{ +*/ +#define WUPTENDSEQ_A 0 /**< End at slot A */ +#define WUPTENDSEQ_B 1 /**< End at slot B */ +#define WUPTENDSEQ_C 2 /**< End at slot C */ +#define WUPTENDSEQ_D 3 /**< End at slot D */ +#define WUPTENDSEQ_E 4 /**< End at slot E */ +#define WUPTENDSEQ_F 5 /**< End at slot F */ +#define WUPTENDSEQ_G 6 /**< End at slot G */ +#define WUPTENDSEQ_H 7 /**< End at slot H */ +/** @} */ + +/** + * @} End of sequencer_and_FIFO block + * @} Sequencer_FIFO + * */ + +/** + * @addtogroup MISC_Block + * @{ + * @defgroup MISC_Block_Const + * @brief This block includes clock, GPIO, configuration. + * @{ +*/ + +/* Helper for calculate clocks needed for various of data type */ +/** + * @defgroup DATATYPE_Const + * @{ +*/ +#define DATATYPE_ADCRAW 0 /**< ADC raw data */ +#define DATATYPE_SINC3 1 /**< SINC3 data */ +#define DATATYPE_SINC2 2 /**< SINC2 Data */ +#define DATATYPE_DFT 3 /**< DFT */ +#define DATATYPE_NOTCH 4 /**< Notch filter output. (when notch is not bypassed) */ +//#define DATATYPE_MEAN +/** @} */ + + +/** + * @defgroup SLPKEY_Const + * @{ +*/ +#define SLPKEY_LOCK 0 /**< any incorrect value will lock the key */ +#define SLPKEY_UNLOCK 0xa47e5 /**< The correct key for register SEQSLPLOCK */ +/** @} */ + +/** + * @defgroup HPOSCOUT_Const + * @brief Set HPOSC output clock frequency, 16MHz or 32MHz. + * @{ +*/ +#define HPOSCOUT_32MHZ 0 /**< Configure internal HFOSC output 32MHz clock */ +#define HPOSCOUT_16MHZ 1 /**< 16MHz Clock */ +/** @} */ + +/* GPIO */ +/** + * @defgroup AGPIOPIN_Const + * @brief The pin masks for register GP0OEN, GP0PE, GP0IEN,..., GP0TGL + * @{ +*/ +#define AGPIO_Pin0 0x01 /**< AFE GPIO0, only available on AD5940 and AD5941, not ADuCM355 */ +#define AGPIO_Pin1 0x02 /**< AFE GPIO1, only available on AD5940 and AD5941, not ADuCM355 */ +#define AGPIO_Pin2 0x04 /**< AFE GPIO2, only available on AD5940 and AD5941, not ADuCM355 */ +#define AGPIO_Pin3 0x08 /**< AFE GPIO3, only available on AD5941. */ +#define AGPIO_Pin4 0x10 /**< AFE GPIO4, only available on AD5941. */ +#define AGPIO_Pin5 0x20 /**< AFE GPIO5, only available on AD5941. */ +#define AGPIO_Pin6 0x40 /**< AFE GPIO6, only available on AD5941. */ +#define AGPIO_Pin7 0x80 /**< AFE GPIO7, only available on AD5941. */ +/** @} */ + +/** + * @defgroup GP0FUNC_Const + * @{ +*/ +#define GP0_INT 0 /**< Interrupt Controller 0 output */ +#define GP0_TRIG 1 /**< Sequence0 trigger */ +#define GP0_SYNC 2 /**< Use Sequencer to controll GP0 output level */ +#define GP0_GPIO 3 /**< Normal GPIO function */ +/** @} */ + +/** + * @defgroup GP1FUNC_Const + * @{ +*/ +#define GP1_GPIO (0<<2) /**< Normal GPIO function */ +#define GP1_TRIG (1<<2) /**< Sequence1 trigger */ +#define GP1_SYNC (2<<2) /**< Use Sequencer to controll GP1 output level */ +#define GP1_SLEEP (3<<2) /**< Internal Sleep Signal */ +/** @} */ + +/** + * @defgroup GP2FUNC_Const + * @{ +*/ +#define GP2_PORB (0<<4) /**< Internal Power ON reset signal */ +#define GP2_TRIG (1<<4) /**< Sequence1 trigger */ +#define GP2_SYNC (2<<4) /**< Use Sequencer to controll GP2 output level */ +#define GP2_EXTCLK (3<<4) /**< External Clock input(32kHz/16MHz/32MHz) */ +/** @} */ + +/** + * @defgroup GP3FUNC_Const + * @{ +*/ +#define GP3_GPIO (0<<6) /**< Normal GPIO function */ +#define GP3_TRIG (1<<6) /**< Sequence3 trigger */ +#define GP3_SYNC (2<<6) /**< Use Sequencer to controll GP3 output level */ +#define GP3_INT0 (3<<6) /**< Interrupt Controller 0 output */ +/** @} */ + +/** + * @defgroup GP4FUNC_Const + * @note GP4 (Not available on AD5941) + * @{ +*/ +#define GP4_GPIO (0<<8) /**< Normal GPIO function */ +#define GP4_TRIG (1<<8) /**< Sequence0 trigger */ +#define GP4_SYNC (2<<8) /**< Use Sequencer to controll GP4 output level */ +#define GP4_INT1 (3<<8) /**< Interrupt Controller 1 output */ +/** @} */ + +/** + * @defgroup GP5FUNC_Const + * @note GP5 (Not available on AD5941) + * @{ +*/ +#define GP5_GPIO (0<<10) /**< Internal Power ON reset signal */ +#define GP5_TRIG (1<<10) /**< Sequence1 trigger */ +#define GP5_SYNC (2<<10) /**< Use Sequencer to controll GP5 output level */ +#define GP5_EXTCLK (3<<10) /**< External Clock input(32kHz/16MHz/32MHz) */ +/** @} */ + +/** + * @defgroup GP6FUNC_Const + * @note GP6 (Not available on AD5941) + * @{ +*/ +#define GP6_GPIO (0<<12) /**< Normal GPIO function */ +#define GP6_TRIG (1<<12) /**< Sequence2 trigger */ +#define GP6_SYNC (2<<12) /**< Use Sequencer to controll GP6 output level */ +#define GP6_INT0 (3<<12) /**< Interrupt Controller 0 output */ +/** @} */ + +/** + * @defgroup GP7FUNC_Const + * @note GP7 (Not available on AD5941) + * @{ +*/ +#define GP7_GPIO (0<<14) /**< Normal GPIO function */ +#define GP7_TRIG (1<<14) /**< Sequence2 trigger */ +#define GP7_SYNC (2<<14) /**< Use Sequencer to controll GP7 output level */ +#define GP7_INT (3<<14) /**< Interrupt Controller 1 output */ +/** @} */ + +//LPModeClk +/** + * @defgroup LPMODECLK_Const + * @{ +*/ +#define LPMODECLK_HFOSC 0 /**< Use HFOSC 16MHz/32MHz clock as system clock */ +#define LPMODECLK_LFOSC 1 /**< Use LFOSC 32kHz clock as system clock */ +/** @} */ + +/* Clock */ +/** + * @defgroup SYSCLKSRC_Const + * @brief Select system clock source. The clock must be available. If unavailable clock is selected, we can reset AD5940. + * The system clock should be limited to 32MHz. If external clock or XTAL is faster than 16MHz, we use system clock divider to ensure it's always in range of 16MHz. + * @warning Maximum SPI clock has relation with system clock. Limit the SPI clock to ensure SPI clock is slower than system clock. + * @{ +*/ +#define SYSCLKSRC_HFOSC 0 /**< Internal HFOSC. CLock is 16MHz or 32MHz configurable. Set clock divider to ensure system clock is always 16MHz */ +#define SYSCLKSRC_XTAL 1 /**< External crystal. It can be 16MHz or 32MHz.Set clock divider to ensure system clock is always 16MHz */ +#define SYSCLKSRC_LFOSC 2 /**< Internal 32kHz clock. Note the SPI clock also sourced with 32kHz so the register read/write frequency is lower down. */ +#define SYSCLKSRC_EXT 3 /**< External clock from GPIO, AD594x Only */ +/** @} */ + +/** + * @defgroup ADCCLKSRC_Const + * @brief Select ADC clock source. + * The maximum clock is 32MHz. + * @warning The ADC raw data update rate is equal to ADCClock/20. When ADC clock is 32MHz, sample rate is 1.6MSPS. + * The SINC3 filter clock are sourced from ADC clock and should be limited to 16MHz. When ADC clock is set to 32MHz. Clear bit ADCFILTERCON.BIT0 + * to enable the SINC3 clock divider. + * @{ +*/ +#define ADCCLKSRC_HFOSC 0 /**< Internal HFOSC. 16MHz or 32MHz which is configurable */ +#define ADCCLKSRC_XTAL 1 /**< External crystal. Set ADC clock divider to get either 16MHz or 32MHz clock */ +//#define ADCCLKSRC_LFOSC 2 /**< Do not use */ +#define ADCCLKSRC_EXT 3 /**< External clock from GPIO. Set ADC clock divider to get the clock you want */ +/** @} */ + + +/** + * @defgroup ADCCLKDIV_Const + * @brief The divider for ADC clock. ADC clock = ClockSrc/Divider. + * @{ +*/ +#define ADCCLKDIV_1 1 /**< Divider ADCClk = ClkSrc/1 */ +#define ADCCLKDIV_2 2 /**< Divider ADCClk = ClkSrc/2 */ +/** @} */ + +/** + * @defgroup SYSCLKDV_Const + * @brief The divider for system clock. System clock = ClockSrc/Divider. + * @{ +*/ +#define SYSCLKDIV_1 1 /**< Divider SysClk = ClkSrc/1 */ +#define SYSCLKDIV_2 2 /**< Divider SysClk = ClkSrc/2 */ +/** @} */ + +/** + * @defgroup PGACALTYPE_Const + * @brief Calibration Type + * @{ +*/ +#define PGACALTYPE_OFFSET 0 /**< Calibrate offset */ +#define PGACALTYPE_GAIN 1 /**< Calibrate gain */ +#define PGACALTYPE_OFFSETGAIN 2 /**< Calibrate offset and gain */ +/** @} */ + +/** + * @defgroup AD5940ERR_Const + * @brief AD5940 error code used by library and example codes. + * @{ +*/ +#define AD5940ERR_OK 0 /**< No error */ +#define AD5940ERR_ERROR -1 /**< General error message */ +#define AD5940ERR_PARA -2 /**< Parameter is illegal */ +#define AD5940ERR_NULLP -3 /**< Null pointer */ +#define AD5940ERR_BUFF -4 /**< Buffer limited. */ +#define AD5940ERR_ADDROR -5 /**< Out of Range. Register address is out of range. */ +#define AD5940ERR_SEQGEN -6 /**< Sequence generator error */ +#define AD5940ERR_SEQREG -7 /**< Register info is not found */ +#define AD5940ERR_SEQLEN -8 /**< Sequence length is too long. */ +#define AD5940ERR_WAKEUP -9 /**< Unable to wakeup AFE in specified time */ +#define AD5940ERR_TIMEOUT -10 /**< Time out error. */ +#define AD5940ERR_CALOR -11 /**< calibration out of range. */ +#define AD5940ERR_APPERROR -100 /**< Used in example code to indicated the application has not been initialized. */ +/** @} */ + +#ifndef NULL + #define NULL (void *) 0 /**< Null, if it's not defined. */ +#endif +#define MATH_PI 3.1415926f /**< Pi defination. */ + +#define AD5940_ADIID 0x4144 /**< ADIID is fixed to 0x4144 */ +#define AD5940_CHIPID 0x0000 /**< CHIPID is changing with silicon version */ +#define M355_ADIID 0x4144 /**< ADIID is fixed to 0x4144 */ +#define M355_CHIPID 0x0000 /**< CHIPID is changing with silicon version */ + +#define AD5940_SWRST 0xa158 /**< AD594x only. The value to perform software reset via reigster SWRSTCON */ +#define KEY_OSCCON 0xcb14 /**< key of register OSCCON. The key is auto locked after writing to any other register */ +#define KEY_CALDATLOCK 0xde87a5af /**< Calibration key. */ +#define KEY_LPMODEKEY 0xc59d6 /**< LP mode key */ + +#define PARA_CHECK(n) /** add parameter check, Add DEBUG switch */ + +/** + * @} MISC_Block_Const + * @} MISC_Block + * */ +/** + * @defgroup TypeDefinitions + * @{ +*/ + +typedef int32_t AD5940Err; /**< error number defination */ + +/** + * bool definition for ad5940lib. +*/ +typedef enum +{ + bFALSE = 0, bTRUE = !bFALSE, /**< True and False definition*/ +}BoolFlag; + +typedef struct +{ + /* ADC/DAC/TIA reference and buffer */ + BoolFlag HpBandgapEn; /**< Enable High power band-gap. Clear bit AFECON.HPREFDIS will enable Bandgap, while set this bit will disable bandgap */ + BoolFlag Hp1V8BuffEn; /**< High power 1.8V reference buffer enable */ + BoolFlag Hp1V1BuffEn; /**< High power 1.1V reference buffer enable */ + BoolFlag Lp1V8BuffEn; /**< Low power 1.8V reference buffer enable */ + BoolFlag Lp1V1BuffEn; /**< Low power 1.1V reference buffer enable */ + /* Low bandwidth loop reference and buffer */ + BoolFlag LpBandgapEn; /**< Enable Low power band-gap. */ + BoolFlag LpRefBufEn; /**< Enable the 2.5V low power reference buffer */ + BoolFlag LpRefBoostEn; /**< Boost buffer current */ + /* DAC Reference Buffer */ + BoolFlag HSDACRefEn; /**< Enable DAC reference buffer from HP Bandgap */ + /* Misc. control */ + BoolFlag Hp1V8ThemBuff; /**< Thermal Buffer for internal 1.8V reference to AIN3 pin */ + BoolFlag Hp1V8Ilimit; /**< Current limit for High power 1.8V reference buffer */ + BoolFlag Disc1V8Cap; /**< Discharge 1.8V capacitor. Short external 1.8V decouple capacitor to ground. Be careful when use this bit */ + BoolFlag Disc1V1Cap; /**< Discharge 1.1V capacitor. Short external 1.1V decouple capacitor to ground. Be careful when use this bit */ +}AFERefCfg_Type; + +/** + * @defgroup ADC_BlockType + * @{ +*/ + +/** + * Structure for ADC Basic settings include MUX and PGA. +*/ +typedef struct +{ + uint32_t ADCMuxP; /**< ADC Positive input channel selection. select from @ref ADCMUXP */ + uint32_t ADCMuxN; /**< ADC negative input channel selection. select from @ref ADCMUXN */ + uint32_t ADCPga; /**< ADC PGA settings, select from @ref ADCPGA */ +}ADCBaseCfg_Type; + +/** + * Structure for ADC filter settings. +*/ +typedef struct +{ + uint32_t ADCSinc3Osr; + uint32_t ADCSinc2Osr; + uint32_t ADCAvgNum; /**< Average filter is enabled when DFT source is @ref DFTSRC_AVG in function @ref AD5940_DFTCfgS. This average filter is only used by DFT engine. */ + uint32_t ADCRate; /**< ADC Core sample rate */ + BoolFlag BpNotch; /**< Bypass Notch filter in SINC2+Notch block, so only SINC2 is used. ADCFILTERCON.BIT4 */ + BoolFlag BpSinc3; /**< Bypass SINC3 Module */ + BoolFlag Sinc3ClkEnable; /**< Enable SINC3 clock */ + BoolFlag Sinc2NotchClkEnable; /**< Enable SINC2+Notch clock */ + BoolFlag Sinc2NotchEnable; /**< Enable SINC2+Notch block */ + BoolFlag DFTClkEnable; /**< Enable DFT clock */ + BoolFlag WGClkEnable; /**< Enable Waveform Generator clock */ +}ADCFilterCfg_Type; +/** @} */ + +/** + * DFT Configuration structure. +*/ +typedef struct +{ + uint32_t DftNum; /**< DFT number */ + uint32_t DftSrc; /**< DFT Source */ + BoolFlag HanWinEn; /**< Enable Hanning window */ +}DFTCfg_Type; + +/** + * ADC digital comparator +*/ +typedef struct +{ + uint16_t ADCMin; /**< The ADC code minimum limit value */ + uint16_t ADCMinHys; + uint16_t ADCMax; /**< The ADC code maximum limit value */ + uint16_t ADCMaxHys; +}ADCDigComp_Type; + +/** + * Statistic function +*/ +typedef struct +{ + uint32_t StatDev; /**< Statistic standard deviation configure */ + uint32_t StatSample; /**< Sample size */ + BoolFlag StatEnable; /**< Set true to enable statistic block */ +}StatCfg_Type; + +/** + * Switch matrix configure */ +typedef struct +{ + uint32_t Dswitch; /**< D switch settings. Select from @ref SWD_Const*/ + uint32_t Pswitch; /**< P switch settings. Select from @ref SWP_Const */ + uint32_t Nswitch; /**< N switch settings. Select from @ref SWN_Const */ + uint32_t Tswitch; /**< T switch settings. Select from @ref SWT_Const */ +}SWMatrixCfg_Type; + +/** HSTIA Configure */ +typedef struct +{ + uint32_t HstiaBias; /**< When select Vzero as bias, the related switch(VZERO2HSTIA) at LPDAC should be closed */ + uint32_t HstiaRtiaSel; /**< RTIA selection @ref HSTIARTIA_Const */ + uint32_t ExtRtia; /**< Value of external RTIA*/ + uint32_t HstiaCtia; /**< Set internal CTIA value from 1 to 32 pF */ + BoolFlag DiodeClose; /**< Close the switch for internal back to back diode */ + uint32_t HstiaDeRtia; /**< DE0 node RTIA selection @ref HSTIADERTIA_Const */ + uint32_t HstiaDeRload; /**< DE0 node Rload selection @ref HSTIADERLOAD_Const */ + uint32_t HstiaDe1Rtia; /**< (ADuCM355 only, ignored on AD594x)DE1 node RTIA selection @ref HSTIADERTIA_Const */ + uint32_t HstiaDe1Rload; /**< (ADuCM355 only)DE1 node Rload selection @ref HSTIADERLOAD_Const */ +}HSTIACfg_Type; + +/** HSDAC Configure */ +typedef struct +{ + uint32_t ExcitBufGain; /**< Select from EXCITBUFGAIN_2, EXCITBUFGAIN_0P25 */ + uint32_t HsDacGain; /**< Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + uint32_t HsDacUpdateRate; /**< Divider for DAC update. Available range is 7~255. */ +}HSDACCfg_Type; + +/** LPDAC Configure + * @note The LPDAC structure: + * @code + * Switch to select DAC output to Vzero and Vbias nodes. Vzero and Vbias can select from DAC6BIT and DAC12BIT output freely. + * LPDAC >DAC6BIT ---- Vzero LPDACVZERO_12BIT + * \--- Vbias LPDACVBIAS_6BIT + * >DAC12BIT---- Vzero LPDACVZERO_6BIT + * \--- Vbias LPDACVBIAS_12BIT + * Vzero/Vbias switch, controlled by @ref LPDACCfg_Type LpDacSW + * Vzero ------PIN + * \-----LPTIA LPDACSW_VZERO2LPTIA. LPTIA positive input + * \----HSTIA LPDACSW_VZERO2LPAMP. HSTIA positive input. Note, there is a MUX on HSTIA positive input pin to select the bias voltage between Vzero and 1.1V fixed internal reference. + * Vbias ------PIN LPDACSW_VBIAS2PIN + * \-----LPAMP LPDACSW_VBIAS2LPAMP positive input. The potential state amplifier input, or called LPAMP or PA(potential amplifier). + * @endcode +*/ +typedef struct +{ + uint32_t LpdacSel; /**< Selectr from LPDAC0 or LPDAC1. LPDAC1 is only available on ADuCM355. */ + uint32_t LpDacSrc; /**< LPDACSRC_MMR or LPDACSRC_WG. Note: HSDAC is always connects to WG. Disable HSDAC if there is need. */ + uint32_t LpDacVzeroMux; /**< Select which DAC output connects to Vzero. 6Bit or 12Bit DAC */ + uint32_t LpDacVbiasMux; /**< Select which DAC output connects to Vbias */ + uint32_t LpDacSW; /**< LPDAC switch set. Only available from Si2 */ + uint32_t LpDacRef; /**< Reference selection. Either internal 2.5V LPRef or AVDD. select from @ref LPDACREF_Const*/ + BoolFlag DataRst; /**< Keep Reset register REG_AFE_LPDACDAT0DATA */ + BoolFlag PowerEn; /**< Power up REG_AFE_LPDACDAT0 */ + uint16_t DacData12Bit; /**< Data for 12bit DAC */ + uint16_t DacData6Bit; /**< Data for 6bit DAC */ +}LPDACCfg_Type; + +/** + * Low power amplifiers(PA and TIA) +*/ +typedef struct +{ + uint32_t LpAmpSel; /**< Select from LPAMP0 and LPAMP1. LPAMP1 is only available on ADuCM355. */ + uint32_t LpTiaRf; /**< The one order RC filter resistor selection. Select from @ref LPTIARF_Const */ + uint32_t LpTiaRload; /**< The Rload resistor right in front of LPTIA negative input terminal. Select from @ref LPTIARLOAD_Const*/ + uint32_t LpTiaRtia; /**< LPTIA RTIA resistor selection. Set it to open(@ref LPTIARTIA_Const) when use external resistor. */ + uint32_t LpAmpPwrMod; /**< Power mode for LP PA and LPTIA */ + uint32_t LpTiaSW; /**< Set of switches, using macro LPTIASW() to close switch */ + BoolFlag LpPaPwrEn; /**< Enable(bTRUE) or disable(bFALSE) power of PA(potential amplifier) */ + BoolFlag LpTiaPwrEn; /**< Enable(bTRUE) or Disable(bFALSE) power of LPTIA amplifier */ +}LPAmpCfg_Type; + +/** + * @brief Trapezoid Generator parameters + * The definition of the Trapezoid waveform is shown below. Note the Delay and Slope are all in clock unit. + * @code + * + * DCLevel2 _________ + * / \ + * / \ + * DCLevel1 _____/ \______ + * | | | | | + * Delay1|S1|Delay2 |S2| Delay1 repeat... + * Where S1 is slope1 and S2 is slop2 + * @endcode + * The DAC update rate from Trapezoid generator is SystemClock/50. The default SystemClock + * is internal HFOSC 16MHz. So the update rate is 320kHz. + * The time parameter specifies in clock number. + * For example, if Delay1 is set to 10, S1 is set 20, the time for Delay1 period is 10/320kHz = 31.25us, + * and time for S1 period is 20/320kHz = 62.5us. +*/ +typedef struct +{ + uint32_t WGTrapzDCLevel1; /**< Trapezoid generator DC level1, this value is written directly to corresponding register */ + uint32_t WGTrapzDCLevel2; /**< DC level2, similar to DCLevel1 */ + uint32_t WGTrapzDelay1; /**< Trapezoid generator delay 1 */ + uint32_t WGTrapzDelay2; /**< Trapezoid generator delay 2 */ + uint32_t WGTrapzSlope1; /**< Trapezoid generator Slope 1 */ + uint32_t WGTrapzSlope2; /**< Trapezoid generator Slope 2 */ +}WGTrapzCfg_Type; + +/** + * Sin wave generator parameters +*/ +typedef struct +{ + uint32_t SinFreqWord; /**< Frequency word */ + uint32_t SinAmplitudeWord; /**< Amplitude word, range is 0 to 2047. Amplitude range is 0 to 800mV */ + uint32_t SinOffsetWord; /**< Offset word, range is -2048 to 2047. Offset voltage range is -800 to +800mV */ + uint32_t SinPhaseWord; /**< the start phase of sine wave. Use to tune start phase of signal. */ +}WGSinCfg_Type; + +/** + * Waveform generator configuration +*/ +typedef struct +{ + uint32_t WgType; /**< Select from WGTYPE_MMR, WGTYPE_SIN, WGTYPE_TRAPZ. HSDAC is always connected to WG. */ + BoolFlag GainCalEn; /**< Enable Gain calibration */ + BoolFlag OffsetCalEn; /**< Enable offset calibration */ + WGTrapzCfg_Type TrapzCfg; /**< Configure Trapezoid generator */ + WGSinCfg_Type SinCfg; /**< Configure Sine wave generator */ + uint32_t WgCode; /**< The 12bit data WG will move to DAC data register. */ +}WGCfg_Type; + +/** + * High speed loop configuration + * */ +typedef struct +{ + SWMatrixCfg_Type SWMatCfg; /**< switch matrix configuration. */ + HSDACCfg_Type HsDacCfg; /**< HSDAC configuration. */ + WGCfg_Type WgCfg; /**< Waveform generator configuration. */ + HSTIACfg_Type HsTiaCfg; /**< HSTIA configuration. */ +}HSLoopCfg_Type; + +/** + * Low power loop Configure + * */ +typedef struct +{ + LPDACCfg_Type LpDacCfg; /**< LPDAC configuration. @note Must select LPDAC0 or LPDAC1 in structure. */ + LPAmpCfg_Type LpAmpCfg; /**< LPAMP(LPTIA and PA) configuration. @note Must select LPAMP0 or LPAMP1 in structure. */ +}LPLoopCfg_Type; + +/** + * DSP Configure + * */ +typedef struct +{ + ADCBaseCfg_Type ADCBaseCfg; /**< ADC base configuration */ + ADCFilterCfg_Type ADCFilterCfg; /**< ADC filter configuration include SINC3/SINC2/Notch/Average(for DFT only) */ + ADCDigComp_Type ADCDigCompCfg; /**< ADC digital comparator */ + DFTCfg_Type DftCfg; /**< DFT configuration include data source, DFT number and Hanning Window */ + StatCfg_Type StatCfg; /**< Statistic block */ +}DSPCfg_Type; + +/** + * GPIO Configure + * */ +typedef struct +{ + uint32_t FuncSet; /**< AGP0 to AGP7 function sets */ + uint32_t OutputEnSet; /**< AGPIO_Pin0|AGPIO_Pin1|...|AGPIO_Pin7, Enable output of selected pins, disable other pins */ + uint32_t InputEnSet; /**< Enable input of selected pins, disable other pins */ + uint32_t PullEnSet; /**< Enable pull up or down on selected pin. disable other pins */ + uint32_t OutVal; /**< Value for GPIOOUT register */ +}AGPIOCfg_Type; + +/** + * FIFO configure +*/ +typedef struct +{ + BoolFlag FIFOEn; /**< Enable DATAFIFO. Disable FIFO will reset FIFO */ + uint32_t FIFOMode; /**< Stream mode or standard FIFO mode */ + uint32_t FIFOSize; /**< How to allocate the internal 6kB SRAM. Data FIFO and sequencer share all 6kB SRAM */ + uint32_t FIFOSrc; /**< Select which data source will be stored to FIFO */ + uint32_t FIFOThresh; /**< FIFO threshold value, 0 to 1023. Threshold can be used to generate interrupt so MCU can read back data before FIFO is full */ +}FIFOCfg_Type; + +/** + * Sequencer configure +*/ +typedef struct +{ + uint32_t SeqMemSize; /**< Sequencer memory size. SRAM is used by both FIFO and Sequencer. Make sure the total SRAM used is less than 6kB. */ + BoolFlag SeqEnable; /**< Enable sequencer. Only with valid trigger, sequencer can run */ + BoolFlag SeqBreakEn; /**< Do not use it */ + BoolFlag SeqIgnoreEn; /**< Do not use it */ + BoolFlag SeqCntCRCClr; /**< Clear sequencer count and CRC */ + uint32_t SeqWrTimer; /**< Set wait how much clocks after every commands executed */ +}SEQCfg_Type; + +/** + * Sequence info structure +*/ +typedef struct +{ + uint32_t SeqId; /**< The Sequence ID @ref SEQID_Const */ + uint32_t SeqRamAddr; /**< The start address that in AF5940 SRAM */ + uint32_t SeqLen; /**< Sequence length */ + BoolFlag WriteSRAM; /**< Write command to SRAM or not. */ + const uint32_t *pSeqCmd; /**< Pointer to the sequencer commands that stored in MCU */ +}SEQInfo_Type; + +typedef struct +{ + uint32_t PinSel; /**< Select which pin are going to be configured. @ref AGPIOPIN_Const */ + uint32_t SeqPinTrigMode; /**< The pin detect mode. Select from @ref SEQPINTRIGMODE_Const */ + BoolFlag bEnable; /**< Allow detected pin action to trigger corresponding sequence. */ +}SeqGpioTrig_Cfg; + +/** + * Wakeup Timer Configure + * */ +typedef struct +{ + uint32_t WuptEndSeq; /**< end sequence selection @ref WUPTENDSEQ_Const. Wupt will go back to slot A after this one is executed. */ + uint32_t WuptOrder[8]; /**< The 8 slots for WakeupTimer. Place @ref SEQID_Const to this array. */ + uint32_t SeqxSleepTime[4]; /**< Time before put AFE to sleep. 0 to 0x000f_ffff. We normally don't use this feature and it's disabled in @ref AD5940_Initialize */ + uint32_t SeqxWakeupTime[4]; /**< Time before Wakeup AFE. */ + BoolFlag WuptEn; /**< Timer enable. Once enabled, it starts to run. */ +}WUPTCfg_Type; + +/** + * Clock configure +*/ +typedef struct +{ + uint32_t SysClkSrc; /**< System clock source @ref SYSCLKSRC_Const */ + uint32_t ADCCLkSrc; /**< ADC clock source @ref ADCCLKSRC_Const */ + uint32_t SysClkDiv; /**< System clock divider. Use this to ensure System clock < 16MHz. */ + uint32_t ADCClkDiv; /**< ADC control clock divider. ADC core clock is @ADCCLkSrc, but control clock should be <16MHz. */ + BoolFlag HFOSCEn; /**< Enable internal 16MHz/32MHz HFOSC */ + BoolFlag HfOSC32MHzMode; /**< Enable internal HFOSC to output 32MHz */ + BoolFlag LFOSCEn; /**< Enable internal 32kHZ OSC */ + BoolFlag HFXTALEn; /**< Enable XTAL driver */ +}CLKCfg_Type; + +/** + * HSTIA internal RTIA calibration structure + * @note ADC filter settings and DFT should be configured properly based on signal frequency. +*/ +typedef struct +{ + float fFreq; /**< Calibration frequency */ + float fRcal; /**< Rcal resistor value in Ohm*/ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + + HSTIACfg_Type HsTiaCfg; /**< HSTIA configuration */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + DFTCfg_Type DftCfg; /**< DFT configuration. */ + uint32_t bPolarResult; /**< bTRUE-Polar coordinate:Return results in Magnitude and Phase. bFALSE-Cartesian coordinate: Return results in Real part and Imaginary Part */ +}HSRTIACal_Type; + +/** + * LPTIA internal RTIA calibration structure +*/ +typedef struct +{ + float fFreq; /**< Calibration frequency. Set it to 0.0 for DC calibration */ + float fRcal; /**< Rcal resistor value in Ohm*/ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + + uint32_t LpAmpSel; /**< Select from LPAMP0 and LPAMP1. LPAMP1 is only available on ADuCM355. */ + BoolFlag bWithCtia; /**< Connect external CTIA or not. */ + uint32_t LpTiaRtia; /**< LPTIA RTIA selection. */ + uint32_t LpAmpPwrMod; /**< Amplifiers power mode setting */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + DFTCfg_Type DftCfg; /**< DFT configuration */ + uint32_t bPolarResult; /**< bTRUE-Polar coordinate:Return results in Magnitude and Phase. bFALSE-Cartesian coordinate: Return results in Real part and Imaginary Part */ +}LPRTIACal_Type; + +/** + * HSDAC calibration structure. +*/ +typedef struct +{ + float fRcal; /**< Rcal resistor value in Ohm*/ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + + uint32_t AfePwrMode; /**< Calibrate DAC in High power mode */ + uint32_t ExcitBufGain; /**< Select from EXCITBUFGAIN_2, EXCITBUFGAIN_0P25 */ + uint32_t HsDacGain; /**< Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ +}HSDACCal_Type; + +/** + * LPDAC calibration structure. +*/ +typedef struct +{ + uint32_t LpdacSel; /**< Select from LPDAC0 and LPDAC1. LPDAC1 is ADuCM355 only. */ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + float ADCRefVolt; /**< ADC reference voltage. Default is 1.82V*/ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC2 OSR settings. */ + int32_t SettleTime10us; /**< Wait how much time after TIA is enabled? */ + int32_t TimeOut10us; /**< ADC converts signal need time. Specify the maximum time allowed. Timeout in 10us. negative number means wait no time. */ +}LPDACCal_Type; + +/** + * LPDAC parameters: LPDAC code to voltage transfer function. + * Voltage(mV) = kC2V_DACxB * Code + bC2V_DACxB; + * where x is 12 or 6 represent 12Bit DAC and 6Bit DAC. C2V means code to voltage. + * Code is the data register value for LPDAC. The equation gives real output voltage of LPDAC. + * Similarly, Code(LSB) = kV2C_DACxB * Voltage(mV) + bV2C_DACxB; + * + * Apparently, kV2C_DACxB = 1/kC2V_DACxB; + * bV2C_DACxB = -bC2V_DACxB/kC2V_DACxB; +*/ +typedef struct +{ + /* Code to voltage equation parameters */ + float kC2V_DAC12B; /**< the k factor of code to voltage(in mV) transfer function */ + float bC2V_DAC12B; /**< the offset of code to voltage transfer function. It's the voltage in mV when code is zero. */ + float kC2V_DAC6B; /**< the k factor for LPDAC 6 bit output. */ + float bC2V_DAC6B; /**< the offset for LPDAC 6 bit output. */ + /* Code to voltage equation parameters */ + float kV2C_DAC12B; /**< the k factor for converting voltage to code for LPDAC 12bit output. */ + float bV2C_DAC12B; /**< the offset for converting voltage to code for LPDAC 12bit output. */ + float kV2C_DAC6B; /**< the k factor for converting voltage to code for LPDAC 6bit output. */ + float bV2C_DAC6B; /**< the offset for converting voltage to code for LPDAC 6bit output. */ +}LPDACPara_Type; + +/** + * LFOSC frequency measure structure +*/ +typedef struct +{ + uint32_t CalSeqAddr; /**< Sequence start address */ + float CalDuration; /**< Time can be used for calibration in unit of ms. Recommend to use tens of millisecond like 10ms */ + float SystemClkFreq; /**< System clock frequency. */ +}LFOSCMeasure_Type; + +/** + * ADC PGA calibration type +*/ +typedef struct +{ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + float VRef1p82; /**< The real voltage of 1.82 reference. Unit is volt. */ + float VRef1p11; /**< The real voltage of 1.1 reference. Unit is volt. */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCPga; /**< Which PGA gain we are going to calibrate? */ + uint32_t PGACalType; /**< Calibrate gain of offset or gain+offset? */ + int32_t TimeOut10us; /**< Timeout in 10us. -1 means no time-out*/ +}ADCPGACal_Type; + +/** + * LPTIA Offset calibration type +*/ +typedef struct +{ + uint32_t LpAmpSel; /**< Select from LPAMP0 and LPAMP1. LPAMP1 is only available on ADuCM355. */ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCPga; /**< PGA Gain selection */ + uint32_t DacData12Bit; /**< 12Bit DAC data */ + uint32_t DacData6Bit; /**< 6Bit DAC data */ + uint32_t LpDacVzeroMux; /**< Vzero is used as LPTIA bias voltage, select 12Bit/6Bit DAC */ + uint32_t LpAmpPwrMod; /**< LP amplifiers power mode, select from LPAMPPWR_NORM, LPAMPPWR_BOOSTn*/ + uint32_t LpTiaSW; /**< Switch configuration for LPTIA. Normally for SW(5) and SW(9).*/ + uint32_t LpTiaRtia; /**< LPTIA RTIA resistor selection. */ + int32_t SettleTime10us; /**< Wait how much time after TIA is enabled? */ + int32_t TimeOut10us; /**< ADC converts signal need time. Specify the maximum time allowed. Timeout in 10us. negative number means wait no time. */ +}LPTIAOffsetCal_Type; + +/** + * Structure for calculating how much system clocks needed for specified number of data +*/ +typedef struct +{ + uint32_t DataType; /**< The final data output selection. @ref DATATYPE_Const */ + uint32_t DataCount; /**< How many data you want. */ + uint32_t ADCSinc3Osr; /**< ADC SINC3 filter OSR setting */ + uint32_t ADCSinc2Osr; /**< ADC SINC2 filter OSR setting */ + uint32_t ADCAvgNum; /**< Average number for DFT engine. Only used when data type is DATATYPE_DFT and DftSrc is DFTSRC_AVG */ + uint32_t DftSrc; /**< The DFT source. Only used when data type is DATATYPE_DFT */ + uint8_t ADCRate; /**< ADCRate @ref ADCRATE_Const. Only used when data type is DATATYPE_NOTCH */ + BoolFlag BpNotch; /**< Bypass notch filter or not. Only used when data type is DATATYPE_DFT and DftSrc is DFTSRC_SINC2NOTCH */ + float RatioSys2AdcClk; /**< Ratio of system clock to ADC clock frequency */ +}ClksCalInfo_Type; + +/** + * Software controlled Sweep Function + * */ +typedef struct +{ + BoolFlag SweepEn; /**< Software can automatically sweep frequency from following parameters. Set value to 1 to enable it. */ + float SweepStart; /**< Sweep start frequency. Software will go back to the start frequency when it reaches SWEEP_STOP */ + float SweepStop; /**< Sweep end frequency. */ + uint32_t SweepPoints; /**< How many points from START to STOP frequency */ + BoolFlag SweepLog; /**< The step is linear or logarithmic. 0: Linear, 1: Logarithmic*/ + uint32_t SweepIndex; /**< Current position of sweep */ +}SoftSweepCfg_Type; + +/** + * Impedance result in Polar coordinate +*/ +typedef struct +{ + float Magnitude; /**< The magnitude in polar coordinate */ + float Phase; /**< The phase in polar coordinate */ +}fImpPol_Type; //Polar + +/** + * Impedance result in Cartesian coordinate +*/ +typedef struct +{ + float Real; /**< The real part in Cartesian coordinate */ + float Image; /**< The imaginary in Cartesian coordinate */ +}fImpCar_Type; //Cartesian + +/** + * int32_t type Impedance result in Cartesian coordinate +*/ +typedef struct +{ + int32_t Real; /**< The real part in Cartesian coordinate */ + int32_t Image; /**< The real imaginary in Cartesian coordinate */ +}iImpCar_Type; + +/** + * FreqParams_Type - Structure to store optimum filter settings +*/ +typedef struct +{ + BoolFlag HighPwrMode; + uint32_t DftNum; + uint32_t DftSrc; + uint32_t ADCSinc3Osr; + uint32_t ADCSinc2Osr; + uint32_t NumClks; +}FreqParams_Type; + +/** + * @} TypeDefinitions +*/ + +/** + * @defgroup Exported_Functions + * @{ +*/ +/* 1. Basic SPI functions */ +void AD5940_WriteReg(uint16_t RegAddr, uint32_t RegData); +uint32_t AD5940_ReadReg(uint16_t RegAddr); +void AD5940_FIFORd(uint32_t *pBuffer,uint32_t uiReadCount); + +/* 2. AD5940 Top Control functions */ +void AD5940_Initialize(void); /* Call this function firstly once AD5940 power on or come from soft reset */ +void AD5940_AFECtrlS(uint32_t AfeCtrlSet, BoolFlag State); +AD5940Err AD5940_LPModeCtrlS(uint32_t EnSet); +void AD5940_AFEPwrBW(uint32_t AfePwr, uint32_t AfeBw); /* AFE power mode and system bandwidth control */ +void AD5940_REFCfgS(AFERefCfg_Type *pBufCfg); + +/* 3. High_Speed_Loop Functions */ +void AD5940_HSLoopCfgS(HSLoopCfg_Type *pHsLoopCfg); +void AD5940_SWMatrixCfgS(SWMatrixCfg_Type *pSwMatrix); +void AD5940_HSDacCfgS(HSDACCfg_Type *pHsDacCfg); +AD5940Err AD5940_HSTIACfgS(HSTIACfg_Type *pHsTiaCfg); +void AD5940_HSRTIACfgS(uint32_t HSTIARtia); +void __AD5940_SetDExRTIA(uint32_t DExPin, uint32_t DeRtia, uint32_t DeRload); + +/* 4. Low_Power_Loop Functions*/ +void AD5940_LPLoopCfgS(LPLoopCfg_Type *pLpLoopCfg); +void AD5940_LPDACCfgS(LPDACCfg_Type *pLpDacCfg); +//void AD5940_LPDACWriteS(uint16_t Data12Bit, uint8_t Data6Bit); +void AD5940_LPDAC0WriteS(uint16_t Data12Bit, uint8_t Data6Bit); +void AD5940_LPDAC1WriteS(uint16_t Data12Bit, uint8_t Data6Bit); +void AD5940_LPAMPCfgS(LPAmpCfg_Type *pLpAmpCfg); + +/* 5. DSP_Block_Functions */ +void AD5940_DSPCfgS(DSPCfg_Type *pDSPCfg); +uint32_t AD5940_ReadAfeResult(uint32_t AfeResultSel); +/* 5.1 ADC Block */ +void AD5940_ADCBaseCfgS(ADCBaseCfg_Type *pADCInit); +void AD5940_ADCFilterCfgS(ADCFilterCfg_Type *pFiltCfg); +void AD5940_ADCPowerCtrlS(BoolFlag State); +void AD5940_ADCConvtCtrlS(BoolFlag State); +void AD5940_ADCMuxCfgS(uint32_t ADCMuxP, uint32_t ADCMuxN); +void AD5940_ADCDigCompCfgS(ADCDigComp_Type *pCompCfg); +void AD5940_StatisticCfgS(StatCfg_Type *pStatCfg); +void AD5940_ADCRepeatCfgS(uint32_t Number); +void AD5940_DFTCfgS(DFTCfg_Type *pDftCfg); +/* 5.2 Waveform Generator Block */ +void AD5940_WGCfgS(WGCfg_Type *pWGInit); +AD5940Err AD5940_WGDACCodeS(uint32_t code); /* Directly write DAC Code */ +void AD5940_WGFreqCtrlS(float SinFreqHz, float WGClock); +uint32_t AD5940_WGFreqWordCal(float SinFreqHz, float WGClock); +//uint32_t AD5940_WGAmpWordCal(float Amp, BoolFlag DacGain, BoolFlag ExcitGain); + +/* 6. Sequencer_FIFO */ +void AD5940_FIFOCfg(FIFOCfg_Type *pFifoCfg); +AD5940Err AD5940_FIFOGetCfg(FIFOCfg_Type *pFifoCfg); /* Read back current configuration */ +void AD5940_FIFOCtrlS(uint32_t FifoSrc, BoolFlag FifoEn); /* Configure FIFO data source. And disable/enable it.*/ +void AD5940_FIFOThrshSet(uint32_t FIFOThresh); +uint32_t AD5940_FIFOGetCnt(void); /* Get current FIFO count */ +void AD5940_SEQCfg(SEQCfg_Type *pSeqCfg); +AD5940Err AD5940_SEQGetCfg(SEQCfg_Type *pSeqCfg); /* Read back current configuration */ +void AD5940_SEQCtrlS(BoolFlag SeqEn); +void AD5940_SEQHaltS(void); +void AD5940_SEQMmrTrig(uint32_t SeqId); /* Manually trigger sequence */ +void AD5940_SEQCmdWrite(uint32_t StartAddr, const uint32_t *pCommand, uint32_t CmdCnt); +void AD5940_SEQInfoCfg(SEQInfo_Type *pSeq); +AD5940Err AD5940_SEQInfoGet(uint32_t SeqId, SEQInfo_Type *pSeqInfo); +void AD5940_SEQGpioCtrlS(uint32_t GpioSet); /* Sequencer can control GPIO0~7 if the GPIO function is set to SYNC */ +uint32_t AD5940_SEQTimeOutRd(void); /* Read back current sequence time out value */ +AD5940Err AD5940_SEQGpioTrigCfg(SeqGpioTrig_Cfg *pSeqGpioTrigCfg); +void AD5940_WUPTCfg(WUPTCfg_Type *pWuptCfg); +void AD5940_WUPTCtrl(BoolFlag Enable); /* Enable or disable Wakeup timer */ +AD5940Err AD5940_WUPTTime(uint32_t SeqId, uint32_t SleepTime, uint32_t WakeupTime); + +/* 7. MISC_Block */ +/* 7.1 Clock system */ +void AD5940_CLKCfg(CLKCfg_Type *pClkCfg); +void AD5940_HFOSC32MHzCtrl(BoolFlag Mode32MHz); +void AD5940_HPModeEn(BoolFlag Enable); /* Switch system clocks to high power mode for EIS >80kHz)*/ +/* 7.2 AFE Interrupt */ +void AD5940_INTCCfg(uint32_t AfeIntcSel, uint32_t AFEIntSrc, BoolFlag State); +uint32_t AD5940_INTCGetCfg(uint32_t AfeIntcSel); +void AD5940_INTCClrFlag(uint32_t AfeIntSrcSel); +BoolFlag AD5940_INTCTestFlag(uint32_t AfeIntcSel, uint32_t AfeIntSrcSel); /* Check if selected interrupt happened */ +uint32_t AD5940_INTCGetFlag(uint32_t AfeIntcSel); /* Get current INTC interrupt flag */ +/* 7.3 GPIO */ +void AD5940_AGPIOCfg(AGPIOCfg_Type *pAgpioCfg); +void AD5940_AGPIOFuncCfg(uint32_t uiCfgSet); +void AD5940_AGPIOOen(uint32_t uiPinSet); +void AD5940_AGPIOIen(uint32_t uiPinSet); +uint32_t AD5940_AGPIOIn(void); +void AD5940_AGPIOPen(uint32_t uiPinSet); +void AD5940_AGPIOSet(uint32_t uiPinSet); +void AD5940_AGPIOClr(uint32_t uiPinSet); +void AD5940_AGPIOToggle(uint32_t uiPinSet); + +/* 7.4 LPMODE */ +AD5940Err AD5940_LPModeEnS(BoolFlag LPModeEn); /* Enable LP mode or disable it. */ +void AD5940_LPModeClkS(uint32_t LPModeClk); +void AD5940_ADCRepeatCfg(uint32_t Number); +/* 7.5 Power */ +void AD5940_SleepKeyCtrlS(uint32_t SlpKey); /* enter the correct key to allow AFE to enter sleep mode */ +void AD5940_EnterSleepS(void); /* Put AFE to hibernate/sleep mode and keep LP loop as the default settings. */ +void AD5940_ShutDownS(void); /* Unlock the key, turn off LP loop and enter sleep/hibernate mode */ +uint32_t AD5940_WakeUp(int32_t TryCount); /* Try to wakeup AFE by read register */ +uint32_t AD5940_GetADIID(void); /* Read ADIID */ +uint32_t AD5940_GetChipID(void); /* Read Chip ID */ +AD5940Err AD5940_SoftRst(void); +void AD5940_HWReset(void); /* Do hardware reset to AD5940 using RESET pin */ +/* Calibration functions */ +/* 8. Calibration */ +AD5940Err AD5940_ADCPGACal(ADCPGACal_Type *ADCPGACal); +AD5940Err AD5940_LPDACCal(LPDACCal_Type *pCalCfg, LPDACPara_Type *pResult); +AD5940Err AD5940_LPTIAOffsetCal(LPTIAOffsetCal_Type *pLPTIAOffsetCal); +AD5940Err AD5940_HSRtiaCal(HSRTIACal_Type *pCalCfg, void *pResult); +AD5940Err AD5940_HSDACCal(HSDACCal_Type *pCalCfg); +AD5940Err AD5940_LPRtiaCal(LPRTIACal_Type *pCalCfg, void *pResult); +AD5940Err AD5940_LFOSCMeasure(LFOSCMeasure_Type *pCfg, float *pFreq); +//void AD5940_LFOSCTrim(uint32_t TrimValue); /* TrimValue: 0 to 15 */ +//void AD5940_HFOSC16MHzTrim(uint32_t TrimValue); +//void AD5940_HFOSC32MHzTrim(uint32_t TrimValue); + +/* 9. Pure software functions. Functions with no register access. These functions are helpers */ + /* Sequence Generator */ +void AD5940_SEQGenInit(uint32_t *pBuffer, uint32_t BufferSize);/* Initialize sequence generator workspace */ +void AD5940_SEQGenCtrl(BoolFlag bFlag); /* Enable or disable sequence generator */ +void AD5940_SEQGenInsert(uint32_t CmdWord); /* Manually insert a sequence command */ +AD5940Err AD5940_SEQGenFetchSeq(const uint32_t **ppSeqCmd, uint32_t *pSeqCount); /* Fetch generated sequence and start a new sequence */ +void AD5940_ClksCalculate(ClksCalInfo_Type *pFilterInfo, uint32_t *pClocks); +uint32_t AD5940_SEQCycleTime(void); +void AD5940_SweepNext(SoftSweepCfg_Type *pSweepCfg, float *pNextFreq); +void AD5940_StructInit(void *pStruct, uint32_t StructSize); +float AD5940_ADCCode2Volt(uint32_t code, uint32_t ADCPga, float VRef1p82); /* Calculate ADC code to voltage */ +BoolFlag AD5940_Notch50HzAvailable(ADCFilterCfg_Type *pFilterInfo, uint8_t *dl); +BoolFlag AD5940_Notch60HzAvailable(ADCFilterCfg_Type *pFilterInfo, uint8_t *dl); +fImpCar_Type AD5940_ComplexDivFloat(fImpCar_Type *a, fImpCar_Type *b); +fImpCar_Type AD5940_ComplexMulFloat(fImpCar_Type *a, fImpCar_Type *b); +fImpCar_Type AD5940_ComplexAddFloat(fImpCar_Type *a, fImpCar_Type *b); +fImpCar_Type AD5940_ComplexSubFloat(fImpCar_Type *a, fImpCar_Type *b); + +fImpCar_Type AD5940_ComplexDivInt(iImpCar_Type *a, iImpCar_Type *b); +fImpCar_Type AD5940_ComplexMulInt(iImpCar_Type *a, iImpCar_Type *b); +float AD5940_ComplexMag(fImpCar_Type *a); +float AD5940_ComplexPhase(fImpCar_Type *a); +FreqParams_Type AD5940_GetFreqParameters(float freq); +/** + * @} Exported_Functions +*/ + +/** + * @defgroup Library_Interface + * The functions user should provide for specific MCU platform + * @{ +*/ +void AD5940_CsClr(void); +void AD5940_CsSet(void); +void AD5940_RstClr(void); +void AD5940_RstSet(void); +void AD5940_Delay10us(uint32_t time); +/* (Not used for now.)AD5940 has 8 GPIOs, some of them are connected to MCU. MCU can set or read the status of these pins. */ +void AD5940_MCUGpioWrite(uint32_t data); /* */ +uint32_t AD5940_MCUGpioRead(uint32_t); +void AD5940_MCUGpioCtrl(uint32_t, BoolFlag); +void AD5940_ReadWriteNBytes(unsigned char *pSendBuffer,unsigned char *pRecvBuff,unsigned long length); +/* Below functions are frequently used in example code but not necessary for library */ +uint32_t AD5940_GetMCUIntFlag(void); +uint32_t AD5940_ClrMCUIntFlag(void); +uint32_t AD5940_MCUResourceInit(void *pCfg); +/** + * @} Library_Interface +*/ + + +/** + * @} AD5940_Library + */ + +#endif + + +#ifdef __cplusplus +} +#endif diff --git a/examples/rp2040_port/ad5940.h.shortlist.md b/examples/rp2040_port/ad5940.h.shortlist.md new file mode 100644 index 0000000..9ff53a4 --- /dev/null +++ b/examples/rp2040_port/ad5940.h.shortlist.md @@ -0,0 +1,415 @@ +# Call Graph: ad5940 + +## Common Infrastructure +> Functions called > 5 times. Shown once here. + +### AD5940_ReadAfeResult +└── AD5940_ReadAfeResult + └── #FF4500 **AD5940_ReadReg** ->> + +### __AD5940_TakeMeasurement +└── #00FFFF **__AD5940_TakeMeasurement** + ├── #008000 **AD5940_AFECtrlS** ->> + ├── #FFD700 **AD5940_Delay10us** ->> + ├── AD5940_INTCClrFlag ->> + ├── AD5940_INTCTestFlag ->> + └── AD5940_ReadAfeResult ->> + +### AD5940_HSLoopCfgS +└── AD5940_HSLoopCfgS + ├── AD5940_HSDacCfgS + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_HSTIACfgS + │ ├── #FF0000 **AD5940_WriteReg** ->> + │ └── __AD5940_SetDExRTIA + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_SWMatrixCfgS + │ └── #FF0000 **AD5940_WriteReg** ->> + └── AD5940_WGCfgS + └── #FF0000 **AD5940_WriteReg** ->> + +### AD5940_ADCFilterCfgS +└── AD5940_ADCFilterCfgS + ├── #008000 **AD5940_AFECtrlS** ->> + ├── #FF4500 **AD5940_ReadReg** ->> + └── #FF0000 **AD5940_WriteReg** ->> + +### AD5940_ReadReg +└── #FF4500 **AD5940_ReadReg** + ├── AD5940_D2DReadReg + ├── AD5940_SEQReadReg + │ ├── AD5940_SEQGenGetRegDefault + │ │ ├── AD5940_D2DReadReg + │ │ └── AD5940_SPIReadReg + │ │ ├── AD5940_CsClr ->> + │ │ ├── AD5940_CsSet ->> + │ │ ├── AD5940_ReadWrite16B ->> + │ │ ├── AD5940_ReadWrite32B ->> + │ │ └── AD5940_ReadWrite8B ->> + │ ├── AD5940_SEQGenSearchReg + │ └── AD5940_SEQRegInfoInsert + └── AD5940_SPIReadReg + ├── AD5940_CsClr ->> + ├── AD5940_CsSet ->> + ├── AD5940_ReadWrite16B ->> + ├── AD5940_ReadWrite32B ->> + └── AD5940_ReadWrite8B ->> + +### AD5940_WriteReg +└── #FF0000 **AD5940_WriteReg** + ├── AD5940_D2DWriteReg + ├── AD5940_SEQWriteReg + │ ├── AD5940_SEQGenInsert + │ ├── AD5940_SEQGenSearchReg + │ └── AD5940_SEQRegInfoInsert + └── AD5940_SPIWriteReg + ├── AD5940_CsClr ->> + ├── AD5940_CsSet ->> + ├── AD5940_ReadWrite16B ->> + ├── AD5940_ReadWrite32B ->> + └── AD5940_ReadWrite8B ->> + +### AD5940_ADCMuxCfgS +└── AD5940_ADCMuxCfgS + ├── #FF4500 **AD5940_ReadReg** ->> + └── #FF0000 **AD5940_WriteReg** ->> + +### AD5940_INTCGetCfg +└── AD5940_INTCGetCfg + └── #FF4500 **AD5940_ReadReg** ->> + +### AD5940_AFECtrlS +└── #008000 **AD5940_AFECtrlS** + ├── #FF4500 **AD5940_ReadReg** ->> + └── #FF0000 **AD5940_WriteReg** ->> + +### AD5940_INTCCfg +└── #0000FF **AD5940_INTCCfg** + ├── #FF4500 **AD5940_ReadReg** ->> + └── #FF0000 **AD5940_WriteReg** ->> + +### AD5940_ReadWrite16B +└── AD5940_ReadWrite16B + └── AD5940_ReadWriteNBytes + +### AD5940_ReadWrite8B +└── AD5940_ReadWrite8B + └── AD5940_ReadWriteNBytes + +### __AD5940_ReferenceON +└── __AD5940_ReferenceON + └── AD5940_REFCfgS + ├── #FF4500 **AD5940_ReadReg** ->> + └── #FF0000 **AD5940_WriteReg** ->> + +### AD5940_INTCTestFlag +└── AD5940_INTCTestFlag + └── #FF4500 **AD5940_ReadReg** ->> + +### AD5940_INTCClrFlag +└── AD5940_INTCClrFlag + └── #FF0000 **AD5940_WriteReg** ->> + +### AD5940_ADCBaseCfgS +└── #8B00FF **AD5940_ADCBaseCfgS** + └── #FF0000 **AD5940_WriteReg** ->> + +### AD5940_ReadWrite32B +└── AD5940_ReadWrite32B + └── AD5940_ReadWriteNBytes + +## Execution Tree +└── AD5940_ADCPGACal + ├── #8B00FF **AD5940_ADCBaseCfgS** ->> + ├── #008000 **AD5940_AFECtrlS** ->> + ├── #FFD700 **AD5940_Delay10us** ->> + ├── #0000FF **AD5940_INTCCfg** ->> + ├── #FF4500 **AD5940_ReadReg** ->> + ├── #FF0000 **AD5940_WriteReg** ->> + ├── #00FFFF **__AD5940_TakeMeasurement** ->> + ├── AD5940_ADCConvtCtrlS + │ ├── #FF4500 **AD5940_ReadReg** ->> + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_ADCFilterCfgS ->> + ├── AD5940_HSLoopCfgS ->> + ├── AD5940_INTCGetCfg ->> + └── __AD5940_ReferenceON ->> +└── AD5940_ADCPowerCtrlS + ├── #FF4500 **AD5940_ReadReg** ->> + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_ADCRepeatCfgS + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_AGPIOCfg + ├── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_AGPIOFuncCfg + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_AGPIOIen + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_AGPIOOen + │ └── #FF0000 **AD5940_WriteReg** ->> + └── AD5940_AGPIOPen + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_AGPIOClr + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_AGPIOIn + └── #FF4500 **AD5940_ReadReg** ->> +└── AD5940_AGPIOSet + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_AGPIOToggle + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_ClksCalculate + ├── AD5940_Notch50HzAvailable + │ └── _is_value_in_table ->> + └── AD5940_Notch60HzAvailable + └── _is_value_in_table ->> +└── AD5940_FIFOCfg + ├── #FF4500 **AD5940_ReadReg** ->> + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_FIFOCtrlS + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_FIFOGetCfg + └── #FF4500 **AD5940_ReadReg** ->> +└── AD5940_FIFOGetCnt + └── #FF4500 **AD5940_ReadReg** ->> +└── AD5940_FIFORd + ├── AD5940_CsClr ->> + ├── AD5940_CsSet ->> + ├── AD5940_ReadWrite16B ->> + ├── AD5940_ReadWrite32B ->> + └── AD5940_ReadWrite8B ->> +└── AD5940_FIFOThrshSet + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_GetADIID + └── #FF4500 **AD5940_ReadReg** ->> +└── AD5940_GetChipID + └── #FF4500 **AD5940_ReadReg** ->> +└── AD5940_HPModeEn + ├── #FF4500 **AD5940_ReadReg** ->> + ├── AD5940_AFEPwrBW + │ └── #FF0000 **AD5940_WriteReg** ->> + └── AD5940_CLKCfg + ├── #FFD700 **AD5940_Delay10us** ->> + ├── #FF4500 **AD5940_ReadReg** ->> + ├── #FF0000 **AD5940_WriteReg** ->> + └── AD5940_HFOSC32MHzCtrl + ├── #FF4500 **AD5940_ReadReg** ->> + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_HSDACCal + ├── #8B00FF **AD5940_ADCBaseCfgS** ->> + ├── #008000 **AD5940_AFECtrlS** ->> + ├── #FFD700 **AD5940_Delay10us** ->> + ├── #0000FF **AD5940_INTCCfg** ->> + ├── #FF0000 **AD5940_WriteReg** ->> + ├── #00FFFF **__AD5940_TakeMeasurement** ->> + ├── AD5940_ADCCode2Volt + ├── AD5940_ADCConvtCtrlS + │ ├── #FF4500 **AD5940_ReadReg** ->> + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_ADCFilterCfgS ->> + ├── AD5940_HSLoopCfgS ->> + ├── AD5940_LPLoopCfgS + │ ├── AD5940_LPAMPCfgS + │ │ └── #FF0000 **AD5940_WriteReg** ->> + │ └── AD5940_LPDACCfgS + │ ├── #FF0000 **AD5940_WriteReg** ->> + │ ├── AD5940_LPDAC0WriteS + │ │ └── #FF0000 **AD5940_WriteReg** ->> + │ └── AD5940_LPDAC1WriteS + │ └── #FF0000 **AD5940_WriteReg** ->> + └── __AD5940_ReferenceON ->> +└── AD5940_HSRTIACfgS + ├── #FF4500 **AD5940_ReadReg** ->> + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_HSRtiaCal + ├── #008000 **AD5940_AFECtrlS** ->> + ├── #FFD700 **AD5940_Delay10us** ->> + ├── #0000FF **AD5940_INTCCfg** ->> + ├── AD5940_ADCMuxCfgS ->> + ├── AD5940_ComplexDivInt + ├── AD5940_ComplexMag + ├── AD5940_ComplexPhase + ├── AD5940_DSPCfgS + │ ├── #8B00FF **AD5940_ADCBaseCfgS** ->> + │ ├── AD5940_ADCDigCompCfgS + │ │ └── #FF0000 **AD5940_WriteReg** ->> + │ ├── AD5940_ADCFilterCfgS ->> + │ ├── AD5940_DFTCfgS + │ │ ├── #FF4500 **AD5940_ReadReg** ->> + │ │ └── #FF0000 **AD5940_WriteReg** ->> + │ └── AD5940_StatisticCfgS + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_HSLoopCfgS ->> + ├── AD5940_INTCClrFlag ->> + ├── AD5940_INTCGetCfg ->> + ├── AD5940_INTCTestFlag ->> + ├── AD5940_REFCfgS + │ ├── #FF4500 **AD5940_ReadReg** ->> + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_ReadAfeResult ->> + ├── AD5940_StructInit ->> + └── AD5940_WGFreqWordCal +└── AD5940_HWReset + ├── #FFD700 **AD5940_Delay10us** ->> + ├── AD5940_RstClr + └── AD5940_RstSet +└── AD5940_INTCGetFlag + └── #FF4500 **AD5940_ReadReg** ->> +└── AD5940_Initialize + ├── #FF4500 **AD5940_ReadReg** ->> + ├── #FF0000 **AD5940_WriteReg** ->> + └── AD5940_CsSet ->> +└── AD5940_LFOSCMeasure + ├── #0000FF **AD5940_INTCCfg** ->> + ├── AD5940_INTCClrFlag ->> + ├── AD5940_INTCGetCfg ->> + ├── AD5940_INTCTestFlag ->> + ├── AD5940_SEQCfg + │ ├── #FF4500 **AD5940_ReadReg** ->> + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_SEQCtrlS + │ ├── #FF4500 **AD5940_ReadReg** ->> + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_SEQGetCfg + │ └── #FF4500 **AD5940_ReadReg** ->> + ├── AD5940_SEQInfoCfg + │ ├── #FF0000 **AD5940_WriteReg** ->> + │ └── AD5940_SEQCmdWrite + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_SEQTimeOutRd + │ └── #FF4500 **AD5940_ReadReg** ->> + ├── AD5940_WUPTCfg + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_WUPTCtrl + │ ├── #FF4500 **AD5940_ReadReg** ->> + │ └── #FF0000 **AD5940_WriteReg** ->> + └── AD5940_WUPTTime + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_LPDACCal + ├── #8B00FF **AD5940_ADCBaseCfgS** ->> + ├── #008000 **AD5940_AFECtrlS** ->> + ├── #FFD700 **AD5940_Delay10us** ->> + ├── #0000FF **AD5940_INTCCfg** ->> + ├── #00FFFF **__AD5940_TakeMeasurement** ->> + ├── AD5940_ADCConvtCtrlS + │ ├── #FF4500 **AD5940_ReadReg** ->> + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_ADCFilterCfgS ->> + ├── AD5940_ADCMuxCfgS ->> + ├── AD5940_INTCGetCfg ->> + ├── AD5940_LPDACCfgS + │ ├── #FF0000 **AD5940_WriteReg** ->> + │ ├── AD5940_LPDAC0WriteS + │ │ └── #FF0000 **AD5940_WriteReg** ->> + │ └── AD5940_LPDAC1WriteS + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_LPDACWriteS + │ └── #FF0000 **AD5940_WriteReg** ->> + └── __AD5940_ReferenceON ->> +└── AD5940_LPModeClkS + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_LPModeCtrlS + ├── #FF4500 **AD5940_ReadReg** ->> + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_LPModeEnS + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_LPRtiaCal + ├── #8B00FF **AD5940_ADCBaseCfgS** ->> + ├── #008000 **AD5940_AFECtrlS** ->> + ├── #FFD700 **AD5940_Delay10us** ->> + ├── #0000FF **AD5940_INTCCfg** ->> + ├── #FF4500 **AD5940_ReadReg** ->> + ├── #FF0000 **AD5940_WriteReg** ->> + ├── #00FFFF **__AD5940_TakeMeasurement** ->> + ├── AD5940_ComplexDivInt + ├── AD5940_ComplexMag + ├── AD5940_ComplexPhase + ├── AD5940_DSPCfgS + │ ├── #8B00FF **AD5940_ADCBaseCfgS** ->> + │ ├── AD5940_ADCDigCompCfgS + │ │ └── #FF0000 **AD5940_WriteReg** ->> + │ ├── AD5940_ADCFilterCfgS ->> + │ ├── AD5940_DFTCfgS + │ │ ├── #FF4500 **AD5940_ReadReg** ->> + │ │ └── #FF0000 **AD5940_WriteReg** ->> + │ └── AD5940_StatisticCfgS + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_HSLoopCfgS ->> + ├── AD5940_INTCClrFlag ->> + ├── AD5940_INTCGetCfg ->> + ├── AD5940_INTCTestFlag ->> + ├── AD5940_LPLoopCfgS + │ ├── AD5940_LPAMPCfgS + │ │ └── #FF0000 **AD5940_WriteReg** ->> + │ └── AD5940_LPDACCfgS + │ ├── #FF0000 **AD5940_WriteReg** ->> + │ ├── AD5940_LPDAC0WriteS + │ │ └── #FF0000 **AD5940_WriteReg** ->> + │ └── AD5940_LPDAC1WriteS + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_ReadAfeResult ->> + ├── AD5940_SWMatrixCfgS + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_StructInit ->> + ├── AD5940_WGDACCodeS + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_WGFreqWordCal + └── __AD5940_ReferenceON ->> +└── AD5940_LPTIAOffsetCal + ├── #8B00FF **AD5940_ADCBaseCfgS** ->> + ├── #008000 **AD5940_AFECtrlS** ->> + ├── #FFD700 **AD5940_Delay10us** ->> + ├── #0000FF **AD5940_INTCCfg** ->> + ├── #FF0000 **AD5940_WriteReg** ->> + ├── #00FFFF **__AD5940_TakeMeasurement** ->> + ├── AD5940_ADCConvtCtrlS + │ ├── #FF4500 **AD5940_ReadReg** ->> + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_ADCFilterCfgS ->> + ├── AD5940_INTCGetCfg ->> + ├── AD5940_LPLoopCfgS + │ ├── AD5940_LPAMPCfgS + │ │ └── #FF0000 **AD5940_WriteReg** ->> + │ └── AD5940_LPDACCfgS + │ ├── #FF0000 **AD5940_WriteReg** ->> + │ ├── AD5940_LPDAC0WriteS + │ │ └── #FF0000 **AD5940_WriteReg** ->> + │ └── AD5940_LPDAC1WriteS + │ └── #FF0000 **AD5940_WriteReg** ->> + └── __AD5940_ReferenceON ->> +└── AD5940_SEQGpioCtrlS + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_SEQGpioTrigCfg + ├── #FF4500 **AD5940_ReadReg** ->> + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_SEQHaltS + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_SEQInfoGet + └── #FF4500 **AD5940_ReadReg** ->> +└── AD5940_SEQMmrTrig + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_ShutDownS + ├── AD5940_EnterSleepS + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_LPLoopCfgS + │ ├── AD5940_LPAMPCfgS + │ │ └── #FF0000 **AD5940_WriteReg** ->> + │ └── AD5940_LPDACCfgS + │ ├── #FF0000 **AD5940_WriteReg** ->> + │ ├── AD5940_LPDAC0WriteS + │ │ └── #FF0000 **AD5940_WriteReg** ->> + │ └── AD5940_LPDAC1WriteS + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_REFCfgS + │ ├── #FF4500 **AD5940_ReadReg** ->> + │ └── #FF0000 **AD5940_WriteReg** ->> + ├── AD5940_SleepKeyCtrlS + │ └── #FF0000 **AD5940_WriteReg** ->> + └── AD5940_StructInit ->> +└── AD5940_SoftRst + ├── #FFD700 **AD5940_Delay10us** ->> + └── #FF0000 **AD5940_WriteReg** ->> +└── AD5940_WGFreqCtrlS + ├── #FF0000 **AD5940_WriteReg** ->> + └── AD5940_WGFreqWordCal +└── AD5940_WakeUp + └── #FF4500 **AD5940_ReadReg** ->> diff --git a/examples/rp2040_port/build.sh b/examples/rp2040_port/build.sh new file mode 100755 index 0000000..2d88719 --- /dev/null +++ b/examples/rp2040_port/build.sh @@ -0,0 +1,6 @@ +#!/bin/bash +rm -rf build +mkdir build +cd build +cmake .. +make -j4 diff --git a/examples/rp2040_port/host/.gitignore b/examples/rp2040_port/host/.gitignore new file mode 100644 index 0000000..cc66a45 --- /dev/null +++ b/examples/rp2040_port/host/.gitignore @@ -0,0 +1,7 @@ +build/ +build_android/ +build_ios/ +build_macos/ +build_windows/ +icons +*.png \ No newline at end of file diff --git a/examples/rp2040_port/host/CMakeLists.txt b/examples/rp2040_port/host/CMakeLists.txt new file mode 100644 index 0000000..410385f --- /dev/null +++ b/examples/rp2040_port/host/CMakeLists.txt @@ -0,0 +1,265 @@ +# host/CMakeLists.txt + +cmake_minimum_required(VERSION 3.18) + +project(EISConfigurator VERSION 1.0 LANGUAGES CXX C) + +set(CMAKE_CXX_STANDARD 17) +set(CMAKE_CXX_STANDARD_REQUIRED ON) +set(CMAKE_AUTOMOC ON) +set(CMAKE_AUTORCC ON) +set(CMAKE_AUTOUIC ON) + +# --- FOR WINDOWS MSVC ERRORS --- +if(MSVC) + add_compile_options($<$:/std:clatest>) + add_compile_definitions(_CRT_SECURE_NO_WARNINGS) +endif() + +include(FetchContent) + +option(BUILD_ANDROID "Build for Android" OFF) +option(BUILD_IOS "Build for iOS" OFF) + +find_package(Qt6 REQUIRED COMPONENTS Core Gui Widgets SerialPort PrintSupport) + +if(ANDROID) + find_package(Qt6 REQUIRED COMPONENTS AndroidExtras) +endif() + +# ========================================== +# --- FFTW3 CONFIGURATION --- +# ========================================== + + +# --- FFTW3 Configuration (Double Precision) --- + +if(WIN32) + # Windows: Expects FFTW3 to be installed/found via Config + find_package(FFTW3 CONFIG REQUIRED) + if(TARGET FFTW3::fftw3) + add_library(fftw3 ALIAS FFTW3::fftw3) + endif() +elseif(APPLE AND CMAKE_SYSTEM_PROCESSOR STREQUAL "arm64" AND NOT BUILD_IOS) + message(STATUS "Detected Apple Silicon Desktop. Using Homebrew FFTW3 (Double).") + find_library(FFTW3_LIB NAMES fftw3 libfftw3 PATHS /opt/homebrew/lib NO_DEFAULT_PATH) + find_path(FFTW3_INCLUDE_DIR fftw3.h PATHS /opt/homebrew/include NO_DEFAULT_PATH) + + if(NOT FFTW3_LIB OR NOT FFTW3_INCLUDE_DIR) + message(FATAL_ERROR "FFTW3 not found in /opt/homebrew. Please run: brew install fftw") + endif() + + add_library(fftw3 STATIC IMPORTED) + set_target_properties(fftw3 PROPERTIES + IMPORTED_LOCATION "${FFTW3_LIB}" + INTERFACE_INCLUDE_DIRECTORIES "${FFTW3_INCLUDE_DIR}" + ) + +else() + message(STATUS "Building FFTW3 from source (Double Precision)...") + + set(ENABLE_FLOAT OFF CACHE BOOL "Build double precision" FORCE) + set(ENABLE_SSE OFF CACHE BOOL "Disable SSE" FORCE) + set(ENABLE_SSE2 OFF CACHE BOOL "Disable SSE2" FORCE) + set(ENABLE_AVX OFF CACHE BOOL "Disable AVX" FORCE) + set(ENABLE_AVX2 OFF CACHE BOOL "Disable AVX2" FORCE) + set(ENABLE_THREADS OFF CACHE BOOL "Disable Threads" FORCE) + set(ENABLE_OPENMP OFF CACHE BOOL "Disable OpenMP" FORCE) + set(ENABLE_MPI OFF CACHE BOOL "Disable MPI" FORCE) + set(BUILD_SHARED_LIBS OFF CACHE BOOL "Build Static Libs" FORCE) + set(BUILD_TESTS OFF CACHE BOOL "Disable Tests" FORCE) + + # Enhanced NEON detection for Windows on Arm as well + if(ANDROID_ABI STREQUAL "arm64-v8a") + message(STATUS "Enabling NEON for Android ARM64") + set(ENABLE_NEON ON CACHE BOOL "Enable NEON" FORCE) + elseif(BUILD_IOS) + set(ENABLE_NEON ON CACHE BOOL "Enable NEON" FORCE) + elseif(MSVC AND CMAKE_SYSTEM_PROCESSOR MATCHES "(ARM64|arm64|aarch64)") + set(ENABLE_NEON ON CACHE BOOL "Enable NEON" FORCE) + endif() + + # Only apply sed patch on UNIX-like systems + if(UNIX) + set(PATCH_CMD sed -i.bak "s/cmake_minimum_required.*/cmake_minimum_required(VERSION 3.16)/" /CMakeLists.txt) + else() + set(PATCH_CMD "") + endif() + + FetchContent_Declare( + fftw3_source + URL https://www.fftw.org/fftw-3.3.10.tar.gz + DOWNLOAD_EXTRACT_TIMESTAMP TRUE + PATCH_COMMAND ${PATCH_CMD} + ) + + FetchContent_MakeAvailable(fftw3_source) +endif() + +# ========================================== +# --- QCUSTOMPLOT --- +# ========================================== +FetchContent_Declare( + QCustomPlot + URL https://www.qcustomplot.com/release/2.1.1/QCustomPlot.tar.gz +) +FetchContent_MakeAvailable(QCustomPlot) + +# ========================================== +# --- ICON GENERATION --- +# ========================================== + +set(ICON_SOURCE "${CMAKE_CURRENT_SOURCE_DIR}/assets/icon_source.png") + +find_program(MAGICK_EXECUTABLE NAMES magick) +if(NOT MAGICK_EXECUTABLE) + message(WARNING "ImageMagick 'magick' not found. Icons will not be generated.") +endif() + +if(EXISTS "${ICON_SOURCE}" AND MAGICK_EXECUTABLE) + if(WIN32) + set(WINDOWS_ICON "${CMAKE_CURRENT_BINARY_DIR}/app_icon.ico") + set(WINDOWS_RC "${CMAKE_CURRENT_BINARY_DIR}/app_icon.rc") + set(ICON_SCRIPT "${CMAKE_CURRENT_SOURCE_DIR}/scripts/generate_icons.bat") + file(WRITE "${WINDOWS_RC}" "IDI_ICON1 ICON \"app_icon.ico\"\n") + add_custom_command( + OUTPUT "${WINDOWS_ICON}" + COMMAND "${ICON_SCRIPT}" "${MAGICK_EXECUTABLE}" "${ICON_SOURCE}" "${WINDOWS_ICON}" + WORKING_DIRECTORY "${CMAKE_CURRENT_BINARY_DIR}" + DEPENDS "${ICON_SOURCE}" "${ICON_SCRIPT}" + COMMENT "Generating Windows Icon..." + VERBATIM + ) + add_custom_target(GenerateIcons DEPENDS "${WINDOWS_ICON}") + else() + set(MACOS_ICON "${CMAKE_CURRENT_SOURCE_DIR}/assets/icons/app_icon.icns") + set(IOS_ASSETS_PATH "${CMAKE_CURRENT_SOURCE_DIR}/ios/Assets.xcassets") + set(IOS_CONTENTS_JSON "${IOS_ASSETS_PATH}/Contents.json") + set(ANDROID_RES_PATH "${CMAKE_CURRENT_SOURCE_DIR}/android/res/mipmap-mdpi/ic_launcher.png") + set(ICON_SCRIPT "${CMAKE_CURRENT_SOURCE_DIR}/scripts/generate_icons.sh") + execute_process(COMMAND chmod +x "${ICON_SCRIPT}") + add_custom_command( + OUTPUT "${MACOS_ICON}" "${IOS_CONTENTS_JSON}" "${ANDROID_RES_PATH}" + COMMAND "${ICON_SCRIPT}" "${MAGICK_EXECUTABLE}" + WORKING_DIRECTORY "${CMAKE_CURRENT_SOURCE_DIR}" + DEPENDS "${ICON_SOURCE}" "${ICON_SCRIPT}" + COMMENT "Generating Cross-Platform Icons..." + VERBATIM + ) + add_custom_target(GenerateIcons DEPENDS "${MACOS_ICON}" "${IOS_CONTENTS_JSON}" "${ANDROID_RES_PATH}") + endif() +endif() + +# --- Sources --- + +set(PROJECT_SOURCES + src/main.cpp + src/MainWindow.cpp + src/MainWindow_UI.cpp + src/MainWindow_Actions.cpp + src/MainWindow_Serial.cpp + src/GraphWidget.cpp + ${qcustomplot_SOURCE_DIR}/qcustomplot.cpp +) + +if(EXISTS "${ICON_SOURCE}") + if(WIN32) + list(APPEND PROJECT_SOURCES ${WINDOWS_RC} ${WINDOWS_ICON}) + elseif(APPLE AND NOT BUILD_IOS) + list(APPEND PROJECT_SOURCES ${MACOS_ICON}) + endif() +endif() + +set(PROJECT_HEADERS + src/MainWindow.h + src/GraphWidget.h + ${qcustomplot_SOURCE_DIR}/qcustomplot.h +) + +# Use qt_add_executable for proper Android/iOS handling +qt_add_executable(EISConfigurator MANUAL_FINALIZATION ${PROJECT_SOURCES} ${PROJECT_HEADERS}) + +if(EXISTS "${ICON_SOURCE}" AND MAGICK_EXECUTABLE) + add_dependencies(EISConfigurator GenerateIcons) +endif() + +# --- Mobile Definitions --- +if(BUILD_ANDROID OR BUILD_IOS) + target_compile_definitions(EISConfigurator PRIVATE IS_MOBILE) +endif() + +# --- Linking --- + +# Handle FFTW3 Linking and Include Paths +if(TARGET fftw3) + set(FFTW_TARGET fftw3) + # If built from source via FetchContent, we need to manually add include dirs + if(DEFINED fftw3_source_SOURCE_DIR) + target_include_directories(EISConfigurator PRIVATE + "${fftw3_source_SOURCE_DIR}/api" + "${fftw3_source_BINARY_DIR}" + ) + endif() +else() + # Fallback if target isn't defined (shouldn't happen with above logic) + set(FFTW_TARGET fftw3) +endif() + +target_include_directories(EISConfigurator PRIVATE ${qcustomplot_SOURCE_DIR}) + + +if(BUILD_ANDROID) + target_link_libraries(EISConfigurator PRIVATE log m) + set_property(TARGET EISConfigurator PROPERTY QT_ANDROID_PACKAGE_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/android) + + target_link_libraries(EISConfigurator PRIVATE Qt6::Widgets Qt6::SerialPort Qt6::AndroidExtras) + else() + target_link_libraries(EISConfigurator PRIVATE Qt6::Widgets Qt6::SerialPort Qt6::PrintSupport) + if(APPLE) + target_link_libraries(EISConfigurator PRIVATE ${FFTW_TARGET}) + endif() +endif() + + + + +if(BUILD_IOS) + if(NOT EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/ios/Info.plist") + message(FATAL_ERROR "Missing ios/Info.plist. Please create it before building.") + endif() + set_target_properties(EISConfigurator PROPERTIES + MACOSX_BUNDLE TRUE + MACOSX_BUNDLE_BUNDLE_NAME "EIS Configurator" + MACOSX_BUNDLE_GUI_IDENTIFIER "com.eis.configurator" + MACOSX_BUNDLE_INFO_PLIST "${CMAKE_CURRENT_SOURCE_DIR}/ios/Info.plist" + XCODE_ATTRIBUTE_ASSETCATALOG_COMPILER_APPICON_NAME "AppIcon" + RESOURCE "${IOS_ASSETS_PATH}" + ) + if(EXISTS "${ICON_SOURCE}") + file(MAKE_DIRECTORY "${IOS_ASSETS_PATH}") + target_sources(EISConfigurator PRIVATE "${IOS_ASSETS_PATH}") + endif() +endif() + +if(APPLE AND NOT BUILD_IOS) + set_target_properties(EISConfigurator PROPERTIES + MACOSX_BUNDLE TRUE + MACOSX_BUNDLE_BUNDLE_NAME "EIS Configurator" + MACOSX_BUNDLE_GUI_IDENTIFIER "com.eis.configurator" + MACOSX_BUNDLE_ICON_FILE "app_icon.icns" + RESOURCE "${MACOS_ICON}" + ) +elseif(WIN32) + set_target_properties(EISConfigurator PROPERTIES + WIN32_EXECUTABLE TRUE + ) + + target_link_libraries(EISConfigurator PRIVATE + Qt6::Core Qt6::Gui Qt6::Widgets Qt6::SerialPort Qt6::PrintSupport + ${FFTW_TARGET} +) + +endif() + + +qt_finalize_executable(EISConfigurator) \ No newline at end of file diff --git a/examples/rp2040_port/host/Makefile b/examples/rp2040_port/host/Makefile new file mode 100644 index 0000000..30e8ed6 --- /dev/null +++ b/examples/rp2040_port/host/Makefile @@ -0,0 +1,95 @@ +# host/Makefile + +QT_ANDROID_KIT ?= $(HOME)/Qt/6.8.3/android_arm64_v8a +QT_IOS_KIT ?= $(HOME)/Qt/6.8.3/ios +QT_MACOS_PATH ?= /opt/homebrew/opt/qt@6 +QT_WIN_PATH ?= C:/Qt/6.8.3/msvc2019_64 + +BUILD_DIR_MACOS = build_macos +BUILD_DIR_WIN = build_windows +BUILD_DIR_ANDROID = build_android +BUILD_DIR_IOS = build_ios +TARGET = EISConfigurator + +# Android Specifics +PKG_NAME = org.qtproject.example.EISConfigurator +# Qt6 generates 'android-build-debug.apk' by default +APK_PATH = $(BUILD_DIR_ANDROID)/android-build/build/outputs/apk/debug/android-build-debug.apk + +all: macos + +desktop: macos + +macos: + @echo "Building for macOS (Apple Silicon)..." + @mkdir -p $(BUILD_DIR_MACOS) + @cd $(BUILD_DIR_MACOS) && cmake .. \ + -DCMAKE_PREFIX_PATH="$(QT_MACOS_PATH);/opt/homebrew" \ + -DCMAKE_BUILD_TYPE=Release + @$(MAKE) -C $(BUILD_DIR_MACOS) + @echo "Build Complete. Run with: open $(BUILD_DIR_MACOS)/$(TARGET).app" + +windows: + @echo "Building for Windows..." + @mkdir -p $(BUILD_DIR_WIN) + @cd $(BUILD_DIR_WIN) && cmake .. \ + -DCMAKE_PREFIX_PATH="$(QT_WIN_PATH)" \ + -DCMAKE_BUILD_TYPE=Release + @cmake --build $(BUILD_DIR_WIN) + +android: + @if [ ! -d "$(QT_ANDROID_KIT)" ]; then echo "Error: QT_ANDROID_KIT not found at $(QT_ANDROID_KIT)"; exit 1; fi + @mkdir -p $(BUILD_DIR_ANDROID) + @cd $(BUILD_DIR_ANDROID) && cmake .. \ + -DCMAKE_TOOLCHAIN_FILE=$(QT_ANDROID_KIT)/lib/cmake/Qt6/qt.toolchain.cmake \ + -DQT_ANDROID_ABIS="arm64-v8a" \ + -DANDROID_PLATFORM=android-24 \ + -DQT_ANDROID_BUILD_ALL_ABIS=OFF \ + -DBUILD_ANDROID=ON \ + -DCMAKE_BUILD_TYPE=Debug + @cmake --build $(BUILD_DIR_ANDROID) --target apk + @echo "APK generated at $(APK_PATH)" + +ios: + @if [ ! -d "$(QT_IOS_KIT)" ]; then echo "Error: QT_IOS_KIT not found at $(QT_IOS_KIT)"; exit 1; fi + @mkdir -p $(BUILD_DIR_IOS) + @echo "Configuring iOS CMake..." + @cd $(BUILD_DIR_IOS) && cmake .. -G Xcode \ + -DCMAKE_TOOLCHAIN_FILE=$(QT_IOS_KIT)/lib/cmake/Qt6/qt.toolchain.cmake \ + -DCMAKE_SYSTEM_NAME=iOS \ + -DCMAKE_OSX_DEPLOYMENT_TARGET=16.0 \ + -DBUILD_IOS=ON + @echo "iOS Project generated at $(BUILD_DIR_IOS)/$(TARGET).xcodeproj" + + +run: + @open $(BUILD_DIR_MACOS)/$(TARGET).app + +# --- Android Deployment Wrappers --- + +install_android: android + @echo "Installing $(APK_PATH) to device..." + @adb install -r $(APK_PATH) + +run_android: install_android + @echo "Launching $(PKG_NAME)..." + @adb shell am start -n $(PKG_NAME)/org.qtproject.qt.android.bindings.QtActivity + +debug_android: run_android + @echo "Attaching Logcat (Ctrl+C to exit)..." + @adb logcat -v color -s EISConfigurator Qt:* DEBUG + +# --- Cleaning --- + +clean: + @echo "Cleaning build artifacts..." + @if [ -f "$(BUILD_DIR_MACOS)/Makefile" ]; then cmake --build $(BUILD_DIR_MACOS) --target clean; fi + @if [ -f "$(BUILD_DIR_WIN)/Makefile" ] || [ -f "$(BUILD_DIR_WIN)/build.ninja" ]; then cmake --build $(BUILD_DIR_WIN) --target clean; fi + @if [ -f "$(BUILD_DIR_ANDROID)/Makefile" ] || [ -f "$(BUILD_DIR_ANDROID)/build.ninja" ]; then cmake --build $(BUILD_DIR_ANDROID) --target clean; fi + @if [ -d "$(BUILD_DIR_IOS)/$(TARGET).xcodeproj" ]; then cmake --build $(BUILD_DIR_IOS) --target clean; fi + +distclean: + @rm -rf $(BUILD_DIR_MACOS) $(BUILD_DIR_WIN) $(BUILD_DIR_ANDROID) $(BUILD_DIR_IOS) + @echo "Removed all build directories." + +.PHONY: all desktop macos windows android ios run install_android run_android debug_android clean distclean \ No newline at end of file diff --git a/examples/rp2040_port/host/android/AndroidManifest.xml b/examples/rp2040_port/host/android/AndroidManifest.xml new file mode 100644 index 0000000..24ec5ef --- /dev/null +++ b/examples/rp2040_port/host/android/AndroidManifest.xml @@ -0,0 +1,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/examples/rp2040_port/host/ios/Assets.xcassets/AppIcon.appiconset/Contents.json b/examples/rp2040_port/host/ios/Assets.xcassets/AppIcon.appiconset/Contents.json new file mode 100644 index 0000000..e9b5a67 --- /dev/null +++ b/examples/rp2040_port/host/ios/Assets.xcassets/AppIcon.appiconset/Contents.json @@ -0,0 +1,27 @@ +{ + "images" : [ + { "size" : "20x20", "idiom" : "iphone", "filename" : "Icon-20@2x.png", "scale" : "2x" }, + { "size" : "20x20", "idiom" : "iphone", "filename" : "Icon-20@3x.png", "scale" : "3x" }, + { "size" : "29x29", "idiom" : "iphone", "filename" : "Icon-29.png", "scale" : "1x" }, + { "size" : "29x29", "idiom" : "iphone", "filename" : "Icon-29@2x.png", "scale" : "2x" }, + { "size" : "29x29", "idiom" : "iphone", "filename" : "Icon-29@3x.png", "scale" : "3x" }, + { "size" : "40x40", "idiom" : "iphone", "filename" : "Icon-40@2x.png", "scale" : "2x" }, + { "size" : "40x40", "idiom" : "iphone", "filename" : "Icon-40@3x.png", "scale" : "3x" }, + { "size" : "60x60", "idiom" : "iphone", "filename" : "Icon-60@2x.png", "scale" : "2x" }, + { "size" : "60x60", "idiom" : "iphone", "filename" : "Icon-60@3x.png", "scale" : "3x" }, + { "size" : "20x20", "idiom" : "ipad", "filename" : "Icon-20.png", "scale" : "1x" }, + { "size" : "20x20", "idiom" : "ipad", "filename" : "Icon-20@2x.png", "scale" : "2x" }, + { "size" : "29x29", "idiom" : "ipad", "filename" : "Icon-29.png", "scale" : "1x" }, + { "size" : "29x29", "idiom" : "ipad", "filename" : "Icon-29@2x.png", "scale" : "2x" }, + { "size" : "40x40", "idiom" : "ipad", "filename" : "Icon-40.png", "scale" : "1x" }, + { "size" : "40x40", "idiom" : "ipad", "filename" : "Icon-40@2x.png", "scale" : "2x" }, + { "size" : "76x76", "idiom" : "ipad", "filename" : "Icon-76.png", "scale" : "1x" }, + { "size" : "76x76", "idiom" : "ipad", "filename" : "Icon-76@2x.png", "scale" : "2x" }, + { "size" : "83.5x83.5", "idiom" : "ipad", "filename" : "Icon-83.5@2x.png", "scale" : "2x" }, + { "size" : "1024x1024", "idiom" : "ios-marketing", "filename" : "Icon-1024.png", "scale" : "1x" } + ], + "info" : { + "version" : 1, + "author" : "xcode" + } +} diff --git a/examples/rp2040_port/host/ios/Assets.xcassets/Contents.json b/examples/rp2040_port/host/ios/Assets.xcassets/Contents.json new file mode 100644 index 0000000..2d92bd5 --- /dev/null +++ b/examples/rp2040_port/host/ios/Assets.xcassets/Contents.json @@ -0,0 +1,6 @@ +{ + "info" : { + "version" : 1, + "author" : "xcode" + } +} diff --git a/examples/rp2040_port/host/ios/Info.plist b/examples/rp2040_port/host/ios/Info.plist new file mode 100644 index 0000000..644f189 --- /dev/null +++ b/examples/rp2040_port/host/ios/Info.plist @@ -0,0 +1,78 @@ + + + + + CFBundleDisplayName + Yr Crystals + CFBundleExecutable + $(EXECUTABLE_NAME) + CFBundleIdentifier + $(PRODUCT_BUNDLE_IDENTIFIER) + CFBundleName + $(PRODUCT_NAME) + CFBundlePackageType + APPL + CFBundleShortVersionString + 1.0 + CFBundleVersion + 1 + LSRequiresIPhoneOS + + UIRequiresFullScreen + + UILaunchStoryboardName + LaunchScreen + UIRequiredDeviceCapabilities + + arm64 + + UISupportedInterfaceOrientations + + UIInterfaceOrientationPortrait + UIInterfaceOrientationLandscapeLeft + UIInterfaceOrientationLandscapeRight + + + + NSMicrophoneUsageDescription + This app requires audio access to visualize music. + NSAppleMusicUsageDescription + This app requires access to your music library to play tracks. + NSPhotoLibraryUsageDescription + This app requires access to the photo library to load album art. + NSCameraUsageDescription + This app requires camera access for visualizer input. + + + UIFileSharingEnabled + + LSSupportsOpeningDocumentsInPlace + + + + CFBundleDocumentTypes + + + CFBundleTypeName + Audio + LSHandlerRank + Alternate + LSItemContentTypes + + public.audio + public.mp3 + public.mpeg-4-audio + public.folder + public.directory + public.content + public.data + + + + + UIBackgroundModes + + audio + + + \ No newline at end of file diff --git a/examples/rp2040_port/host/scripts/build_windows.bat b/examples/rp2040_port/host/scripts/build_windows.bat new file mode 100644 index 0000000..afcbcf2 --- /dev/null +++ b/examples/rp2040_port/host/scripts/build_windows.bat @@ -0,0 +1,108 @@ +@echo off +setlocal enabledelayedexpansion + +:: ============================================================================== +:: PATHS +:: ============================================================================== +:: This script lives in scripts/ +set "SCRIPT_DIR=%~dp0" + +:: The build scripts live in windows/ +pushd "%SCRIPT_DIR%..\windows" +set "WINDOWS_SCRIPTS_DIR=%CD%" +popd + +:: The output dir is build_windows/ +pushd "%SCRIPT_DIR%.." +set "PROJECT_ROOT=%CD%" +popd +set "OUTPUT_ROOT=%PROJECT_ROOT%\build_windows" + +echo [MASTER] Project Root: %PROJECT_ROOT% +echo [MASTER] Scripts Dir: %WINDOWS_SCRIPTS_DIR% +echo [MASTER] Output Dir: %OUTPUT_ROOT% +echo. + +:: ============================================================================== +:: 1. BUILD ARM64 +:: ============================================================================== +echo [MASTER] Starting ARM64 Build... +echo ------------------------------------------------------------------------------ + +:: Navigate to the windows directory so the script runs in its native context +pushd "%WINDOWS_SCRIPTS_DIR%" + +:: Run the script +call build_arm64.bat + +if %errorlevel% neq 0 ( + echo. + echo [MASTER] CRITICAL ERROR: ARM64 Build Failed. + popd + pause + exit /b %errorlevel% +) + +:: Return to master context +popd +echo. + +:: ============================================================================== +:: 2. ZIP ARM64 +:: ============================================================================== +echo [MASTER] Packaging ARM64... +set "ARM64_SOURCE=%OUTPUT_ROOT%\arm64" +set "ARM64_ZIP=%OUTPUT_ROOT%\YrCrystals_Win_ARM64.zip" + +if exist "%ARM64_SOURCE%\YrCrystals.exe" ( + if exist "%ARM64_ZIP%" del "%ARM64_ZIP%" + powershell -NoProfile -Command "Compress-Archive -Path '%ARM64_SOURCE%\*' -DestinationPath '%ARM64_ZIP%' -Force" + echo [SUCCESS] Created: %ARM64_ZIP% +) else ( + echo [ERROR] ARM64 Output directory missing or empty. Skipping Zip. +) +echo. + +:: ============================================================================== +:: 3. BUILD x64 +:: ============================================================================== +echo [MASTER] Starting x64 Build... +echo ------------------------------------------------------------------------------ + +pushd "%WINDOWS_SCRIPTS_DIR%" +call build_x64.bat + +if %errorlevel% neq 0 ( + echo. + echo [MASTER] CRITICAL ERROR: x64 Build Failed. + popd + pause + exit /b %errorlevel% +) +popd +echo. + +:: ============================================================================== +:: 4. ZIP x64 +:: ============================================================================== +echo [MASTER] Packaging x64... +set "X64_SOURCE=%OUTPUT_ROOT%\x64" +set "X64_ZIP=%OUTPUT_ROOT%\YrCrystals_Win_x64.zip" + +if exist "%X64_SOURCE%\YrCrystals.exe" ( + if exist "%X64_ZIP%" del "%X64_ZIP%" + powershell -NoProfile -Command "Compress-Archive -Path '%X64_SOURCE%\*' -DestinationPath '%X64_ZIP%' -Force" + echo [SUCCESS] Created: %X64_ZIP% +) else ( + echo [ERROR] x64 Output directory missing or empty. Skipping Zip. +) + +:: ============================================================================== +:: DONE +:: ============================================================================== +echo. +echo ------------------------------------------------------------------------------ +echo [MASTER] All builds completed successfully. +echo [OUTPUT] %OUTPUT_ROOT% +echo ------------------------------------------------------------------------------ +pause \ No newline at end of file diff --git a/examples/rp2040_port/host/scripts/generate_icons.bat b/examples/rp2040_port/host/scripts/generate_icons.bat new file mode 100644 index 0000000..7befa1c --- /dev/null +++ b/examples/rp2040_port/host/scripts/generate_icons.bat @@ -0,0 +1,52 @@ +@echo off +setlocal + +:: Arguments passed from CMake: +:: %1 = Path to magick.exe +:: %2 = Source Image +:: %3 = Destination Icon + +set "MAGICK_EXE=%~1" +set "SOURCE_IMG=%~2" +set "DEST_ICO=%~3" + +:: -- FOR MISSING DELEGATES / REGISTRY ERRORS --- +for %%I in ("%MAGICK_EXE%") do set "MAGICK_DIR=%%~dpI" +if "%MAGICK_DIR:~-1%"=="\" set "MAGICK_DIR=%MAGICK_DIR:~0,-1%" +set "MAGICK_HOME=%MAGICK_DIR%" +set "MAGICK_CONFIGURE_PATH=%MAGICK_DIR%" +set "MAGICK_CODER_MODULE_PATH=%MAGICK_DIR%\modules\coders" +:: --------------------------------------------------- + +:: 1. Validate Source +if not exist "%SOURCE_IMG%" ( + echo [ERROR] Icon source not found at: %SOURCE_IMG% + exit /b 1 +) + +:: 2. Ensure Destination Directory Exists +if not exist "%~dp3" mkdir "%~dp3" + +:: 3. Generate the .ico (Nearest Neighbor / Pixel Art Mode) +echo [ICONS] Generating Pixel-Perfect Windows Icon: %DEST_ICO% + +:: We use -sample (Nearest Neighbor) explicitly for each standard icon size. +:: We clone the original (index 0) for every resize to ensure maximum accuracy from the source. +"%MAGICK_EXE%" "%SOURCE_IMG%" ^ + -background none -alpha on ^ + ( -clone 0 -sample 256x256 ) ^ + ( -clone 0 -sample 128x128 ) ^ + ( -clone 0 -sample 64x64 ) ^ + ( -clone 0 -sample 48x48 ) ^ + ( -clone 0 -sample 32x32 ) ^ + ( -clone 0 -sample 16x16 ) ^ + -delete 0 ^ + "%DEST_ICO%" + +if %errorlevel% neq 0 ( + echo [ERROR] ImageMagick failed to generate icon. + exit /b %errorlevel% +) + +echo [SUCCESS] Icon generated. +exit /b 0 \ No newline at end of file diff --git a/examples/rp2040_port/host/scripts/generate_icons.sh b/examples/rp2040_port/host/scripts/generate_icons.sh new file mode 100755 index 0000000..78c434f --- /dev/null +++ b/examples/rp2040_port/host/scripts/generate_icons.sh @@ -0,0 +1,144 @@ +#!/bin/bash + +# Argument 1: Path to magick executable +MAGICK_BIN="$1" + +# Fallback if not provided +if [ -z "$MAGICK_BIN" ]; then + MAGICK_BIN="magick" +fi + +# Assumes running from Project Root +SOURCE="assets/icon_source.png" + +if [ ! -f "$SOURCE" ]; then + echo "Error: Source image '$SOURCE' not found in $(pwd)" + exit 1 +fi + +# Verify magick works +"$MAGICK_BIN" -version >/dev/null 2>&1 +if [ $? -ne 0 ]; then + echo "Error: ImageMagick tool '$MAGICK_BIN' not found or not working." + exit 1 +fi + +# --- macOS --- +# Keep macOS icons in assets/icons as they are linked explicitly +MACOS_OUT_DIR="assets/icons" +mkdir -p "$MACOS_OUT_DIR" +ICONSET="$MACOS_OUT_DIR/icon.iconset" +mkdir -p "$ICONSET" + +echo "[ICONS] Generating macOS iconset (Pixel Perfect)..." +"$MAGICK_BIN" "$SOURCE" -sample 16x16 "$ICONSET/icon_16x16.png" +"$MAGICK_BIN" "$SOURCE" -sample 32x32 "$ICONSET/icon_16x16@2x.png" +"$MAGICK_BIN" "$SOURCE" -sample 32x32 "$ICONSET/icon_32x32.png" +"$MAGICK_BIN" "$SOURCE" -sample 64x64 "$ICONSET/icon_32x32@2x.png" +"$MAGICK_BIN" "$SOURCE" -sample 128x128 "$ICONSET/icon_128x128.png" +"$MAGICK_BIN" "$SOURCE" -sample 256x256 "$ICONSET/icon_128x128@2x.png" +"$MAGICK_BIN" "$SOURCE" -sample 256x256 "$ICONSET/icon_256x256.png" +"$MAGICK_BIN" "$SOURCE" -sample 512x512 "$ICONSET/icon_256x256@2x.png" +"$MAGICK_BIN" "$SOURCE" -sample 512x512 "$ICONSET/icon_512x512.png" +"$MAGICK_BIN" "$SOURCE" -sample 1024x1024 "$ICONSET/icon_512x512@2x.png" + +iconutil -c icns "$ICONSET" -o "$MACOS_OUT_DIR/app_icon.icns" +rm -rf "$ICONSET" + +# --- Windows --- +echo "[ICONS] Generating Windows .ico (Pixel Perfect)..." +# Updated to match the high-quality logic from the Windows Batch file +# (Removed -alpha off and -colors 256 which would ruin transparency) +"$MAGICK_BIN" "$SOURCE" \ + -background none -alpha on \ + \( -clone 0 -sample 256x256 \) \ + \( -clone 0 -sample 128x128 \) \ + \( -clone 0 -sample 64x64 \) \ + \( -clone 0 -sample 48x48 \) \ + \( -clone 0 -sample 32x32 \) \ + \( -clone 0 -sample 16x16 \) \ + -delete 0 "$MACOS_OUT_DIR/app_icon.ico" + +# --- Android --- +# Output directly to android/res so QT_ANDROID_PACKAGE_SOURCE_DIR picks it up +echo "[ICONS] Generating Android mipmaps (Pixel Perfect)..." +ANDROID_DIR="android/res" + +mkdir -p "$ANDROID_DIR/mipmap-mdpi" +"$MAGICK_BIN" "$SOURCE" -sample 48x48 "$ANDROID_DIR/mipmap-mdpi/ic_launcher.png" + +mkdir -p "$ANDROID_DIR/mipmap-hdpi" +"$MAGICK_BIN" "$SOURCE" -sample 72x72 "$ANDROID_DIR/mipmap-hdpi/ic_launcher.png" + +mkdir -p "$ANDROID_DIR/mipmap-xhdpi" +"$MAGICK_BIN" "$SOURCE" -sample 96x96 "$ANDROID_DIR/mipmap-xhdpi/ic_launcher.png" + +mkdir -p "$ANDROID_DIR/mipmap-xxhdpi" +"$MAGICK_BIN" "$SOURCE" -sample 144x144 "$ANDROID_DIR/mipmap-xxhdpi/ic_launcher.png" + +mkdir -p "$ANDROID_DIR/mipmap-xxxhdpi" +"$MAGICK_BIN" "$SOURCE" -sample 192x192 "$ANDROID_DIR/mipmap-xxxhdpi/ic_launcher.png" + +# --- iOS --- +# Output directly to ios/Assets.xcassets +echo "[ICONS] Generating iOS AppIcon (Pixel Perfect)..." +XCASSETS_DIR="ios/Assets.xcassets" +IOS_DIR="$XCASSETS_DIR/AppIcon.appiconset" +mkdir -p "$IOS_DIR" + +cat > "$XCASSETS_DIR/Contents.json" < "$IOS_DIR/Contents.json" < +#include +#include +#include +#include +#include + +// Simple Linear Regression Helper +static void linearRegression(const QVector &x, const QVector &y, + double &m, double &c) { + double sumX = 0, sumY = 0, sumXY = 0, sumX2 = 0; + int n = x.size(); + for (int i = 0; i < n; i++) { + sumX += x[i]; + sumY += y[i]; + sumXY += x[i] * y[i]; + sumX2 += x[i] * x[i]; + } + m = (n * sumXY - sumX * sumY) / (n * sumX2 - sumX * sumX); + c = (sumY - m * sumX) / n; +} + +GraphWidget::GraphWidget(QWidget *parent) : QWidget(parent) { + mainLayout = new QVBoxLayout(this); + mainLayout->setContentsMargins(0, 0, 0, 0); + mainLayout->setSpacing(0); + + // Toolbar + toolbar = new QWidget(this); + toolbar->setStyleSheet("background-color: #2D2D2D;"); + QHBoxLayout *toolLayout = new QHBoxLayout(toolbar); + toolLayout->setContentsMargins(5, 2, 5, 2); + + btnScaleX = new QPushButton("Scale X", this); + btnScaleY = new QPushButton("Scale Y", this); + btnScaleBoth = new QPushButton("Scale Both", this); + btnCenter = new QPushButton("Center", this); + btnAnalyze = new QPushButton("Analyze", this); + + QString btnStyle = "QPushButton { background-color: #444; color: white; " + "border: 1px solid #555; padding: 3px 8px; border-radius: " + "3px; } QPushButton:hover { background-color: #555; }"; + btnScaleX->setStyleSheet(btnStyle); + btnScaleY->setStyleSheet(btnStyle); + btnScaleBoth->setStyleSheet(btnStyle); + btnCenter->setStyleSheet(btnStyle); + btnAnalyze->setStyleSheet(btnStyle); + + toolLayout->addWidget(btnScaleX); + toolLayout->addWidget(btnScaleY); + toolLayout->addWidget(btnScaleBoth); + toolLayout->addWidget(btnCenter); + toolLayout->addStretch(); + toolLayout->addWidget(btnAnalyze); + + mainLayout->addWidget(toolbar); + + plot = new QCustomPlot(this); + mainLayout->addWidget(plot); + + plot->setBackground(QBrush(QColor(25, 25, 25))); + + auto styleAxis = [](QCPAxis *axis) { + axis->setBasePen(QPen(Qt::white)); + axis->setTickPen(QPen(Qt::white)); + axis->setSubTickPen(QPen(Qt::white)); + axis->setTickLabelColor(Qt::white); + axis->setLabelColor(Qt::white); + axis->grid()->setPen(QPen(QColor(60, 60, 60), 0, Qt::DotLine)); + axis->grid()->setSubGridVisible(true); + axis->grid()->setSubGridPen(QPen(QColor(40, 40, 40), 0, Qt::DotLine)); + }; + + styleAxis(plot->xAxis); + styleAxis(plot->yAxis); + styleAxis(plot->yAxis2); + + // --- Setup Graphs --- + graphReal = plot->addGraph(); + graphReal->setPen(QPen(QColor(0, 255, 255), 2)); + graphReal->setLineStyle(QCPGraph::lsLine); + graphReal->setScatterStyle( + QCPScatterStyle(QCPScatterStyle::ssCircle, QColor(0, 255, 255), 3)); + + graphImag = plot->addGraph(plot->xAxis, plot->yAxis2); + graphImag->setPen(QPen(QColor(255, 0, 255), 2)); + graphImag->setLineStyle(QCPGraph::lsLine); + graphImag->setScatterStyle( + QCPScatterStyle(QCPScatterStyle::ssTriangle, QColor(255, 0, 255), 3)); + + graphHilbert = plot->addGraph(plot->xAxis, plot->yAxis2); + QPen pen3(Qt::green); + pen3.setWidth(2); + pen3.setStyle(Qt::DashLine); + graphHilbert->setPen(pen3); + + graphNyquistCorr = plot->addGraph(plot->xAxis, plot->yAxis); + graphNyquistCorr->setPen(QPen(QColor(255, 165, 0), 2)); + graphNyquistCorr->setLineStyle(QCPGraph::lsLine); + graphNyquistCorr->setScatterStyle( + QCPScatterStyle(QCPScatterStyle::ssCross, 4)); + graphNyquistCorr->setName("De-embedded (True Cell)"); + + graphAmp = plot->addGraph(); + graphAmp->setPen(QPen(QColor(50, 255, 50), 2)); + graphAmp->setLineStyle(QCPGraph::lsLine); + graphAmp->setScatterStyle(QCPScatterStyle(QCPScatterStyle::ssDisc, 3)); + graphAmp->setName("Current"); + + graphExtrapolated = plot->addGraph(plot->xAxis, plot->yAxis); + graphExtrapolated->setLineStyle(QCPGraph::lsNone); + graphExtrapolated->setScatterStyle( + QCPScatterStyle(QCPScatterStyle::ssStar, QColor(255, 215, 0), 12)); + graphExtrapolated->setPen(QPen(QColor(255, 215, 0), 3)); + graphExtrapolated->setName("Rs (Extrapolated)"); + + graphLSVBlank = plot->addGraph(); + QPen penBlank(QColor(150, 150, 150)); + penBlank.setWidth(2); + penBlank.setStyle(Qt::DashLine); + graphLSVBlank->setPen(penBlank); + graphLSVBlank->setName("Blank (Tap Water)"); + + graphLSVSample = plot->addGraph(); + graphLSVSample->setPen(QPen(Qt::yellow, 2)); + graphLSVSample->setName("Sample (Bleach)"); + + graphLSVDiff = plot->addGraph(); + graphLSVDiff->setPen(QPen(Qt::cyan, 3)); + graphLSVDiff->setName("Diff (Chlorine)"); + + graphFit = plot->addGraph(); + graphFit->setPen(QPen(Qt::red, 2)); + graphFit->setName("Fit"); + + graphNyquistRaw = graphReal; + + plot->yAxis2->setVisible(true); + plot->yAxis2->setTickLabels(true); + + connect(plot->yAxis, SIGNAL(rangeChanged(QCPRange)), plot->yAxis2, + SLOT(setRange(QCPRange))); + connect(plot->yAxis2, SIGNAL(rangeChanged(QCPRange)), plot->yAxis, + SLOT(setRange(QCPRange))); + + plot->setInteractions(QCP::iRangeDrag | QCP::iRangeZoom | + QCP::iSelectPlottables); + + // Right click drag to zoom + plot->axisRect()->setRangeDrag(Qt::Horizontal | Qt::Vertical); + plot->axisRect()->setRangeZoom(Qt::Horizontal | Qt::Vertical); + + plot->legend->setVisible(true); + QFont legendFont = font(); + legendFont.setPointSize(9); + plot->legend->setFont(legendFont); + plot->legend->setBrush(QBrush(QColor(40, 40, 40, 200))); + plot->legend->setBorderPen(QPen(Qt::white)); + plot->legend->setTextColor(Qt::white); + + selectionRect = new QCPItemRect(plot); + selectionRect->setPen(QPen(Qt::yellow, 1, Qt::DashLine)); + selectionRect->setBrush(QBrush(QColor(255, 255, 0, 50))); + selectionRect->setVisible(false); + + connect(btnScaleX, &QPushButton::clicked, this, &GraphWidget::scaleX); + connect(btnScaleY, &QPushButton::clicked, this, &GraphWidget::scaleY); + connect(btnScaleBoth, &QPushButton::clicked, this, &GraphWidget::scaleBoth); + connect(btnCenter, &QPushButton::clicked, this, &GraphWidget::centerView); + connect(btnAnalyze, &QPushButton::clicked, this, &GraphWidget::startAnalyze); + + // Custom mouse handling for selection + connect(plot, &QCustomPlot::mousePress, [this](QMouseEvent *event) { + if (isSelecting && event->button() == Qt::LeftButton) { + selStartX = plot->xAxis->pixelToCoord(event->pos().x()); + selStartY = plot->yAxis->pixelToCoord(event->pos().y()); + selectionRect->topLeft->setCoords(selStartX, selStartY); + selectionRect->bottomRight->setCoords(selStartX, selStartY); + selectionRect->setVisible(true); + plot->replot(); + } + }); + + connect(plot, &QCustomPlot::mouseMove, [this](QMouseEvent *event) { + if (isSelecting && (event->buttons() & Qt::LeftButton)) { + double x = plot->xAxis->pixelToCoord(event->pos().x()); + double y = plot->yAxis->pixelToCoord(event->pos().y()); + selectionRect->bottomRight->setCoords(x, y); + plot->replot(); + } + }); + + connect(plot, &QCustomPlot::mouseRelease, [this](QMouseEvent *event) { + if (isSelecting && event->button() == Qt::LeftButton) { + isSelecting = false; + plot->setInteractions(QCP::iRangeDrag | QCP::iRangeZoom); + + double x2 = plot->xAxis->pixelToCoord(event->pos().x()); + double y2 = plot->yAxis->pixelToCoord(event->pos().y()); + + // Collect data in rect + QVector xData, yData; + double minX = std::min(selStartX, x2); + double maxX = std::max(selStartX, x2); + double minY = std::min(selStartY, y2); + double maxY = std::max(selStartY, y2); + + // Iterate visible graphs to find data + QList graphs = {graphReal, graphAmp, graphLSVSample, + graphLSVDiff}; + for (auto g : graphs) { + if (!g->visible()) + continue; + for (auto it = g->data()->begin(); it != g->data()->end(); ++it) { + if (it->key >= minX && it->key <= maxX && it->value >= minY && + it->value <= maxY) { + xData.append(it->key); + yData.append(it->value); + } + } + if (!xData.isEmpty()) + break; // Only fit one graph + } + + if (xData.size() > 2) { + // Show Dialog + QDialog dlg(this); + dlg.setWindowTitle("Fit Data"); + QFormLayout *layout = new QFormLayout(&dlg); + QComboBox *type = new QComboBox(); + type->addItems({"Linear", "Exponential", "Logarithmic", "Polynomial"}); + QSpinBox *order = new QSpinBox(); + order->setRange(1, 10); + order->setValue(2); + QCheckBox *inverse = new QCheckBox("Inverse"); + + layout->addRow("Type:", type); + layout->addRow("Poly Order:", order); + layout->addRow(inverse); + + QDialogButtonBox *btns = new QDialogButtonBox(QDialogButtonBox::Ok | + QDialogButtonBox::Cancel); + layout->addRow(btns); + connect(btns, &QDialogButtonBox::accepted, &dlg, &QDialog::accept); + connect(btns, &QDialogButtonBox::rejected, &dlg, &QDialog::reject); + + if (dlg.exec() == QDialog::Accepted) { + performFit(xData, yData, type->currentIndex(), order->value(), + inverse->isChecked()); + } + } + + selectionRect->setVisible(false); + plot->replot(); + } + }); + + configureRawPlot(); +} + +void GraphWidget::scaleX() { + plot->rescaleAxes(true); + plot->replot(); +} +void GraphWidget::scaleY() { + plot->yAxis->rescale(true); + plot->yAxis2->rescale(true); + plot->replot(); +} +void GraphWidget::scaleBoth() { + plot->rescaleAxes(true); + plot->replot(); +} +void GraphWidget::centerView() { scaleBoth(); } + +void GraphWidget::startAnalyze() { + isSelecting = true; + // FIX: Use default constructor for empty flags instead of 0 + plot->setInteractions(QCP::Interactions()); +} + +void GraphWidget::performFit(const QVector &x, const QVector &y, + int type, int order, bool inverse) { + graphFit->data()->clear(); + QVector xFit, yFit; + + // Simple Linear Fit Implementation for demo + if (type == 0) { // Linear + double m, c; + QVector yProc = y; + if (inverse) { + for (int i = 0; i < y.size(); i++) + yProc[i] = 1.0 / y[i]; + } + linearRegression(x, yProc, m, c); + + double minX = *std::min_element(x.begin(), x.end()); + double maxX = *std::max_element(x.begin(), x.end()); + + for (int i = 0; i <= 100; i++) { + double xv = minX + (maxX - minX) * i / 100.0; + double yv = m * xv + c; + if (inverse) + yv = 1.0 / yv; + xFit.append(xv); + yFit.append(yv); + } + } + // Add other fits here (Exp, Log, Poly) as needed + + graphFit->setData(xFit, yFit); + graphFit->setVisible(true); + plot->replot(); +} + +// ... (Rest of configuration methods same as before) ... +void GraphWidget::configureRawPlot() { + plot->xAxis->setLabel("Frequency (Hz)"); + plot->xAxis->setScaleType(QCPAxis::stLogarithmic); + QSharedPointer logTicker(new QCPAxisTickerLog); + plot->xAxis->setTicker(logTicker); + plot->xAxis->setNumberFormat("eb"); + + plot->yAxis->setLabel("Magnitude (Ohms)"); + plot->yAxis->setScaleType(QCPAxis::stLogarithmic); + QSharedPointer logTickerY(new QCPAxisTickerLog); + plot->yAxis->setTicker(logTickerY); + plot->yAxis->setNumberFormat("eb"); + + plot->yAxis2->setLabel("Phase (Rad)"); + plot->yAxis2->setScaleType(QCPAxis::stLinear); + QSharedPointer linTicker(new QCPAxisTicker); + plot->yAxis2->setTicker(linTicker); + plot->yAxis2->setNumberFormat("f"); + plot->yAxis2->setVisible(true); + + graphReal->setName("Magnitude"); + graphImag->setName("Phase"); + graphHilbert->setName("Hilbert"); + + graphReal->setVisible(true); + graphImag->setVisible(true); + graphHilbert->setVisible(true); + graphNyquistCorr->setVisible(false); + graphAmp->setVisible(false); + graphExtrapolated->setVisible(false); + graphLSVBlank->setVisible(false); + graphLSVSample->setVisible(false); + graphLSVDiff->setVisible(false); + graphFit->setVisible(false); + + plot->replot(); +} + +void GraphWidget::configureNyquistPlot() { + plot->xAxis->setLabel("Real (Z')"); + plot->xAxis->setScaleType(QCPAxis::stLinear); + QSharedPointer linTicker(new QCPAxisTicker); + plot->xAxis->setTicker(linTicker); + plot->xAxis->setNumberFormat("f"); + + plot->yAxis->setLabel("-Imaginary (-Z'')"); + plot->yAxis->setScaleType(QCPAxis::stLinear); + plot->yAxis->setTicker(linTicker); + plot->yAxis->setNumberFormat("f"); + + plot->yAxis2->setVisible(false); + + graphReal->setName("Measured (Raw)"); + graphReal->setLineStyle(QCPGraph::lsLine); + graphReal->setScatterStyle(QCPScatterStyle(QCPScatterStyle::ssCircle, 4)); + + graphReal->setVisible(true); + graphImag->setVisible(false); + graphHilbert->setVisible(false); + graphNyquistCorr->setVisible(true); + graphAmp->setVisible(false); + graphExtrapolated->setVisible(true); + graphLSVBlank->setVisible(false); + graphLSVSample->setVisible(false); + graphLSVDiff->setVisible(false); + graphFit->setVisible(false); + + plot->replot(); +} + +void GraphWidget::configureAmperometricPlot() { + plot->xAxis->setLabel("Sample Index"); + plot->xAxis->setScaleType(QCPAxis::stLinear); + QSharedPointer linTicker(new QCPAxisTicker); + plot->xAxis->setTicker(linTicker); + plot->xAxis->setNumberFormat("f"); + + plot->yAxis->setLabel("Current (uA)"); + plot->yAxis->setScaleType(QCPAxis::stLinear); + plot->yAxis->setTicker(linTicker); + plot->yAxis->setNumberFormat("f"); + + plot->yAxis2->setVisible(false); + + graphAmp->setName("Current"); + graphAmp->setVisible(true); + + graphReal->setVisible(false); + graphImag->setVisible(false); + graphHilbert->setVisible(false); + graphNyquistCorr->setVisible(false); + graphExtrapolated->setVisible(false); + graphLSVBlank->setVisible(false); + graphLSVSample->setVisible(false); + graphLSVDiff->setVisible(false); + graphFit->setVisible(false); + + plot->replot(); +} + +void GraphWidget::configureLSVPlot() { + plot->xAxis->setLabel("Voltage (mV)"); + plot->xAxis->setScaleType(QCPAxis::stLinear); + QSharedPointer linTicker(new QCPAxisTicker); + plot->xAxis->setTicker(linTicker); + plot->xAxis->setNumberFormat("f"); + + plot->yAxis->setLabel("Current (uA)"); + plot->yAxis->setScaleType(QCPAxis::stLinear); + plot->yAxis->setTicker(linTicker); + plot->yAxis->setNumberFormat("f"); + + plot->yAxis2->setVisible(false); + + graphLSVBlank->setVisible(true); + graphLSVSample->setVisible(true); + graphLSVDiff->setVisible(true); + + graphReal->setVisible(false); + graphImag->setVisible(false); + graphHilbert->setVisible(false); + graphNyquistCorr->setVisible(false); + graphExtrapolated->setVisible(false); + graphAmp->setVisible(false); + graphFit->setVisible(false); + + plot->replot(); +} + +void GraphWidget::addBodeData(double freq, double val1, double val2) { + if (plot->xAxis->scaleType() == QCPAxis::stLogarithmic && freq <= 0) + return; + graphReal->addData(freq, val1); + graphImag->addData(freq, val2); + graphReal->rescaleAxes(false); + graphImag->rescaleAxes(false); + graphHilbert->rescaleAxes(false); + plot->replot(); +} + +void GraphWidget::addNyquistData(double r_meas, double i_meas, double r_corr, + double i_corr, bool showCorr) { + graphNyquistRaw->addData(r_meas, -i_meas); + if (showCorr) { + graphNyquistCorr->addData(r_corr, -i_corr); + } + graphNyquistRaw->rescaleAxes(false); + if (showCorr) { + graphNyquistCorr->rescaleAxes(true); + } + plot->replot(); +} + +void GraphWidget::addAmperometricData(double index, double current) { + graphAmp->addData(index, current); + graphAmp->rescaleAxes(false); + plot->replot(); +} + +void GraphWidget::addLSVData(double voltage, double current, + LSVTrace traceType) { + QCPGraph *target = nullptr; + switch (traceType) { + case LSV_BLANK: + target = graphLSVBlank; + break; + case LSV_SAMPLE: + target = graphLSVSample; + break; + case LSV_DIFF: + target = graphLSVDiff; + break; + } + + if (target) { + target->addData(voltage, current); + target->rescaleAxes(false); + plot->replot(); + } +} + +void GraphWidget::addHilbertData(const QVector &freq, + const QVector &hilbertImag) { + if (plot->xAxis->label() != "Frequency (Hz)") + return; + graphHilbert->setData(freq, hilbertImag); + graphHilbert->rescaleAxes(false); + plot->replot(); +} + +void GraphWidget::setExtrapolatedPoint(double real, double imag) { + graphExtrapolated->data()->clear(); + graphExtrapolated->addData(real, -imag); + plot->replot(); +} + +void GraphWidget::clear() { + graphReal->data()->clear(); + graphImag->data()->clear(); + graphHilbert->data()->clear(); + graphNyquistCorr->data()->clear(); + graphAmp->data()->clear(); + graphExtrapolated->data()->clear(); + graphFit->data()->clear(); + plot->replot(); +} + +void GraphWidget::clearLSV(LSVTrace traceType) { + if (traceType == LSV_BLANK) + graphLSVBlank->data()->clear(); + if (traceType == LSV_SAMPLE) + graphLSVSample->data()->clear(); + if (traceType == LSV_DIFF) + graphLSVDiff->data()->clear(); + plot->replot(); +} \ No newline at end of file diff --git a/examples/rp2040_port/host/src/GraphWidget.h b/examples/rp2040_port/host/src/GraphWidget.h new file mode 100644 index 0000000..108991b --- /dev/null +++ b/examples/rp2040_port/host/src/GraphWidget.h @@ -0,0 +1,78 @@ +// File: host/src/GraphWidget.h +#pragma once + +#include +#include +#include +#include +#include +#include +#include +#include +#include "qcustomplot.h" + +class GraphWidget : public QWidget { + Q_OBJECT + +public: + explicit GraphWidget(QWidget *parent = nullptr); + + // Data Handling + void addBodeData(double freq, double val1, double val2); + void addNyquistData(double r_meas, double i_meas, double r_corr, double i_corr, bool showCorr); + void addAmperometricData(double index, double current); + + enum LSVTrace { LSV_BLANK, LSV_SAMPLE, LSV_DIFF }; + void addLSVData(double voltage, double current, LSVTrace traceType); + + void addHilbertData(const QVector& freq, const QVector& hilbertImag); + void setExtrapolatedPoint(double real, double imag); + + void clear(); + void clearLSV(LSVTrace traceType); + + // View Configurations + void configureRawPlot(); + void configureNyquistPlot(); + void configureAmperometricPlot(); + void configureLSVPlot(); + +private slots: + void scaleX(); + void scaleY(); + void scaleBoth(); + void centerView(); + void startAnalyze(); + +private: + QVBoxLayout *mainLayout; + QCustomPlot *plot; + + // Toolbar + QWidget *toolbar; + QPushButton *btnScaleX; + QPushButton *btnScaleY; + QPushButton *btnScaleBoth; + QPushButton *btnCenter; + QPushButton *btnAnalyze; + + // Graphs + QCPGraph *graphReal; + QCPGraph *graphImag; + QCPGraph *graphHilbert; + QCPGraph *graphNyquistRaw; + QCPGraph *graphNyquistCorr; + QCPGraph *graphExtrapolated; + QCPGraph *graphAmp; + QCPGraph *graphLSVBlank; + QCPGraph *graphLSVSample; + QCPGraph *graphLSVDiff; + QCPGraph *graphFit; // For analysis results + + // Analysis State + bool isSelecting = false; + QCPItemRect *selectionRect; + double selStartX, selStartY; + + void performFit(const QVector& x, const QVector& y, int type, int order, bool inverse); +}; \ No newline at end of file diff --git a/examples/rp2040_port/host/src/MainWindow.cpp b/examples/rp2040_port/host/src/MainWindow.cpp new file mode 100644 index 0000000..79ba7e8 --- /dev/null +++ b/examples/rp2040_port/host/src/MainWindow.cpp @@ -0,0 +1,61 @@ +// File: host/src/MainWindow.cpp +#include "MainWindow.h" +#include +#include + +MainWindow::MainWindow(QWidget *parent) : QMainWindow(parent) { + settings = new QSettings("EISConfigurator", "Settings", this); + loadSettings(); + + serial = new QSerialPort(this); + connect(serial, &QSerialPort::readyRead, this, &MainWindow::handleSerialData); + connect(serial, &QSerialPort::errorOccurred, this, &MainWindow::onPortError); + + blinkTimer = new QTimer(this); + blinkTimer->setInterval(500); + connect(blinkTimer, &QTimer::timeout, this, &MainWindow::onBlinkTimer); + + setupUi(); // Defined in MainWindow_UI.cpp + + // Auto-refresh ports after startup + QTimer::singleShot(1000, this, &MainWindow::refreshPorts); + + grabGesture(Qt::SwipeGesture); +} + +MainWindow::~MainWindow() { + if (serial->isOpen()) { + serial->close(); + } +} + +void MainWindow::loadSettings() { + cellConstant = settings->value("cellConstant", 1.0).toDouble(); +} + +void MainWindow::saveSettings() { + settings->setValue("cellConstant", cellConstant); +} + +bool MainWindow::event(QEvent *event) { + if (event->type() == QEvent::Gesture) { + QGestureEvent *ge = static_cast(event); + if (QGesture *swipe = ge->gesture(Qt::SwipeGesture)) { + handleSwipe(static_cast(swipe)); + return true; + } + } + return QMainWindow::event(event); +} + +void MainWindow::handleSwipe(QSwipeGesture *gesture) { + if (gesture->state() == Qt::GestureFinished) { + if (gesture->horizontalDirection() == QSwipeGesture::Left) { + if (mainTabWidget->currentIndex() < mainTabWidget->count() - 1) + mainTabWidget->setCurrentIndex(mainTabWidget->currentIndex() + 1); + } else if (gesture->horizontalDirection() == QSwipeGesture::Right) { + if (mainTabWidget->currentIndex() > 0) + mainTabWidget->setCurrentIndex(mainTabWidget->currentIndex() - 1); + } + } +} \ No newline at end of file diff --git a/examples/rp2040_port/host/src/MainWindow.h b/examples/rp2040_port/host/src/MainWindow.h new file mode 100644 index 0000000..d3b2ac4 --- /dev/null +++ b/examples/rp2040_port/host/src/MainWindow.h @@ -0,0 +1,148 @@ +// File: host/src/MainWindow.h +#pragma once + +#include "GraphWidget.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +class MainWindow : public QMainWindow { + Q_OBJECT + +public: + explicit MainWindow(QWidget *parent = nullptr); + ~MainWindow(); + +protected: + bool event(QEvent *event) override; + +private slots: + // Serial Slots + void handleSerialData(); + void connectToPort(); + void refreshPorts(); + void onPortError(QSerialPort::SerialPortError error); + + // UI Slots + void onBlinkTimer(); + void onLPFChanged(int index); + + // Action Slots + void checkDeviceId(); + void runCalibration(); + void startSweep(); + void toggleMeasurement(); + void toggleAmperometry(); + + // LSV Slots + void startLSVBlank(); + void startLSVSample(); + void stopLSV(); + + void calibrateCellConstant(); + +private: + // Split Implementation Methods + void setupUi(); + void loadSettings(); + void saveSettings(); + void parseData(const QString &data); + void handleSwipe(QSwipeGesture *gesture); + void computeHilbert(); + void performCircleFit(); + void calculateLSVDiff(); + void setButtonBlinking(QPushButton *btn, bool blinking); + + // Sequence Handling + enum SequenceState { SEQ_IDLE, SEQ_WAIT_BOOT, SEQ_WAIT_CALIB }; + SequenceState currentSequence = SEQ_IDLE; + QString pendingCommand; + void initiateSequence(const QString &cmd); + + QSerialPort *serial; + QSettings *settings; + QTimer *blinkTimer; + QPushButton *activeButton = nullptr; + bool blinkState = false; + + // Views + GraphWidget *rawGraph; + GraphWidget *nyquistGraph; + GraphWidget *ampGraph; + GraphWidget *lsvGraph; + QTextEdit *logWidget; + + // Layout Containers + QTabWidget *mainTabWidget; + QTabWidget *impGraphTabs; + + // --- Global Controls --- + QComboBox *portSelector; + QPushButton *connectBtn; + QPushButton *checkIdBtn; + QPushButton *calibrateBtn; + QComboBox *comboTiaRange; + + // --- Impedance Controls --- + QDoubleSpinBox *spinSweepStart; + QDoubleSpinBox *spinSweepStop; + QSpinBox *spinSweepPPD; + QPushButton *sweepBtn; + + QDoubleSpinBox *spinFreq; + QDoubleSpinBox *spinImpBias; // New: Impedance DC Bias + QPushButton *measureBtn; + + QDoubleSpinBox *spinCondStd; + QPushButton *btnCalCond; + QLabel *lblResultRs; + QLabel *lblResultCond; + + // --- Amperometry Controls --- + QDoubleSpinBox *spinAmpBias; + QPushButton *ampBtn; + QComboBox *comboLPF; + + // --- LSV Controls --- + QDoubleSpinBox *spinLsvStart; + QDoubleSpinBox *spinLsvStop; + QSpinBox *spinLsvSteps; + QSpinBox *spinLsvDuration; + QPushButton *lsvBlankBtn; + QPushButton *lsvSampleBtn; + + // State + double cellConstant = 1.0; + bool isMeasuringImp = false; + bool isMeasuringAmp = false; + bool isSweeping = false; + int expectedSweepPoints = 0; + + enum LSVState { LSV_IDLE, LSV_RUNNING_BLANK, LSV_RUNNING_SAMPLE }; + LSVState lsvState = LSV_IDLE; + + // Data Accumulation + QVector sweepFreqs; + QVector sweepReals; + QVector sweepImags; + + struct LSVPoint { + double voltage; + double current; + }; + QVector lsvBlankData; + QVector lsvSampleData; +}; \ No newline at end of file diff --git a/examples/rp2040_port/host/src/MainWindow_Actions.cpp b/examples/rp2040_port/host/src/MainWindow_Actions.cpp new file mode 100644 index 0000000..5cd736c --- /dev/null +++ b/examples/rp2040_port/host/src/MainWindow_Actions.cpp @@ -0,0 +1,443 @@ +// File: host/src/MainWindow_Actions.cpp +#include "MainWindow.h" +#include +#include +#include +#include + +void MainWindow::checkDeviceId() { + if (serial->isOpen()) + serial->write("v\n"); +} + +void MainWindow::runCalibration() { + if (serial->isOpen()) { + int hpVal = comboTiaRange->currentData().toInt(); + serial->write(QString("r %1\n").arg(hpVal).toUtf8()); + serial->write("c\n"); + } +} + +void MainWindow::onLPFChanged(int index) { + if (serial->isOpen()) { + int val = comboLPF->itemData(index).toInt(); + serial->write(QString("f %1\n").arg(val).toUtf8()); + } +} + +// Removed: onShortRe0Se0Toggled + +void MainWindow::initiateSequence(const QString &cmd) { + if (!serial->isOpen()) + return; + + pendingCommand = cmd; + currentSequence = SEQ_WAIT_BOOT; + + logWidget->append(">> Sequence: Resetting device (z)..."); + serial->write("z\n"); // Watchdog reboot to force clean state +} + +void MainWindow::startSweep() { + if (!serial->isOpen()) + return; + + if (isSweeping) { + // Stop Sweep + serial->write("x\n"); + return; + } + + if (isMeasuringAmp) + toggleAmperometry(); + if (lsvState != LSV_IDLE) + stopLSV(); + if (isMeasuringImp) + toggleMeasurement(); + + rawGraph->clear(); + nyquistGraph->clear(); + + sweepFreqs.clear(); + sweepReals.clear(); + sweepImags.clear(); + + double start = spinSweepStart->value(); + double stop = spinSweepStop->value(); + int ppd = spinSweepPPD->value(); + double bias = spinImpBias->value(); // Use the Imp Bias control + + // Calculate Total Points based on Decades + 1 for Artifact Removal + double decades = std::log10(stop / start); + if (decades < 0) + decades = std::abs(decades); // Handle swap + + // Calculate intended total points (inclusive) + int totalPoints = (int)(decades * ppd) + 1; + if (totalPoints < 2) + totalPoints = 2; + + expectedSweepPoints = totalPoints; // Store what we want to keep + + // Send request for N+1 points to Firmware (Last point is artifact) + QString cmd = QString("s %1 %2 %3 %4") + .arg(start) + .arg(stop) + .arg(totalPoints + 1) + .arg(bias); + + isSweeping = true; + sweepBtn->setText("Stop Sweep"); + setButtonBlinking(sweepBtn, true); + + initiateSequence(cmd); +} + +void MainWindow::toggleMeasurement() { + if (!serial->isOpen()) + return; + if (isMeasuringAmp) + toggleAmperometry(); + if (lsvState != LSV_IDLE) + stopLSV(); + if (isSweeping) + startSweep(); // Stop sweep + + if (isMeasuringImp) { + serial->write("x\n"); + measureBtn->setText("Measure"); + setButtonBlinking(nullptr, false); + isMeasuringImp = false; + } else { + double freq = spinFreq->value(); + double bias = spinImpBias->value(); + QString cmd = QString("m %1 %2").arg(freq).arg(bias); + + measureBtn->setText("Stop"); + setButtonBlinking(measureBtn, true); + isMeasuringImp = true; + + initiateSequence(cmd); + } +} + +void MainWindow::toggleAmperometry() { + if (!serial->isOpen()) + return; + if (isMeasuringImp) + toggleMeasurement(); + if (lsvState != LSV_IDLE) + stopLSV(); + if (isSweeping) + startSweep(); + + if (isMeasuringAmp) { + serial->write("x\n"); + ampBtn->setText("Start Amp"); + setButtonBlinking(nullptr, false); + isMeasuringAmp = false; + } else { + double bias = spinAmpBias->value(); + QString cmd = QString("a %1").arg(bias); + + ampBtn->setText("Stop Amp"); + setButtonBlinking(ampBtn, true); + isMeasuringAmp = true; + ampGraph->clear(); + + initiateSequence(cmd); + } +} + +void MainWindow::startLSVBlank() { + if (!serial->isOpen()) + return; + + // Toggle Logic: If running, stop it. + if (lsvState == LSV_RUNNING_BLANK) { + stopLSV(); + return; + } + + if (isMeasuringImp) + toggleMeasurement(); + if (isMeasuringAmp) + toggleAmperometry(); + if (lsvState != LSV_IDLE) + stopLSV(); // Stop sample if running + if (isSweeping) + startSweep(); + + double start = spinLsvStart->value(); + double stop = spinLsvStop->value(); + int steps = spinLsvSteps->value(); + int duration = spinLsvDuration->value(); + + QString cmd = + QString("l %1 %2 %3 %4").arg(start).arg(stop).arg(steps).arg(duration); + + lsvBlankBtn->setText("Stop Blank"); + setButtonBlinking(lsvBlankBtn, true); + lsvState = LSV_RUNNING_BLANK; + + // Only clear if we are actually starting a new run + lsvGraph->clearLSV(GraphWidget::LSV_BLANK); + lsvGraph->clearLSV(GraphWidget::LSV_DIFF); + lsvBlankData.clear(); + + initiateSequence(cmd); +} + +void MainWindow::startLSVSample() { + if (!serial->isOpen()) + return; + + // Toggle Logic + if (lsvState == LSV_RUNNING_SAMPLE) { + stopLSV(); + return; + } + + if (isMeasuringImp) + toggleMeasurement(); + if (isMeasuringAmp) + toggleAmperometry(); + if (lsvState != LSV_IDLE) + stopLSV(); // Stop blank if running + if (isSweeping) + startSweep(); + + double start = spinLsvStart->value(); + double stop = spinLsvStop->value(); + int steps = spinLsvSteps->value(); + int duration = spinLsvDuration->value(); + + QString cmd = + QString("l %1 %2 %3 %4").arg(start).arg(stop).arg(steps).arg(duration); + + lsvSampleBtn->setText("Stop Sample"); + setButtonBlinking(lsvSampleBtn, true); + lsvState = LSV_RUNNING_SAMPLE; + + // Only clear if we are actually starting a new run + lsvGraph->clearLSV(GraphWidget::LSV_SAMPLE); + lsvGraph->clearLSV(GraphWidget::LSV_DIFF); + lsvSampleData.clear(); + + initiateSequence(cmd); +} + +void MainWindow::stopLSV() { + serial->write("x\n"); + lsvBlankBtn->setText("Run Blank"); + lsvSampleBtn->setText("Run Sample"); + setButtonBlinking(nullptr, false); + + // If we just finished a sample run, calculate the difference + if (lsvState == LSV_RUNNING_SAMPLE) { + calculateLSVDiff(); + } + + lsvState = LSV_IDLE; +} + +void MainWindow::calculateLSVDiff() { + if (lsvBlankData.isEmpty() || lsvSampleData.isEmpty()) + return; + + lsvGraph->clearLSV(GraphWidget::LSV_DIFF); + + // Simple index-based subtraction (assumes same parameters used) + int count = std::min(lsvBlankData.size(), lsvSampleData.size()); + + for (int i = 0; i < count; i++) { + double v = lsvSampleData[i].voltage; // Use sample voltage + double diffCurrent = lsvSampleData[i].current - lsvBlankData[i].current; + lsvGraph->addLSVData(v, diffCurrent, GraphWidget::LSV_DIFF); + } + + logWidget->append(">> Calculated Difference Curve."); +} + +void MainWindow::computeHilbert() { + int n = sweepReals.size(); + if (n == 0) + return; + + // Pad to next power of 2 for efficiency and consistency with previous logic + int n_fft = 1; + while (n_fft < n) + n_fft *= 2; + + // Allocate FFTW arrays + fftw_complex *in = (fftw_complex *)fftw_malloc(sizeof(fftw_complex) * n_fft); + fftw_complex *out = (fftw_complex *)fftw_malloc(sizeof(fftw_complex) * n_fft); + + // Create Plans (ESTIMATE is fast for one-off sizes) + fftw_plan p_fwd = + fftw_plan_dft_1d(n_fft, in, out, FFTW_FORWARD, FFTW_ESTIMATE); + fftw_plan p_bwd = + fftw_plan_dft_1d(n_fft, out, in, FFTW_BACKWARD, FFTW_ESTIMATE); + + // Prepare Input: Copy data and zero-pad + for (int i = 0; i < n; i++) { + in[i][0] = sweepReals[i]; // Real part + in[i][1] = 0.0; // Imag part + } + for (int i = n; i < n_fft; i++) { + in[i][0] = 0.0; + in[i][1] = 0.0; + } + + // Forward FFT + fftw_execute(p_fwd); + + // Apply Hilbert Mask in Frequency Domain (Analytic Signal) + // H[0] (DC) and H[N/2] (Nyquist) are left alone. + // Positive Frequencies (1 to N/2 - 1) multiplied by 2. + // Negative Frequencies (N/2 + 1 to N - 1) zeroed out. + + int half_n = n_fft / 2; + + // Multiply positive frequencies by 2 + for (int i = 1; i < half_n; i++) { + out[i][0] *= 2.0; + out[i][1] *= 2.0; + } + + // Zero out negative frequencies + for (int i = half_n + 1; i < n_fft; i++) { + out[i][0] = 0.0; + out[i][1] = 0.0; + } + + // Inverse FFT + fftw_execute(p_bwd); + + // Extract Imaginary part of Analytic Signal (Hilbert Transform) + // Note: FFTW IFFT is unnormalized, divide by N + QVector hilbertImag; + hilbertImag.reserve(n); + + for (int i = 0; i < n; i++) { + double val = in[i][1] / n_fft; // Imaginary part normalized + hilbertImag.append(val); + } + + rawGraph->addHilbertData(sweepFreqs, hilbertImag); + + // Cleanup + fftw_destroy_plan(p_fwd); + fftw_destroy_plan(p_bwd); + fftw_free(in); + fftw_free(out); +} + +void MainWindow::performCircleFit() { + int n = sweepReals.size(); + if (n < 5) + return; + + // 1. Centering (Crucial for stability) + double meanX = 0, meanY = 0; + for (int i = 0; i < n; i++) { + meanX += sweepReals[i]; + meanY += -sweepImags[i]; + } + meanX /= n; + meanY /= n; + + // 2. Kasa Fit (Algebraic) on Centered Data + // Minimizes sum((x^2 + y^2) - (2Ax + 2By + C))^2 + + double sum_x2 = 0, sum_y2 = 0, sum_xy = 0; + double sum_z = 0, sum_zx = 0, sum_zy = 0; + + for (int i = 0; i < n; i++) { + double xi = sweepReals[i] - meanX; + double yi = -sweepImags[i] - meanY; + double zi = xi * xi + yi * yi; + + sum_x2 += xi * xi; + sum_y2 += yi * yi; + sum_xy += xi * yi; + sum_z += zi; + sum_zx += zi * xi; + sum_zy += zi * yi; + } + + // Solve 3x3 Linear System (Normal Equations) for Centered Kasa + // [ 4*sum_x2 4*sum_xy 0 ] [ A ] [ 2*sum_zx ] + // [ 4*sum_xy 4*sum_y2 0 ] [ B ] = [ 2*sum_zy ] + // [ 0 0 n ] [ C ] [ sum_z ] + + double C = sum_z / n; + + // Solve 2x2 for A, B + double D = 16 * (sum_x2 * sum_y2 - sum_xy * sum_xy); + + if (std::abs(D) < 1e-9) + return; // Collinear or insufficient data + + double A = (2 * sum_zx * 4 * sum_y2 - 2 * sum_zy * 4 * sum_xy) / D; + double B = (4 * sum_x2 * 2 * sum_zy - 4 * sum_xy * 2 * sum_zx) / D; + + double xc = A + meanX; + double yc = B + meanY; + double r_sq = A * A + B * B + C; + + if (r_sq <= 0) + return; + double r = std::sqrt(r_sq); + + // Calculate Intercepts with Real Axis (y=0) + // (x - xc)^2 + (0 - yc)^2 = r^2 + // (x - xc)^2 = r^2 - yc^2 + + double term = r * r - yc * yc; + if (term < 0) + return; // Circle doesn't intersect real axis + + double x1 = xc - std::sqrt(term); + double x2 = xc + std::sqrt(term); + + double Rs = std::min(x1, x2); + if (Rs < 0) + Rs = std::max(x1, x2); // If one is negative, take the positive one + + if (Rs > 0) { + lblResultRs->setText(QString(" Rs: %1 Ω").arg(Rs, 0, 'f', 2)); + + double cond = (cellConstant / Rs) * 1000000.0; + lblResultCond->setText(QString(" Cond: %1 µS/cm").arg(cond, 0, 'f', 2)); + + nyquistGraph->setExtrapolatedPoint(Rs, 0); + } +} + +void MainWindow::calibrateCellConstant() { + QString txt = lblResultRs->text(); + if (txt.contains("--")) { + QMessageBox::warning(this, "Calibration Error", + "No valid Rs measurement found. Run a sweep first."); + return; + } + + QString numStr = txt.section(':', 1).section(QChar(0x03A9), 0, 0).trimmed(); + double measuredRs = numStr.toDouble(); + + if (measuredRs <= 0) + return; + + double stdCond = spinCondStd->value(); + + cellConstant = (stdCond * 1e-6) * measuredRs; + + saveSettings(); + + QMessageBox::information(this, "Calibration Success", + QString("Cell Constant (K) calibrated to: %1 cm⁻¹") + .arg(cellConstant, 0, 'f', 4)); + + performCircleFit(); +} \ No newline at end of file diff --git a/examples/rp2040_port/host/src/MainWindow_Serial.cpp b/examples/rp2040_port/host/src/MainWindow_Serial.cpp new file mode 100644 index 0000000..902a34a --- /dev/null +++ b/examples/rp2040_port/host/src/MainWindow_Serial.cpp @@ -0,0 +1,267 @@ +// File: host/src/MainWindow_Serial.cpp +#include "MainWindow.h" +#include +#include + +void MainWindow::refreshPorts() { + portSelector->clear(); + const auto infos = QSerialPortInfo::availablePorts(); + bool foundTarget = false; + QString targetPort; + + for (const QSerialPortInfo &info : infos) { + portSelector->addItem(info.portName()); + bool isCafe = + (info.hasVendorIdentifier() && info.vendorIdentifier() == 0xCAFE); + bool isUsbModem = info.portName().contains("usbmodem", Qt::CaseInsensitive); + if ((isCafe || isUsbModem) && !foundTarget) { + targetPort = info.portName(); + foundTarget = true; + logWidget->append(">> Found Target Device: " + targetPort); + } + } + if (foundTarget) { + portSelector->setCurrentText(targetPort); + if (!serial->isOpen()) + connectToPort(); + } +} + +void MainWindow::connectToPort() { + if (serial->isOpen()) { + serial->close(); + connectBtn->setText("Connect"); + logWidget->append("--- Disconnected ---"); + + // 1. Disable Global Controls + checkIdBtn->setEnabled(false); + calibrateBtn->setEnabled(false); + comboTiaRange->setEnabled(false); + + // 2. Disable Tabs + mainTabWidget->widget(0)->setEnabled(false); + mainTabWidget->widget(1)->setEnabled(false); + mainTabWidget->widget(2)->setEnabled(false); + + isMeasuringImp = false; + isMeasuringAmp = false; + isSweeping = false; + lsvState = LSV_IDLE; + currentSequence = SEQ_IDLE; + setButtonBlinking(nullptr, false); + + measureBtn->setText("Measure"); + ampBtn->setText("Start Amp"); + lsvBlankBtn->setText("Run Blank"); + lsvSampleBtn->setText("Run Sample"); + return; + } + + if (portSelector->currentText().isEmpty()) + return; + + serial->setPortName(portSelector->currentText()); + serial->setBaudRate(500000); + + if (serial->open(QIODevice::ReadWrite)) { + connectBtn->setText("Disconnect"); + logWidget->append("--- Connected and Synchronized ---"); + + // 1. Enable Global Controls + checkIdBtn->setEnabled(true); + calibrateBtn->setEnabled(true); + comboTiaRange->setEnabled(true); + + // 2. Enable Tabs + mainTabWidget->widget(0)->setEnabled(true); + mainTabWidget->widget(1)->setEnabled(true); + mainTabWidget->widget(2)->setEnabled(true); + + // Sync LPF + onLPFChanged(comboLPF->currentIndex()); + } else { + logWidget->append(">> Connection Error: " + serial->errorString()); + } +} + +void MainWindow::onPortError(QSerialPort::SerialPortError error) { + if (error == QSerialPort::ResourceError) { + logWidget->append(">> Critical Error: Connection Lost."); + serial->close(); + connectBtn->setText("Connect"); + + checkIdBtn->setEnabled(false); + calibrateBtn->setEnabled(false); + comboTiaRange->setEnabled(false); + + mainTabWidget->widget(0)->setEnabled(false); + mainTabWidget->widget(1)->setEnabled(false); + mainTabWidget->widget(2)->setEnabled(false); + + setButtonBlinking(nullptr, false); + currentSequence = SEQ_IDLE; + } +} + +void MainWindow::handleSerialData() { + while (serial->canReadLine()) { + QByteArray line = serial->readLine(); + QString str = QString::fromUtf8(line).trimmed(); + if (str.isEmpty()) + continue; + + QString timestamp = QDateTime::currentDateTime().toString("HH:mm:ss.zzz"); + logWidget->append(QString("[%1] %2").arg(timestamp, str)); + logWidget->moveCursor(QTextCursor::End); + + // --- Sequence State Machine --- + if (currentSequence == SEQ_WAIT_BOOT) { + if (str.contains("AD5940LIB Version:v0.2.1")) { + logWidget->append(">> Sequence: Boot detected. Configuring..."); + + // 1. Restore Settings + int hpVal = comboTiaRange->currentData().toInt(); + serial->write(QString("r %1\n").arg(hpVal).toUtf8()); + + serial->write(QString("t 0\n").toUtf8()); + + // 2. Start Calibration + logWidget->append(">> Sequence: Calibrating..."); + serial->write("c\n"); + + currentSequence = SEQ_WAIT_CALIB; + } + } else if (currentSequence == SEQ_WAIT_CALIB) { + if (str.contains("RCAL,HSTIA")) { + logWidget->append(">> Sequence: Calibration Done. Sending Command."); + serial->write(pendingCommand.toUtf8()); + serial->write("\n"); + currentSequence = SEQ_IDLE; + } + } + // ------------------------------ + + if (str.startsWith("DATA,")) { + parseData(str); + } else if (str.startsWith("RCAL,")) { + parseData(str); + } else if (str.startsWith("AMP,")) { + parseData(str); + } else if (str.startsWith("RAMP,")) { + parseData(str); + } else if (str == "STOPPED") { + // Reset UI state + if (lsvState != LSV_IDLE) + stopLSV(); + if (isSweeping) { + isSweeping = false; + sweepBtn->setText("Sweep"); + setButtonBlinking(nullptr, false); + } + if (isMeasuringImp) { + isMeasuringImp = false; + measureBtn->setText("Measure"); + setButtonBlinking(nullptr, false); + } + if (isMeasuringAmp) { + isMeasuringAmp = false; + ampBtn->setText("Start Amp"); + setButtonBlinking(nullptr, false); + } + } + } +} + +void MainWindow::parseData(const QString &data) { + QStringList parts = data.split(','); + + if (parts[0] == "AMP" && parts.size() >= 3) { + bool okIdx, okCurr; + double index = parts[1].toDouble(&okIdx); + double current = parts[2].toDouble(&okCurr); + if (okIdx && okCurr) + ampGraph->addAmperometricData(index, current); + return; + } + + if (parts[0] == "RAMP" && parts.size() >= 3) { + bool okIdx, okCurr; + double index = parts[1].toDouble(&okIdx); + double current = parts[2].toDouble(&okCurr); + + if (okIdx && okCurr) { + // Calculate Voltage based on UI parameters (Host-side calculation) + double start = spinLsvStart->value(); + double stop = spinLsvStop->value(); + int steps = spinLsvSteps->value(); + + double voltage = start + (index * (stop - start) / steps); + + if (lsvState == LSV_RUNNING_BLANK) { + lsvGraph->addLSVData(voltage, current, GraphWidget::LSV_BLANK); + lsvBlankData.append({voltage, current}); + } else if (lsvState == LSV_RUNNING_SAMPLE) { + lsvGraph->addLSVData(voltage, current, GraphWidget::LSV_SAMPLE); + lsvSampleData.append({voltage, current}); + } + } + return; + } + + if (parts[0] == "RCAL" && parts.size() >= 4) { + QString type = parts[1]; + if (type == "FAIL") { + logWidget->append(QString(">> RCAL FAIL: %1").arg(data)); + return; + } + bool okM, okP; + double mag = parts[2].toDouble(&okM); + double phase = parts[3].toDouble(&okP); + + if (okM && okP) { + logWidget->append(QString(">> Calibration [%1]: Mag=%.2f Phase=%.2f") + .arg(type) + .arg(mag) + .arg(phase)); + // TODO: Store this if needed for UI display + } + return; + } + + if (parts[0] == "DATA" && parts.size() >= 6) { + bool okF, okM, okP; + double freq = parts[1].toDouble(&okF); + double mag = parts[4].toDouble(&okM); + double phase = parts[5].toDouble(&okP); + + if (okF && okM && okP) { + // 1. Plot Bode (Magnitude/Phase) + // Note: Phase from AD5940 is in Radians. + rawGraph->addBodeData(freq, mag, phase); + + // 2. Convert to Cartesian for Nyquist (Real/Imaginary) + // Z = Mag * e^(j*Phase) = Mag * (cos(Phase) + j*sin(Phase)) + // Note: Nyquist Plot expects Z' vs -Z''. + std::complex z = std::polar(mag, phase); + double real = z.real(); + double imag = + z.imag(); // This is Z''. GraphWidget negates it for the plot. + + nyquistGraph->addNyquistData(real, imag, real, imag, false); + + if (sweepFreqs.size() >= expectedSweepPoints) { + // Discard extra points (Artifact removal) + return; + } + + sweepFreqs.append(freq); + sweepReals.append(real); + sweepImags.append(imag); + + if (sweepReals.size() > 10 && sweepReals.size() % 10 == 0) { + computeHilbert(); + performCircleFit(); + } + } + } +} \ No newline at end of file diff --git a/examples/rp2040_port/host/src/MainWindow_UI.cpp b/examples/rp2040_port/host/src/MainWindow_UI.cpp new file mode 100644 index 0000000..3584bdb --- /dev/null +++ b/examples/rp2040_port/host/src/MainWindow_UI.cpp @@ -0,0 +1,392 @@ +// File: host/src/MainWindow_UI.cpp +#include "MainWindow.h" +#include +#include +#include +#include +#include +#include + +void MainWindow::setupUi() { + QWidget *central = new QWidget(this); + setCentralWidget(central); + QVBoxLayout *mainLayout = new QVBoxLayout(central); + mainLayout->setContentsMargins(2, 2, 2, 2); + mainLayout->setSpacing(2); + + // ======================================================================== + // 1. Global Toolbar (Connection & Hardware Settings) + // ======================================================================== + QGroupBox *globalGroup = new QGroupBox("Connection & Hardware", this); + globalGroup->setStyleSheet( + "QGroupBox { font-weight: bold; border: 1px solid #555; border-radius: " + "4px; margin-top: 6px; } QGroupBox::title { subcontrol-origin: margin; " + "left: 10px; padding: 0 3px; }"); + QVBoxLayout *globalLayout = new QVBoxLayout(globalGroup); + globalLayout->setContentsMargins(4, 12, 4, 4); + globalLayout->setSpacing(4); + + // Row 1: Connection + QHBoxLayout *connLayout = new QHBoxLayout(); + portSelector = new QComboBox(this); + portSelector->setMinimumWidth(120); + connectBtn = new QPushButton("Connect", this); + connectBtn->setStyleSheet("background-color: rgba(0, 128, 0, 128); color: " + "white; font-weight: bold;"); + QPushButton *refreshBtn = new QPushButton("Refresh", this); + checkIdBtn = new QPushButton("Check ID", this); + + connLayout->addWidget(portSelector, 1); + connLayout->addWidget(connectBtn); + connLayout->addWidget(refreshBtn); + connLayout->addWidget(checkIdBtn); + globalLayout->addLayout(connLayout); + + // Row 2: Hardware Config + QHBoxLayout *hwLayout = new QHBoxLayout(); + + comboTiaRange = new QComboBox(this); + comboTiaRange->setToolTip("High Speed TIA Range"); + comboTiaRange->addItem("100 Ω (RCAL)", 100); + comboTiaRange->addItem("200 Ω (Internal)", 200); + comboTiaRange->addItem("1 kΩ (Internal)", 1000); + // Removed >1k options to prevent saturation + comboTiaRange->setCurrentIndex(1); // Default 200 (Index 1) + + calibrateBtn = new QPushButton("Calibrate HW", this); + calibrateBtn->setStyleSheet("background-color: rgba(255, 255, 0, 102); " + "color: white; font-weight: bold;"); + + // Removed: checkShortRe0Se0 + + hwLayout->addWidget(new QLabel("TIA Range:")); + hwLayout->addWidget(comboTiaRange, 1); + // Removed: hwLayout->addWidget(checkShortRe0Se0); + hwLayout->addWidget(calibrateBtn); + globalLayout->addLayout(hwLayout); + + mainLayout->addWidget(globalGroup); + + // ======================================================================== + // 2. Main Tab Widget (Modes) + // ======================================================================== + mainTabWidget = new QTabWidget(this); + + // --- Tab 1: Impedance (Sweep & Single) --- + QWidget *impTab = new QWidget(); + QVBoxLayout *impLayout = new QVBoxLayout(impTab); + impLayout->setContentsMargins(4, 4, 4, 4); + + // Controls Area + QGroupBox *impCtrlGroup = new QGroupBox("Impedance Controls", impTab); + QVBoxLayout *impCtrlLayout = new QVBoxLayout(impCtrlGroup); + + // Sweep Row + QHBoxLayout *sweepLayout = new QHBoxLayout(); + spinSweepStart = new QDoubleSpinBox(); + spinSweepStart->setRange(0.1, 200000.0); + spinSweepStart->setValue(1000.0); + spinSweepStart->setSuffix(" Hz"); + spinSweepStop = new QDoubleSpinBox(); + spinSweepStop->setRange(0.1, 200000.0); + spinSweepStop->setValue(200000.0); + spinSweepStop->setSuffix(" Hz"); + spinSweepPPD = new QSpinBox(); + spinSweepPPD->setRange(1, 1000); + spinSweepPPD->setValue(200); + spinSweepPPD->setSuffix(" pts/dec"); + sweepBtn = new QPushButton("Sweep"); + sweepBtn->setStyleSheet("background-color: rgba(173, 216, 230, 76); color: " + "white; font-weight: bold;"); + + sweepLayout->addWidget(new QLabel("Start:")); + sweepLayout->addWidget(spinSweepStart); + sweepLayout->addWidget(new QLabel("Stop:")); + sweepLayout->addWidget(spinSweepStop); + sweepLayout->addWidget(new QLabel("PPD:")); + sweepLayout->addWidget(spinSweepPPD); + sweepLayout->addWidget(sweepBtn); + impCtrlLayout->addLayout(sweepLayout); + + // Single Freq & Calibration Row + QHBoxLayout *singleLayout = new QHBoxLayout(); + spinFreq = new QDoubleSpinBox(); + spinFreq->setRange(0.1, 200000.0); + spinFreq->setValue(1000.0); + spinFreq->setSuffix(" Hz"); + + // New Bias Control + spinImpBias = new QDoubleSpinBox(); + spinImpBias->setRange(-3000.0, 3000.0); + spinImpBias->setValue(0.0); + spinImpBias->setSuffix(" mV"); + spinImpBias->setToolTip("DC Bias Voltage"); + + measureBtn = new QPushButton("Measure"); + measureBtn->setStyleSheet("background-color: rgba(0, 100, 0, 76); color: " + "white; font-weight: bold;"); + + spinCondStd = new QDoubleSpinBox(); + spinCondStd->setRange(0.0, 1000000.0); + spinCondStd->setValue(1413.0); + spinCondStd->setSuffix(" µS/cm"); + btnCalCond = new QPushButton("Cal K"); + btnCalCond->setStyleSheet("background-color: rgba(255, 165, 0, 102); color: " + "white; font-weight: bold;"); + + singleLayout->addWidget(new QLabel("Freq:")); + singleLayout->addWidget(spinFreq); + singleLayout->addWidget(new QLabel("Bias:")); + singleLayout->addWidget(spinImpBias); + singleLayout->addWidget(measureBtn); + // Removed Shunt controls + singleLayout->addWidget(new QLabel("Std:")); + singleLayout->addWidget(spinCondStd); + singleLayout->addWidget(btnCalCond); + impCtrlLayout->addLayout(singleLayout); + + // Results Row + QHBoxLayout *resLayout = new QHBoxLayout(); + lblResultRs = new QLabel(" Rs: -- Ω"); + lblResultRs->setStyleSheet( + "font-weight: bold; color: #FFD700; font-size: 14px;"); + lblResultCond = new QLabel("Cond: -- µS/cm"); + lblResultCond->setStyleSheet( + "font-weight: bold; color: #00FFFF; font-size: 14px;"); + resLayout->addWidget(lblResultRs); + resLayout->addWidget(lblResultCond); + resLayout->addStretch(); + impCtrlLayout->addLayout(resLayout); + + impLayout->addWidget(impCtrlGroup); + + // Graphs (Nested Tab) + impGraphTabs = new QTabWidget(); + rawGraph = new GraphWidget(this); + rawGraph->configureRawPlot(); + nyquistGraph = new GraphWidget(this); + nyquistGraph->configureNyquistPlot(); + + impGraphTabs->addTab(rawGraph, "Bode Plot"); + impGraphTabs->addTab(nyquistGraph, "Nyquist Plot"); + impLayout->addWidget(impGraphTabs); + + mainTabWidget->addTab(impTab, "Impedance"); + + // --- Tab 2: Amperometry --- + QWidget *ampTab = new QWidget(); + QVBoxLayout *ampLayout = new QVBoxLayout(ampTab); + ampLayout->setContentsMargins(4, 4, 4, 4); + + QGroupBox *ampCtrlGroup = new QGroupBox("Amperometry Controls", ampTab); + QHBoxLayout *ampCtrlLayout = new QHBoxLayout(ampCtrlGroup); + + spinAmpBias = new QDoubleSpinBox(); + spinAmpBias->setRange(-3000.0, 3000.0); + spinAmpBias->setValue(0.0); + spinAmpBias->setSuffix(" mV"); + comboLPF = new QComboBox(); + comboLPF->addItem("Bypass", 0); + comboLPF->addItem("20kΩ (8Hz)", 1); + comboLPF->addItem("100kΩ (1.6Hz)", 2); + comboLPF->addItem("200kΩ (0.8Hz)", 3); + comboLPF->addItem("400kΩ (0.4Hz)", 4); + comboLPF->addItem("600kΩ (0.26Hz)", 5); + comboLPF->addItem("1MΩ (0.16Hz)", 6); + comboLPF->setCurrentIndex(1); + + ampBtn = new QPushButton("Start Amp"); + ampBtn->setStyleSheet("background-color: rgba(238, 130, 238, 51); color: " + "white; font-weight: bold;"); + + ampCtrlLayout->addWidget(new QLabel("Bias:")); + ampCtrlLayout->addWidget(spinAmpBias); + ampCtrlLayout->addWidget(new QLabel("LPF:")); + ampCtrlLayout->addWidget(comboLPF); + ampCtrlLayout->addWidget(ampBtn); + + ampLayout->addWidget(ampCtrlGroup); + + ampGraph = new GraphWidget(this); + ampGraph->configureAmperometricPlot(); + ampLayout->addWidget(ampGraph); + + mainTabWidget->addTab(ampTab, "Amperometry"); + + // --- Tab 3: Voltammetry (LSV) --- + QWidget *lsvTab = new QWidget(); + QVBoxLayout *lsvLayout = new QVBoxLayout(lsvTab); + lsvLayout->setContentsMargins(4, 4, 4, 4); + + QGroupBox *lsvCtrlGroup = new QGroupBox("LSV Controls", lsvTab); + QHBoxLayout *lsvCtrlLayout = new QHBoxLayout(lsvCtrlGroup); + + spinLsvStart = new QDoubleSpinBox(); + spinLsvStart->setRange(-3000.0, 3000.0); + spinLsvStart->setValue(800.0); + spinLsvStart->setSuffix(" mV"); + spinLsvStop = new QDoubleSpinBox(); + spinLsvStop->setRange(-3000.0, 3000.0); + spinLsvStop->setValue(-200.0); + spinLsvStop->setSuffix(" mV"); + spinLsvSteps = new QSpinBox(); + spinLsvSteps->setRange(10, 4000); + spinLsvSteps->setValue(200); + spinLsvSteps->setSuffix(" pts"); + spinLsvDuration = new QSpinBox(); + spinLsvDuration->setRange(100, 600000); + spinLsvDuration->setValue(10000); + spinLsvDuration->setSuffix(" ms"); + + lsvBlankBtn = new QPushButton("Run Blank"); + lsvBlankBtn->setStyleSheet( + "background-color: rgba(0, 0, 0, 255); color: white; font-weight: bold;"); + lsvSampleBtn = new QPushButton("Run Sample"); + lsvSampleBtn->setStyleSheet("background-color: rgba(75, 0, 130, 76); color: " + "white; font-weight: bold;"); + + lsvCtrlLayout->addWidget(new QLabel("Start:")); + lsvCtrlLayout->addWidget(spinLsvStart); + lsvCtrlLayout->addWidget(new QLabel("Stop:")); + lsvCtrlLayout->addWidget(spinLsvStop); + lsvCtrlLayout->addWidget(new QLabel("Steps:")); + lsvCtrlLayout->addWidget(spinLsvSteps); + lsvCtrlLayout->addWidget(new QLabel("Time:")); + lsvCtrlLayout->addWidget(spinLsvDuration); + lsvCtrlLayout->addWidget(lsvBlankBtn); + lsvCtrlLayout->addWidget(lsvSampleBtn); + + lsvLayout->addWidget(lsvCtrlGroup); + + lsvGraph = new GraphWidget(this); + lsvGraph->configureLSVPlot(); + lsvLayout->addWidget(lsvGraph); + + mainTabWidget->addTab(lsvTab, "Voltammetry"); + + // ======================================================================== + // 3. Log Widget (Bottom) + // ======================================================================== + logWidget = new QTextEdit(this); + logWidget->setReadOnly(true); + logWidget->setFont(QFont("Monospace")); + logWidget->setPlaceholderText("Scanning for 0xCAFE EIS Device..."); + logWidget->setStyleSheet( + "background-color: #1E1E1E; color: #00FF00; border: 1px solid #444;"); + logWidget->setMaximumHeight(150); + QScroller::grabGesture(logWidget->viewport(), QScroller::TouchGesture); + + // Add to Main Layout + QSplitter *splitter = new QSplitter(Qt::Vertical, this); + splitter->addWidget(mainTabWidget); + splitter->addWidget(logWidget); + splitter->setStretchFactor(0, 4); + splitter->setStretchFactor(1, 1); + + mainLayout->addWidget(splitter); + + // ======================================================================== + // Initial State & Connections + // ======================================================================== + checkIdBtn->setEnabled(false); + calibrateBtn->setEnabled(false); + + comboTiaRange->setEnabled(false); + + // Disable all mode controls initially + impTab->setEnabled(false); + ampTab->setEnabled(false); + lsvTab->setEnabled(false); + + // Connections + connect(connectBtn, &QPushButton::clicked, this, &MainWindow::connectToPort); + connect(refreshBtn, &QPushButton::clicked, this, &MainWindow::refreshPorts); + connect(checkIdBtn, &QPushButton::clicked, this, &MainWindow::checkDeviceId); + connect(calibrateBtn, &QPushButton::clicked, this, + &MainWindow::runCalibration); + + connect(sweepBtn, &QPushButton::clicked, this, &MainWindow::startSweep); + connect(measureBtn, &QPushButton::clicked, this, + &MainWindow::toggleMeasurement); + connect(ampBtn, &QPushButton::clicked, this, &MainWindow::toggleAmperometry); + connect(lsvBlankBtn, &QPushButton::clicked, this, &MainWindow::startLSVBlank); + connect(lsvSampleBtn, &QPushButton::clicked, this, + &MainWindow::startLSVSample); + connect(btnCalCond, &QPushButton::clicked, this, + &MainWindow::calibrateCellConstant); + connect(comboLPF, QOverload::of(&QComboBox::currentIndexChanged), this, + &MainWindow::onLPFChanged); + + connect(mainTabWidget, &QTabWidget::currentChanged, this, [this](int index) { + if (index == 0) + rawGraph->configureRawPlot(); + else if (index == 1) + ampGraph->configureAmperometricPlot(); + else if (index == 2) + lsvGraph->configureLSVPlot(); + }); +} + +void MainWindow::setButtonBlinking(QPushButton *btn, bool blinking) { + if (activeButton && activeButton != btn) { + // Restore original colors manually based on button type + if (activeButton == sweepBtn) + activeButton->setStyleSheet("background-color: rgba(173, 216, 230, 76); " + "color: white; font-weight: bold;"); + else if (activeButton == measureBtn) + activeButton->setStyleSheet("background-color: rgba(0, 100, 0, 76); " + "color: white; font-weight: bold;"); + else if (activeButton == ampBtn) + activeButton->setStyleSheet("background-color: rgba(238, 130, 238, 51); " + "color: white; font-weight: bold;"); + else if (activeButton == lsvBlankBtn) + activeButton->setStyleSheet("background-color: rgba(0, 0, 0, 255); " + "color: white; font-weight: bold;"); + else if (activeButton == lsvSampleBtn) + activeButton->setStyleSheet("background-color: rgba(75, 0, 130, 76); " + "color: white; font-weight: bold;"); + } + + activeButton = btn; + + if (blinking) { + blinkTimer->start(); + } else { + blinkTimer->stop(); + if (activeButton) { + // Restore original colors manually + if (activeButton == sweepBtn) + activeButton->setStyleSheet("background-color: rgba(173, 216, 230, " + "76); color: white; font-weight: bold;"); + else if (activeButton == measureBtn) + activeButton->setStyleSheet("background-color: rgba(0, 100, 0, 76); " + "color: white; font-weight: bold;"); + else if (activeButton == ampBtn) + activeButton->setStyleSheet("background-color: rgba(238, 130, 238, " + "51); color: white; font-weight: bold;"); + else if (activeButton == lsvBlankBtn) + activeButton->setStyleSheet("background-color: rgba(0, 0, 0, 255); " + "color: white; font-weight: bold;"); + else if (activeButton == lsvSampleBtn) + activeButton->setStyleSheet("background-color: rgba(75, 0, 130, 76); " + "color: white; font-weight: bold;"); + } + activeButton = nullptr; + } +} + +void MainWindow::onBlinkTimer() { + if (!activeButton) + return; + + blinkState = !blinkState; + if (blinkState) { + activeButton->setStyleSheet( + "background-color: #FF0000; color: white; border: 1px solid #FF4444; " + "font-weight: bold;"); + } else { + activeButton->setStyleSheet( + "background-color: #880000; color: white; border: 1px solid #AA0000; " + "font-weight: bold;"); + } +} \ No newline at end of file diff --git a/examples/rp2040_port/host/src/main.cpp b/examples/rp2040_port/host/src/main.cpp new file mode 100644 index 0000000..8668905 --- /dev/null +++ b/examples/rp2040_port/host/src/main.cpp @@ -0,0 +1,92 @@ +// host/src/main.cpp +#include +#include +#include +#include +#include "MainWindow.h" + +// Helper to request permissions sequentially +void requestAndroidPermissions() { +#ifdef Q_OS_ANDROID + // Request Location Permission + // Required for hardware discovery (BLE/WiFi) and sometimes USB device enumeration on Android. + // Note: Storage permissions are handled via the Manifest and Scoped Storage; + // explicit runtime requests for storage are often not needed for AppData folders. + + qApp->requestPermission(QLocationPermission{}, [](const QPermission &permission) { + if (permission.status() == Qt::PermissionStatus::Granted) { + qDebug() << "Location Permission Granted"; + } else { + qWarning() << "Location Permission Denied"; + } + }); +#endif +} + +int main(int argc, char *argv[]) { + // High DPI Scaling + QCoreApplication::setAttribute(Qt::AA_EnableHighDpiScaling); + QCoreApplication::setAttribute(Qt::AA_UseHighDpiPixmaps); + + QApplication app(argc, argv); + QApplication::setApplicationName("EIS Configurator"); + QApplication::setApplicationVersion("1.0"); + + // --- Apply Dark Fusion Theme --- + app.setStyle(QStyleFactory::create("Fusion")); + + QPalette p; + p.setColor(QPalette::Window, QColor(53, 53, 53)); + p.setColor(QPalette::WindowText, Qt::white); + p.setColor(QPalette::Base, QColor(25, 25, 25)); + p.setColor(QPalette::AlternateBase, QColor(53, 53, 53)); + p.setColor(QPalette::ToolTipBase, Qt::white); + p.setColor(QPalette::ToolTipText, Qt::white); + p.setColor(QPalette::Text, Qt::white); + p.setColor(QPalette::Button, QColor(53, 53, 53)); + p.setColor(QPalette::ButtonText, Qt::white); + p.setColor(QPalette::BrightText, Qt::red); + p.setColor(QPalette::Link, QColor(42, 130, 218)); + p.setColor(QPalette::Highlight, QColor(42, 130, 218)); + p.setColor(QPalette::HighlightedText, Qt::black); + app.setPalette(p); + + // --- Global Stylesheet for Modern Look --- + app.setStyleSheet( + "QToolTip { color: #ffffff; background-color: #2a82da; border: 1px solid white; }" + "QGroupBox { border: 1px solid #555; border-radius: 5px; margin-top: 10px; font-weight: bold; }" + "QGroupBox::title { subcontrol-origin: margin; left: 10px; padding: 0 3px; }" + "QSpinBox, QDoubleSpinBox, QComboBox, QLineEdit { " + " background: #333; color: #FFF; border: 1px solid #555; padding: 4px; border-radius: 4px; " + " selection-background-color: #2A82DA; " + "}" + "QSpinBox::up-button, QDoubleSpinBox::up-button, QSpinBox::down-button, QDoubleSpinBox::down-button { " + " background: #444; width: 16px; border-radius: 2px;" + "}" + "QPushButton { " + " background-color: #444; border: 1px solid #555; border-radius: 4px; padding: 5px 15px; color: white; font-weight: bold;" + "}" + "QPushButton:hover { background-color: #555; }" + "QPushButton:pressed { background-color: #2A82DA; }" + "QPushButton:disabled { background-color: #333; color: #777; border: 1px solid #444; }" + "QTabWidget::pane { border: 1px solid #444; }" + "QTabBar::tab { background: #333; color: #AAA; padding: 8px 20px; border-top-left-radius: 4px; border-top-right-radius: 4px; }" + "QTabBar::tab:selected { background: #535353; color: #FFF; border-bottom: 2px solid #2A82DA; }" + "QScrollBar:vertical { background: #333; width: 12px; }" + "QScrollBar::handle:vertical { background: #555; min-height: 20px; border-radius: 6px; }" + "QLabel { color: #EEE; }" + ); + + // Set default font size + QFont font = app.font(); + font.setPointSize(12); + app.setFont(font); + + // Request Android Permissions at startup + requestAndroidPermissions(); + + MainWindow w; + w.show(); + + return app.exec(); +} \ No newline at end of file diff --git a/examples/rp2040_port/main.c b/examples/rp2040_port/main.c new file mode 100644 index 0000000..25e4bce --- /dev/null +++ b/examples/rp2040_port/main.c @@ -0,0 +1,175 @@ +// File: main.c +#include "App_Common.h" + +// --- Global Variables --- +uint32_t AppBuff[APPBUFF_SIZE]; +AppMode CurrentMode = MODE_IDLE; +float LFOSCFreq = 32000.0; +uint32_t g_AmpIndex = 0; +uint32_t g_RampIndex = 0; + +uint32_t ConfigLptiaVal = 100000; +uint32_t ConfigHstiaVal = 1000; +uint32_t CurrentLpTiaRf = LPTIARF_20K; +uint32_t ConfigRLoad = LPTIARLOAD_100R; +float CalibratedLptiaVal = 100000.0; +float CalibratedHstiaVal = 1000.0; // Default nominal +float CalibratedHstiaPhase = 0.0; // Default 0 phase shift +BoolFlag GlobalShortRe0Se0 = bFALSE; + +char input_buffer[64]; +int input_pos = 0; + +void process_command() { + char cmd = input_buffer[0]; + sleep_ms(10); + + if (cmd == 'v') { + uint32_t id = AD5940_ReadReg(REG_AFECON_CHIPID); + printf("CHIP_ID:0x%04X\n", id); + } else if (cmd == 'r') { + if (strlen(input_buffer) > 2) { + int hp = 0; + int count = sscanf(input_buffer + 2, "%d", &hp); + if (count >= 1) { + ConfigHstiaVal = hp; + CalibratedHstiaVal = + (float)hp; // Fix: Reset calibration to nominal when range changes + } + printf("RANGE_SET HP:%d\n", ConfigHstiaVal); + } + } else if (cmd == 't') { + if (strlen(input_buffer) > 2) { + int val = atoi(input_buffer + 2); + GlobalShortRe0Se0 = (val > 0) ? bTRUE : bFALSE; + printf("SHORT_RE0_SE0:%d\n", GlobalShortRe0Se0); + } + } else if (cmd == 'c') { + Routine_CalibrateLFO(); + Routine_CalibrateSystem(); + } else if (cmd == 'm') { + float freq = 1000.0f; + float bias = 0.0f; + if (strlen(input_buffer) > 2) { + int count = sscanf(input_buffer + 2, "%f %f", &freq, &bias); + // If only one arg provided, freq is set, bias remains 0. + } + // Routine_Measure needs to handle bias now. + // We'll update Routine_Measure momentarily. + // For now, let's just pass freq as before, but update Routine_Measure + // signature. + Routine_Measure(freq, bias); + } else if (cmd == 's') { + float start = 100.0f, end = 100000.0f; + int steps = 50; + float bias = 0.0f; + if (strlen(input_buffer) > 2) { + int count = + sscanf(input_buffer + 2, "%f %f %d %f", &start, &end, &steps, &bias); + // defaults handled by initialization + } + Routine_Sweep(start, end, steps, bias); + } else if (cmd == 'a') { + float bias = 0.0f; + if (strlen(input_buffer) > 2) + bias = atof(input_buffer + 2); + Routine_Amperometric(bias); + } else if (cmd == 'l') { + float start = -500.0f, end = 500.0f; + int steps = 100, duration = 10000; + if (strlen(input_buffer) > 2) + sscanf(input_buffer + 2, "%f %f %d %d", &start, &end, &steps, &duration); + Routine_LSV(start, end, steps, duration); + } else if (cmd == 'x') { + if (CurrentMode == MODE_IMPEDANCE) + AppIMPCleanup(); + else if (CurrentMode == MODE_AMPEROMETRIC) + AppAMPCtrl(AMPCTRL_SHUTDOWN, 0); + else if (CurrentMode == MODE_RAMP) + AppRAMPCtrl(APPCTRL_SHUTDOWN, 0); + CurrentMode = MODE_IDLE; + printf("STOPPED\n"); + SystemReset(); + } else if (cmd == 'z') { + SystemReset(); + } +} + +int main() { + stdio_init_all(); + sleep_ms(2000); + + setup_pins(); + + AD5940_HWReset(); + AD5940_Initialize(); + AD5940PlatformCfg(); + + Routine_CalibrateLFO(); + + printf("SYSTEM_READY\n"); + + while (true) { + int c = getchar_timeout_us(0); + if (c != PICO_ERROR_TIMEOUT) { + if (c == '\n' || c == '\r') { + input_buffer[input_pos] = 0; + if (input_pos > 0) + process_command(); + input_pos = 0; + } else if (input_pos < 63) { + input_buffer[input_pos++] = (char)c; + } + } + + if (gpio_get(PIN_INT) == 0) { + uint32_t temp = APPBUFF_SIZE; + int32_t status = 0; + + if (CurrentMode == MODE_IMPEDANCE) { + status = AppIMPISR(AppBuff, &temp); + if (status == AD5940ERR_BUFF) { + printf("ERROR: FIFO Overflow/Underflow. Stopping.\n"); + AppIMPCleanup(); + CurrentMode = MODE_IDLE; + SystemReset(); + } else if (temp > 0) { + ImpedanceShowResult(AppBuff, temp); + } + } else if (CurrentMode == MODE_AMPEROMETRIC) { + status = AppAMPISR(AppBuff, &temp); + if (status == AD5940ERR_BUFF) { + printf("ERROR: FIFO Overflow/Underflow. Stopping.\n"); + AppAMPCtrl(AMPCTRL_SHUTDOWN, 0); + CurrentMode = MODE_IDLE; + SystemReset(); + } else if (temp > 0) { + AmperometricShowResult((float *)AppBuff, temp); + } + } else if (CurrentMode == MODE_RAMP) { + status = AppRAMPISR(AppBuff, &temp); + if (status == AD5940ERR_BUFF) { + printf("ERROR: FIFO Overflow/Underflow. Stopping.\n"); + AppRAMPCtrl(APPCTRL_SHUTDOWN, 0); + CurrentMode = MODE_IDLE; + SystemReset(); + } else if (temp > 0) { + RampShowResult((float *)AppBuff, temp); + } + } + + if (status == AD5940ERR_STOP) { + printf("STOPPED\n"); + if (CurrentMode == MODE_IMPEDANCE) + AppIMPCleanup(); + else if (CurrentMode == MODE_AMPEROMETRIC) + AppAMPCtrl(AMPCTRL_SHUTDOWN, 0); + else if (CurrentMode == MODE_RAMP) + AppRAMPCtrl(APPCTRL_SHUTDOWN, 0); + CurrentMode = MODE_IDLE; + SystemReset(); + } + } + } + return 0; +} \ No newline at end of file diff --git a/examples/rp2040_port/pico_sdk_import.cmake b/examples/rp2040_port/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/examples/rp2040_port/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/examples/rp2040_port/rp2040port.c b/examples/rp2040_port/rp2040port.c new file mode 100644 index 0000000..bc63ccf --- /dev/null +++ b/examples/rp2040_port/rp2040port.c @@ -0,0 +1,59 @@ +#include "rp2040port.h" + +// --- Hardware Setup --- +void setup_pins(void) { + // SPI Initialisation. Using SPI0 at 16MHz. + spi_init(spi0, 16000000); + gpio_set_function(PIN_MISO, GPIO_FUNC_SPI); + gpio_set_function(PIN_SCK, GPIO_FUNC_SPI); + gpio_set_function(PIN_MOSI, GPIO_FUNC_SPI); + + // Chip Select + gpio_init(PIN_CS); + gpio_set_dir(PIN_CS, GPIO_OUT); + gpio_put(PIN_CS, 1); + + // Reset Pin + gpio_init(PIN_RST); + gpio_set_dir(PIN_RST, GPIO_OUT); + gpio_put(PIN_RST, 1); + + // Interrupt Pin + gpio_init(PIN_INT); + gpio_set_dir(PIN_INT, GPIO_IN); + gpio_pull_up(PIN_INT); +} + +// --- Platform Interface Implementation --- +void AD5940_CsClr(void) { gpio_put(PIN_CS, 0); } + +void AD5940_CsSet(void) { gpio_put(PIN_CS, 1); } + +void AD5940_RstClr(void) { gpio_put(PIN_RST, 0); } + +void AD5940_RstSet(void) { gpio_put(PIN_RST, 1); } + +void AD5940_Delay10us(uint32_t time) { sleep_us(time * 10); } + +void AD5940_ReadWriteNBytes(unsigned char *pSendBuffer, + unsigned char *pRecvBuff, unsigned long length) { + spi_write_read_blocking(spi0, pSendBuffer, pRecvBuff, length); +} + +uint32_t AD5940_GetMCUIntFlag(void) { return (gpio_get(PIN_INT) == 0); } + +uint32_t AD5940_ClrMCUIntFlag(void) { return 1; } + +uint32_t AD5940_MCUResourceInit(void *pCfg) { return 0; } + +void AD5940_MCUGpioWrite(uint32_t data) { (void)data; } + +uint32_t AD5940_MCUGpioRead(uint32_t pin) { + (void)pin; + return 0; +} + +void AD5940_MCUGpioCtrl(uint32_t pin, BoolFlag enable) { + (void)pin; + (void)enable; +} diff --git a/examples/rp2040_port/rp2040port.h b/examples/rp2040_port/rp2040port.h new file mode 100644 index 0000000..422a94d --- /dev/null +++ b/examples/rp2040_port/rp2040port.h @@ -0,0 +1,35 @@ +#ifndef _RP2040_PORT_H_ +#define _RP2040_PORT_H_ + +#include "ad5940.h" +#include "hardware/gpio.h" +#include "hardware/spi.h" +#include "pico/stdlib.h" + +// Hardware Definitions +#define PIN_MISO 0 +#define PIN_CS 1 +#define PIN_SCK 2 +#define PIN_MOSI 3 +#define PIN_RST 9 +#define PIN_INT 29 + +// Function Prototypes +void setup_pins(void); +void AD5940_CsClr(void); +void AD5940_CsSet(void); +void AD5940_RstClr(void); +void AD5940_RstSet(void); +void AD5940_Delay10us(uint32_t time); +void AD5940_ReadWriteNBytes(unsigned char *pSendBuffer, + unsigned char *pRecvBuff, unsigned long length); +uint32_t AD5940_GetMCUIntFlag(void); +uint32_t AD5940_ClrMCUIntFlag(void); +uint32_t AD5940_MCUResourceInit(void *pCfg); + +// These are stubs in the original platform file, keeping them here as well +void AD5940_MCUGpioWrite(uint32_t data); +uint32_t AD5940_MCUGpioRead(uint32_t pin); +void AD5940_MCUGpioCtrl(uint32_t pin, BoolFlag enable); + +#endif /* _RP2040_PORT_H_ */ diff --git a/examples/rp2040_port/test/AD5940Main.c b/examples/rp2040_port/test/AD5940Main.c new file mode 100644 index 0000000..33c55a5 --- /dev/null +++ b/examples/rp2040_port/test/AD5940Main.c @@ -0,0 +1,181 @@ +/*! + ***************************************************************************** + @file: AD5940Main.c + @author: Neo Xu + @brief: Standard 4-wire or 2-wire impedance measurement example. + ----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*****************************************************************************/ +#include "Impedance.h" + +/** + User could configure following parameters +**/ + +#define APPBUFF_SIZE 512 +uint32_t AppBuff[APPBUFF_SIZE]; + +int32_t ImpedanceShowResult(uint32_t *pData, uint32_t DataCount) { + float freq; + + fImpPol_Type *pImp = (fImpPol_Type *)pData; + AppIMPCtrl(IMPCTRL_GETFREQ, &freq); + + printf("Freq:%.2f ", freq); + /*Process data*/ + for (int i = 0; i < DataCount; i++) { + printf("RzMag: %f Ohm , RzPhase: %f \n", pImp[i].Magnitude, + pImp[i].Phase * 180 / MATH_PI); + } + return 0; +} + +static int32_t AD5940PlatformCfg(void) { + CLKCfg_Type clk_cfg; + FIFOCfg_Type fifo_cfg; + AGPIOCfg_Type gpio_cfg; + + /* Use hardware reset */ + AD5940_HWReset(); + AD5940_Initialize(); + /* Platform configuration */ + /* Step1. Configure clock */ + clk_cfg.ADCClkDiv = ADCCLKDIV_1; + clk_cfg.ADCCLkSrc = ADCCLKSRC_HFOSC; + clk_cfg.SysClkDiv = SYSCLKDIV_1; + clk_cfg.SysClkSrc = SYSCLKSRC_HFOSC; + clk_cfg.HfOSC32MHzMode = bFALSE; + clk_cfg.HFOSCEn = bTRUE; + clk_cfg.HFXTALEn = bFALSE; + clk_cfg.LFOSCEn = bTRUE; + AD5940_CLKCfg(&clk_cfg); + /* Step2. Configure FIFO and Sequencer*/ + fifo_cfg.FIFOEn = bFALSE; + fifo_cfg.FIFOMode = FIFOMODE_FIFO; + fifo_cfg.FIFOSize = + FIFOSIZE_4KB; /* 4kB for FIFO, The reset 2kB for sequencer */ + fifo_cfg.FIFOSrc = FIFOSRC_DFT; + fifo_cfg.FIFOThresh = + 4; // AppIMPCfg.FifoThresh; /* DFT result. One pair for RCAL, + // another for Rz. One DFT result have real part and imaginary part */ + AD5940_FIFOCfg(&fifo_cfg); + fifo_cfg.FIFOEn = bTRUE; + AD5940_FIFOCfg(&fifo_cfg); + + /* Step3. Interrupt controller */ + AD5940_INTCCfg( + AFEINTC_1, AFEINTSRC_ALLINT, + bTRUE); /* Enable all interrupt in INTC1, so we can check INTC flags */ + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + AD5940_INTCCfg(AFEINTC_0, AFEINTSRC_DATAFIFOTHRESH, bTRUE); + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + /* Step4: Reconfigure GPIO */ + gpio_cfg.FuncSet = GP0_INT | GP1_SLEEP | GP2_SYNC; + gpio_cfg.InputEnSet = 0; + gpio_cfg.OutputEnSet = AGPIO_Pin0 | AGPIO_Pin1 | AGPIO_Pin2; + gpio_cfg.OutVal = 0; + gpio_cfg.PullEnSet = 0; + AD5940_AGPIOCfg(&gpio_cfg); + AD5940_SleepKeyCtrlS(SLPKEY_UNLOCK); /* Allow AFE to enter sleep mode. */ + return 0; +} + +void AD5940ImpedanceStructInit(void) { + AppIMPCfg_Type *pImpedanceCfg; + + AppIMPGetCfg(&pImpedanceCfg); + /* Step1: configure initialization sequence Info */ + pImpedanceCfg->SeqStartAddr = 0; + pImpedanceCfg->MaxSeqLen = 512; /* @todo add checker in function */ + + pImpedanceCfg->RcalVal = 100.0; + pImpedanceCfg->SinFreq = 60000.0; + pImpedanceCfg->FifoThresh = 4; + + /* Set switch matrix to onboard(EVAL-AD5940ELECZ) dummy sensor. */ + /* Note the RCAL0 resistor is 10kOhm. */ + /* MODIFIED: Using AIN2/AIN3 for voltage sense as per user setup (CE0, SE0, + * AIN2, AIN3) */ + pImpedanceCfg->DswitchSel = SWD_CE0; + pImpedanceCfg->PswitchSel = SWP_AIN2; + pImpedanceCfg->NswitchSel = SWN_AIN3; + pImpedanceCfg->TswitchSel = SWT_SE0LOAD; + /* The dummy sensor is as low as 5kOhm. We need to make sure RTIA is small + * enough that HSTIA won't be saturated. */ + pImpedanceCfg->HstiaRtiaSel = HSTIARTIA_1K; + + /* Disable Hardware Sweep */ + pImpedanceCfg->SweepCfg.SweepEn = bFALSE; +} + +void AD5940_Main(void) { + uint32_t temp; + AD5940PlatformCfg(); + AD5940ImpedanceStructInit(); + + AppIMPInit(AppBuff, + APPBUFF_SIZE); /* Initialize IMP application. Provide a buffer, + which is used to store sequencer commands */ + AppIMPCtrl(IMPCTRL_START, + 0); /* Control IMP measurement to start. Second parameter has no + meaning with this command. */ + + AppIMPCfg_Type *pImpedanceCfg; + AppIMPGetCfg(&pImpedanceCfg); + + printf("\n--- EIS Configuration ---\n"); + printf("RcalVal: %.2f Ohm\n", pImpedanceCfg->RcalVal); + printf("BiasVolt: %.2f mV\n", pImpedanceCfg->BiasVolt); + printf("HstiaRtiaSel: 0x%02X\n", pImpedanceCfg->HstiaRtiaSel); + printf("AC Volts PP: %.2f mV\n", pImpedanceCfg->DacVoltPP); + printf("-------------------------\n\n"); + + /* Calculate Sweep Points */ + float start_freq = 100.0f; + float stop_freq = 100000.0f; + int num_points = 101; + // float log_step = pow(stop_freq / start_freq, 1.0 / (num_points - 1)); + float log_step = 1.0715193f; // 1000^(1/100) + float curr_freq = start_freq; + + printf("Starting Software Sweep: %.2f Hz to %.2f Hz, %d points\n", start_freq, + stop_freq, num_points); + + for (int i = 0; i < num_points; i++) { + uint32_t temp; + /* Update Frequency */ + pImpedanceCfg->SinFreq = curr_freq; + + /* Re-Initialize App to apply new frequency (this regenerates sequences) */ + AppIMPInit(AppBuff, APPBUFF_SIZE); + + /* Calibrate RTIA at this frequency */ + AppIMPRtiaCal(); + + /* Measure Impedance */ + AppIMPCtrl(IMPCTRL_START, 0); + + /* Wait for result */ + while (1) { + if (AD5940_GetMCUIntFlag()) { + AD5940_ClrMCUIntFlag(); + temp = APPBUFF_SIZE; + AppIMPISR(AppBuff, &temp); + ImpedanceShowResult(AppBuff, temp); + break; // Done with this point + } + } + + /* Next Frequency */ + curr_freq *= log_step; + } + printf("Sweep Completed.\n"); + while (1) + ; // Stop +} diff --git a/examples/rp2040_port/test/CMakeLists.txt b/examples/rp2040_port/test/CMakeLists.txt new file mode 100644 index 0000000..206a471 --- /dev/null +++ b/examples/rp2040_port/test/CMakeLists.txt @@ -0,0 +1,37 @@ +cmake_minimum_required(VERSION 3.13) + +include(pico_sdk_import.cmake) + +project(TestImpedance C CXX ASM) + +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 17) + +pico_sdk_init() + +add_executable(TestImpedance + main.c + AD5940Main.c + Impedance.c + ad5940.c + rp2040port.c +) + +target_compile_definitions(TestImpedance PRIVATE CHIPSEL_594X) +target_include_directories(TestImpedance PRIVATE ${CMAKE_CURRENT_LIST_DIR}) + +target_link_libraries(TestImpedance + pico_stdlib + hardware_spi + hardware_gpio + hardware_dma + hardware_irq + hardware_vreg + hardware_clocks + m +) + +pico_enable_stdio_usb(TestImpedance 1) +pico_enable_stdio_uart(TestImpedance 0) + +pico_add_extra_outputs(TestImpedance) diff --git a/examples/rp2040_port/test/Impedance.c b/examples/rp2040_port/test/Impedance.c new file mode 100644 index 0000000..9526c0d --- /dev/null +++ b/examples/rp2040_port/test/Impedance.c @@ -0,0 +1,660 @@ +/*! + ***************************************************************************** + @file: Impedance.c + @author: Neo Xu + @brief: standard 4-wire or 2-wire impedance measurement sequences. + ----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*****************************************************************************/ +#include "Impedance.h" +#include "ad5940.h" +#include "math.h" +#include "string.h" +#include + +/* Default LPDAC resolution(2.5V internal reference). */ +#define DAC12BITVOLT_1LSB (2200.0f / 4095) // mV +#define DAC6BITVOLT_1LSB (DAC12BITVOLT_1LSB * 64) // mV + +static uint32_t const HpRtiaTable[] = {200, 1000, 5000, 10000, 20000, + 40000, 80000, 160000, 0}; +static float ResRtiaCal = 0.0f; + +/* + Application configuration structure. Specified by user from template. + The variables are usable in this whole application. + It includes basic configuration for sequencer generator and application + related parameters +*/ +AppIMPCfg_Type AppIMPCfg = { + .bParaChanged = bFALSE, + .SeqStartAddr = 0, + .MaxSeqLen = 0, + + .SeqStartAddrCal = 0, + .MaxSeqLenCal = 0, + + .ImpODR = 20.0, /* 20.0 Hz*/ + .NumOfData = -1, + .SysClkFreq = 16000000.0, + .WuptClkFreq = 32000.0, + .AdcClkFreq = 16000000.0, + .RcalVal = 10000.0, + + .DswitchSel = SWD_CE0, + .PswitchSel = SWP_CE0, + .NswitchSel = SWN_AIN1, + .TswitchSel = SWT_AIN1, + + .PwrMod = AFEPWR_HP, + + .HstiaRtiaSel = HSTIARTIA_1K, + .ExcitBufGain = EXCITBUFGAIN_2, + .HsDacGain = HSDACGAIN_1, + .HsDacUpdateRate = 7, + .DacVoltPP = 800.0, + .BiasVolt = -0.0f, + + .SinFreq = 100000.0, /* 1000Hz */ + + .DftNum = DFTNUM_16384, + .DftSrc = DFTSRC_SINC3, + .HanWinEn = bTRUE, + + .AdcPgaGain = ADCPGA_1, + .ADCSinc3Osr = ADCSINC3OSR_2, + .ADCSinc2Osr = ADCSINC2OSR_22, + + .ADCAvgNum = ADCAVGNUM_16, + + .SweepCfg.SweepEn = bTRUE, + .SweepCfg.SweepStart = 1000, + .SweepCfg.SweepStop = 100000.0, + .SweepCfg.SweepPoints = 101, + .SweepCfg.SweepLog = bFALSE, + .SweepCfg.SweepIndex = 0, + + .FifoThresh = 4, + .IMPInited = bFALSE, + .StopRequired = bFALSE, +}; + +/** + This function is provided for upper controllers that want to change + application parameters specially for user defined parameters. +*/ +int32_t AppIMPGetCfg(void *pCfg) { + if (pCfg) { + *(AppIMPCfg_Type **)pCfg = &AppIMPCfg; + return AD5940ERR_OK; + } + return AD5940ERR_PARA; +} + +int32_t AppIMPCtrl(uint32_t Command, void *pPara) { + + switch (Command) { + case IMPCTRL_START: { + WUPTCfg_Type wupt_cfg; + + if (AD5940_WakeUp(10) > + 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + if (AppIMPCfg.IMPInited == bFALSE) + return AD5940ERR_APPERROR; + /* Start it */ + wupt_cfg.WuptEn = bTRUE; + wupt_cfg.WuptEndSeq = WUPTENDSEQ_A; + wupt_cfg.WuptOrder[0] = SEQID_0; + wupt_cfg.SeqxSleepTime[SEQID_0] = 4; + wupt_cfg.SeqxWakeupTime[SEQID_0] = + (uint32_t)(AppIMPCfg.WuptClkFreq / AppIMPCfg.ImpODR) - 4; + AD5940_WUPTCfg(&wupt_cfg); + + AppIMPCfg.FifoDataCount = 0; /* restart */ + break; + } + case IMPCTRL_STOPNOW: { + if (AD5940_WakeUp(10) > + 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + /* Start Wupt right now */ + AD5940_WUPTCtrl(bFALSE); + /* There is chance this operation will fail because sequencer could put AFE + back to hibernate mode just after waking up. Use STOPSYNC is better. */ + AD5940_WUPTCtrl(bFALSE); + break; + } + case IMPCTRL_STOPSYNC: { + AppIMPCfg.StopRequired = bTRUE; + break; + } + case IMPCTRL_GETFREQ: { + if (pPara == 0) + return AD5940ERR_PARA; + if (AppIMPCfg.SweepCfg.SweepEn == bTRUE) + *(float *)pPara = AppIMPCfg.FreqofData; + else + *(float *)pPara = AppIMPCfg.SinFreq; + } break; + case IMPCTRL_SHUTDOWN: { + AppIMPCtrl(IMPCTRL_STOPNOW, 0); /* Stop the measurement if it's running. */ + /* Turn off LPloop related blocks which are not controlled automatically by + * hibernate operation */ + AFERefCfg_Type aferef_cfg; + LPLoopCfg_Type lp_loop; + memset(&aferef_cfg, 0, sizeof(aferef_cfg)); + AD5940_REFCfgS(&aferef_cfg); + memset(&lp_loop, 0, sizeof(lp_loop)); + AD5940_LPLoopCfgS(&lp_loop); + AD5940_EnterSleepS(); /* Enter Hibernate */ + } break; + default: + break; + } + return AD5940ERR_OK; +} + +/* generated code snnipet */ +float AppIMPGetCurrFreq(void) { + if (AppIMPCfg.SweepCfg.SweepEn == bTRUE) + return AppIMPCfg.FreqofData; + else + return AppIMPCfg.SinFreq; +} + +/* Application initialization */ +static AD5940Err AppIMPSeqCfgGen(void) { + AD5940Err error = AD5940ERR_OK; + const uint32_t *pSeqCmd; + uint32_t SeqLen; + AFERefCfg_Type aferef_cfg; + HSLoopCfg_Type HsLoopCfg; + DSPCfg_Type dsp_cfg; + float sin_freq; + + /* Start sequence generator here */ + AD5940_SEQGenCtrl(bTRUE); + + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Init all to disable state */ + + aferef_cfg.HpBandgapEn = bTRUE; + aferef_cfg.Hp1V1BuffEn = bTRUE; + aferef_cfg.Hp1V8BuffEn = bTRUE; + aferef_cfg.Disc1V1Cap = bFALSE; + aferef_cfg.Disc1V8Cap = bFALSE; + aferef_cfg.Hp1V8ThemBuff = bFALSE; + aferef_cfg.Hp1V8Ilimit = bFALSE; + aferef_cfg.Lp1V1BuffEn = bFALSE; + aferef_cfg.Lp1V8BuffEn = bFALSE; + /* LP reference control - turn off them to save power*/ + if (AppIMPCfg.BiasVolt != 0.0f) /* With bias voltage */ + { + aferef_cfg.LpBandgapEn = bTRUE; + aferef_cfg.LpRefBufEn = bTRUE; + } else { + aferef_cfg.LpBandgapEn = bFALSE; + aferef_cfg.LpRefBufEn = bFALSE; + } + aferef_cfg.LpRefBoostEn = bFALSE; + AD5940_REFCfgS(&aferef_cfg); + HsLoopCfg.HsDacCfg.ExcitBufGain = AppIMPCfg.ExcitBufGain; + HsLoopCfg.HsDacCfg.HsDacGain = AppIMPCfg.HsDacGain; + HsLoopCfg.HsDacCfg.HsDacUpdateRate = AppIMPCfg.HsDacUpdateRate; + + HsLoopCfg.HsTiaCfg.DiodeClose = bFALSE; + if (AppIMPCfg.BiasVolt != 0.0f) /* With bias voltage */ + HsLoopCfg.HsTiaCfg.HstiaBias = HSTIABIAS_VZERO0; + else + HsLoopCfg.HsTiaCfg.HstiaBias = HSTIABIAS_1P1; + HsLoopCfg.HsTiaCfg.HstiaCtia = 31; /* 31pF + 2pF */ + HsLoopCfg.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_OPEN; + HsLoopCfg.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_OPEN; + HsLoopCfg.HsTiaCfg.HstiaRtiaSel = AppIMPCfg.HstiaRtiaSel; + + HsLoopCfg.SWMatCfg.Dswitch = AppIMPCfg.DswitchSel; + HsLoopCfg.SWMatCfg.Pswitch = AppIMPCfg.PswitchSel; + HsLoopCfg.SWMatCfg.Nswitch = AppIMPCfg.NswitchSel; + HsLoopCfg.SWMatCfg.Tswitch = SWT_TRTIA | AppIMPCfg.TswitchSel; + + HsLoopCfg.WgCfg.WgType = WGTYPE_SIN; + HsLoopCfg.WgCfg.GainCalEn = bTRUE; + HsLoopCfg.WgCfg.OffsetCalEn = bTRUE; + if (AppIMPCfg.SweepCfg.SweepEn == bTRUE) { + AppIMPCfg.FreqofData = AppIMPCfg.SweepCfg.SweepStart; + AppIMPCfg.SweepCurrFreq = AppIMPCfg.SweepCfg.SweepStart; + AD5940_SweepNext(&AppIMPCfg.SweepCfg, &AppIMPCfg.SweepNextFreq); + sin_freq = AppIMPCfg.SweepCurrFreq; + } else { + sin_freq = AppIMPCfg.SinFreq; + AppIMPCfg.FreqofData = sin_freq; + } + HsLoopCfg.WgCfg.SinCfg.SinFreqWord = + AD5940_WGFreqWordCal(sin_freq, AppIMPCfg.SysClkFreq); + HsLoopCfg.WgCfg.SinCfg.SinAmplitudeWord = + (uint32_t)(AppIMPCfg.DacVoltPP / 800.0f * 2047 + 0.5f); + HsLoopCfg.WgCfg.SinCfg.SinOffsetWord = 0; + HsLoopCfg.WgCfg.SinCfg.SinPhaseWord = 0; + AD5940_HSLoopCfgS(&HsLoopCfg); + if (AppIMPCfg.BiasVolt != 0.0f) /* With bias voltage */ + { + LPDACCfg_Type lpdac_cfg; + + lpdac_cfg.LpdacSel = LPDAC0; + lpdac_cfg.LpDacVbiasMux = + LPDACVBIAS_12BIT; /* Use Vbias to tuning BiasVolt. */ + lpdac_cfg.LpDacVzeroMux = LPDACVZERO_6BIT; /* Vbias-Vzero = BiasVolt */ + lpdac_cfg.DacData6Bit = 0x40 >> 1; /* Set Vzero to middle scale. */ + if (AppIMPCfg.BiasVolt < -1100.0f) + AppIMPCfg.BiasVolt = -1100.0f + DAC12BITVOLT_1LSB; + if (AppIMPCfg.BiasVolt > 1100.0f) + AppIMPCfg.BiasVolt = 1100.0f - DAC12BITVOLT_1LSB; + lpdac_cfg.DacData12Bit = + (uint32_t)((AppIMPCfg.BiasVolt + 1100.0f) / DAC12BITVOLT_1LSB); + lpdac_cfg.DataRst = bFALSE; /* Do not reset data register */ + lpdac_cfg.LpDacSW = LPDACSW_VBIAS2LPPA | LPDACSW_VBIAS2PIN | + LPDACSW_VZERO2LPTIA | LPDACSW_VZERO2PIN | + LPDACSW_VZERO2HSTIA; + lpdac_cfg.LpDacRef = LPDACREF_2P5; + lpdac_cfg.LpDacSrc = LPDACSRC_MMR; /* Use MMR data, we use LPDAC to generate + bias voltage for LPTIA - the Vzero */ + lpdac_cfg.PowerEn = bTRUE; /* Power up LPDAC */ + AD5940_LPDACCfgS(&lpdac_cfg); + } + dsp_cfg.ADCBaseCfg.ADCMuxN = ADCMUXN_HSTIA_N; + dsp_cfg.ADCBaseCfg.ADCMuxP = ADCMUXP_HSTIA_P; + dsp_cfg.ADCBaseCfg.ADCPga = AppIMPCfg.AdcPgaGain; + + memset(&dsp_cfg.ADCDigCompCfg, 0, sizeof(dsp_cfg.ADCDigCompCfg)); + + dsp_cfg.ADCFilterCfg.ADCAvgNum = AppIMPCfg.ADCAvgNum; + dsp_cfg.ADCFilterCfg.ADCRate = + ADCRATE_800KHZ; /* Tell filter block clock rate of ADC*/ + dsp_cfg.ADCFilterCfg.ADCSinc2Osr = AppIMPCfg.ADCSinc2Osr; + dsp_cfg.ADCFilterCfg.ADCSinc3Osr = AppIMPCfg.ADCSinc3Osr; + dsp_cfg.ADCFilterCfg.BpNotch = bTRUE; + dsp_cfg.ADCFilterCfg.BpSinc3 = bFALSE; + dsp_cfg.ADCFilterCfg.Sinc2NotchEnable = bTRUE; + dsp_cfg.DftCfg.DftNum = AppIMPCfg.DftNum; + dsp_cfg.DftCfg.DftSrc = AppIMPCfg.DftSrc; + dsp_cfg.DftCfg.HanWinEn = AppIMPCfg.HanWinEn; + + memset(&dsp_cfg.StatCfg, 0, sizeof(dsp_cfg.StatCfg)); + AD5940_DSPCfgS(&dsp_cfg); + + /* Enable all of them. They are automatically turned off during hibernate mode + * to save power */ + if (AppIMPCfg.BiasVolt == 0.0f) + AD5940_AFECtrlS(AFECTRL_HSTIAPWR | AFECTRL_INAMPPWR | AFECTRL_EXTBUFPWR | + AFECTRL_WG | AFECTRL_DACREFPWR | AFECTRL_HSDACPWR | + AFECTRL_SINC2NOTCH, + bTRUE); + else + AD5940_AFECtrlS(AFECTRL_HSTIAPWR | AFECTRL_INAMPPWR | AFECTRL_EXTBUFPWR | + AFECTRL_WG | AFECTRL_DACREFPWR | AFECTRL_HSDACPWR | + AFECTRL_SINC2NOTCH | AFECTRL_DCBUFPWR, + bTRUE); + /* Sequence end. */ + AD5940_SEQGenInsert(SEQ_STOP()); /* Add one extra command to disable sequencer + for initialization sequence because we + only want it to run one time. */ + + /* Stop here */ + error = AD5940_SEQGenFetchSeq(&pSeqCmd, &SeqLen); + AD5940_SEQGenCtrl(bFALSE); /* Stop sequencer generator */ + if (error == AD5940ERR_OK) { + AppIMPCfg.InitSeqInfo.SeqId = SEQID_1; + AppIMPCfg.InitSeqInfo.SeqRamAddr = AppIMPCfg.SeqStartAddr; + AppIMPCfg.InitSeqInfo.pSeqCmd = pSeqCmd; + AppIMPCfg.InitSeqInfo.SeqLen = SeqLen; + /* Write command to SRAM */ + AD5940_SEQCmdWrite(AppIMPCfg.InitSeqInfo.SeqRamAddr, pSeqCmd, SeqLen); + } else + return error; /* Error */ + return AD5940ERR_OK; +} + +static AD5940Err AppIMPSeqMeasureGen(void) { + AD5940Err error = AD5940ERR_OK; + const uint32_t *pSeqCmd; + uint32_t SeqLen; + + uint32_t WaitClks; + SWMatrixCfg_Type sw_cfg; + ClksCalInfo_Type clks_cal; + + clks_cal.DataType = DATATYPE_DFT; + clks_cal.DftSrc = AppIMPCfg.DftSrc; + clks_cal.DataCount = 1L << (AppIMPCfg.DftNum + 2); /* 2^(DFTNUMBER+2) */ + clks_cal.ADCSinc2Osr = AppIMPCfg.ADCSinc2Osr; + clks_cal.ADCSinc3Osr = AppIMPCfg.ADCSinc3Osr; + clks_cal.ADCAvgNum = AppIMPCfg.ADCAvgNum; + clks_cal.RatioSys2AdcClk = AppIMPCfg.SysClkFreq / AppIMPCfg.AdcClkFreq; + AD5940_ClksCalculate(&clks_cal, &WaitClks); + + AD5940_SEQGenCtrl(bTRUE); + AD5940_SEQGpioCtrlS( + AGPIO_Pin2); /* Set GPIO1, clear others that under control */ + AD5940_SEQGenInsert(SEQ_WAIT(16 * 250)); /* @todo wait 250us? */ + sw_cfg.Dswitch = SWD_RCAL0; + sw_cfg.Pswitch = SWP_RCAL0; + sw_cfg.Nswitch = SWN_RCAL1; + sw_cfg.Tswitch = SWT_RCAL1 | SWT_TRTIA; + AD5940_SWMatrixCfgS(&sw_cfg); + AD5940_AFECtrlS(AFECTRL_HSTIAPWR | AFECTRL_INAMPPWR | AFECTRL_EXTBUFPWR | + AFECTRL_WG | AFECTRL_DACREFPWR | AFECTRL_HSDACPWR | + AFECTRL_SINC2NOTCH, + bTRUE); + AD5940_AFECtrlS(AFECTRL_WG | AFECTRL_ADCPWR, + bTRUE); /* Enable Waveform generator */ + // delay for signal settling DFT_WAIT + AD5940_SEQGenInsert(SEQ_WAIT(16 * 10)); + AD5940_AFECtrlS(AFECTRL_ADCCNV | AFECTRL_DFT, + bTRUE); /* Start ADC convert and DFT */ + AD5940_SEQGenInsert(SEQ_WAIT(WaitClks)); + // wait for first data ready + AD5940_AFECtrlS(AFECTRL_ADCPWR | AFECTRL_ADCCNV | AFECTRL_DFT | AFECTRL_WG, + bFALSE); /* Stop ADC convert and DFT */ + + /* Configure matrix for external Rz */ + sw_cfg.Dswitch = AppIMPCfg.DswitchSel; + sw_cfg.Pswitch = AppIMPCfg.PswitchSel; + sw_cfg.Nswitch = AppIMPCfg.NswitchSel; + sw_cfg.Tswitch = SWT_TRTIA | AppIMPCfg.TswitchSel; + AD5940_SWMatrixCfgS(&sw_cfg); + AD5940_AFECtrlS(AFECTRL_ADCPWR | AFECTRL_WG, + bTRUE); /* Enable Waveform generator */ + AD5940_SEQGenInsert(SEQ_WAIT(16 * 10)); // delay for signal settling DFT_WAIT + AD5940_AFECtrlS(AFECTRL_ADCCNV | AFECTRL_DFT, + bTRUE); /* Start ADC convert and DFT */ + AD5940_SEQGenInsert(SEQ_WAIT(WaitClks)); /* wait for first data ready */ + AD5940_AFECtrlS(AFECTRL_ADCCNV | AFECTRL_DFT | AFECTRL_WG | AFECTRL_ADCPWR, + bFALSE); /* Stop ADC convert and DFT */ + AD5940_AFECtrlS(AFECTRL_HSTIAPWR | AFECTRL_INAMPPWR | AFECTRL_EXTBUFPWR | + AFECTRL_WG | AFECTRL_DACREFPWR | AFECTRL_HSDACPWR | + AFECTRL_SINC2NOTCH, + bFALSE); + AD5940_SEQGpioCtrlS(0); /* Clr GPIO1 */ + + AD5940_EnterSleepS(); /* Goto hibernate */ + + /* Sequence end. */ + error = AD5940_SEQGenFetchSeq(&pSeqCmd, &SeqLen); + AD5940_SEQGenCtrl(bFALSE); /* Stop sequencer generator */ + + if (error == AD5940ERR_OK) { + AppIMPCfg.MeasureSeqInfo.SeqId = SEQID_0; + AppIMPCfg.MeasureSeqInfo.SeqRamAddr = + AppIMPCfg.InitSeqInfo.SeqRamAddr + AppIMPCfg.InitSeqInfo.SeqLen; + AppIMPCfg.MeasureSeqInfo.pSeqCmd = pSeqCmd; + AppIMPCfg.MeasureSeqInfo.SeqLen = SeqLen; + /* Write command to SRAM */ + AD5940_SEQCmdWrite(AppIMPCfg.MeasureSeqInfo.SeqRamAddr, pSeqCmd, SeqLen); + } else + return error; /* Error */ + return AD5940ERR_OK; +} + +AD5940Err AppIMPRtiaCal(void) { + HSRTIACal_Type hs_cal; + fImpPol_Type res; + AD5940Err error; + + hs_cal.fFreq = AppIMPCfg.SinFreq; + hs_cal.fRcal = AppIMPCfg.RcalVal; + hs_cal.SysClkFreq = AppIMPCfg.SysClkFreq; + hs_cal.AdcClkFreq = AppIMPCfg.AdcClkFreq; + + hs_cal.HsTiaCfg.DiodeClose = bFALSE; + if (AppIMPCfg.BiasVolt != 0.0f) + hs_cal.HsTiaCfg.HstiaBias = HSTIABIAS_VZERO0; + else + hs_cal.HsTiaCfg.HstiaBias = HSTIABIAS_1P1; + + hs_cal.HsTiaCfg.HstiaCtia = 31; + hs_cal.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_OPEN; + hs_cal.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_OPEN; + hs_cal.HsTiaCfg.HstiaRtiaSel = AppIMPCfg.HstiaRtiaSel; + + hs_cal.ADCSinc3Osr = AppIMPCfg.ADCSinc3Osr; + hs_cal.ADCSinc2Osr = AppIMPCfg.ADCSinc2Osr; + + hs_cal.DftCfg.DftNum = AppIMPCfg.DftNum; + hs_cal.DftCfg.DftSrc = AppIMPCfg.DftSrc; + hs_cal.DftCfg.HanWinEn = AppIMPCfg.HanWinEn; + + hs_cal.bPolarResult = bTRUE; + + hs_cal.bPolarResult = bTRUE; + + error = AD5940_HSRtiaCal(&hs_cal, &res); + if (error == AD5940ERR_OK) { + ResRtiaCal = res.Magnitude; + printf("Calibrated RTIA: %f Ohm, Phase: %f\n", res.Magnitude, res.Phase); + } else + printf("RTIA Calibration Failed: %d\n", error); + + return error; +} + +/* This function provide application initialize. It can also enable Wupt that + * will automatically trigger sequence. Or it can configure */ +int32_t AppIMPInit(uint32_t *pBuffer, uint32_t BufferSize) { + AD5940Err error = AD5940ERR_OK; + SEQCfg_Type seq_cfg; + FIFOCfg_Type fifo_cfg; + + if (AD5940_WakeUp(10) > + 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + + /* Configure sequencer and stop it */ + seq_cfg.SeqMemSize = + SEQMEMSIZE_2KB; /* 2kB SRAM is used for sequencer, others for data FIFO */ + seq_cfg.SeqBreakEn = bFALSE; + seq_cfg.SeqIgnoreEn = bTRUE; + seq_cfg.SeqCntCRCClr = bTRUE; + seq_cfg.SeqEnable = bFALSE; + seq_cfg.SeqWrTimer = 0; + AD5940_SEQCfg(&seq_cfg); + + /* Reconfigure FIFO */ + AD5940_FIFOCtrlS(FIFOSRC_DFT, bFALSE); /* Disable FIFO firstly */ + fifo_cfg.FIFOEn = bTRUE; + fifo_cfg.FIFOMode = FIFOMODE_FIFO; + fifo_cfg.FIFOSize = + FIFOSIZE_4KB; /* 4kB for FIFO, The reset 2kB for sequencer */ + fifo_cfg.FIFOSrc = FIFOSRC_DFT; + fifo_cfg.FIFOThresh = + AppIMPCfg + .FifoThresh; /* DFT result. One pair for RCAL, another for Rz. One DFT + result have real part and imaginary part */ + AD5940_FIFOCfg(&fifo_cfg); + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + + /* Perform RTIA Calibration */ + AppIMPRtiaCal(); + + /* Start sequence generator */ + /* Initialize sequencer generator */ + if ((AppIMPCfg.IMPInited == bFALSE) || (AppIMPCfg.bParaChanged == bTRUE)) { + if (pBuffer == 0) + return AD5940ERR_PARA; + if (BufferSize == 0) + return AD5940ERR_PARA; + AD5940_SEQGenInit(pBuffer, BufferSize); + + /* Generate initialize sequence */ + error = AppIMPSeqCfgGen(); /* Application initialization sequence using + either MCU or sequencer */ + if (error != AD5940ERR_OK) + return error; + + /* Generate measurement sequence */ + error = AppIMPSeqMeasureGen(); + if (error != AD5940ERR_OK) + return error; + + AppIMPCfg.bParaChanged = bFALSE; /* Clear this flag as we already + implemented the new configuration */ + } + + /* Initialization sequencer */ + AppIMPCfg.InitSeqInfo.WriteSRAM = bFALSE; + AD5940_SEQInfoCfg(&AppIMPCfg.InitSeqInfo); + seq_cfg.SeqEnable = bTRUE; + AD5940_SEQCfg(&seq_cfg); /* Enable sequencer */ + AD5940_SEQMmrTrig(AppIMPCfg.InitSeqInfo.SeqId); + while (AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_ENDSEQ) == bFALSE) + ; + + /* Measurement sequence */ + AppIMPCfg.MeasureSeqInfo.WriteSRAM = bFALSE; + AD5940_SEQInfoCfg(&AppIMPCfg.MeasureSeqInfo); + + seq_cfg.SeqEnable = bTRUE; + AD5940_SEQCfg(&seq_cfg); /* Enable sequencer, and wait for trigger */ + AD5940_ClrMCUIntFlag(); /* Clear interrupt flag generated before */ + + AD5940_AFEPwrBW(AppIMPCfg.PwrMod, AFEBW_250KHZ); + + AppIMPCfg.IMPInited = bTRUE; /* IMP application has been initialized. */ + return AD5940ERR_OK; +} + +/* Modify registers when AFE wakeup */ +int32_t AppIMPRegModify(int32_t *const pData, uint32_t *pDataCount) { + if (AppIMPCfg.NumOfData > 0) { + AppIMPCfg.FifoDataCount += *pDataCount / 4; + if (AppIMPCfg.FifoDataCount >= AppIMPCfg.NumOfData) { + AD5940_WUPTCtrl(bFALSE); + return AD5940ERR_OK; + } + } + if (AppIMPCfg.StopRequired == bTRUE) { + AD5940_WUPTCtrl(bFALSE); + return AD5940ERR_OK; + } + if (AppIMPCfg.SweepCfg + .SweepEn) /* Need to set new frequency and set power mode */ + { + AD5940_WGFreqCtrlS(AppIMPCfg.SweepNextFreq, AppIMPCfg.SysClkFreq); + } + return AD5940ERR_OK; +} + +/* Depending on the data type, do appropriate data pre-process before return + * back to controller */ +int32_t AppIMPDataProcess(int32_t *const pData, uint32_t *pDataCount) { + uint32_t DataCount = *pDataCount; + uint32_t ImpResCount = DataCount / 4; + + fImpPol_Type *const pOut = (fImpPol_Type *)pData; + iImpCar_Type *pSrcData = (iImpCar_Type *)pData; + + *pDataCount = 0; + + DataCount = (DataCount / 4) * + 4; /* We expect RCAL data together with Rz data. One DFT result + has two data in FIFO, real part and imaginary part. */ + + /* Convert DFT result to int32_t type */ + for (uint32_t i = 0; i < DataCount; i++) { + pData[i] &= 0x3ffff; /* @todo option to check ECC */ + if (pData[i] & (1L << 17)) /* Bit17 is sign bit */ + { + pData[i] |= 0xfffc0000; /* Data is 18bit in two's complement, bit17 is the + sign bit */ + } + } + for (uint32_t i = 0; i < ImpResCount; i++) { + iImpCar_Type *pDftRcal, *pDftRz; + + pDftRcal = pSrcData++; + pDftRz = pSrcData++; + float RzMag, RzPhase; + float RcalMag, RcalPhase; + + RcalMag = sqrt((float)pDftRcal->Real * pDftRcal->Real + + (float)pDftRcal->Image * pDftRcal->Image); + RcalPhase = atan2(-pDftRcal->Image, pDftRcal->Real); + RzMag = sqrt((float)pDftRz->Real * pDftRz->Real + + (float)pDftRz->Image * pDftRz->Image); + RzPhase = atan2(-pDftRz->Image, pDftRz->Real); + + RzMag = RcalMag / RzMag * AppIMPCfg.RcalVal; + RzPhase = RcalPhase - RzPhase; + + // DEBUG: Print raw magnitudes and Rcal used + if (i == 0) { + uint32_t RtiaSel = AppIMPCfg.HstiaRtiaSel; + float ExpectedRtia = (float)HpRtiaTable[RtiaSel]; + printf("\n--- RTIA Calibration Info ---\n"); + printf("Selected RTIA Index: %d\n", RtiaSel); + printf("Expected RTIA: %.2f Ohm\n", ExpectedRtia); + printf("Calibrated RTIA: %f Ohm\n", ResRtiaCal); + printf("-----------------------------\n"); + } + printf("DEBUG: RcalMag: %f, DutMag: %f, RcalVal: %f, RTIA_Cal: %f\n", + RcalMag, (RcalMag * AppIMPCfg.RcalVal) / RzMag, AppIMPCfg.RcalVal, + ResRtiaCal); + + pOut[i].Magnitude = RzMag; + pOut[i].Phase = RzPhase; + } + *pDataCount = ImpResCount; + AppIMPCfg.FreqofData = AppIMPCfg.SweepCurrFreq; + /* Calculate next frequency point */ + if (AppIMPCfg.SweepCfg.SweepEn == bTRUE) { + AppIMPCfg.FreqofData = AppIMPCfg.SweepCurrFreq; + AppIMPCfg.SweepCurrFreq = AppIMPCfg.SweepNextFreq; + AD5940_SweepNext(&AppIMPCfg.SweepCfg, &AppIMPCfg.SweepNextFreq); + } + + return 0; +} + +/** + +*/ +int32_t AppIMPISR(void *pBuff, uint32_t *pCount) { + uint32_t BuffCount; + uint32_t FifoCnt; + BuffCount = *pCount; + + *pCount = 0; + + if (AD5940_WakeUp(10) > + 10) /* Wakeup AFE by read register, read 10 times at most */ + return AD5940ERR_WAKEUP; /* Wakeup Failed */ + AD5940_SleepKeyCtrlS(SLPKEY_LOCK); /* Prohibit AFE to enter sleep mode. */ + + if (AD5940_INTCTestFlag(AFEINTC_0, AFEINTSRC_DATAFIFOTHRESH) == bTRUE) { + /* Now there should be 4 data in FIFO */ + FifoCnt = (AD5940_FIFOGetCnt() / 4) * 4; + + if (FifoCnt > BuffCount) { + ///@todo buffer is limited. + } + AD5940_FIFORd((uint32_t *)pBuff, FifoCnt); + AD5940_INTCClrFlag(AFEINTSRC_DATAFIFOTHRESH); + AppIMPRegModify(pBuff, + &FifoCnt); /* If there is need to do AFE re-configure, do it + here when AFE is in active state */ + // AD5940_EnterSleepS(); /* Manually put AFE back to hibernate mode. This + // operation only takes effect when register value is ACTIVE previously */ + AD5940_SleepKeyCtrlS(SLPKEY_UNLOCK); /* Allow AFE to enter sleep mode. */ + /* Process data */ + AppIMPDataProcess((int32_t *)pBuff, &FifoCnt); + *pCount = FifoCnt; + return 0; + } + + return 0; +} diff --git a/examples/rp2040_port/test/Impedance.h b/examples/rp2040_port/test/Impedance.h new file mode 100644 index 0000000..76b1f31 --- /dev/null +++ b/examples/rp2040_port/test/Impedance.h @@ -0,0 +1,104 @@ +/*! + ***************************************************************************** + @file: Impedance.h + @author: Neo XU + @brief: 4-wire/2-wire impedance measurement header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + +This software is proprietary to Analog Devices, Inc. and its licensors. +By using this software you agree to the terms of the associated +Analog Devices Software License Agreement. + +*****************************************************************************/ +#ifndef _IMPEDANCESEQUENCES_H_ +#define _IMPEDANCESEQUENCES_H_ +#include "ad5940.h" +#include "math.h" +#include "string.h" +#include + +typedef struct { + /* Common configurations for all kinds of Application. */ + BoolFlag bParaChanged; /* Indicate to generate sequence again. It's auto + cleared by AppBIAInit */ + uint32_t + SeqStartAddr; /* Initialaztion sequence start address in SRAM of AD5940 */ + uint32_t MaxSeqLen; /* Limit the maximum sequence. */ + uint32_t SeqStartAddrCal; /* Measurement sequence start address in SRAM of + AD5940 */ + uint32_t MaxSeqLenCal; + /* Application related parameters */ + float ImpODR; /* */ + int32_t NumOfData; /* By default it's '-1'. If you want the engine stops after + get NumofData, then set the value here. Otherwise, set + it to '-1' which means never stop. */ + float WuptClkFreq; /* The clock frequency of Wakeup Timer in Hz. Typically + it's 32kHz. Leave it here in case we calibrate clock in + software method */ + float SysClkFreq; /* The real frequency of system clock */ + float AdcClkFreq; /* The real frequency of ADC clock */ + float RcalVal; /* Rcal value in Ohm */ + /* Switch Configuration */ + uint32_t DswitchSel; + uint32_t PswitchSel; + uint32_t NswitchSel; + uint32_t TswitchSel; + uint32_t PwrMod; /* Control Chip power mode(LP/HP) */ + uint32_t + HstiaRtiaSel; /* Use internal RTIA, select from RTIA_INT_200, RTIA_INT_1K, + RTIA_INT_5K, RTIA_INT_10K, RTIA_INT_20K, RTIA_INT_40K, + RTIA_INT_80K, RTIA_INT_160K */ + uint32_t ExcitBufGain; /* Select from EXCTBUFGAIN_2, EXCTBUFGAIN_0P25 */ + uint32_t HsDacGain; /* Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + uint32_t HsDacUpdateRate; + float DacVoltPP; /* DAC output voltage in mV peak to peak. Maximum value is + 800mVpp. Peak to peak voltage */ + float BiasVolt; /* The excitation signal is DC+AC. This parameter decides the + DC value in mV unit. 0.0mV means no DC bias.*/ + float SinFreq; /* Frequency of excitation signal */ + uint32_t DftNum; /* DFT number */ + uint32_t DftSrc; /* DFT Source */ + BoolFlag HanWinEn; /* Enable Hanning window */ + uint32_t AdcPgaGain; /* PGA Gain select from GNPGA_1, GNPGA_1_5, GNPGA_2, + GNPGA_4, GNPGA_9 !!! We must ensure signal is in range + of +-1.5V which is limited by ADC input stage */ + uint8_t ADCSinc3Osr; + uint8_t ADCSinc2Osr; + uint8_t ADCAvgNum; + /* Sweep Function Control */ + SoftSweepCfg_Type SweepCfg; + uint32_t FifoThresh; /* FIFO threshold. Should be N*4 */ + /* Private variables for internal usage */ + /* Private variables for internal usage */ + float SweepCurrFreq; + float SweepNextFreq; + float FreqofData; /* The frequency of latest data sampled */ + BoolFlag + IMPInited; /* If the program run firstly, generated sequence commands */ + SEQInfo_Type InitSeqInfo; + SEQInfo_Type MeasureSeqInfo; + BoolFlag + StopRequired; /* After FIFO is ready, stop the measurement sequence */ + uint32_t + FifoDataCount; /* Count how many times impedance have been measured */ +} AppIMPCfg_Type; + +#define IMPCTRL_START 0 +#define IMPCTRL_STOPNOW 1 +#define IMPCTRL_STOPSYNC 2 +#define IMPCTRL_GETFREQ \ + 3 /* Get Current frequency of returned data from ISR \ + */ +#define IMPCTRL_SHUTDOWN \ + 4 /* Note: shutdown here means turn off everything and put AFE to hibernate \ + mode. The word 'SHUT DOWN' is only used here. */ + +int32_t AppIMPInit(uint32_t *pBuffer, uint32_t BufferSize); +int32_t AppIMPGetCfg(void *pCfg); +int32_t AppIMPISR(void *pBuff, uint32_t *pCount); +int32_t AppIMPCtrl(uint32_t Command, void *pPara); +AD5940Err AppIMPRtiaCal(void); + +#endif diff --git a/examples/rp2040_port/test/Makefile b/examples/rp2040_port/test/Makefile new file mode 100644 index 0000000..b885112 --- /dev/null +++ b/examples/rp2040_port/test/Makefile @@ -0,0 +1,28 @@ +# Name of your build directory +BUILD_DIR = build + +# Name of the output file (Must match what is in CMakeLists.txt) +TARGET = TestImpedance + +# Default target: Build the project +all: $(BUILD_DIR)/Makefile + @$(MAKE) -C $(BUILD_DIR) + +# Ensure the build directory exists and run CMake if needed +$(BUILD_DIR)/Makefile: CMakeLists.txt + @mkdir -p $(BUILD_DIR) + @cd $(BUILD_DIR) && cmake .. + +# Clean up the build directory +clean: + @rm -rf $(BUILD_DIR) + +# Helper to automatically flash (Mac specific path) +flash: all + @echo "Waiting for RPI-RP2 volume..." + @while [ ! -d /Volumes/RPI-RP2 ]; do sleep 0.1; done + @echo "Flashing..." + @cp $(BUILD_DIR)/$(TARGET).uf2 /Volumes/RPI-RP2/ + @echo "Done." + +.PHONY: all clean flash diff --git a/examples/rp2040_port/test/ad5940.c b/examples/rp2040_port/test/ad5940.c new file mode 100644 index 0000000..79e89dc --- /dev/null +++ b/examples/rp2040_port/test/ad5940.c @@ -0,0 +1,4422 @@ +/** + * @file ad5940.c + * @brief AD5940 library. This file contains all AD5940 library functions. + * @author ADI + * @date March 2019 + * @par Revision History: + * + * Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + * + * This software is proprietary to Analog Devices, Inc. and its licensors. + * By using this software you agree to the terms of the associated + * Analog Devices Software License Agreement. +**/ +#include "ad5940.h" + +/*! \mainpage AD5940 Library Introduction + * + * ![AD5940 EVAL Board](https://www.analog.com/-/media/analog/en/evaluation-board-images/images/eval-ad5940elcztop-web.gif?h=500&thn=1&hash=1F38F7CC1002894616F74D316365C0A2631C432B "ADI logo") + * + * # Introduction + * + * The documentation is for AD594x library and examples. + * + * # Manual Structure + * + * @ref AD5940_Library + * - @ref AD5940_Functions + * - @ref TypeDefinitions + * @ref AD5940_Standard_Examples + * @ref AD5940_System_Examples + * + * # How to Use It + * We provide examples that can directly run out of box. + * The files can generally be separated to three parts: + * - AD5940 Library files. ad5940.c and ad5940.h specifically. These two files are shared among all examples. + * - AD5940 System Examples. The system examples mean system level application like measuring impedance. + * - Standard examples. These include basic block level examples like ADC. It shows how to setup and use one specific block. + * + * ## Requirements to run these examples + * ### Hardware + * - Use EVAL_AD5940 or EVAL_AD5941. The default MCU board we used is ADICUP3029. We also provide project for ST NUCLEO board. + * - Or use EVAL_ADuCM355 + * ### Software + * - Pull all the source file from [GitHub](https://github.com/analogdevicesinc/ad5940-examples.git) + * - CMSIS pack that related to specific MCU. This normally is done by IDE you use. + * + * ## Materials + * Please use this library together with following materials. + * - [AD5940 Data Sheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5940.pdf) + * - [AD5940 Eval Board](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD5940.html) + * + */ + +/* Remove below variables after AD594x is released. */ +static BoolFlag bIsS2silicon = bFALSE; + +/* Declare of SPI functions used to read/write registers */ +#ifndef CHIPSEL_M355 +static uint32_t AD5940_SPIReadReg(uint16_t RegAddr); +static void AD5940_SPIWriteReg(uint16_t RegAddr, uint32_t RegData); +#else +static uint32_t AD5940_D2DReadReg(uint16_t RegAddr); +static void AD5940_D2DWriteReg(uint16_t RegAddr, uint32_t RegData); +#endif + +/** + * @addtogroup AD5940_Library + * The library functions, structures and constants. + * @{ + * @defgroup AD5940_Functions + * @{ + * @defgroup Function_Helpers + * @brief The functions with no hardware access. They are helpers. + * @{ + * @defgroup Sequencer_Generator_Functions + * @brief The set of function used to track all register read and write once it's enabled. It can translate register write operation to sequencer commands. + * @{ +*/ + +#define SEQUENCE_GENERATOR /*!< Build sequence generator part in to lib. Comment this line to remove this feature */ + +#ifdef SEQUENCE_GENERATOR +/** + * Structure used to store register information(address and its data) + * */ +typedef struct +{ + uint32_t RegAddr :8; /**< 8bit address is enough for sequencer */ + uint32_t RegValue :24; /**< Reg data is limited to 24bit by sequencer */ +}SEQGenRegInfo_Type; + +/** + * Sequencer generator data base. +*/ +struct +{ + BoolFlag EngineStart; /**< Flag to mark start of the generator */ + uint32_t BufferSize; /**< Total buffer size */ + + uint32_t *pSeqBuff; /**< The buffer for sequence generator(both sequences and RegInfo) */ + uint32_t SeqLen; /**< Generated sequence length till now */ + SEQGenRegInfo_Type *pRegInfo; /**< Pointer to buffer where stores register info */ + uint32_t RegCount; /**< The count of register info available in buffer *pRegInfo. */ + AD5940Err LastError; /**< The last error message. */ +}SeqGenDB; /* Data base of Seq Generator */ + +/** + * @brief Manually input a command to sequencer generator. + * @param CmdWord: The 32-bit width sequencer command word. @ref Sequencer_Helper can be used to generate commands. + * @return None; +*/ +void AD5940_SEQGenInsert(uint32_t CmdWord) +{ + uint32_t temp; + temp = SeqGenDB.RegCount + SeqGenDB.SeqLen; + /* Generate Sequence command */ + if(temp < SeqGenDB.BufferSize) + { + SeqGenDB.pSeqBuff[SeqGenDB.SeqLen] = CmdWord; + SeqGenDB.SeqLen ++; + } + else /* There is no buffer */ + SeqGenDB.LastError = AD5940ERR_BUFF; +} + +/** + * @brief Search data-base to get current register value. + * @param RegAddr: The register address. + * @param pIndex: Pointer to a variable that used to store index of found register-info. + * @return Return AD5940ERR_OK if register found in data-base. Otherwise return AD5940ERR_SEQREG. +*/ +static AD5940Err AD5940_SEQGenSearchReg(uint32_t RegAddr, uint32_t *pIndex) +{ + uint32_t i; + + RegAddr = (RegAddr>>2)&0xff; + for(i=0;i>2)&0xff; + SeqGenDB.pRegInfo[0].RegValue = RegData&0x00ffffff; + SeqGenDB.RegCount ++; + } + else /* There is no more buffer */ + { + SeqGenDB.LastError = AD5940ERR_BUFF; + } +} + +/** + * @brief Get current register value. If we have record in data-base, read it. Otherwise, return the register default value. + * @param RegAddr: The register address. + * @return Return register value. +*/ +static uint32_t AD5940_SEQReadReg(uint16_t RegAddr) +{ + uint32_t RegIndex, RegData; + + if(AD5940_SEQGenSearchReg(RegAddr, &RegIndex) != AD5940ERR_OK) + { + /* There is no record in data-base, read the default value. */ + AD5940_SEQGenGetRegDefault(RegAddr, &RegData); + AD5940_SEQRegInfoInsert(RegAddr, RegData); + } + else + { + /* return the current register value stored in data-base */ + RegData = SeqGenDB.pRegInfo[RegIndex].RegValue; + } + + return RegData; +} + +/** + * @brief Generate a sequencer command to write register. If the register address is out of range, it won't generate a command. + * This function will also update the register-info in data-base to record current register value. + * @param RegAddr: The register address. + * @param RegData: The register value. + * @return Return None. +*/ +static void AD5940_SEQWriteReg(uint16_t RegAddr, uint32_t RegData) +{ + uint32_t RegIndex; + + if(RegAddr > 0x21ff) + { + SeqGenDB.LastError = AD5940ERR_ADDROR; /* address out of range */ + return; + } + + if(AD5940_SEQGenSearchReg(RegAddr, &RegIndex) == AD5940ERR_OK) + { + /* Store register value */ + SeqGenDB.pRegInfo[RegIndex].RegValue = RegData; + /* Generate Sequence command */ + AD5940_SEQGenInsert(SEQ_WR(RegAddr, RegData)); + } + else + { + AD5940_SEQRegInfoInsert(RegAddr, RegData); + /* Generate Sequence command */ + AD5940_SEQGenInsert(SEQ_WR(RegAddr, RegData)); + } +} + +/** + * @brief Initialize sequencer generator with specified buffer. + * The buffer is used to store sequencer generated and record register value changes. + * The command is stored from start address of buffer while register value is stored from end of buffer. + * Buffer[0] : First sequencer command; + * Buffer[1] : Second Sequencer command; + * ... + * Buffer[Last-1]: The second register value record. + * Buffer[Last]: The first register value record. + * @param pBuffer: Pointer to the buffer. + * @param BufferSize: The buffer length. + * @return Return None. +*/ +void AD5940_SEQGenInit(uint32_t *pBuffer, uint32_t BufferSize) +{ + if(BufferSize < 2) return; + SeqGenDB.BufferSize = BufferSize; + SeqGenDB.pSeqBuff = pBuffer; + SeqGenDB.pRegInfo = (SEQGenRegInfo_Type*)pBuffer + BufferSize - 1; /* Point to the last element in buffer */ + SeqGenDB.SeqLen = 0; + + SeqGenDB.RegCount = 0; + SeqGenDB.LastError = AD5940ERR_OK; + SeqGenDB.EngineStart = bFALSE; +} + +/** + * @brief Get sequencer command generated. + * @param ppSeqCmd: Pointer to a variable(pointer) used to store the pointer to generated sequencer command. + * @param pSeqLen: Pointer to a variable that used to store how many commands available in buffer. + * @return Return lasterror. +*/ +AD5940Err AD5940_SEQGenFetchSeq(const uint32_t **ppSeqCmd, uint32_t *pSeqLen) +{ + AD5940Err lasterror; + + if(ppSeqCmd) + *ppSeqCmd = SeqGenDB.pSeqBuff; + if(pSeqLen) + *pSeqLen = SeqGenDB.SeqLen; + + //SeqGenDB.SeqLen = 0; /* Start a new sequence */ + lasterror = SeqGenDB.LastError; + //SeqGenDB.LastError = AD5940ERR_OK; /* Clear error message */ + return lasterror; +} + +/** + * @brief Start or stop the sequencer generator. Once started, the register write will be recorded to sequencer generator. + * Once it's disabled, the register write is written to AD5940 directly by SPI bus. + * @param bFlag: Enable or disable sequencer generator. + * @return Return None. +*/ +void AD5940_SEQGenCtrl(BoolFlag bFlag) +{ + if(bFlag == bFALSE) /* Disable sequence generator */ + { + SeqGenDB.EngineStart = bFALSE; + } + else + { + SeqGenDB.SeqLen = 0; + SeqGenDB.LastError = AD5940ERR_OK; /* Clear error message */ + SeqGenDB.EngineStart = bTRUE; + } +} + +/** + * @brief Calculate the number of cycles in the sequence + * @return Return Number of ACLK Cycles that a generated sequence will take. +*/ +uint32_t AD5940_SEQCycleTime(void) +{ + uint32_t i, Cycles, Cmd; + Cycles = 0; + for(i=0;i> 30) & 0x3; + if (Cmd & 0x2) + { + /* A write command */ + Cycles += 1; + } + else + { + if (Cmd & 0x1) + { + /* Timeout Command */ + Cycles += 1; + } + else + { + /* Wait command */ + Cycles += SeqGenDB.pSeqBuff[i] & 0x3FFFFFFF; + } + } + } + return Cycles; +} +#endif +/** + * @} Sequencer_Generator_Functions +*/ + +/** + * Check if an uint8_t value exist in table. +*/ +static int32_t _is_value_in_table(uint8_t value, const uint8_t *table, uint8_t len, uint8_t *index) +{ + for(int i=0; iADCRate == ADCRATE_800KHZ && pFilterInfo->ADCSinc3Osr == ADCSINC3OSR_2)||\ + (pFilterInfo->ADCRate == ADCRATE_1P6MHZ && pFilterInfo->ADCSinc3Osr != ADCSINC3OSR_2)) + { + //this combination suits for filter: + //SINC3 OSR2, for 800kSPS + //and SINC3 OSR4 and OSR5 for 1.6MSPS, + const uint8_t available_sinc2_osr[] = {ADCSINC2OSR_533, ADCSINC2OSR_667,ADCSINC2OSR_800, ADCSINC2OSR_889, ADCSINC2OSR_1333}; + const uint8_t dl_50Hz[] = {15,12,10,9,6}; + uint8_t index; + if(_is_value_in_table(pFilterInfo->ADCSinc2Osr, available_sinc2_osr, sizeof(available_sinc2_osr), &index)) + { + *dl = dl_50Hz[index]; + return bTRUE; + } + } + else if(pFilterInfo->ADCRate == ADCRATE_1P6MHZ && pFilterInfo->ADCSinc3Osr == ADCSINC3OSR_2) + { + //this combination suits for filter: + //SINC3 OSR2 for 1.6MSPS + const uint8_t available_sinc2_osr[] = {ADCSINC2OSR_889, ADCSINC2OSR_1067, ADCSINC2OSR_1333}; + const uint8_t dl_50Hz[] = {18,15,12}; + uint8_t index; + if(_is_value_in_table(pFilterInfo->ADCSinc2Osr, available_sinc2_osr, sizeof(available_sinc2_osr), &index)) + { + *dl = dl_50Hz[index]; + return bTRUE; + } + } + else if(pFilterInfo->ADCRate == ADCRATE_800KHZ && pFilterInfo->ADCSinc3Osr != ADCSINC3OSR_2) + { + //this combination suits for filter: + //SINC3 OSR4 and OSR5 for 800kSPS, + const uint8_t available_sinc2_osr[] = {ADCSINC2OSR_178, ADCSINC2OSR_267, ADCSINC2OSR_533, ADCSINC2OSR_640,\ + ADCSINC2OSR_800, ADCSINC2OSR_1067}; + const uint8_t dl_50Hz[] = {18,12,6,5,4,3}; + uint8_t index; + if(_is_value_in_table(pFilterInfo->ADCSinc2Osr, available_sinc2_osr, sizeof(available_sinc2_osr), &index)) + { + *dl = dl_50Hz[index]; + return bTRUE; + } + } + *dl = 0; + return bFALSE; +} + +/** + * @brief return if the SINC3/SINC2 combination is available for notch 60Hz filter. + * If it's not availabe, hardware automatically bypass Notch even if it's enabled. + * @param pFilterInfo the filter configuration, need sinc2/sinc3 osr and adc data rate information. + * @return return bTRUE if notch 60Hz filter is available. +*/ +BoolFlag AD5940_Notch60HzAvailable(ADCFilterCfg_Type *pFilterInfo, uint8_t *dl) +{ + if((pFilterInfo->ADCRate == ADCRATE_800KHZ && pFilterInfo->ADCSinc3Osr == ADCSINC3OSR_2)||\ + (pFilterInfo->ADCRate == ADCRATE_1P6MHZ && pFilterInfo->ADCSinc3Osr != ADCSINC3OSR_2)) + { + //this combination suits for filter: + //SINC3 OSR2, for 800kSPS + //and SINC3 OSR4 and OSR5 for 1.6MSPS, + const uint8_t available_sinc2_osr[] = {ADCSINC2OSR_667, ADCSINC2OSR_1333}; + const uint8_t dl_60Hz[] = {10,5}; + uint8_t index; + if(_is_value_in_table(pFilterInfo->ADCSinc2Osr, available_sinc2_osr, sizeof(available_sinc2_osr), &index)) + { + *dl = dl_60Hz[index]; + return bTRUE; + } + } + else if(pFilterInfo->ADCRate == ADCRATE_1P6MHZ && pFilterInfo->ADCSinc3Osr == ADCSINC3OSR_2) + { + //this combination suits for filter: + //SINC3 OSR2 for 1.6MSPS + const uint8_t available_sinc2_osr[] = {ADCSINC2OSR_889, ADCSINC2OSR_1333}; + const uint8_t dl_60Hz[] = {15,10}; + uint8_t index; + if(_is_value_in_table(pFilterInfo->ADCSinc2Osr, available_sinc2_osr, sizeof(available_sinc2_osr), &index)) + { + *dl = dl_60Hz[index]; + return bTRUE; + } + } + else if(pFilterInfo->ADCRate == ADCRATE_800KHZ && pFilterInfo->ADCSinc3Osr != ADCSINC3OSR_2) + { + //this combination suits for filter: + //SINC3 OSR4 and OSR5 for 800kSPS, + const uint8_t available_sinc2_osr[] = {ADCSINC2OSR_178, ADCSINC2OSR_267, ADCSINC2OSR_533, ADCSINC2OSR_667,\ + ADCSINC2OSR_889, ADCSINC2OSR_1333}; + const uint8_t dl_60Hz[] = {15,10,5,4,3,2}; + uint8_t index; + if(_is_value_in_table(pFilterInfo->ADCSinc2Osr, available_sinc2_osr, sizeof(available_sinc2_osr), &index)) + { + *dl = dl_60Hz[index]; + return bTRUE; + } + } + *dl = 0; + return bFALSE; +} + +/** + * @brief Calculate how many clocks are needed in sequencer wait command to generate required number of data from filter output. + * @note When measurement is done, it's recommend to disable blocks like ADCPWR, ADCCNV, SINC2, DFT etc. If blocks remain powered up, + * they may need less clocks to generate required number of output. Use function @ref AD5940_AFECtrlS to control these blocks. + * @param pFilterInfo: Pointer to configuration structure. + * @param pClocks: pointer used to store results. + * @return return none. +*/ +void AD5940_ClksCalculate(ClksCalInfo_Type *pFilterInfo, uint32_t *pClocks) +{ + uint32_t temp = 0; + const uint32_t sinc2osr_table[] = {22,44,89,178,267,533,640,667,800,889,1067,1333,0}; + const uint32_t sinc3osr_table[] = {5,4,2,0}; + + *pClocks = 0; + if(pFilterInfo == NULL) return; + if(pClocks == NULL) return; + if(pFilterInfo->ADCSinc2Osr > ADCSINC2OSR_1333) return; + if(pFilterInfo->ADCSinc3Osr > 2) return; /* 0: OSR5, 1:OSR4, 2:OSR2 */ + if(pFilterInfo->ADCAvgNum > ADCAVGNUM_16) return; /* Average number index:0,1,2,3 */ + switch(pFilterInfo->DataType) + { + case DATATYPE_ADCRAW: + temp = (uint32_t)(20*pFilterInfo->DataCount*pFilterInfo->RatioSys2AdcClk); + break; + case DATATYPE_SINC3: + temp = (uint32_t)(((pFilterInfo->DataCount+2)*sinc3osr_table[pFilterInfo->ADCSinc3Osr]+1)*20*pFilterInfo->RatioSys2AdcClk + 0.5f); + break; + case DATATYPE_SINC2: + temp = (pFilterInfo->DataCount+1)*sinc2osr_table[pFilterInfo->ADCSinc2Osr] + 1; + pFilterInfo->DataType = DATATYPE_SINC3; + pFilterInfo->DataCount = temp; + AD5940_ClksCalculate(pFilterInfo, &temp); + pFilterInfo->DataType = DATATYPE_SINC2; + temp += 15; /* Need extra 15 clocks for FIFO etc. Just to be safe. */ + break; + case DATATYPE_NOTCH: + { + ADCFilterCfg_Type filter; + filter.ADCRate = pFilterInfo->ADCRate; + filter.ADCSinc3Osr = pFilterInfo->ADCSinc3Osr; + filter.ADCSinc2Osr = pFilterInfo->ADCSinc2Osr; + uint8_t dl=0, dl_50, dl_60; + if(AD5940_Notch50HzAvailable(&filter, &dl_50)){ + dl += dl_50 - 1; + } + if(AD5940_Notch60HzAvailable(&filter, &dl_60)){ + dl += dl_60 - 1; + } + pFilterInfo->DataType = DATATYPE_SINC2; + pFilterInfo->DataCount += dl; //DL is the extra data input needed for filter to output first data. + AD5940_ClksCalculate(pFilterInfo,&temp); + //restore the filter info. + pFilterInfo->DataType = DATATYPE_NOTCH; + pFilterInfo->DataCount -= dl; + break; + } + case DATATYPE_DFT: + switch(pFilterInfo->DftSrc) + { + case DFTSRC_ADCRAW: + pFilterInfo->DataType = DATATYPE_ADCRAW; + AD5940_ClksCalculate(pFilterInfo, &temp); + break; + case DFTSRC_SINC3: + pFilterInfo->DataType = DATATYPE_SINC3; + AD5940_ClksCalculate(pFilterInfo, &temp); + break; + case DFTSRC_SINC2NOTCH: + if(pFilterInfo->BpNotch) + pFilterInfo->DataType = DATATYPE_SINC2; + else + pFilterInfo->DataType = DATATYPE_NOTCH; + AD5940_ClksCalculate(pFilterInfo, &temp); + break; + case DFTSRC_AVG: + pFilterInfo->DataType = DATATYPE_SINC3; + pFilterInfo->DataCount *= 1L<<(pFilterInfo->ADCAvgNum+1); /* 0: average2, 1: average4, 2: average8, 3: average16 */ + AD5940_ClksCalculate(pFilterInfo, &temp); + break; + default: + break; + } + pFilterInfo->DataType = DATATYPE_DFT; + temp += 25; /* add margin */ + break; + default: + break; + } + *pClocks = temp; +} + +/** + @brief void AD5940_SweepNext(SoftSweepCfg_Type *pSweepCfg, float *pNextFreq) + For sweep function, calculate next frequency point according to pSweepCfg info. + @return Return next frequency point in Hz. +*/ +void AD5940_SweepNext(SoftSweepCfg_Type *pSweepCfg, float *pNextFreq) +{ + float frequency; + + if(pSweepCfg->SweepLog)/* Log step */ + { + if(pSweepCfg->SweepStartSweepStop) /* Normal */ + { + if(++pSweepCfg->SweepIndex == pSweepCfg->SweepPoints) + pSweepCfg->SweepIndex = 0; + frequency = pSweepCfg->SweepStart*pow(10,pSweepCfg->SweepIndex*log10(pSweepCfg->SweepStop/pSweepCfg->SweepStart)/(pSweepCfg->SweepPoints-1)); + } + else + { + pSweepCfg->SweepIndex --; + if(pSweepCfg->SweepIndex >= pSweepCfg->SweepPoints) + pSweepCfg->SweepIndex = pSweepCfg->SweepPoints-1; + frequency = pSweepCfg->SweepStop*pow(10,pSweepCfg->SweepIndex* + (log10(pSweepCfg->SweepStart/pSweepCfg->SweepStop)/(pSweepCfg->SweepPoints-1))); + } + } + else/* Linear step */ + { + if(pSweepCfg->SweepStartSweepStop) /* Normal */ + { + if(++pSweepCfg->SweepIndex == pSweepCfg->SweepPoints) + pSweepCfg->SweepIndex = 0; + frequency = pSweepCfg->SweepStart + pSweepCfg->SweepIndex*(double)(pSweepCfg->SweepStop-pSweepCfg->SweepStart)/(pSweepCfg->SweepPoints-1); + } + else + { + pSweepCfg->SweepIndex --; + if(pSweepCfg->SweepIndex >= pSweepCfg->SweepPoints) + pSweepCfg->SweepIndex = pSweepCfg->SweepPoints-1; + frequency = pSweepCfg->SweepStop + pSweepCfg->SweepIndex*(double)(pSweepCfg->SweepStart - pSweepCfg->SweepStop)/(pSweepCfg->SweepPoints-1); + } + } + + *pNextFreq = frequency; +} + +/** + @brief Initialize Structure members to zero + @param pStruct: Pointer to the structure. + @param StructSize: The structure size in Byte. + @return Return None. +**/ +void AD5940_StructInit(void *pStruct, uint32_t StructSize) +{ + memset(pStruct, 0, StructSize); +} + +/** + @brief Convert ADC Code to voltage. + @param ADCPga: The ADC PGA used for this result. + @param code: ADC code. + @param VRef1p82: the actual 1.82V reference voltage. + @return Voltage in volt. +**/ +float AD5940_ADCCode2Volt(uint32_t code, uint32_t ADCPga, float VRef1p82) +{ + float kFactor = 1.835/1.82; + float fVolt = 0.0; + float tmp = 0; + tmp = (int32_t)code - 32768; + switch(ADCPga) + { + case ADCPGA_1: + break; + case ADCPGA_1P5: + tmp /= 1.5f; + break; + case ADCPGA_2: + tmp /= 2.0f; + break; + case ADCPGA_4: + tmp /= 4.0f; + break; + case ADCPGA_9: + tmp /= 9.0f; + break; + default:break; + } + fVolt = tmp*VRef1p82/32768*kFactor; + return fVolt; +} + +/** + * @brief Do complex number division. + * @param a: The dividend. + * @param b: The divisor. + * @return Return result. +**/ +fImpCar_Type AD5940_ComplexDivFloat(fImpCar_Type *a, fImpCar_Type *b) +{ + fImpCar_Type res; + float temp; + temp = b->Real*b->Real + b->Image*b->Image; + res.Real = a->Real*b->Real + a->Image*b->Image; + res.Real /= temp; + res.Image = a->Image*b->Real - a->Real*b->Image; + res.Image /= temp; + return res; +} + +/** + * @brief Do complex number multiplication. + * @param a: The multiplicand. + * @param b: The multiplier . + * @return Return result. +**/ +fImpCar_Type AD5940_ComplexMulFloat(fImpCar_Type *a, fImpCar_Type *b) +{ + fImpCar_Type res; + + res.Real = a->Real*b->Real - a->Image*b->Image; + res.Image = a->Image*b->Real + a->Real*b->Image; + + return res; +} +/** + * @brief Do complex number addition. + * @param a: The addend. + * @param b: The addend . + * @return Return result. +**/ +fImpCar_Type AD5940_ComplexAddFloat(fImpCar_Type *a, fImpCar_Type *b) +{ + fImpCar_Type res; + + res.Real = a->Real + b->Real; + res.Image = a->Image + b->Image; + + return res; +} + +/** + * @brief Do complex number subtraction. + * @param a: The minuend. + * @param b: The subtrahend . + * @return Return result. +**/ +fImpCar_Type AD5940_ComplexSubFloat(fImpCar_Type *a, fImpCar_Type *b) +{ + fImpCar_Type res; + + res.Real = a->Real - b->Real; + res.Image = a->Image - b->Image; + + return res; +} + +/** + * @brief Do complex number division. + * @param a: The dividend. + * @param b: The divisor. + * @return Return result. +**/ +fImpCar_Type AD5940_ComplexDivInt(iImpCar_Type *a, iImpCar_Type *b) +{ + fImpCar_Type res; + float temp; + temp = (float)b->Real*b->Real + (float)b->Image*b->Image; + res.Real = (float)a->Real*b->Real + (float)a->Image*b->Image; + res.Real /= temp; + res.Image = (float)a->Image*b->Real - (float)a->Real*b->Image; + res.Image /= temp; + return res; +} + +/** + * @brief Do complex number multiplication. + * @param a: The multiplicand. + * @param b: The multiplier . + * @return Return result. +**/ +fImpCar_Type AD5940_ComplexMulInt(iImpCar_Type *a, iImpCar_Type *b) +{ + fImpCar_Type res; + + res.Real = (float)a->Real*b->Real - (float)a->Image*b->Image; + res.Image = (float)a->Image*b->Real + (float)a->Real*b->Image; + + return res; +} + +/** + * @brief Calculate the complex number magnitude. + * @param a: The complex number. + * @return Return magnitude. +**/ +float AD5940_ComplexMag(fImpCar_Type *a) +{ + return sqrt(a->Real*a->Real + a->Image*a->Image); +} + +/** + * @brief Calculate the complex number phase. + * @param a: The complex number. + * @return Return phase. +**/ +float AD5940_ComplexPhase(fImpCar_Type *a) +{ + return atan2(a->Image, a->Real); +} + +/** + * @brief Calculate the optimum filter settings based on signal frequency. + * @param freq: Frequency of signalr. + * @return Return FreqParams. +**/ +FreqParams_Type AD5940_GetFreqParameters(float freq) +{ + const uint32_t dft_table[] = {4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384}; + const uint32_t sinc2osr_table[] = {1, 22,44,89,178,267,533,640,667,800,889,1067,1333}; + const uint32_t sinc3osr_table[] = {2, 4, 5}; + float AdcRate = 800000; + uint32_t n1 = 0; // Sample rate after ADC filters + uint32_t n2 = 0; // Sample rate after DFT block + uint32_t iCycle = 0; + FreqParams_Type freq_params; + /* High power mode */ + if(freq >= 20000) + { + freq_params. DftSrc = DFTSRC_SINC3; + freq_params.ADCSinc2Osr = 0; + freq_params.ADCSinc3Osr = 2; + freq_params.DftNum = DFTNUM_8192; + freq_params.NumClks = 0; + freq_params.HighPwrMode = bTRUE; + return freq_params; + } + + if(freq < 0.51) + { + freq_params. DftSrc = DFTSRC_SINC2NOTCH; + freq_params.ADCSinc2Osr = 6; + freq_params.ADCSinc3Osr = 1; + freq_params.DftNum = DFTNUM_8192; + freq_params.NumClks = 0; + freq_params.HighPwrMode = bTRUE; + return freq_params; + } + + /* Start with SINC2 setting */ + for(uint8_t i = 0; i=0x1000)&&(RegAddr<=0x3014))) /* 32bit register */ + *(volatile uint32_t *)(RegAddr+0x400c0000) = RegData; + else /* 16bit register */ + *(volatile uint16_t *)(RegAddr+0x400c0000) = RegData; +} + +static uint32_t AD5940_D2DReadReg(uint16_t RegAddr) +{ + if(((RegAddr>=0x1000)&&(RegAddr<=0x3014))) /* 32bit register */ + return *(volatile uint32_t *)(RegAddr+0x400c0000); + else /* 16bit register */ + return *(volatile uint16_t *)(RegAddr+0x400c0000); +} + +void AD5940_FIFORd(uint32_t *pBuffer, uint32_t uiReadCount) +{ + while(uiReadCount--) + *pBuffer++ = *(volatile uint32_t *)(0x400c206C); +} +#else +/** + * @defgroup SPI_Block + * @brief Functions to communicate with AD5940 registers following AD5940 SPI protocols + * @{ + * + * @defgroup SPI_Block_Functions + * @brief The basic SPI protocols. All functions are basic on AD5940_ReadWriteNBytes which + * provided by user. + * + * ##SPI basic protocol + * All SPI protocol starts with one-byte command word. Following are data(16B or 32B) + * There are four SPI commands available @ref SPI_Block_Const. + * @{ +*/ + +/** + @brief Using SPI to transmit one byte and return the received byte. + @param data: The 8-bit data SPI will transmit. + @return received data. +**/ +static unsigned char AD5940_ReadWrite8B(unsigned char data) +{ + uint8_t tx[1], rx[1]; + tx[0] = data; + AD5940_ReadWriteNBytes(tx,rx,1); + return rx[0]; +} + +/** + @brief Using SPI to transmit two bytes and return the received bytes. + @param data: The 16-bit data SPI will transmit. + @return received data. +**/ +static uint16_t AD5940_ReadWrite16B(uint16_t data) +{ + uint8_t SendBuffer[2]; + uint8_t RecvBuffer[2]; + SendBuffer[0] = data>>8; + SendBuffer[1] = data&0xff; + AD5940_ReadWriteNBytes(SendBuffer,RecvBuffer,2); + return (((uint16_t)RecvBuffer[0])<<8)|RecvBuffer[1]; +} + +/** + * @brief Using SPI to transmit four bytes and return the received bytes. + * @param data: The 32-bit data SPI will transmit. + * @return received data. +**/ +static uint32_t AD5940_ReadWrite32B(uint32_t data) +{ + uint8_t SendBuffer[4]; + uint8_t RecvBuffer[4]; + + SendBuffer[0] = (data>>24)&0xff; + SendBuffer[1] = (data>>16)&0xff; + SendBuffer[2] = (data>> 8)&0xff; + SendBuffer[3] = (data )&0xff; + AD5940_ReadWriteNBytes(SendBuffer,RecvBuffer,4); + return (((uint32_t)RecvBuffer[0])<<24)|(((uint32_t)RecvBuffer[1])<<16)|(((uint32_t)RecvBuffer[2])<<8)|RecvBuffer[3]; +} + +/** + * @brief Write register through SPI. + * @param RegAddr: The register address. + * @param RegData: The register data. + * @return Return None. +**/ +static void AD5940_SPIWriteReg(uint16_t RegAddr, uint32_t RegData) +{ + /* Set register address */ + AD5940_CsClr(); + AD5940_ReadWrite8B(SPICMD_SETADDR); + AD5940_ReadWrite16B(RegAddr); + AD5940_CsSet(); + /* Add delay here to meet the SPI timing. */ + AD5940_CsClr(); + AD5940_ReadWrite8B(SPICMD_WRITEREG); + if(((RegAddr>=0x1000)&&(RegAddr<=0x3014))) + AD5940_ReadWrite32B(RegData); + else + AD5940_ReadWrite16B(RegData); + AD5940_CsSet(); +} + +/** + * @brief Read register through SPI. + * @param RegAddr: The register address. + * @return Return register data. +**/ +static uint32_t AD5940_SPIReadReg(uint16_t RegAddr) +{ + uint32_t Data = 0; + /* Set register address that we want to read */ + AD5940_CsClr(); + AD5940_ReadWrite8B(SPICMD_SETADDR); + AD5940_ReadWrite16B(RegAddr); + AD5940_CsSet(); + /* Read it */ + AD5940_CsClr(); + AD5940_ReadWrite8B(SPICMD_READREG); + AD5940_ReadWrite8B(0); //Dummy read + /* The real data is coming */ + if((RegAddr>=0x1000)&&(RegAddr<=0x3014)) + Data = AD5940_ReadWrite32B(0); + else + Data = AD5940_ReadWrite16B(0); + AD5940_CsSet(); + return Data; +} + +/** + @brief Read specific number of data from FIFO with optimized SPI access. + @param pBuffer: Pointer to a buffer that used to store data read back. + @param uiReadCount: How much data to be read. + @return none. +**/ +void AD5940_FIFORd(uint32_t *pBuffer, uint32_t uiReadCount) +{ + /* Use function AD5940_SPIReadReg to read REG_AFE_DATAFIFORD is also one method. */ + uint32_t i; + + if(uiReadCount < 3) + { + /* This method is more efficient when readcount < 3 */ + uint32_t i; + AD5940_CsClr(); + AD5940_ReadWrite8B(SPICMD_SETADDR); + AD5940_ReadWrite16B(REG_AFE_DATAFIFORD); + AD5940_CsSet(); + for(i=0;iHpBandgapEn == bFALSE) + tempreg |= BITM_AFE_AFECON_HPREFDIS; + AD5940_WriteReg(REG_AFE_AFECON, tempreg); + /* Reference buffer configure */ + tempreg = AD5940_ReadReg(REG_AFE_BUFSENCON); + if(pBufCfg->Hp1V8BuffEn == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P8HPADCEN; + if(pBufCfg->Hp1V1BuffEn == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P1HPADCEN; + if(pBufCfg->Lp1V8BuffEn == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P8LPADCEN; + if(pBufCfg->Lp1V1BuffEn == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P1LPADCEN; + if(pBufCfg->Hp1V8ThemBuff == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P8THERMSTEN; + if(pBufCfg->Hp1V8Ilimit == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P8HPADCILIMITEN; + if(pBufCfg->Disc1V8Cap == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P8HPADCCHGDIS; + if(pBufCfg->Disc1V1Cap == bTRUE) + tempreg |= BITM_AFE_BUFSENCON_V1P1LPADCCHGDIS; + AD5940_WriteReg(REG_AFE_BUFSENCON, tempreg); + + /* LPREFBUFCON */ + tempreg = 0; + if(pBufCfg->LpRefBufEn == bFALSE) + tempreg |= BITM_AFE_LPREFBUFCON_LPBUF2P5DIS; + if(pBufCfg->LpBandgapEn == bFALSE) + tempreg |= BITM_AFE_LPREFBUFCON_LPREFDIS; + if(pBufCfg->LpRefBoostEn == bTRUE) + tempreg |= BITM_AFE_LPREFBUFCON_BOOSTCURRENT; + AD5940_WriteReg(REG_AFE_LPREFBUFCON, tempreg); +} +/** + * @} End of AFE_Control_Functions + * @} End of AFE_Control + * */ + +/** + * @defgroup High_Speed_Loop + * @brief The high speed loop + * @{ + * @defgroup High_Speed_Loop_Functions + * @{ +*/ + +/** + @brief Configure High speed loop(high bandwidth loop or + called excitation loop). This configuration includes HSDAC, HSTIA and Switch matrix. + @param pHsLoopCfg : Pointer to configure structure; + @return return none. +*/ +void AD5940_HSLoopCfgS(HSLoopCfg_Type *pHsLoopCfg) +{ + AD5940_HSDacCfgS(&pHsLoopCfg->HsDacCfg); + AD5940_HSTIACfgS(&pHsLoopCfg->HsTiaCfg); + AD5940_SWMatrixCfgS(&pHsLoopCfg->SWMatCfg); + AD5940_WGCfgS(&pHsLoopCfg->WgCfg); +} + +/** + @brief Initialize switch matrix + @param pSwMatrix: Pointer to configuration structure + @return return none. +*/ +void AD5940_SWMatrixCfgS(SWMatrixCfg_Type *pSwMatrix) +{ + AD5940_WriteReg(REG_AFE_DSWFULLCON, pSwMatrix->Dswitch); + AD5940_WriteReg(REG_AFE_PSWFULLCON, pSwMatrix->Pswitch); + AD5940_WriteReg(REG_AFE_NSWFULLCON, pSwMatrix->Nswitch); + AD5940_WriteReg(REG_AFE_TSWFULLCON, pSwMatrix->Tswitch); + AD5940_WriteReg(REG_AFE_SWCON, BITM_AFE_SWCON_SWSOURCESEL); /* Update switch configuration */ +} + +/** + @brief Initialize HSDAC + @param pHsDacCfg: Pointer to configuration structure + @return return none. +*/ +void AD5940_HSDacCfgS(HSDACCfg_Type *pHsDacCfg) +{ + uint32_t tempreg; + //Check parameters + tempreg = 0; + if(pHsDacCfg->ExcitBufGain == EXCITBUFGAIN_0P25) + tempreg |= BITM_AFE_HSDACCON_INAMPGNMDE; /* Enable attenuator */ + if(pHsDacCfg->HsDacGain == HSDACGAIN_0P2) + tempreg |= BITM_AFE_HSDACCON_ATTENEN; /* Enable attenuator */ + tempreg |= (pHsDacCfg->HsDacUpdateRate&0xff)<= HSTIADERTIA_OPEN) + tempreg = 0x1f << 3; /* bit field HPTIRES03CON[7:3] */ + else if(DeRtia >= HSTIADERTIA_1K) + { + tempreg = (DeRtia - 3 + 11) << 3; + } + else /* DERTIA 50/100/200Ohm */ + { + const uint8_t DeRtiaTable[3][5] = + { +//Rload 0 10 30 50 100 + {0x00, 0x01, 0x02, 0x03, 0x06}, /* RTIA 50Ohm */ + {0x03, 0x04, 0x05, 0x06, 0x07}, /* RTIA 100Ohm */ + {0x07, 0x07, 0x09, 0x09, 0x0a}, /* RTIA 200Ohm */ + }; + if(DeRload < HSTIADERLOAD_OPEN) + tempreg = (uint32_t)(DeRtiaTable[DeRtia][DeRload])<<3; + else + tempreg = (0x1f)<<3; /* Set it to HSTIADERTIA_OPEN. This setting is illegal */ + } + /* deal with HSTIA Rload */ + tempreg |= DeRload; + if(DExPin) //DE1 + AD5940_WriteReg(REG_AFE_DE1RESCON, tempreg); + else //DE0 + AD5940_WriteReg(REG_AFE_DE0RESCON, tempreg); +} + +/** + @brief Initialize High speed TIA amplifier + @param pHsTiaCfg: Pointer to configuration structure + @return return none. +*/ +AD5940Err AD5940_HSTIACfgS(HSTIACfg_Type *pHsTiaCfg) +{ + uint32_t tempreg; + //Check parameters + if(pHsTiaCfg == NULL) return AD5940ERR_NULLP; + /* Available parameter is 1k, 5k,...,160k, short, OPEN */ + if(pHsTiaCfg->HstiaDeRtia < HSTIADERTIA_1K) + return AD5940ERR_PARA; + if(pHsTiaCfg->HstiaDeRtia > HSTIADERTIA_OPEN) + return AD5940ERR_PARA; /* Parameter is invalid */ + + if(pHsTiaCfg->HstiaDeRload > HSTIADERLOAD_OPEN) + return AD5940ERR_PARA; /* Available parameter is OPEN, 0R,..., 100R */ + + tempreg = 0; + tempreg |= pHsTiaCfg->HstiaBias; + AD5940_WriteReg(REG_AFE_HSTIACON, tempreg); + /* HSRTIACON */ + /* Calculate CTIA value */ + tempreg = pHsTiaCfg->HstiaCtia << BITP_AFE_HSRTIACON_CTIACON; + tempreg |= pHsTiaCfg->HstiaRtiaSel; + if(pHsTiaCfg->DiodeClose == bTRUE) + tempreg |= BITM_AFE_HSRTIACON_TIASW6CON; /* Close switch 6 */ + AD5940_WriteReg(REG_AFE_HSRTIACON, tempreg); + /* DExRESCON */ + __AD5940_SetDExRTIA(0, pHsTiaCfg->HstiaDeRtia, pHsTiaCfg->HstiaDeRload); +#ifdef CHIPSEL_M355 + __AD5940_SetDExRTIA(1, pHsTiaCfg->HstiaDe1Rtia, pHsTiaCfg->HstiaDe1Rload); +#endif + + /* Done */ + return AD5940ERR_OK; +} +/** + * @brief Configure HSTIA RTIA resistor and keep other parameters unchanged. + * @param HSTIARtia: The RTIA setting, select it from @ref HSTIARTIA_Const + * @return return none. +*/ +void AD5940_HSRTIACfgS(uint32_t HSTIARtia) +{ + uint32_t tempreg; + tempreg = AD5940_ReadReg(REG_AFE_HSRTIACON); + tempreg &= ~BITM_AFE_HSRTIACON_RTIACON; + HSTIARtia &= BITM_AFE_HSRTIACON_RTIACON; + tempreg |= HSTIARtia<WgType == WGTYPE_SIN) + { + /* Configure Sine wave Generator */ + AD5940_WriteReg(REG_AFE_WGFCW, pWGInit->SinCfg.SinFreqWord); + AD5940_WriteReg(REG_AFE_WGAMPLITUDE, pWGInit->SinCfg.SinAmplitudeWord); + AD5940_WriteReg(REG_AFE_WGOFFSET, pWGInit->SinCfg.SinOffsetWord); + AD5940_WriteReg(REG_AFE_WGPHASE, pWGInit->SinCfg.SinPhaseWord); + } + else if(pWGInit->WgType == WGTYPE_TRAPZ) + { + /* Configure Trapezoid Generator */ + AD5940_WriteReg(REG_AFE_WGDCLEVEL1, pWGInit->TrapzCfg.WGTrapzDCLevel1); + AD5940_WriteReg(REG_AFE_WGDCLEVEL2, pWGInit->TrapzCfg.WGTrapzDCLevel2); + AD5940_WriteReg(REG_AFE_WGDELAY1, pWGInit->TrapzCfg.WGTrapzDelay1); + AD5940_WriteReg(REG_AFE_WGDELAY2, pWGInit->TrapzCfg.WGTrapzDelay2); + AD5940_WriteReg(REG_AFE_WGSLOPE1, pWGInit->TrapzCfg.WGTrapzSlope1); + AD5940_WriteReg(REG_AFE_WGSLOPE2, pWGInit->TrapzCfg.WGTrapzSlope2); + } + else + { + /* Write DAC data. It's only have effect when WgType set to WGTYPE_MMR */ + AD5940_WriteReg(REG_AFE_HSDACDAT, pWGInit->WgCode); + } + tempreg = 0; + + if(pWGInit->GainCalEn == bTRUE) + tempreg |= BITM_AFE_WGCON_DACGAINCAL; + if(pWGInit->OffsetCalEn == bTRUE) + tempreg |= BITM_AFE_WGCON_DACOFFSETCAL; + tempreg |= (pWGInit->WgType) << BITP_AFE_WGCON_TYPESEL; + AD5940_WriteReg(REG_AFE_WGCON, tempreg); +} + +/** + * @brief Write HSDAC code directly when WG configured to MMR type + * @param code: The 12-bit HSDAC code. + * @return return none. +*/ +AD5940Err AD5940_WGDACCodeS(uint32_t code) +{ + code &= 0xfff; + AD5940_WriteReg(REG_AFE_HSDACDAT, code); + return AD5940ERR_OK; +} + +/** + * @brief Update WG SIN wave frequency in Hz. + * @param SinFreqHz: The desired frequency in Hz. + * @param WGClock: The clock for WG. It's same as system clock and the default value is internal 16MHz HSOSC. + * @return return none. +*/ +void AD5940_WGFreqCtrlS(float SinFreqHz, float WGClock) +{ + uint32_t freq_word; + freq_word = AD5940_WGFreqWordCal(SinFreqHz, WGClock); + AD5940_WriteReg(REG_AFE_WGFCW, freq_word); +} + +/** + @brief Calculate sine wave generator frequency word. The maxim frequency is 250kHz-1LSB + @param SinFreqHz : Target frequency in Hz unit. + @param WGClock: Waveform generator clock frequency in Hz unit. The clock is sourced from system clock, default value is 16MHz HFOSC. + @return return none. +*/ +uint32_t AD5940_WGFreqWordCal(float SinFreqHz, float WGClock) +{ + uint32_t temp; + uint32_t __BITWIDTH_WGFCW = 26; + if(bIsS2silicon == bTRUE) + __BITWIDTH_WGFCW = 30; + if(WGClock == 0) return 0; + temp = (uint32_t)(SinFreqHz*(1LL<<__BITWIDTH_WGFCW)/WGClock + 0.5f); + if(temp > ((__BITWIDTH_WGFCW == 26)?0xfffff:0xffffff)) + temp = (__BITWIDTH_WGFCW == 26)?0xfffff:0xffffff; + + return temp; +} + +/** + * @} Waveform_Generator_Functions + * @} High_Speed_Loop_Functions + * @} High_Speed_Loop +*/ + + +/** + * @defgroup Low_Power_Loop + * @brief The low power loop. + * @{ + * @defgroup Low_Power_Loop_Functions + * @{ +*/ + +/** + @brief Configure low power loop include LPDAC LPAmp(PA and TIA) + @param pLpLoopCfg: Pointer to configure structure; + @return return none. +*/ +void AD5940_LPLoopCfgS(LPLoopCfg_Type *pLpLoopCfg) +{ + AD5940_LPDACCfgS(&pLpLoopCfg->LpDacCfg); + AD5940_LPAMPCfgS(&pLpLoopCfg->LpAmpCfg); +} + +/** + @brief Initialize LPDAC + @param pLpDacCfg: Pointer to configuration structure + @return return none. +*/ +void AD5940_LPDACCfgS(LPDACCfg_Type *pLpDacCfg) +{ + uint32_t tempreg; + tempreg = 0; + tempreg = (pLpDacCfg->LpDacSrc)<LpDacVzeroMux)<LpDacVbiasMux)<LpDacRef)<DataRst == bFALSE) + tempreg |= BITM_AFE_LPDACCON0_RSTEN; + if(pLpDacCfg->PowerEn == bFALSE) + tempreg |= BITM_AFE_LPDACCON0_PWDEN; + if(pLpDacCfg->LpdacSel == LPDAC0) + { + AD5940_WriteReg(REG_AFE_LPDACCON0, tempreg); + AD5940_LPDAC0WriteS(pLpDacCfg->DacData12Bit, pLpDacCfg->DacData6Bit); + AD5940_WriteReg(REG_AFE_LPDACSW0, pLpDacCfg->LpDacSW|BITM_AFE_LPDACSW0_LPMODEDIS); /* Overwrite LPDACSW settings. On Si1, this register is not accessible. */ + } + else + { + AD5940_WriteReg(REG_AFE_LPDACCON1, tempreg); + AD5940_LPDAC1WriteS(pLpDacCfg->DacData12Bit, pLpDacCfg->DacData6Bit); + AD5940_WriteReg(REG_AFE_LPDACSW1, pLpDacCfg->LpDacSW|BITM_AFE_LPDACSW0_LPMODEDIS); /* Overwrite LPDACSW settings. On Si1, this register is not accessible. */ + } +} + +/** + @brief Write LPDAC data + @param Data12Bit: 12Bit DAC data + @param Data6Bit: 6Bit DAC data + @return return none. +*/ +void AD5940_LPDACWriteS(uint16_t Data12Bit, uint8_t Data6Bit) +{ + /* Check parameter */ + Data6Bit &= 0x3f; + Data12Bit &= 0xfff; + AD5940_WriteReg(REG_AFE_LPDACDAT0, ((uint32_t)Data6Bit<<12)|Data12Bit); +} + +/** + @brief Write LPDAC0 data + @param Data12Bit: 12Bit DAC data + @param Data6Bit: 6Bit DAC data + @return return none. +*/ +void AD5940_LPDAC0WriteS(uint16_t Data12Bit, uint8_t Data6Bit) +{ + /* Check parameter */ + Data6Bit &= 0x3f; + Data12Bit &= 0xfff; + AD5940_WriteReg(REG_AFE_LPDACDAT0, ((uint32_t)Data6Bit<<12)|Data12Bit); +} + +/** + @brief Write LPDAC1 data + @param Data12Bit: 12Bit DAC data + @param Data6Bit: 6Bit DAC data + @return return none. +*/ +void AD5940_LPDAC1WriteS(uint16_t Data12Bit, uint8_t Data6Bit) +{ + /* Check parameter */ + Data6Bit &= 0x3f; + Data12Bit &= 0xfff; + AD5940_WriteReg(REG_AFE_LPDACDAT1, ((uint32_t)Data6Bit<<12)|Data12Bit); +} + +/** + @brief Initialize LP TIA and PA + @param pLpAmpCfg: Pointer to configuration structure + @return return none. +*/ +void AD5940_LPAMPCfgS(LPAmpCfg_Type *pLpAmpCfg) +{ + //check parameters + uint32_t tempreg; + + tempreg = 0; + if(pLpAmpCfg->LpPaPwrEn == bFALSE) + tempreg |= BITM_AFE_LPTIACON0_PAPDEN; + if(pLpAmpCfg->LpTiaPwrEn == bFALSE) + tempreg |= BITM_AFE_LPTIACON0_TIAPDEN; + if(pLpAmpCfg->LpAmpPwrMod == LPAMPPWR_HALF) + tempreg |= BITM_AFE_LPTIACON0_HALFPWR; + else + { + tempreg |= pLpAmpCfg->LpAmpPwrMod<LpTiaRtia<LpTiaRload<LpTiaRf<LpAmpSel == LPAMP0) + { + AD5940_WriteReg(REG_AFE_LPTIACON0, tempreg); + AD5940_WriteReg(REG_AFE_LPTIASW0, pLpAmpCfg->LpTiaSW); + } + else + { + AD5940_WriteReg(REG_AFE_LPTIACON1, tempreg); + AD5940_WriteReg(REG_AFE_LPTIASW1, pLpAmpCfg->LpTiaSW); + } +} +/** + * @} Low_Power_Loop_Functions + * @} Low_Power_Loop +*/ + + +/** + * @defgroup DSP_Block + * @brief DSP block includes ADC, filters, DFT and statistic functions. + * @{ + * @defgroup DSP_Block_Functions + * @{ + * */ + +/** + @brief Configure low power loop include LPDAC LPAmp(PA and TIA) + @param pDSPCfg: Pointer to configure structure; + @return return none. +*/ +void AD5940_DSPCfgS(DSPCfg_Type *pDSPCfg) +{ + AD5940_ADCBaseCfgS(&pDSPCfg->ADCBaseCfg); + AD5940_ADCFilterCfgS(&pDSPCfg->ADCFilterCfg); + AD5940_ADCDigCompCfgS(&pDSPCfg->ADCDigCompCfg); + AD5940_DFTCfgS(&pDSPCfg->DftCfg); + AD5940_StatisticCfgS(&pDSPCfg->StatCfg); +} + +/** + @brief Read AD5940 generated data like ADC and DFT etc. + @param AfeResultSel: available parameters are @ref AFERESULT_Const + - AFERESULT_SINC3: Read SINC3 filter data result + - AFERESULT_SINC2: Read SINC2+NOTCH filter result, when Notch filter is bypassed, the result is SINC2 + - AFERESULT_STATSVAR: Statistic variance result + @return return data read back. +*/ +uint32_t AD5940_ReadAfeResult(uint32_t AfeResultSel) +{ + uint32_t rd = 0; + //PARA_CHECK((AfeResultSel)); + switch (AfeResultSel) + { + case AFERESULT_SINC3: + rd = AD5940_ReadReg(REG_AFE_ADCDAT); + break; + case AFERESULT_SINC2: + rd = AD5940_ReadReg(REG_AFE_SINC2DAT); + break; + case AFERESULT_TEMPSENSOR: + rd = AD5940_ReadReg(REG_AFE_TEMPSENSDAT); + break; + case AFERESULT_DFTREAL: + rd = AD5940_ReadReg(REG_AFE_DFTREAL); + break; + case AFERESULT_DFTIMAGE: + rd = AD5940_ReadReg(REG_AFE_DFTIMAG); + break; + case AFERESULT_STATSMEAN: + rd = AD5940_ReadReg(REG_AFE_STATSMEAN); + break; + case AFERESULT_STATSVAR: + rd = AD5940_ReadReg(REG_AFE_STATSVAR); + break; + } + + return rd; +} + +/** + * @defgroup ADC_Block_Functions + * @{ +*/ + +/** + @brief Initializes ADC peripheral according to the specified parameters in the pADCInit. + @param pADCInit: Pointer to ADC initialize structure. + @return return none. +*/ +void AD5940_ADCBaseCfgS(ADCBaseCfg_Type *pADCInit) +{ + uint32_t tempreg = 0; + //PARA_CHECK(IS_ADCMUXP(pADCInit->ADCMuxP)); + //PARA_CHECK(IS_ADCMUXN(pADCInit->ADCMuxN)); + PARA_CHECK(IS_ADCPGA(pADCInit->ADCPga)); + PARA_CHECK(IS_ADCAAF(pADCInit->ADCAAF)); + + tempreg = pADCInit->ADCMuxP; + tempreg |= (uint32_t)(pADCInit->ADCMuxN)<OffCancEnable == bTRUE) + // tempreg |= BITM_AFE_ADCCON_GNOFSELPGA; + tempreg |= (uint32_t)(pADCInit->ADCPga)<ADCSinc3Osr)); + PARA_CHECK(IS_ADCSINC2OSR(pFiltCfg->ADCSinc2Osr)); + PARA_CHECK(IS_ADCAVGNUM(pFiltCfg->ADCAvgNum)); + PARA_CHECK(IS_ADCRATE(pFiltCfg->ADCRate)); + + tempreg = AD5940_ReadReg(REG_AFE_ADCFILTERCON); + tempreg &= BITM_AFE_ADCFILTERCON_AVRGEN; /* Keep this bit setting. */ + + tempreg |= pFiltCfg->ADCRate; + if(pFiltCfg->BpNotch == bTRUE) + tempreg |= BITM_AFE_ADCFILTERCON_LPFBYPEN; + if(pFiltCfg->BpSinc3 == bTRUE) + tempreg |= BITM_AFE_ADCFILTERCON_SINC3BYP; + /** + * Average filter is enabled when DFT source is @ref DFTSRC_AVG in function @ref AD5940_DFTCfgS. + * Once average function is enabled, it's automatically set as DFT source, register DFTCON.DFTINSEL is ignored. + */ + //if(pFiltCfg->AverageEnable == bTRUE) + // tempreg |= BITM_AFE_ADCFILTERCON_AVRGEN; + tempreg |= (uint32_t)(pFiltCfg->ADCSinc2Osr)<ADCSinc3Osr)<ADCAvgNum)<Sinc2NotchEnable) + { + AD5940_AFECtrlS(AFECTRL_SINC2NOTCH,bTRUE); + } +} + +/** + @brief Power up or power down ADC block(including ADC PGA and FRONTBUF). + @param State : {bTRUE, bFALSE} + - bTRUE: Power up ADC + - bFALSE: Power down ADC + @return return none. +*/ +void AD5940_ADCPowerCtrlS(BoolFlag State) +{ + uint32_t tempreg; + tempreg = AD5940_ReadReg(REG_AFE_AFECON); + if(State == bTRUE) + { + tempreg |= BITM_AFE_AFECON_ADCEN; + } + else + { + tempreg &= ~BITM_AFE_AFECON_ADCEN; + } + AD5940_WriteReg(REG_AFE_AFECON,tempreg); +} + +/** + @brief Start or stop ADC convert. + @param State : {bTRUE, bFALSE} + - bTRUE: Start ADC convert + - bFALSE: Stop ADC convert + @return return none. +*/ +void AD5940_ADCConvtCtrlS(BoolFlag State) +{ + uint32_t tempreg; + tempreg = AD5940_ReadReg(REG_AFE_AFECON); + if(State == bTRUE) + { + tempreg |= BITM_AFE_AFECON_ADCCONVEN; + } + else + { + tempreg &= ~BITM_AFE_AFECON_ADCCONVEN; + } + AD5940_WriteReg(REG_AFE_AFECON,tempreg); +} + +/** + @brief Configure ADC input MUX + @param ADCMuxP : {ADCMUXP_FLOAT, ADCMUXP_HSTIA_P, ,,, ,ADCMUXP_P_NODE} + - ADCMUXP_FLOAT: float ADC MUX positive input + - ADCMUXP_HSTIA_P: High speed TIA output sense terminal + - ADCMUXP_P_NODE: Excitation loop P node + @param ADCMuxN : {ADCMUXP_FLOAT, ADCMUXP_HSTIA_P, ,,, ,ADCMUXP_P_NODE} + - ADCMUXP_FLOAT: float ADC MUX positive input + - ADCMUXP_HSTIA_P: High speed TIA output sense terminal + - ADCMUXP_P_NODE: Excitation loop P node + + @return return none. +*/ +void AD5940_ADCMuxCfgS(uint32_t ADCMuxP, uint32_t ADCMuxN) +{ + uint32_t tempreg; + //PARA_CHECK(IS_ADCMUXP(ADCMuxP)); + //PARA_CHECK(IS_ADCMUXN(ADCMuxN)); + + tempreg = AD5940_ReadReg(REG_AFE_ADCCON); + tempreg &= ~(BITM_AFE_ADCCON_MUXSELN|BITM_AFE_ADCCON_MUXSELP); + tempreg |= ADCMuxP<ADCMin); + AD5940_WriteReg(REG_AFE_ADCMINSM, pCompCfg->ADCMinHys); + AD5940_WriteReg(REG_AFE_ADCMAX, pCompCfg->ADCMax); + AD5940_WriteReg(REG_AFE_ADCMAXSMEN, pCompCfg->ADCMaxHys); +} +/** @} ADC_Block_Functions */ + +/** + @brief Configure statistic functions + @param pStatCfg: Pointer to configuration structure + @return return none. +*/ +void AD5940_StatisticCfgS(StatCfg_Type *pStatCfg) +{ + uint32_t tempreg; + //check parameters + tempreg = 0; + if(pStatCfg->StatEnable == bTRUE) + tempreg |= BITM_AFE_STATSCON_STATSEN; + tempreg |= (pStatCfg->StatSample) << BITP_AFE_STATSCON_SAMPLENUM; + tempreg |= (pStatCfg->StatDev) << BITP_AFE_STATSCON_STDDEV; + AD5940_WriteReg(REG_AFE_STATSCON, tempreg); +} + +/** + * @brief Set ADC Repeat convert function number. Turn off ADC automatically after Number samples of ADC raw data are ready + * @param Number: Specify after how much ADC raw data need to sample before shutdown ADC + * @return return none. +*/ +void AD5940_ADCRepeatCfgS(uint32_t Number) +{ + //check parameter if(number<255) + AD5940_WriteReg(REG_AFE_REPEATADCCNV, Number<DftSrc == DFTSRC_AVG) + { + reg_adcfilter |= BITM_AFE_ADCFILTERCON_AVRGEN; + AD5940_WriteReg(REG_AFE_ADCFILTERCON, reg_adcfilter); + } + else + { + /* Disable Average function and set correct DFT source */ + reg_adcfilter &= ~BITM_AFE_ADCFILTERCON_AVRGEN; + AD5940_WriteReg(REG_AFE_ADCFILTERCON, reg_adcfilter); + + /* Set new DFT source */ + reg_dftcon |= (pDftCfg->DftSrc) << BITP_AFE_DFTCON_DFTINSEL; + } + /* Set DFT number */ + reg_dftcon |= (pDftCfg->DftNum) << BITP_AFE_DFTCON_DFTNUM; + + if(pDftCfg->HanWinEn == bTRUE) + reg_dftcon |= BITM_AFE_DFTCON_HANNINGEN; + AD5940_WriteReg(REG_AFE_DFTCON, reg_dftcon); +} + +/** + * @} DSP_Block_Functions + * @} DSP_Block +*/ + +/** + * @defgroup Sequencer_FIFO + * @brief Sequencer and FIFO. + * @{ + * @defgroup Sequencer_FIFO_Functions + * @{ +*/ + +/** + @brief Configure AD5940 FIFO + @param pFifoCfg: Pointer to configuration structure. + @return return none. +*/ +void AD5940_FIFOCfg(FIFOCfg_Type *pFifoCfg) +{ + uint32_t tempreg; + //check parameters + AD5940_WriteReg(REG_AFE_FIFOCON, 0); /* Disable FIFO firstly! */ + /* CMDDATACON register. Configure this firstly */ + tempreg = AD5940_ReadReg(REG_AFE_CMDDATACON); + tempreg &= BITM_AFE_CMDDATACON_CMD_MEM_SEL|BITM_AFE_CMDDATACON_CMDMEMMDE; /* Keep sequencer memory settings */ + tempreg |= pFifoCfg->FIFOMode << BITP_AFE_CMDDATACON_DATAMEMMDE; /* Data FIFO mode: stream or FIFO */ + tempreg |= pFifoCfg->FIFOSize << BITP_AFE_CMDDATACON_DATA_MEM_SEL; /* Data FIFO memory size */ + /* The reset memory can be used for sequencer, configure it by function AD5940_SEQCfg() */ + AD5940_WriteReg(REG_AFE_CMDDATACON, tempreg); + + /* FIFO Threshold */ + AD5940_WriteReg(REG_AFE_DATAFIFOTHRES, pFifoCfg->FIFOThresh << BITP_AFE_DATAFIFOTHRES_HIGHTHRES); + /* FIFOCON register. Final step is to enable FIFO */ + tempreg = 0; + if(pFifoCfg->FIFOEn == bTRUE) + tempreg |= BITM_AFE_FIFOCON_DATAFIFOEN; /* Enable FIFO after everything set. */ + tempreg |= pFifoCfg->FIFOSrc << BITP_AFE_FIFOCON_DATAFIFOSRCSEL; + AD5940_WriteReg(REG_AFE_FIFOCON, tempreg); +} + +/** + @brief Read current FIFO configuration. + @param pFifoCfg: Pointer to a buffer that used to store FIFO configuration. + @return return AD5940ERR_OK if succeed. +*/ +AD5940Err AD5940_FIFOGetCfg(FIFOCfg_Type *pFifoCfg) +{ + uint32_t tempreg; + //check parameters + if(pFifoCfg == NULL) return AD5940ERR_NULLP; + /* CMDDATACON register. */ + tempreg = AD5940_ReadReg(REG_AFE_CMDDATACON); + pFifoCfg->FIFOMode = (tempreg&BITM_AFE_CMDDATACON_DATAMEMMDE)>>BITP_AFE_CMDDATACON_DATAMEMMDE; + pFifoCfg->FIFOSize = (tempreg&BITM_AFE_CMDDATACON_DATA_MEM_SEL)>>BITP_AFE_CMDDATACON_DATA_MEM_SEL; + + /* FIFO Threshold */ + tempreg = AD5940_ReadReg(REG_AFE_DATAFIFOTHRES); + pFifoCfg->FIFOThresh = (tempreg&BITM_AFE_DATAFIFOTHRES_HIGHTHRES)>>BITP_AFE_DATAFIFOTHRES_HIGHTHRES; + /* FIFOCON register. */ + tempreg = AD5940_ReadReg(REG_AFE_FIFOCON); + pFifoCfg->FIFOEn = (tempreg&BITM_AFE_FIFOCON_DATAFIFOEN)?bTRUE:bFALSE; + pFifoCfg->FIFOSrc = (tempreg&BITM_AFE_FIFOCON_DATAFIFOSRCSEL)>>BITP_AFE_FIFOCON_DATAFIFOSRCSEL; + + return AD5940ERR_OK; +} + +/** + * @brief Configure AD5940 FIFO Source and enable or disable FIFO. + * @param FifoSrc : available choices are @ref FIFOSRC_Const + * - FIFOSRC_SINC3 SINC3 data + * - FIFOSRC_DFT DFT real and imaginary part + * - FIFOSRC_SINC2NOTCH SINC2+NOTCH block. Notch can be bypassed, so SINC2 data can be feed to FIFO + * - FIFOSRC_VAR Statistic variance output + * - FIFOSRC_MEAN Statistic mean output + * @param FifoEn: enable or disable the FIFO. + * @return return none. +*/ +void AD5940_FIFOCtrlS(uint32_t FifoSrc, BoolFlag FifoEn) +{ + uint32_t tempreg; + + tempreg = 0; + if(FifoEn == bTRUE) + tempreg |= BITM_AFE_FIFOCON_DATAFIFOEN; + tempreg |= FifoSrc << BITP_AFE_FIFOCON_DATAFIFOSRCSEL; + AD5940_WriteReg(REG_AFE_FIFOCON, tempreg); +} + +/** + * @brief Configure AD5940 Data FIFO threshold value + @param FIFOThresh: FIFO threshold value + @return return none. +*/ +void AD5940_FIFOThrshSet(uint32_t FIFOThresh) +{ + /* FIFO Threshold */ + AD5940_WriteReg(REG_AFE_DATAFIFOTHRES, FIFOThresh << BITP_AFE_DATAFIFOTHRES_HIGHTHRES); +} + +/** + * @brief Get Data count in FIFO + * @return return none. +*/ +uint32_t AD5940_FIFOGetCnt(void) +{ + return AD5940_ReadReg(REG_AFE_FIFOCNTSTA) >> BITP_AFE_FIFOCNTSTA_DATAFIFOCNTSTA; +} + + +/* Sequencer */ +/** + * @brief Initialize Sequencer + * @param pSeqCfg: Pointer to configuration structure + @return return none. +*/ +void AD5940_SEQCfg(SEQCfg_Type *pSeqCfg) +{ + /* check parameters */ + uint32_t tempreg, fifocon; + + fifocon = AD5940_ReadReg(REG_AFE_FIFOCON); + AD5940_WriteReg(REG_AFE_FIFOCON, 0); /* Disable FIFO before changing memory configuration */ + /* Configure CMDDATACON register */ + tempreg = AD5940_ReadReg(REG_AFE_CMDDATACON); + tempreg &= ~(BITM_AFE_CMDDATACON_CMDMEMMDE|BITM_AFE_CMDDATACON_CMD_MEM_SEL); /* Clear settings for sequencer memory */ + tempreg |= (1L) << BITP_AFE_CMDDATACON_CMDMEMMDE; /* Sequencer is always in memory mode */ + tempreg |= (pSeqCfg->SeqMemSize) << BITP_AFE_CMDDATACON_CMD_MEM_SEL; + AD5940_WriteReg(REG_AFE_CMDDATACON, tempreg); + + if(pSeqCfg->SeqCntCRCClr) + { + AD5940_WriteReg(REG_AFE_SEQCON, 0); /* Disable sequencer firstly */ + AD5940_WriteReg(REG_AFE_SEQCNT, 0); /* When sequencer is disabled, any write to SEQCNT will clear CNT and CRC register */ + } + tempreg = 0; + if(pSeqCfg->SeqEnable == bTRUE) + tempreg |= BITM_AFE_SEQCON_SEQEN; + tempreg |= (pSeqCfg->SeqWrTimer) << BITP_AFE_SEQCON_SEQWRTMR; + AD5940_WriteReg(REG_AFE_SEQCON, tempreg); + AD5940_WriteReg(REG_AFE_FIFOCON, fifocon); /* restore FIFO configuration */ + + // tempreg = 0; + // if(pSeqCfg->SeqBreakEn) + // tempreg |= 0x01; // add register definition? bitm_afe_ + // if(pSeqCfg->SeqIgnoreEn) + // tempreg |= 0x02; + // AD5940_WriteReg(0x21dc, tempreg); +} +/** + * @brief Read back current sequencer configuration and store it to pSeqCfg + * @param pSeqCfg: Pointer to structure + * @return return AD5940ERR_OK if succeed. +*/ +AD5940Err AD5940_SEQGetCfg(SEQCfg_Type *pSeqCfg) +{ + /* check parameters */ + uint32_t tempreg; + if(pSeqCfg == NULL) + return AD5940ERR_NULLP; + /* Read CMDDATACON register */ + tempreg = AD5940_ReadReg(REG_AFE_CMDDATACON); + pSeqCfg->SeqMemSize = (tempreg&BITM_AFE_CMDDATACON_CMD_MEM_SEL) >> BITP_AFE_CMDDATACON_CMD_MEM_SEL; + pSeqCfg->SeqCntCRCClr = bFALSE; /* Has no meaning */ + /* SEQCON register */ + tempreg = AD5940_ReadReg(REG_AFE_SEQCON); + pSeqCfg->SeqEnable = (tempreg&BITM_AFE_SEQCON_SEQEN)?bTRUE:bFALSE; + pSeqCfg->SeqWrTimer = (tempreg&BITM_AFE_SEQCON_SEQWRTMR) >> BITP_AFE_SEQCON_SEQWRTMR; + return AD5940ERR_OK; +} + +/** + * @brief Enable or Disable sequencer. + * @note Only after valid trigger signal, sequencer can run. + * @return return none. +*/ +void AD5940_SEQCtrlS(BoolFlag SeqEn) +{ + uint32_t tempreg = AD5940_ReadReg(REG_AFE_SEQCON); + if(SeqEn == bTRUE) + tempreg |= BITM_AFE_SEQCON_SEQEN; + else + tempreg &= ~BITM_AFE_SEQCON_SEQEN; + + AD5940_WriteReg(REG_AFE_SEQCON, tempreg); +} + +/** + * @brief Halt sequencer immediately. Use this to debug. In normal application, there is no situation that can use this function. + * @return return none. +*/ +void AD5940_SEQHaltS(void) +{ + AD5940_WriteReg(REG_AFE_SEQCON, BITM_AFE_SEQCON_SEQHALT|BITM_AFE_SEQCON_SEQEN); +} + +/** + * @brief Trigger sequencer by register write. + * @return return none. +**/ +void AD5940_SEQMmrTrig(uint32_t SeqId) +{ + if(SeqId > SEQID_3) + return; + AD5940_WriteReg(REG_AFECON_TRIGSEQ, 1L<SeqId) + { + case SEQID_0: + /* Configure SEQINFO register */ + AD5940_WriteReg(REG_AFE_SEQ0INFO, (pSeq->SeqLen<< 16) | pSeq->SeqRamAddr); + break; + case SEQID_1: + AD5940_WriteReg(REG_AFE_SEQ1INFO, (pSeq->SeqLen<< 16) | pSeq->SeqRamAddr); + break; + case SEQID_2: + AD5940_WriteReg(REG_AFE_SEQ2INFO, (pSeq->SeqLen<< 16) | pSeq->SeqRamAddr); + break; + case SEQID_3: + AD5940_WriteReg(REG_AFE_SEQ3INFO, (pSeq->SeqLen<< 16) | pSeq->SeqRamAddr); + break; + default: + break; + } + if(pSeq->WriteSRAM == bTRUE) + { + AD5940_SEQCmdWrite(pSeq->SeqRamAddr, pSeq->pSeqCmd, pSeq->SeqLen); + } +} + +/** + * @brief Get sequence info: start address and sequence length. + * @param SeqId: Select from {SEQID_0, SEQID_1, SEQID_2, SEQID_3} + - Select which sequence we want to get the information. + @param pSeqInfo: Pointer to sequence info structure. + @return return AD5940ERR_OK when succeed. +*/ +AD5940Err AD5940_SEQInfoGet(uint32_t SeqId, SEQInfo_Type *pSeqInfo) +{ + uint32_t tempreg; + if(pSeqInfo == NULL) return AD5940ERR_NULLP; + switch(SeqId) + { + case SEQID_0: + tempreg = AD5940_ReadReg(REG_AFE_SEQ0INFO); + break; + case SEQID_1: + tempreg = AD5940_ReadReg(REG_AFE_SEQ1INFO); + break; + case SEQID_2: + tempreg = AD5940_ReadReg(REG_AFE_SEQ2INFO); + break; + case SEQID_3: + tempreg = AD5940_ReadReg(REG_AFE_SEQ3INFO); + break; + default: + return AD5940ERR_PARA; + } + pSeqInfo->pSeqCmd = 0; /* We don't know where you store the sequence in MCU SRAM */ + pSeqInfo->SeqId = SeqId; + pSeqInfo->SeqLen = (tempreg>>16)&0x7ff; + pSeqInfo->SeqRamAddr = tempreg&0x7ff; + pSeqInfo->WriteSRAM = bFALSE; /* Don't care */ + + return AD5940ERR_OK; +} + + +/** + @brief Control GPIO with register SYNCEXTDEVICE. Because sequencer have no ability to access register GPIOOUT, + so we use this register for sequencer. + @param Gpio : Select from {AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin2|AGPIO_Pin3|AGPIO_Pin4|AGPIO_Pin5|AGPIO_Pin6|AGPIO_Pin7} + - The combination of GPIO pins. The selected pins will be set to High. Others will be pulled low. + @return return None. + +**/ +void AD5940_SEQGpioCtrlS(uint32_t Gpio) +{ + AD5940_WriteReg(REG_AFE_SYNCEXTDEVICE, Gpio); +} + +/** + * @brief Read back current count down timer value for Sequencer Timer Out command. + * @return return register value of Sequencer Timer out value. +**/ +uint32_t AD5940_SEQTimeOutRd(void) +{ + return AD5940_ReadReg(REG_AFE_SEQTIMEOUT); +} + +/** + * @brief Configure GPIO to allow it to trigger corresponding sequence(SEQ0/1/2/3). + * @details There are four sequences. We can use GPIO to trigger each sequence. For example, + * GP0 or GP4 can be used to trigger sequence0 and GP3 or GP7 to trigger sequence3. + * There are five mode available to detect pin action: Rising edge, falling edge, both rising and falling + * edge, low level or high level. + * Be careful to use level detection. The trigger signal is always available if the pin level is matched. + * Once the sequence is done, it will immediately run again if the pin level is still matched. + * @return return AD5940ERR_OK if succeed. +**/ +AD5940Err AD5940_SEQGpioTrigCfg(SeqGpioTrig_Cfg *pSeqGpioTrigCfg) +{ + uint32_t reg_ei0con, reg_ei1con; + uint32_t pin_count, pin_mask; + uint32_t mode, en; + if(pSeqGpioTrigCfg == NULL) + return AD5940ERR_NULLP; + reg_ei0con = AD5940_ReadReg(REG_ALLON_EI0CON); + reg_ei1con = AD5940_ReadReg(REG_ALLON_EI1CON); + + pin_count = 0; /* Start from pin0 */ + pin_mask = 0x01; /* start from pin0, mask 0x01 */ + pSeqGpioTrigCfg->SeqPinTrigMode &= 0x07; /* 3bit width */ + + mode = pSeqGpioTrigCfg->SeqPinTrigMode; + en = pSeqGpioTrigCfg->bEnable?1:0; + for(;;) + { + uint32_t bit_position; + if(pSeqGpioTrigCfg->PinSel&pin_mask) + { + if(pin_count < 4) /* EI0CON register */ + { + bit_position = pin_count*4; + reg_ei0con &= ~(0xfL<SeqxWakeupTime[0] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ0WUPH, (pWuptCfg->SeqxWakeupTime[0] & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ0SLEEPL, (pWuptCfg->SeqxSleepTime[0] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ0SLEEPH, (pWuptCfg->SeqxSleepTime[0] & 0xF0000)>>16); + + AD5940_WriteReg(REG_WUPTMR_SEQ1WUPL, (pWuptCfg->SeqxWakeupTime[1] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ1WUPH, (pWuptCfg->SeqxWakeupTime[1] & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ1SLEEPL, (pWuptCfg->SeqxSleepTime[1] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ1SLEEPH, (pWuptCfg->SeqxSleepTime[1] & 0xF0000)>>16); + + AD5940_WriteReg(REG_WUPTMR_SEQ2WUPL, (pWuptCfg->SeqxWakeupTime[2] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ2WUPH, (pWuptCfg->SeqxWakeupTime[2] & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ2SLEEPL, (pWuptCfg->SeqxSleepTime[2] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ2SLEEPH, (pWuptCfg->SeqxSleepTime[2] & 0xF0000)>>16); + + AD5940_WriteReg(REG_WUPTMR_SEQ3WUPL, (pWuptCfg->SeqxWakeupTime[3] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ3WUPH, (pWuptCfg->SeqxWakeupTime[3] & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ3SLEEPL, (pWuptCfg->SeqxSleepTime[3] & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ3SLEEPH, (pWuptCfg->SeqxSleepTime[3] & 0xF0000)>>16); + + /* TMRCON register */ + //if(pWuptCfg->WakeupEn == bTRUE) /* enable use Wupt to wakeup AFE */ + /* We always allow Wupt to wakeup AFE automatically. */ + AD5940_WriteReg(REG_ALLON_TMRCON, BITM_ALLON_TMRCON_TMRINTEN); + /* Wupt order */ + tempreg = 0; + tempreg |= (pWuptCfg->WuptOrder[0]&0x03) << BITP_WUPTMR_SEQORDER_SEQA; /* position A */ + tempreg |= (pWuptCfg->WuptOrder[1]&0x03) << BITP_WUPTMR_SEQORDER_SEQB; /* position B */ + tempreg |= (pWuptCfg->WuptOrder[2]&0x03) << BITP_WUPTMR_SEQORDER_SEQC; /* position C */ + tempreg |= (pWuptCfg->WuptOrder[3]&0x03) << BITP_WUPTMR_SEQORDER_SEQD; /* position D */ + tempreg |= (pWuptCfg->WuptOrder[4]&0x03) << BITP_WUPTMR_SEQORDER_SEQE; /* position E */ + tempreg |= (pWuptCfg->WuptOrder[5]&0x03) << BITP_WUPTMR_SEQORDER_SEQF; /* position F */ + tempreg |= (pWuptCfg->WuptOrder[6]&0x03) << BITP_WUPTMR_SEQORDER_SEQG; /* position G */ + tempreg |= (pWuptCfg->WuptOrder[7]&0x03) << BITP_WUPTMR_SEQORDER_SEQH; /* position H */ + AD5940_WriteReg(REG_WUPTMR_SEQORDER, tempreg); + + tempreg = 0; + if(pWuptCfg->WuptEn == bTRUE) + tempreg |= BITM_WUPTMR_CON_EN; + /* We always allow Wupt to trigger sequencer */ + tempreg |= pWuptCfg->WuptEndSeq << BITP_WUPTMR_CON_ENDSEQ; + //tempreg |= 1L<<4; + AD5940_WriteReg(REG_WUPTMR_CON, tempreg); +} + +/** + * @brief Enable or disable wakeup timer + * @param Enable : {bTRUE, bFALSE} + * - bTRUE: enable wakeup timer + * - bFALSE: Disable wakeup timer + * @return return none. +*/ +void AD5940_WUPTCtrl(BoolFlag Enable) +{ + uint16_t tempreg; + tempreg = AD5940_ReadReg(REG_WUPTMR_CON); + tempreg &= ~BITM_WUPTMR_CON_EN; + + if(Enable == bTRUE) + tempreg |= BITM_WUPTMR_CON_EN; + + AD5940_WriteReg(REG_WUPTMR_CON, tempreg); +} + +/** + * @brief Configure WakeupTimer. + * @param SeqId: Select from SEQID_0/1/2/3. The wakeup timer will load corresponding value from four sets of registers. + * @param SleepTime: After how much time, AFE will try to enter hibernate. We disabled this feature in AD59840_Initialize. After this timer expired, nothing will happen. + * @param WakeupTime: After how much time, AFE will wakeup and trigger corresponding sequencer. + * @note By SleepTime and WakeupTime, the sequencer is triggered periodically and period is (SleepTime+WakeupTime) + * @return return none. +*/ +AD5940Err AD5940_WUPTTime(uint32_t SeqId, uint32_t SleepTime, uint32_t WakeupTime) +{ + switch (SeqId) + { + case SEQID_0: + { + AD5940_WriteReg(REG_WUPTMR_SEQ0WUPL, (WakeupTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ0WUPH, (WakeupTime & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ0SLEEPL, (SleepTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ0SLEEPH, (SleepTime & 0xF0000)>>16); + break; + } + case SEQID_1: + { + AD5940_WriteReg(REG_WUPTMR_SEQ1WUPL, (WakeupTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ1WUPH, (WakeupTime & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ1SLEEPL, (SleepTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ1SLEEPH, (SleepTime & 0xF0000)>>16); + break; + } + case SEQID_2: + { + AD5940_WriteReg(REG_WUPTMR_SEQ2WUPL, (WakeupTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ2WUPH, (WakeupTime & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ2SLEEPL, (SleepTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ2SLEEPH, (SleepTime & 0xF0000)>>16); + break; + } + case SEQID_3: + { + AD5940_WriteReg(REG_WUPTMR_SEQ3WUPL, (WakeupTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ3WUPH, (WakeupTime & 0xF0000)>>16); + AD5940_WriteReg(REG_WUPTMR_SEQ3SLEEPL, (SleepTime & 0xFFFF)); + AD5940_WriteReg(REG_WUPTMR_SEQ3SLEEPH, (SleepTime & 0xF0000)>>16); + break; + } + default: + return AD5940ERR_PARA; + } + return AD5940ERR_OK; +} + +/** + * @} end-of Sequencer_FIFO_Functions + * @} end-of Sequencer_FIFO +*/ + +/** + * @defgroup MISC_Block + * @brief Other functions not included in above blocks. Clock, GPIO, INTC etc. + * @{ + * @defgroup MISC_Block_Functions + * @{ +*/ + +/** + * @brief Configure AD5940 clock + * @param pClkCfg: Pointer to configuration structure. + * @return return none. +*/ +void AD5940_CLKCfg(CLKCfg_Type *pClkCfg) +{ + uint32_t tempreg, reg_osccon; + + reg_osccon = AD5940_ReadReg(REG_ALLON_OSCCON); + /* Enable clocks */ + if(pClkCfg->HFXTALEn == bTRUE) + { + reg_osccon |= BITM_ALLON_OSCCON_HFXTALEN; + AD5940_WriteReg(REG_ALLON_OSCKEY,KEY_OSCCON); /* Write Key */ + AD5940_WriteReg(REG_ALLON_OSCCON, reg_osccon); /* Enable HFXTAL */ + while((AD5940_ReadReg(REG_ALLON_OSCCON)&BITM_ALLON_OSCCON_HFXTALOK) == 0); /* Wait for clock ready */ + } + + if(pClkCfg->HFOSCEn == bTRUE) + { + reg_osccon |= BITM_ALLON_OSCCON_HFOSCEN; + AD5940_WriteReg(REG_ALLON_OSCKEY,KEY_OSCCON); /* Write Key */ + AD5940_WriteReg(REG_ALLON_OSCCON, reg_osccon); /* Enable HFOSC */ + while((AD5940_ReadReg(REG_ALLON_OSCCON)&BITM_ALLON_OSCCON_HFOSCOK) == 0); /* Wait for clock ready */ + /* Configure HFOSC mode if it's enabled. */ + if(pClkCfg->HfOSC32MHzMode == bTRUE) + AD5940_HFOSC32MHzCtrl(bTRUE); + else + AD5940_HFOSC32MHzCtrl(bFALSE); + } + + if(pClkCfg->LFOSCEn == bTRUE) + { + reg_osccon |= BITM_ALLON_OSCCON_LFOSCEN; + AD5940_WriteReg(REG_ALLON_OSCKEY,KEY_OSCCON); /* Write Key */ + AD5940_WriteReg(REG_ALLON_OSCCON, reg_osccon); /* Enable LFOSC */ + while((AD5940_ReadReg(REG_ALLON_OSCCON)&BITM_ALLON_OSCCON_LFOSCOK) == 0); /* Wait for clock ready */ + } + + /* Switch clocks */ + /* step1. Set clock divider */ + tempreg = pClkCfg->SysClkDiv&0x3f; + tempreg |= (pClkCfg->SysClkDiv&0x3f) << BITP_AFECON_CLKCON0_SYSCLKDIV; + tempreg |= (pClkCfg->ADCClkDiv&0xf) << BITP_AFECON_CLKCON0_ADCCLKDIV; + AD5940_WriteReg(REG_AFECON_CLKCON0, tempreg); + AD5940_Delay10us(10); + /* Step2. set clock source */ + tempreg = pClkCfg->SysClkSrc; + tempreg |= pClkCfg->ADCCLkSrc << BITP_AFECON_CLKSEL_ADCCLKSEL; + AD5940_WriteReg(REG_AFECON_CLKSEL, tempreg); + + /* Disable clocks */ + if(pClkCfg->HFXTALEn == bFALSE) + reg_osccon &= ~BITM_ALLON_OSCCON_HFXTALEN; + if(pClkCfg->HFOSCEn == bFALSE) + reg_osccon &= ~BITM_ALLON_OSCCON_HFOSCEN; + if(pClkCfg->LFOSCEn == bFALSE) + reg_osccon &= ~BITM_ALLON_OSCCON_LFOSCEN; + AD5940_WriteReg(REG_ALLON_OSCKEY, KEY_OSCCON); /* Write Key */ + AD5940_WriteReg(REG_ALLON_OSCCON, reg_osccon); +} + +/** + * @brief Configure Internal HFOSC to output 32MHz or 16MHz. + * @param Mode32MHz : {bTRUE, bFALSE} + * - bTRUE: HFOSC 32MHz mode. + * - bFALSE: HFOSC 16MHz mode. + * @return return none. +*/ +void AD5940_HFOSC32MHzCtrl(BoolFlag Mode32MHz) +{ + uint32_t RdCLKEN1; + uint32_t RdHPOSCCON; + + uint32_t bit8,bit9; + + RdCLKEN1 = AD5940_ReadReg(REG_AFECON_CLKEN1); + bit8 = (RdCLKEN1>>9)&0x01; + bit9 = (RdCLKEN1>>8)&0x01; /* Fix bug in silicon, bit8 and bit9 is swapped when read back. */ + RdCLKEN1 = RdCLKEN1&0xff; + RdCLKEN1 |= (bit8<<8)|(bit9<<9); + AD5940_WriteReg(REG_AFECON_CLKEN1,RdCLKEN1|BITM_AFECON_CLKEN1_ACLKDIS); /* Disable ACLK during clock changing */ + + RdHPOSCCON = AD5940_ReadReg(REG_AFE_HPOSCCON); + if(Mode32MHz == bTRUE) + { + AD5940_WriteReg(REG_AFE_HPOSCCON,RdHPOSCCON&(~BITM_AFE_HPOSCCON_CLK32MHZEN)); /* Enable 32MHz output(bit definition-0: 32MHz, 1: 16MHz) */ + while((AD5940_ReadReg(REG_ALLON_OSCCON)&BITM_ALLON_OSCCON_HFOSCOK) == 0); /* Wait for clock ready */ + } + else + { + AD5940_WriteReg(REG_AFE_HPOSCCON,RdHPOSCCON|BITM_AFE_HPOSCCON_CLK32MHZEN); /* Enable 16MHz output(bit definition-0: 32MHz, 1: 16MHz) */ + while((AD5940_ReadReg(REG_ALLON_OSCCON)&BITM_ALLON_OSCCON_HFOSCOK) == 0); /* Wait for clock ready */ + } + + AD5940_WriteReg(REG_AFECON_CLKEN1,RdCLKEN1&(~BITM_AFECON_CLKEN1_ACLKDIS)); /* Enable ACLK */ +} +/** + * @brief Enable high power mode for high frequency EIS + * @param Mode32MHz : {bTRUE, bFALSE} + * - bTRUE: HFOSC 32MHz mode. + * - bFALSE: HFOSC 16MHz mode. + * @return return none. +*/ +void AD5940_HPModeEn(BoolFlag Enable) +{ + CLKCfg_Type clk_cfg; + uint32_t temp_reg = 0; + + /* Check what the system clock is */ + temp_reg = AD5940_ReadReg(REG_AFECON_CLKSEL); + clk_cfg.ADCCLkSrc = (temp_reg>>2)&0x3; + clk_cfg.SysClkSrc = temp_reg & 0x3; + if(Enable == bTRUE) + { + clk_cfg.SysClkDiv = SYSCLKDIV_2; + clk_cfg.HfOSC32MHzMode = bTRUE; + AD5940_AFEPwrBW(AFEPWR_HP, AFEBW_250KHZ); + } + else + { + clk_cfg.SysClkDiv = SYSCLKDIV_1; + clk_cfg.HfOSC32MHzMode = bFALSE; + AD5940_AFEPwrBW(AFEPWR_LP, AFEBW_100KHZ); + } + clk_cfg.ADCClkDiv = ADCCLKDIV_1; + clk_cfg.HFOSCEn = (temp_reg & 0x3) == 0x1? bFALSE : bTRUE;; + clk_cfg.HFXTALEn = (temp_reg & 0x3) == 0x1? bTRUE : bFALSE; + clk_cfg.LFOSCEn = bTRUE; + AD5940_CLKCfg(&clk_cfg); +} + +/** + * @defgroup Interrupt_Controller_Functions + * @{ +*/ +/* AFE Interrupt Controller */ +/** + * @brief Enable or Disable selected interrupt source(s) + * @param AfeIntcSel : {AFEINTC_0, AFEINTC_1} + * - AFEINTC_0: Configure Interrupt Controller 0 + * - AFEINTC_1: Configure Interrupt Controller 1 + * @param AFEIntSrc: select from @ref AFEINTC_SRC_Const + * - AFEINTSRC_ADCRDY : Bit0 ADC Result Ready Status + * - AFEINTSRC_DFTRDY : Bit1 DFT Result Ready Status + * - AFEINTSRC_SUPPLYFILTRDY : Bit2 Low Pass Filter Result Status + * - AFEINTSRC_TEMPRDY : Bit3, Temp Sensor Result Ready + * - AFEINTSRC_ADCMINERR : Bit4, ADC Minimum Value + * - AFEINTSRC_ADCMAXERR : Bit5, ADC Maximum Value + * - AFEINTSRC_ADCDIFFERR : Bit6, ADC Delta Ready + * - AFEINTSRC_MEANRDY : Bit7, Mean Result Ready + * - AFEINTSRC_VARRDY : Bit8, Variance Result Ready + * - AFEINTSRC_DLYCMDDONE : Bit9, User controlled interrupt by writing AFEGENINTSTA. Provides an Early Indication for the End of the Test _Block. + * - AFEINTSRC_HWSETUPDONE : Bit10, User controlled interrupt by writing AFEGENINTSTA. Indicates the MMR Setup for the Measurement Step Finished + * - AFEINTSRC_BRKSEQ : Bit11, User controlled interrupt by writing AFEGENINTSTA. + * - AFEINTSRC_CUSTOMINS : Bit12, User controlled interrupt by writing AFEGENINTSTA. General Purpose Custom Interrupt. + * - AFEINTSRC_BOOTLDDONE : Bit13, OTP Boot Loading Done + * - AFEINTSRC_WAKEUP : Bit14, AFE Woken up + * - AFEINTSRC_ENDSEQ : Bit15, End of Sequence Interrupt. + * - AFEINTSRC_SEQTIMEOUT : Bit16, Sequencer Timeout Command Finished. + * - AFEINTSRC_SEQTIMEOUTERR : Bit17, Sequencer Timeout Command Error. + * - AFEINTSRC_CMDFIFOFULL : Bit18, Command FIFO Full Interrupt. + * - AFEINTSRC_CMDFIFOEMPTY : Bit19, Command FIFO Empty + * - AFEINTSRC_CMDFIFOTHRESH: Bit20, Command FIFO Threshold Interrupt. + * - AFEINTSRC_CMDFIFOOF : Bit21, Command FIFO Overflow Interrupt. + * - AFEINTSRC_CMDFIFOUF : Bit22, Command FIFO Underflow Interrupt. + * - AFEINTSRC_DATAFIFOFULL : Bit23, Data FIFO Full Interrupt. + * - AFEINTSRC_DATAFIFOEMPTY: Bit24, Data FIFO Empty + * - AFEINTSRC_DATAFIFOTHRESH: Bit25, Data FIFO Threshold Interrupt. + * - AFEINTSRC_DATAFIFOOF : Bit26, Data FIFO Overflow Interrupt. + * - AFEINTSRC_DATAFIFOUF : Bit27, Data FIFO Underflow Interrupt. + * - AFEINTSRC_WDTIRQ : Bit28, WDT Timeout Interrupt. + * - AFEINTSRC_CRC_OUTLIER : Bit29, CRC interrupt for M355, Outliers Int for AD5940 + * - AFEINTSRC_GPT0INT_SLPWUT: Bit30, General Purpose Timer0 IRQ for M355. Sleep or Wakeup Timer timeout for AD5940 + * - AFEINTSRC_GPT1INT_TRYBRK: Bit31, General Purpose Timer1 IRQ for M355. Tried to Break IRQ for AD5940 + * - AFE_INTC_ALLINT : All interrupts + * @param State : {bTRUE, bFALSE} + * - bTRUE: Enable these interrupt source(s) + * - bFALSE: Disable interrupt source(s) + * @return return none. +*/ +void AD5940_INTCCfg(uint32_t AfeIntcSel, uint32_t AFEIntSrc, BoolFlag State) +{ + uint32_t tempreg; + uint32_t regaddr = REG_INTC_INTCSEL0; + + if(AfeIntcSel == AFEINTC_1) + regaddr = REG_INTC_INTCSEL1; + + tempreg = AD5940_ReadReg(regaddr); + if(State == bTRUE) + tempreg |= AFEIntSrc; /* Enable this interrupt */ + else + tempreg &= ~(AFEIntSrc); /* Disable this interrupt */ + AD5940_WriteReg(regaddr,tempreg); +} + +/** + * @brief Check if current interrupt configuration. + * @param AfeIntcSel : {AFEINTC_0, AFEINTC_1} + * - AFEINTC_0: Configure Interrupt Controller 0 + * - AFEINTC_1: Configure Interrupt Controller 1 +*/ +uint32_t AD5940_INTCGetCfg(uint32_t AfeIntcSel) +{ + uint32_t tempreg; + if(AfeIntcSel == AFEINTC_0) + tempreg = AD5940_ReadReg(REG_INTC_INTCSEL0); + else + tempreg = AD5940_ReadReg(REG_INTC_INTCSEL1); + return tempreg; +} + +/** + * @brief Clear selected interrupt(s) flag(INTC0Flag and INTC1Flag are both cleared). + * @param AfeIntSrcSel: Select from @ref AFEINTC_SRC_Const + * @return return none. +**/ +void AD5940_INTCClrFlag(uint32_t AfeIntSrcSel) +{ + AD5940_WriteReg(REG_INTC_INTCCLR,AfeIntSrcSel); +} + +/** + * @brief Test if selected interrupt source(s) is(are) bTRUE. + * @param AfeIntcSel : {AFEINTC_0, AFEINTC_1} + * - AFEINTC_0: Read Interrupt Controller 0 flag + * - AFEINTC_1: Read Interrupt Controller 1 flag + * @param AfeIntSrcSel: Select from @ref AFEINTC_SRC_Const + * @return If selected interrupt source(s) are all cleared, return bFALSE. Otherwise return bTRUE. +**/ +BoolFlag AD5940_INTCTestFlag(uint32_t AfeIntcSel, uint32_t AfeIntSrcSel) +{ + uint32_t tempreg; + uint32_t regaddr = (AfeIntcSel == AFEINTC_0)? REG_INTC_INTCFLAG0: REG_INTC_INTCFLAG1; + + tempreg = AD5940_ReadReg(regaddr); + if(tempreg & AfeIntSrcSel) + return bTRUE; + else + return bFALSE; +} + +/** + * @brief return register value of REG_INTC_INTCFLAGx + * @param AfeIntcSel : {AFEINTC_0, AFEINTC_1} + * - AFEINTC_0: Read Interrupt Controller 0 flag + * - AFEINTC_1: Read Interrupt Controller 1 flag + * @return register value of REG_INTC_INTCFLAGx. +**/ +uint32_t AD5940_INTCGetFlag(uint32_t AfeIntcSel) +{ + uint32_t tempreg; + uint32_t regaddr = (AfeIntcSel == AFEINTC_0)? REG_INTC_INTCFLAG0: REG_INTC_INTCFLAG1; + + tempreg = AD5940_ReadReg(regaddr); + return tempreg; +} + +/** + * @} Interrupt_Controller_Functions +*/ + +/** + * @defgroup GPIO_Block_Functions + * @{ +*/ + +/** + * @brief Initialize AFE GPIO + * @param pAgpioCfg: Pointer to configuration structure + * @return return none. +*/ +void AD5940_AGPIOCfg(AGPIOCfg_Type *pAgpioCfg) +{ + AD5940_AGPIOFuncCfg(pAgpioCfg->FuncSet); + AD5940_AGPIOOen(pAgpioCfg->OutputEnSet); + AD5940_AGPIOIen(pAgpioCfg->InputEnSet); + AD5940_AGPIOPen(pAgpioCfg->PullEnSet); + AD5940_WriteReg(REG_AGPIO_GP0OUT, pAgpioCfg->OutVal); +} + +/** + * @brief Configure the function of GP0 to GP7. + * @param uiCfgSet :{GP0_INT,GP0_TRIG,GP0_SYNC,GP0_GPIO| + * GP1_GPIO,GP1_TRIG,GP1_SYNC,GP1_SLEEP| + * GP2_PORB,GP2_TRIG,GP2_SYNC,GP2_EXTCLK| + * GP3_GPIO,GP3_TRIG,GP3_SYNC,GP3_INT0|\ + * GP4_GPIO,GP4_TRIG,GP4_SYNC,GP4_INT1| + * GP5_GPIO,GP5_TRIG,GP5_SYNC,GP5_EXTCLK| + * GP6_GPIO,GP6_TRIG,GP6_SYNC,GP6_INT0| + * GP7_GPIO,GP7_TRIG,GP7_SYNC,GP7_INT} + * @return return none. +**/ +void AD5940_AGPIOFuncCfg(uint32_t uiCfgSet) +{ + AD5940_WriteReg(REG_AGPIO_GP0CON,uiCfgSet); +} + +/** + * @brief Enable GPIO output mode on selected pins. Disable output on non-selected pins. + * @param uiPinSet :Select from {AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin2|AGPIO_Pin3|AGPIO_Pin4|AGPIO_Pin5|AGPIO_Pin6|AGPIO_Pin7} + * @return return none +**/ +void AD5940_AGPIOOen(uint32_t uiPinSet) +{ + AD5940_WriteReg(REG_AGPIO_GP0OEN,uiPinSet); +} + +/** + * @brief Enable input on selected pins while disable others. + * @param uiPinSet: Select from {AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin2|AGPIO_Pin3|AGPIO_Pin4|AGPIO_Pin5|AGPIO_Pin6|AGPIO_Pin7} + * @return return none +**/ +void AD5940_AGPIOIen(uint32_t uiPinSet) +{ + AD5940_WriteReg(REG_AGPIO_GP0IEN,uiPinSet); +} + +/** + * @brief Read the GPIO status. + * @return return GP0IN register which is the GPIO status. +**/ +uint32_t AD5940_AGPIOIn(void) +{ + return AD5940_ReadReg(REG_AGPIO_GP0IN); +} + +/** + * @brief Enable pull-up or down on selected pins while disable other pins. + * @param uiPinSet: Select from: {AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin2|AGPIO_Pin3|AGPIO_Pin4|AGPIO_Pin5|AGPIO_Pin6|AGPIO_Pin7} + * @return return none +**/ +void AD5940_AGPIOPen(uint32_t uiPinSet) +{ + AD5940_WriteReg(REG_AGPIO_GP0PE,uiPinSet); +} + +/** + * @brief Put selected GPIOs to high level. + * @param uiPinSet: Select from: {AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin2|AGPIO_Pin3|AGPIO_Pin4|AGPIO_Pin5|AGPIO_Pin6|AGPIO_Pin7} + * @return return none +**/ +void AD5940_AGPIOSet(uint32_t uiPinSet) +{ + AD5940_WriteReg(REG_AGPIO_GP0SET,uiPinSet); +} + +/** + * @brief Put selected GPIOs to low level. + * @param uiPinSet: Select from: {AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin2|AGPIO_Pin3|AGPIO_Pin4|AGPIO_Pin5|AGPIO_Pin6|AGPIO_Pin7} + * @return return none +**/ +void AD5940_AGPIOClr(uint32_t uiPinSet) +{ + AD5940_WriteReg(REG_AGPIO_GP0CLR,uiPinSet); +} + +/** + * @brief Toggle selected GPIOs. + * @param uiPinSet: Select from: {AGPIO_Pin0|AGPIO_Pin1|AGPIO_Pin2|AGPIO_Pin3|AGPIO_Pin4|AGPIO_Pin5|AGPIO_Pin6|AGPIO_Pin7} + * @return return none +**/ +void AD5940_AGPIOToggle(uint32_t uiPinSet) +{ + AD5940_WriteReg(REG_AGPIO_GP0TGL,uiPinSet); +} + +/** + * @} GPIO_Block_Functions +*/ + +/** + * @defgroup LPMode_Block_Functions + * @{ +*/ +/** + * @brief Enter or leave LPMODE. + * @details Once enter this mode, some registers are collected together to a new register so we can + * Control most blocks with in one register. The so called LPMODE has nothing to do with AD5940 power. + * @return return AD5940ERR_OK +**/ +AD5940Err AD5940_LPModeEnS(BoolFlag LPModeEn) +{ + if(LPModeEn == bTRUE) + AD5940_WriteReg(REG_AFE_LPMODEKEY, KEY_LPMODEKEY); /* Enter LP mode by right key. */ + else + AD5940_WriteReg(REG_AFE_LPMODEKEY, 0); /* Write wrong key to exit LP mode */ + return AD5940ERR_OK; +} + +/** + * @brief Select system clock source for LPMODE. + * @note Only in LP Mode, this operation takes effect. Enter LPMODE by function @ref AD5940_LPModeEnS. + * @param LPModeClk: Select from @ref LPMODECLK_Const + * - LPMODECLK_LFOSC: Select LFOSC 32kHz for system clock + * - LPMODECLK_HFOSC: Select HFOSC 16MHz/32MHz for system clock + * @return none. +*/ +void AD5940_LPModeClkS(uint32_t LPModeClk) +{ + AD5940_WriteReg(REG_AFE_LPMODECLKSEL, LPModeClk); +} + +/** + * @} LPMode_Block_Functions +*/ + +/** + * @brief Enter sleep mode key to unlock it or enter incorrect key to lock it. \ + * Once key is unlocked, it will always be effect until manually lock it + * @param SlpKey : {SLPKEY_UNLOCK, SLPKEY_LOCK} + - SLPKEY_UNLOCK Unlock Key so we can enter sleep(or called hibernate) mode. + - SLPKEY_LOCK Lock key so AD5940 is prohibited to enter sleep mode. + @return return none. +*/ +void AD5940_SleepKeyCtrlS(uint32_t SlpKey) +{ + AD5940_WriteReg(REG_AFE_SEQSLPLOCK, SlpKey); +} + +/** + * @brief Put AFE to hibernate. + * @details This will only take effect when SLP_KEY has been unlocked. Use function @ref AD5940_SleepKeyCtrlS to enter correct key. + * @return return none. +*/ +void AD5940_EnterSleepS(void) +{ + AD5940_WriteReg(REG_AFE_SEQTRGSLP, 0); + AD5940_WriteReg(REG_AFE_SEQTRGSLP, 1); +} + +/** + * @brief Turn off LP-Loop and put AFE to hibernate mode; + * @details By function @ref AD5940_EnterSleepS, we can put most blocks to hibernate mode except LP block. + * This function will shut down LP block and then enter sleep mode. + * @return return none. +*/ +void AD5940_ShutDownS(void) +{ + /* Turn off LPloop related blocks which are not controlled automatically by hibernate operation */ + AFERefCfg_Type aferef_cfg; + LPLoopCfg_Type lp_loop; + /* Turn off LP-loop manually because it's not affected by sleep/hibernate mode */ + AD5940_StructInit(&aferef_cfg, sizeof(aferef_cfg)); + AD5940_StructInit(&lp_loop, sizeof(lp_loop)); + AD5940_REFCfgS(&aferef_cfg); + AD5940_LPLoopCfgS(&lp_loop); + AD5940_SleepKeyCtrlS(SLPKEY_UNLOCK); /* Unlock the key */ + AD5940_EnterSleepS(); /* Enter Hibernate */ +} + +/** + * @brief Try to wakeup AD5940 by read register. + * @details Any SPI operation can wakeup AD5940. AD5940_Initialize must be called to enable this function. + * @param TryCount Specify how many times we will read register. Zero or negative number means always waiting here. + * @return How many times register is read. If returned value is bigger than TryCount, it means wakeup failed. +*/ +uint32_t AD5940_WakeUp(int32_t TryCount) +{ + uint32_t count = 0; + while(1) + { + count++; + if(AD5940_ReadReg(REG_AFECON_ADIID) == AD5940_ADIID) + break; /* Succeed */ + if(TryCount<=0) + continue; /* Always try to wakeup AFE */ + + if(count > TryCount) + break; /* Failed */ + } + return count; +} + +/** + * @brief Read ADIID register, the value for current version is @ref AD5940_ADIID + * @return return none. +*/ +uint32_t AD5940_GetADIID(void) +{ + return AD5940_ReadReg(REG_AFECON_ADIID); +} + +/** + * @brief Read CHIPID register, the value for current version is 0x5501. + * @return return none. +*/ +uint32_t AD5940_GetChipID(void) +{ + return AD5940_ReadReg(REG_AFECON_CHIPID); +} +/** + * @brief Reset AD5940 by register. + * @note AD5940 must be in active state so we can access registers. + * If AD5940 system clock is too low, we consider to use hardware reset, or + * we need to make sure register write is successfully. + * @return return none. +*/ +AD5940Err AD5940_SoftRst(void) +{ + AD5940_WriteReg(REG_AFECON_SWRSTCON, AD5940_SWRST); + AD5940_Delay10us(20); /* AD5940 need some time to exit reset status. 200us looks good. */ + /* We can check RSTSTA register to make sure software reset happened. */ + return AD5940ERR_OK; +} + +/** + * @brief Reset AD5940 with RESET pin. + * @note This will call function AD5940_RstClr which locates in file XXXPort.C + * @return return none. +*/ +void AD5940_HWReset(void) +{ +#ifndef CHIPSEL_M355 + AD5940_RstClr(); + AD5940_Delay10us(200); /* Delay some time */ + AD5940_RstSet(); + AD5940_Delay10us(500); /* AD5940 need some time to exit reset status. 200us looks good. */ +#else + //There is no method to reset AFE only for M355. +#endif +} + +/** + * @} MISC_Block_Functions + * @} MISC_Block +*/ + +/** + * @defgroup Calibration_Block + * @brief The non-factory calibration routines. + * @{ + * @defgroup Calibration_Functions + * @{ + * + * + */ +/** + * @brief Turn on High power 1.8V/1.1V reference and 2.5V LP reference. + * @return return none. +*/ +static void __AD5940_ReferenceON(void) +{ + AFERefCfg_Type ref_cfg; + /* Turn ON ADC/DAC and LPDAC reference */ + ref_cfg.Hp1V1BuffEn = bTRUE; + ref_cfg.Hp1V8BuffEn = bTRUE; + ref_cfg.HpBandgapEn = bTRUE; + ref_cfg.HSDACRefEn = bTRUE; + ref_cfg.LpBandgapEn = bTRUE; + ref_cfg.LpRefBufEn = bTRUE; + + ref_cfg.Disc1V1Cap = bFALSE; + ref_cfg.Disc1V8Cap = bFALSE; + ref_cfg.Hp1V8Ilimit = bFALSE; + ref_cfg.Hp1V8ThemBuff = bFALSE; + ref_cfg.Lp1V1BuffEn = bFALSE; + ref_cfg.Lp1V8BuffEn = bFALSE; + ref_cfg.LpRefBoostEn = bFALSE; + AD5940_REFCfgS(&ref_cfg); +} + +/** + * @brief Turn on ADC to sample one SINC2 data. + * @return return ADCCode. +*/ +static uint32_t __AD5940_TakeMeasurement(int32_t *time_out) +{ + uint32_t ADCCode = 0; + AD5940_INTCClrFlag(AFEINTSRC_SINC2RDY); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_SINC2NOTCH, bTRUE);/* Start conversion */ + do + { + AD5940_Delay10us(1); /* Delay 10us */ + if(AD5940_INTCTestFlag(AFEINTC_1,AFEINTSRC_SINC2RDY)) + { + ADCCode = AD5940_ReadAfeResult(AFERESULT_SINC2); + break; + } + if(*time_out != -1) + (*time_out)--; + }while(*time_out != 0); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_SINC2NOTCH, bFALSE);/* Stop conversion */ + return ADCCode; +} + +/** + @brief Calibrate ADC PGA + @param pADCPGACal: PGA calibration parameters include filter setup and PGA gain. + @return AD5940ERR_OK. +**/ +AD5940Err AD5940_ADCPGACal(ADCPGACal_Type *pADCPGACal) +{ + const float kFactor = 1.835f/1.82f; + ADCBaseCfg_Type adc_base; + + int32_t time_out; + uint32_t INTCCfg; + int32_t ADCCode; + BoolFlag bADCClk32MHzMode; + + uint32_t regaddr_gain, regaddr_offset; + + if(pADCPGACal == NULL) return AD5940ERR_NULLP; + if(pADCPGACal->ADCPga > ADCPGA_9) return AD5940ERR_PARA; /* Parameter Error */ + + if(pADCPGACal->AdcClkFreq > (32000000*0.8)) + bADCClk32MHzMode = bTRUE; + + /** + * Determine Gain calibration method according to different gain value... + * and calibration register + * */ + static const struct _cal_registers + { + uint16_t gain_reg; + uint16_t offset_reg; + }cal_registers[] = { + {REG_AFE_ADCGAINGN1,REG_AFE_ADCOFFSETGN1}, + {REG_AFE_ADCGAINGN1P5,REG_AFE_ADCOFFSETGN1P5}, + {REG_AFE_ADCGAINGN2,REG_AFE_ADCOFFSETGN2}, + {REG_AFE_ADCGAINGN4,REG_AFE_ADCOFFSETGN4}, + {REG_AFE_ADCGAINGN9,REG_AFE_ADCOFFSETGN9}, + }; + regaddr_gain = cal_registers[pADCPGACal->ADCPga].gain_reg; + regaddr_offset = cal_registers[pADCPGACal->ADCPga].offset_reg; + + /* Do initialization */ + __AD5940_ReferenceON(); + ADCFilterCfg_Type adc_filter; + /* Initialize ADC filters ADCRawData-->SINC3-->SINC2+NOTCH. Use SIN2 data for calibration-->Lower noise */ + adc_filter.ADCSinc3Osr = pADCPGACal->ADCSinc3Osr; + adc_filter.ADCSinc2Osr = pADCPGACal->ADCSinc2Osr; /* 800KSPS/4/1333 = 150SPS */ + adc_filter.ADCAvgNum = ADCAVGNUM_2; /* Don't care about it. Average function is only used for DFT */ + adc_filter.ADCRate = bADCClk32MHzMode?ADCRATE_1P6MHZ:ADCRATE_800KHZ; /* If ADC clock is 32MHz, then set it to ADCRATE_1P6MHZ. Default is 16MHz, use ADCRATE_800KHZ. */ + adc_filter.BpNotch = bTRUE; /* SINC2+Notch is one block, when bypass notch filter, we can get fresh data from SINC2 filter. */ + adc_filter.BpSinc3 = bFALSE; /* We use SINC3 filter. */ + adc_filter.Sinc2NotchEnable = bTRUE; /* Enable the SINC2+Notch block. You can also use function AD5940_AFECtrlS */ + AD5940_ADCFilterCfgS(&adc_filter); + /* Turn ON reference and ADC power, and DAC reference. We use DAC 1.8V reference to calibrate ADC because of the ADC reference bug. */ + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Disable all */ + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_HPREFPWR|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|AFECTRL_SINC2NOTCH, bTRUE); + AD5940_Delay10us(25); /* Wait 250us for reference power up */ + /* INTC configure and open calibration lock */ + INTCCfg = AD5940_INTCGetCfg(AFEINTC_1); + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bTRUE); /* Enable SINC2 Interrupt in INTC1 */ + AD5940_WriteReg(REG_AFE_CALDATLOCK, KEY_CALDATLOCK); /* Unlock KEY */ + + /* Do offset calibration. */ + if(pADCPGACal->PGACalType != PGACALTYPE_GAIN){ /* Need offset calibration */ + int32_t ExpectedCode = 0x8000; /* Ideal ADC output */ + AD5940_WriteReg(regaddr_offset, 0); /* Reset offset register */ + + adc_base.ADCMuxP = ADCMUXP_VSET1P1; + adc_base.ADCMuxN = ADCMUXN_VSET1P1; /* Short input with common voltage set to 1.11v */ + adc_base.ADCPga = pADCPGACal->ADCPga; /* Set correct Gain value. */ + AD5940_ADCBaseCfgS(&adc_base); + AD5940_Delay10us(5); /* Wait for sometime */ + ADCCode = 0; + for(int i=0; i<8; i++) + { /* ADC offset calibration register has resolution of 0.25LSB. take full use of it. */ + time_out = pADCPGACal->TimeOut10us; /* Reset time out counter */ + ADCCode += __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + if(time_out == 0) goto ADCPGACALERROR_TIMEOUT; /* Time out error. */ + } + /* Calculate and write the result to registers before gain calibration */ + ADCCode = (ExpectedCode<<3) - ADCCode; /* We will shift back 1bit below */ + /** + * AD5940 use formular Output = gain*(input + offset) for calibration. + * So, the measured results should be divided by gain to get value for offset register. + */ + uint32_t gain = AD5940_ReadReg(regaddr_gain); + ADCCode = (ADCCode*0x4000)/gain; + ADCCode = ((ADCCode+1)>>1)&0x7fff; /* Round 0.5 */ + AD5940_WriteReg(regaddr_offset, ADCCode); + } + + /* Do gain calibration */ + if(pADCPGACal->PGACalType != PGACALTYPE_OFFSET) /* Need gain calibration */ + { + int32_t ExpectedGainCode; + static const float ideal_pga_gain[]={1,1.5,2,4,9}; + AD5940_WriteReg(regaddr_gain, 0x4000); /* Reset gain register */ + if(pADCPGACal->ADCPga <= ADCPGA_2) + { + //gain1,1.5,2 could use reference directly + adc_base.ADCMuxP = ADCMUXP_VREF1P8DAC; + adc_base.ADCMuxN = ADCMUXN_VSET1P1; + ExpectedGainCode = (int32_t)((pADCPGACal->VRef1p82 - pADCPGACal->VRef1p11)*ideal_pga_gain[pADCPGACal->ADCPga]/\ + pADCPGACal->VRef1p82*32768/kFactor)\ + + 0x8000; + } + else + { + //gain4,9 use DAC generated voltage + adc_base.ADCMuxP = ADCMUXP_P_NODE; + adc_base.ADCMuxN = ADCMUXN_N_NODE; + /* Setup HSLOOP to generate voltage for GAIN4/9 calibration. */ + AD5940_AFECtrlS(AFECTRL_EXTBUFPWR|AFECTRL_INAMPPWR|AFECTRL_HSTIAPWR|AFECTRL_WG, bTRUE); + HSLoopCfg_Type hsloop_cfg; + hsloop_cfg.HsDacCfg.ExcitBufGain = EXCITBUFGAIN_2; + hsloop_cfg.HsDacCfg.HsDacGain = HSDACGAIN_1; + hsloop_cfg.HsDacCfg.HsDacUpdateRate = 7; + hsloop_cfg.HsTiaCfg.DiodeClose = bFALSE; + hsloop_cfg.HsTiaCfg.HstiaBias = HSTIABIAS_1P1; + hsloop_cfg.HsTiaCfg.HstiaCtia = 31; + hsloop_cfg.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_OPEN; + hsloop_cfg.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_OPEN; + hsloop_cfg.HsTiaCfg.HstiaDe1Rload = HSTIADERLOAD_OPEN; + hsloop_cfg.HsTiaCfg.HstiaDe1Rtia = HSTIADERTIA_OPEN; + hsloop_cfg.HsTiaCfg.HstiaRtiaSel = HSTIARTIA_200; + hsloop_cfg.SWMatCfg.Dswitch = SWD_OPEN; + hsloop_cfg.SWMatCfg.Pswitch = SWP_PL; + hsloop_cfg.SWMatCfg.Nswitch = SWN_NL; + hsloop_cfg.SWMatCfg.Tswitch = SWT_TRTIA; + hsloop_cfg.WgCfg.GainCalEn = bTRUE; + hsloop_cfg.WgCfg.OffsetCalEn = bTRUE; + hsloop_cfg.WgCfg.WgType = WGTYPE_MMR; + uint32_t HSDACCode; + if(pADCPGACal->ADCPga == ADCPGA_4) + HSDACCode = 0x800 + 0x300; /* 0x300--> 0x300/0x1000*0.8*BUFFERGAIN2 = 0.3V. */ + else if(pADCPGACal->ADCPga == ADCPGA_9) + HSDACCode = 0x800 + 0x155; /* 0x155--> 0x155/0x1000*0.8*BUFFERGAIN2 = 0.133V. */ + hsloop_cfg.WgCfg.WgCode = HSDACCode; + AD5940_HSLoopCfgS(&hsloop_cfg); + + //measure expected code + adc_base.ADCPga = ADCPGA_1P5; + AD5940_ADCBaseCfgS(&adc_base); + AD5940_Delay10us(5); + time_out = pADCPGACal->TimeOut10us; /* Reset time out counter */ + ExpectedGainCode = 0x8000 + (int32_t)((__AD5940_TakeMeasurement(&time_out) - 0x8000)/1.5f\ + *ideal_pga_gain[pADCPGACal->ADCPga]); + if(time_out == 0) goto ADCPGACALERROR_TIMEOUT; + } + adc_base.ADCPga = pADCPGACal->ADCPga; /* Set to gain under calibration */ + AD5940_ADCBaseCfgS(&adc_base); + AD5940_Delay10us(5); + time_out = pADCPGACal->TimeOut10us; /* Reset time out counter */ + ADCCode = __AD5940_TakeMeasurement(&time_out); + if(time_out == 0) goto ADCPGACALERROR_TIMEOUT; + /* Calculate and write the result to registers */ + ADCCode = (ExpectedGainCode - 0x8000)*0x4000/(ADCCode-0x8000); + ADCCode &= 0x7fff; + AD5940_WriteReg(regaddr_gain, ADCCode); + } + + /* Restore INTC1 SINC2 configure */ + if(INTCCfg&AFEINTSRC_SINC2RDY); + else + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bFALSE); /* Disable SINC2 Interrupt */ + + AD5940_WriteReg(REG_AFE_CALDATLOCK, 0); /* Lock KEY */ + /* Done */ + return AD5940ERR_OK; + +ADCPGACALERROR_TIMEOUT: + AD5940_ADCConvtCtrlS(bFALSE); /* Stop conversion */ + AD5940_WriteReg(REG_AFE_CALDATLOCK, 0); /* Lock KEY */ + return AD5940ERR_TIMEOUT; +} + +/** + * @brief Calibrate LPTIA offset + * @param pLPTIAOffsetCal Pointer to LPTIA offset calibration settings. + * @return AD5940ERR_OK. +**/ +AD5940Err AD5940_LPTIAOffsetCal(LPTIAOffsetCal_Type *pLPTIAOffsetCal) +{ + AD5940Err error = AD5940ERR_OK; + LPLoopCfg_Type lploop_cfg; + ADCBaseCfg_Type adc_base; + ADCFilterCfg_Type adc_filter; + + int32_t time_out; + uint32_t INTCCfg; + int32_t ADCCode; + BoolFlag bADCClk32MHzMode; + + if(pLPTIAOffsetCal == NULL) return AD5940ERR_NULLP; + if(pLPTIAOffsetCal->AdcClkFreq > (32000000*0.8)) + bADCClk32MHzMode = bTRUE; + + /* Step0: Do initialization */ + /* Turn on AD5940 references in case it's disabled. */ + __AD5940_ReferenceON(); + lploop_cfg.LpAmpCfg.LpAmpSel = pLPTIAOffsetCal->LpAmpSel; + lploop_cfg.LpAmpCfg.LpAmpPwrMod = pLPTIAOffsetCal->LpAmpPwrMod; /* Power mode will affect amp offset. */ + lploop_cfg.LpAmpCfg.LpPaPwrEn = bTRUE; + lploop_cfg.LpAmpCfg.LpTiaPwrEn = bTRUE; + lploop_cfg.LpAmpCfg.LpTiaRf = LPTIARF_OPEN; + lploop_cfg.LpAmpCfg.LpTiaRload = LPTIARLOAD_100R; + lploop_cfg.LpAmpCfg.LpTiaRtia = pLPTIAOffsetCal->LpTiaRtia; + lploop_cfg.LpAmpCfg.LpTiaSW = pLPTIAOffsetCal->LpTiaSW; /* Disconnect capacitors so it settles quickly */ + lploop_cfg.LpDacCfg.LpdacSel = (pLPTIAOffsetCal->LpAmpSel == LPAMP0)?LPDAC0:LPDAC1; + lploop_cfg.LpDacCfg.DacData12Bit = pLPTIAOffsetCal->DacData12Bit; + lploop_cfg.LpDacCfg.DacData6Bit = pLPTIAOffsetCal->DacData6Bit; + lploop_cfg.LpDacCfg.DataRst = bFALSE; + lploop_cfg.LpDacCfg.LpDacRef = LPDACREF_2P5; + lploop_cfg.LpDacCfg.LpDacSrc = LPDACSRC_MMR; + lploop_cfg.LpDacCfg.LpDacVzeroMux = pLPTIAOffsetCal->LpDacVzeroMux; + lploop_cfg.LpDacCfg.LpDacSW = LPDACSW_VZERO2LPTIA; + lploop_cfg.LpDacCfg.LpDacVbiasMux = LPDACVBIAS_12BIT; + lploop_cfg.LpDacCfg.PowerEn = bTRUE; + AD5940_LPLoopCfgS(&lploop_cfg); + + /* Initialize ADC filters ADCRawData-->SINC3-->SINC2+NOTCH. Use SIN2 data for calibration-->Lower noise */ + adc_filter.ADCSinc3Osr = pLPTIAOffsetCal->ADCSinc3Osr; + adc_filter.ADCSinc2Osr = pLPTIAOffsetCal->ADCSinc2Osr; /* 800KSPS/4/1333 = 150SPS */ + adc_filter.ADCAvgNum = ADCAVGNUM_2; /* Don't care about it. Average function is only used for DFT */ + adc_filter.ADCRate = bADCClk32MHzMode?ADCRATE_1P6MHZ:ADCRATE_800KHZ; /* If ADC clock is 32MHz, then set it to ADCRATE_1P6MHZ. Default is 16MHz, use ADCRATE_800KHZ. */ + adc_filter.BpNotch = bTRUE; /* SINC2+Notch is one block, when bypass notch filter, we can get fresh data from SINC2 filter. */ + adc_filter.BpSinc3 = bFALSE; /* We use SINC3 filter. */ + adc_filter.Sinc2NotchEnable = bTRUE; /* Enable the SINC2+Notch block. You can also use function AD5940_AFECtrlS */ + AD5940_ADCFilterCfgS(&adc_filter); + /* Initialize ADC MUx and PGA */ + if(pLPTIAOffsetCal->LpAmpSel == LPAMP0) + { + adc_base.ADCMuxP = ADCMUXP_LPTIA0_P; + adc_base.ADCMuxN = ADCMUXN_LPTIA0_N; + } + else + { + adc_base.ADCMuxP = ADCMUXP_LPTIA1_P; + adc_base.ADCMuxN = ADCMUXN_LPTIA1_N; + } + adc_base.ADCPga = pLPTIAOffsetCal->ADCPga; /* Set correct Gain value. */ + AD5940_ADCBaseCfgS(&adc_base); + /* Turn ON ADC and its reference. And SINC2. */ + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Disable all firstly, we only enable things we use */ + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_HPREFPWR|AFECTRL_SINC2NOTCH, bTRUE); + AD5940_Delay10us(25); /* Wait 250us for reference power up */ + /* INTC configure and open calibration lock */ + INTCCfg = AD5940_INTCGetCfg(AFEINTC_1); + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bTRUE); /* Enable SINC2 Interrupt in INTC1 */ + AD5940_WriteReg(REG_AFE_CALDATLOCK, KEY_CALDATLOCK); /* Unlock KEY */ + + /* Do offset calibration. */ + { + int32_t ExpectedCode = 0x8000; /* Ideal ADC output */ + AD5940_WriteReg(REG_AFE_ADCOFFSETLPTIA0, 0); /* Reset offset register */ + + if(pLPTIAOffsetCal->SettleTime10us > 0) + AD5940_Delay10us(pLPTIAOffsetCal->SettleTime10us); /* Delay 10us */ + time_out = pLPTIAOffsetCal->TimeOut10us; /* Reset time out counter */ + ADCCode = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + if(time_out == 0) + { + error = AD5940ERR_TIMEOUT; + goto LPTIAOFFSETCALERROR; + } /* Time out error. */ + /* Calculate and write the result to registers before gain calibration */ + ADCCode = ((ExpectedCode - ADCCode)<<3); /* We will shift back 1bit below */ + ADCCode = ((ADCCode+1)>>1); /* Round 0.5 */ + if((ADCCode > 0x3fff) || + (ADCCode < -0x4000)) /* The register used for offset calibration is limited to -0x4000 to 0x3fff */ + { + error = AD5940ERR_CALOR; + goto LPTIAOFFSETCALERROR; + } + ADCCode &= 0x7fff; + if(pLPTIAOffsetCal->LpAmpSel == LPAMP0) + AD5940_WriteReg(REG_AFE_ADCOFFSETLPTIA0, ADCCode); + else + AD5940_WriteReg(REG_AFE_ADCOFFSETLPTIA1, ADCCode); + } + /* Restore INTC1 SINC2 configure */ + if(INTCCfg&AFEINTSRC_SINC2RDY); + else + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bFALSE); /* Disable SINC2 Interrupt */ + + AD5940_WriteReg(REG_AFE_CALDATLOCK, 0); /* Lock KEY */ + /* Done */ + return AD5940ERR_OK; + +LPTIAOFFSETCALERROR: + AD5940_ADCConvtCtrlS(bFALSE); /* Stop conversion */ + AD5940_WriteReg(REG_AFE_CALDATLOCK, 0); /* Lock KEY */ + return error; +} + +/** + * @brief Calibrate HSTIA offset-ongoing. + * @param pHSTIAOffsetCal: pointer to configuration. + * @return AD5940ERR_OK. +**/ +AD5940Err AD5940_HSTIAOffsetCal(LPTIAOffsetCal_Type *pHSTIAOffsetCal) +{ + return AD5940ERR_OK; +} + +/** + * @brief Measure HSTIA internal RTIA impedance. + * @param pCalCfg: pointer to calibration structure. + * @param pResult: Pointer to a variable that used to store result. + * If bPolarResult in structure is set, then use type fImpPol_Type otherwise use fImpCar_Type. + * @return AD5940ERR_OK if succeed. +**/ +AD5940Err AD5940_HSRtiaCal(HSRTIACal_Type *pCalCfg, void *pResult) +{ + /***** CALIBRATION METHOD ****** + 1) Measure the complex voltage V_Rcal across the calibration DUT (Rcal). + 2) Measure the complex voltage V_Rtia across Rtia [HSTIA_P (output) - HSTIA_N]. + 3) Note Rtia carries the same current as Rcal; I_Rtia = I_exc = I_Rcal + 4) Implement the equation: Rtia = V_Rtia / I_Rtia + --> Rtia = (V_Rtia / V_Rcal) * Rcal + *******************************/ + + AFERefCfg_Type aferef_cfg; + HSLoopCfg_Type hs_loop; + DSPCfg_Type dsp_cfg; + uint32_t INTCCfg; + + BoolFlag bADCClk32MHzMode = bFALSE; + uint32_t ExcitBuffGain = EXCITBUFGAIN_2; + uint32_t HsDacGain = HSDACGAIN_1; + + float ExcitVolt; /* Excitation voltage, unit is mV */ + uint32_t RtiaVal; + uint32_t const HpRtiaTable[]={200,1000,5000,10000,20000,40000,80000,160000,0}; + uint32_t const HSTIADERLOADTable[]={0,10,30,50,100,999999999999}; + uint32_t const HSTIADERTIATable[] = {50,100,200,1000,5000,10000,20000,40000,80000,160000,0,999999999999999}; + uint32_t WgAmpWord; + + iImpCar_Type DftRcalVolt, DftRtiaVolt; + + if(pCalCfg == NULL) return AD5940ERR_NULLP; + if(pCalCfg->fRcal == 0) + return AD5940ERR_PARA; + //if(pCalCfg->HsTiaCfg.HstiaRtiaSel > HSTIARTIA_160K) + // return AD5940ERR_PARA; + //if(pCalCfg->HsTiaCfg.HstiaRtiaSel == HSTIARTIA_OPEN) + // return AD5940ERR_PARA; /* Do not support calibrating DE0-RTIA */ + if(pResult == NULL) + return AD5940ERR_NULLP; + + if(pCalCfg->AdcClkFreq > (32000000*0.8)) + bADCClk32MHzMode = bTRUE; + + /* Calculate the excitation voltage we should use based on RCAL/Rtia */ + if(pCalCfg->HsTiaCfg.HstiaRtiaSel == HSTIARTIA_OPEN) + { + if(pCalCfg->HsTiaCfg.HstiaDeRtia == HSTIADERTIA_TODE) + { + RtiaVal = pCalCfg->HsTiaCfg.ExtRtia; + } + else + { + RtiaVal = pCalCfg->HsTiaCfg.ExtRtia + HSTIADERLOADTable[pCalCfg->HsTiaCfg.HstiaDeRload] + HSTIADERTIATable[pCalCfg->HsTiaCfg.HstiaDeRtia]; + } + } + else + RtiaVal = HpRtiaTable[pCalCfg->HsTiaCfg.HstiaRtiaSel]; + /* + DAC output voltage calculation + Note: RCAL value should be similar to RTIA so the accuracy is best. + HSTIA output voltage should be limited to 0.2V to AVDD-0.2V, with 1.1V bias. We use 80% of this range for safe. + Because the bias voltage is fixed to 1.1V, so for AC signal maximum amplitude is 1.1V-0.2V = 0.9Vp. That's 1.8Vpp. + Formula is: ExcitVolt(in mVpp) = (1800mVpp*80% / RTIA) * RCAL + ADC input range is +-1.5V which is enough for calibration. + + */ + ExcitVolt = 1800*0.8*pCalCfg->fRcal/RtiaVal; + + if(ExcitVolt <= 800*0.05) /* Voltage is so small that we can enable the attenuator of DAC(1/5) and Excitation buffer(1/4). 800mVpp is the DAC output voltage */ + { + ExcitBuffGain = EXCITBUFGAIN_0P25; + HsDacGain = HSDACGAIN_0P2; + /* Excitation buffer voltage full range is 800mVpp*0.05 = 40mVpp */ + WgAmpWord = ((uint32_t)(ExcitVolt/40*2047*2)+1)>>1; /* Assign value with rounding (0.5 LSB error) */ + } + else if(ExcitVolt <= 800*0.25) /* Enable Excitation buffer attenuator */ + { + ExcitBuffGain = EXCITBUFGAIN_0P25; + HsDacGain = HSDACGAIN_1; + /* Excitation buffer voltage full range is 800mVpp*0.25 = 200mVpp */ + WgAmpWord = ((uint32_t)(ExcitVolt/200*2047*2)+1)>>1; /* Assign value with rounding (0.5 LSB error) */ + } + else if(ExcitVolt <= 800*0.4) /* Enable DAC attenuator */ + { + ExcitBuffGain = EXCITBUFGAIN_2; + HsDacGain = HSDACGAIN_0P2; + /* Excitation buffer voltage full range is 800mVpp*0.4 = 320mV */ + WgAmpWord = ((uint32_t)(ExcitVolt/320*2047*2)+1)>>1; /* Assign value with rounding (0.5 LSB error) */ + } + else /* No attenuator is needed. This is the best condition which means RTIA is close to RCAL */ + { + ExcitBuffGain = EXCITBUFGAIN_2; + HsDacGain = HSDACGAIN_1; + /* Excitation buffer voltage full range is 800mVpp*2=1600mVpp */ + WgAmpWord = ((uint32_t)(ExcitVolt/1600*2047*2)+1)>>1; /* Assign value with rounding (0.5 LSB error) */ + } + + if(WgAmpWord > 0x7ff) + WgAmpWord = 0x7ff; + + /*INTC configuration */ + INTCCfg = AD5940_INTCGetCfg(AFEINTC_1); + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_DFTRDY, bTRUE); /* Enable SINC2 Interrupt in INTC1 */ + + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Init all to disable state */ + /* Configure reference system */ + aferef_cfg.HpBandgapEn = bTRUE; + aferef_cfg.Hp1V1BuffEn = bTRUE; + aferef_cfg.Hp1V8BuffEn = bTRUE; + aferef_cfg.Disc1V1Cap = bFALSE; + aferef_cfg.Disc1V8Cap = bFALSE; + aferef_cfg.Hp1V8ThemBuff = bFALSE; + aferef_cfg.Hp1V8Ilimit = bFALSE; + aferef_cfg.Lp1V1BuffEn = bFALSE; + aferef_cfg.Lp1V8BuffEn = bFALSE; + aferef_cfg.LpBandgapEn = bFALSE; + aferef_cfg.LpRefBufEn = bFALSE; + aferef_cfg.LpRefBoostEn = bFALSE; + AD5940_REFCfgS(&aferef_cfg); + /* Configure HP Loop */ + hs_loop.HsDacCfg.ExcitBufGain = ExcitBuffGain; + hs_loop.HsDacCfg.HsDacGain = HsDacGain; + hs_loop.HsDacCfg.HsDacUpdateRate = 7; /* Set it to highest update rate */ + memcpy(&hs_loop.HsTiaCfg, &pCalCfg->HsTiaCfg, sizeof(pCalCfg->HsTiaCfg)); + hs_loop.SWMatCfg.Dswitch = SWD_RCAL0; + hs_loop.SWMatCfg.Pswitch = SWP_RCAL0; + hs_loop.SWMatCfg.Nswitch = SWN_RCAL1; + hs_loop.SWMatCfg.Tswitch = SWT_RCAL1|SWT_TRTIA|SWT_AIN1; + hs_loop.WgCfg.WgType = WGTYPE_SIN; + hs_loop.WgCfg.GainCalEn = bTRUE; + hs_loop.WgCfg.OffsetCalEn = bTRUE; + hs_loop.WgCfg.SinCfg.SinFreqWord = AD5940_WGFreqWordCal(pCalCfg->fFreq, pCalCfg->SysClkFreq); + hs_loop.WgCfg.SinCfg.SinAmplitudeWord = WgAmpWord; + hs_loop.WgCfg.SinCfg.SinOffsetWord = 0; + hs_loop.WgCfg.SinCfg.SinPhaseWord = 0; + AD5940_HSLoopCfgS(&hs_loop); + /* Configure DSP */ + dsp_cfg.ADCBaseCfg.ADCMuxN = ADCMUXN_N_NODE; + dsp_cfg.ADCBaseCfg.ADCMuxP = ADCMUXP_P_NODE; + dsp_cfg.ADCBaseCfg.ADCPga = ADCPGA_1P5; + AD5940_StructInit(&dsp_cfg.ADCDigCompCfg, sizeof(dsp_cfg.ADCDigCompCfg)); + dsp_cfg.ADCFilterCfg.ADCAvgNum = ADCAVGNUM_16; /* Don't care because it's disabled */ + dsp_cfg.ADCFilterCfg.ADCRate = bADCClk32MHzMode?ADCRATE_1P6MHZ:ADCRATE_800KHZ; + dsp_cfg.ADCFilterCfg.ADCSinc2Osr = pCalCfg->ADCSinc2Osr; + dsp_cfg.ADCFilterCfg.ADCSinc3Osr = pCalCfg->ADCSinc3Osr; + dsp_cfg.ADCFilterCfg.BpNotch = bTRUE; + dsp_cfg.ADCFilterCfg.BpSinc3 = bFALSE; + dsp_cfg.ADCFilterCfg.Sinc2NotchEnable = bTRUE; + + memcpy(&dsp_cfg.DftCfg, &pCalCfg->DftCfg, sizeof(pCalCfg->DftCfg)); + memset(&dsp_cfg.StatCfg, 0, sizeof(dsp_cfg.StatCfg)); + AD5940_DSPCfgS(&dsp_cfg); + + /* Enable all of them. They are automatically turned off during hibernate mode to save power */ + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_EXTBUFPWR|\ + /*AFECTRL_WG|*/AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|\ + AFECTRL_SINC2NOTCH, bTRUE); + + /***** MEASURE VOLTAGE ACROSS RCAL *****/ + AD5940_AFECtrlS(AFECTRL_WG|AFECTRL_ADCPWR, bTRUE); /* Enable Waveform generator, ADC power */ + //wait for sometime. + AD5940_Delay10us(25); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT, bTRUE); /* Start ADC convert and DFT */ + /* Wait until DFT ready */ + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_DFTRDY) == bFALSE); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT|AFECTRL_WG|AFECTRL_ADCPWR, bFALSE); /* Stop ADC convert and DFT */ + AD5940_INTCClrFlag(AFEINTSRC_DFTRDY); + + DftRcalVolt.Real = AD5940_ReadAfeResult(AFERESULT_DFTREAL); + DftRcalVolt.Image = AD5940_ReadAfeResult(AFERESULT_DFTIMAGE); + + /***** MEASURE VOLTAGE ACROSS RTIA *****/ + AD5940_ADCMuxCfgS(ADCMUXP_HSTIA_P, ADCMUXN_HSTIA_N); + AD5940_AFECtrlS(AFECTRL_WG|AFECTRL_ADCPWR, bTRUE); /* Enable Waveform generator, ADC power */ + //wait for sometime. + AD5940_Delay10us(25); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT, bTRUE); /* Start ADC convert and DFT */ + /* Wait until DFT ready */ + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_DFTRDY) == bFALSE); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT|AFECTRL_WG|AFECTRL_ADCPWR, bFALSE); /* Stop ADC convert and DFT */ + AD5940_INTCClrFlag(AFEINTSRC_DFTRDY); + + DftRtiaVolt.Real = AD5940_ReadAfeResult(AFERESULT_DFTREAL); + DftRtiaVolt.Image = AD5940_ReadAfeResult(AFERESULT_DFTIMAGE); + + if(DftRcalVolt.Real&(1L<<17)) + DftRcalVolt.Real |= 0xfffc0000; + if(DftRcalVolt.Image&(1L<<17)) + DftRcalVolt.Image |= 0xfffc0000; + if(DftRtiaVolt.Real&(1L<<17)) + DftRtiaVolt.Real |= 0xfffc0000; + if(DftRtiaVolt.Image&(1L<<17)) + DftRtiaVolt.Image |= 0xfffc0000; + /* + ADC MUX is set to HSTIA_P and HSTIA_N. + While the current flow through RCAL and then into RTIA, the current direction should be from HSTIA_N to HSTIA_P if we + measure the voltage across RCAL by MUXSELP_P_NODE and MUXSELN_N_NODE. + So here, we add a negative sign to results + */ + DftRtiaVolt.Image = -DftRtiaVolt.Image; + DftRtiaVolt.Real = -DftRtiaVolt.Real; /* Current is measured by MUX HSTIA_P-HSTIA_N. It should be */ + /* + The impedance engine inside of AD594x give us Real part and Imaginary part of DFT. Due to technology used, the Imaginary + part in register is the opposite number. So we add a negative sign on the Imaginary part of results. + */ + DftRtiaVolt.Image = -DftRtiaVolt.Image; + DftRcalVolt.Image = -DftRcalVolt.Image; + + + /***** Implement RTIA = (V_Rtia / V_Rcal) * Rcal ******/ + fImpCar_Type temp; + temp = AD5940_ComplexDivInt(&DftRtiaVolt, &DftRcalVolt); + temp.Real *= pCalCfg->fRcal; + temp.Image *= pCalCfg->fRcal; + if(pCalCfg->bPolarResult == bFALSE) + { + *(fImpCar_Type*)pResult = temp; + } + else + { + ((fImpPol_Type*)pResult)->Magnitude = AD5940_ComplexMag(&temp); + ((fImpPol_Type*)pResult)->Phase = AD5940_ComplexPhase(&temp); + } + + /* Restore INTC1 DFT configure */ + if(INTCCfg&AFEINTSRC_DFTRDY); + else + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_DFTRDY, bFALSE); /* Disable DFT Interrupt */ + + return AD5940ERR_OK; +} + +/** + * @brief Measure LPTIA internal RTIA impedance with HSTIA. This is the recommended method for LPTIA RTIA calibration. + * @param pCalCfg: pointer to calibration structure. + * @param pResult: Pointer to a variable that used to store result. + * If bPolarResult in structure is set, then use type fImpPol_Type otherwise use fImpCar_Type. + * @return AD5940ERR_OK if succeed. +**/ +AD5940Err AD5940_LPRtiaCal(LPRTIACal_Type *pCalCfg, void *pResult) +{ + HSLoopCfg_Type hs_loop; + LPLoopCfg_Type lp_loop; + DSPCfg_Type dsp_cfg; + ADCBaseCfg_Type *pADCBaseCfg; + SWMatrixCfg_Type *pSWCfg; + uint32_t INTCCfg, reg_afecon; + BoolFlag bADCClk32MHzMode = bFALSE; + BoolFlag bDCMode = bFALSE; /* Indicate if frequency is 0, which means we calibrate at DC. */ + + float ExcitVolt; /* Excitation voltage, unit is mV */ + uint32_t RtiaVal; + /* RTIA value table when RLOAD set to 100Ohm */ + uint32_t const LpRtiaTable[]={0,110,1000,2000,3000,4000,6000,8000,10000,12000,16000,20000,24000,30000,32000,40000,48000,64000,85000,96000,100000,120000,128000,160000,196000,256000,512000}; + float const ADCPGAGainTable[] = {1, 1.5, 2, 4, 9}; + uint32_t WgAmpWord; + + uint32_t ADCPgaGainRtia, ADCPgaGainRcal; + float GainRatio; + + iImpCar_Type DftRcal, DftRtia; + + if(pCalCfg == NULL) return AD5940ERR_NULLP; /* Parameters illegal */ + + if(pCalCfg->fRcal == 0) + return AD5940ERR_PARA; + if(pCalCfg->LpTiaRtia > LPTIARTIA_512K) + return AD5940ERR_PARA; + if(pCalCfg->LpTiaRtia == LPTIARTIA_OPEN) + return AD5940ERR_PARA; /* Not supported now. By setting RTIA to open and set corresponding switches can calibrate external RTIA */ + if(pResult == NULL) + return AD5940ERR_NULLP; + + if(pCalCfg->AdcClkFreq > (32000000*0.8)) + bADCClk32MHzMode = bTRUE; /* Clock frequency is high. */ + if(pCalCfg->fFreq == 0.0f) /* Frequency is zero means we calibrate RTIA at DC. */ + bDCMode = bTRUE; + /* Init two pointers */ + pSWCfg = &hs_loop.SWMatCfg; + pADCBaseCfg = &dsp_cfg.ADCBaseCfg; + /* Calculate the excitation voltage we should use based on RCAL/Rtia */ + RtiaVal = LpRtiaTable[pCalCfg->LpTiaRtia]; + /* + * DAC output voltage calculation + * Note: RCAL value should be similar to RTIA so the accuracy is best. + * LPTIA output voltage should be limited to 0.3V to AVDD-0.4V, with 1.3V bias. We use 80% of this range for safe. + * That's 2.0Vpp*80%@2.7V AVDD + * Formula is: ExcitVolt(in mVpp) = (2000mVpp*80% / RTIA) * RCAL + * ADC input range is +-1.5V which is enough for calibration. + * Limitations: + * Note: HSTIA output range is AVDD-0.4V to AGND+0.2V + * HSTIA input common voltage range is 0.3V to AVDD-0.7V; + * When AVDD is 2.7V, the input range is 0.3V to 2.0V; + * If we set Vbias to 1.3V, then maximum AC signal is 0.7Vp*2 = 1.4Vpp. + * Maximum AC signal is further limited by HSTIA RTIA=200Ohm, when RCAL is 200Ohm(for ADuCM355). The maximum output of HSTIA is limited to 2.3V. + * Maximum Vzero voltage is 1.9V when Rcal is 200Ohm and Switch On resistance is 50Ohm*2. Vzero_max = 1.3V + (2.3V-1.3V)/(200+200+50*2)*300. + * Maximum AC signal is (1.9-1.3)*2 = 1.2Vpp(for ADuCM355, RCAl=200Ohm). + */ + /** @cond */ + #define MAXVOLT_P2P 1400 /* Maximum peak to peak voltage 1200mV for ADuCM355. */ + /* Maximum peak2peak voltage for AD5940 10kOhm RCAL is 1400mV */ + #define __MAXVOLT_AMP_CODE (MAXVOLT_P2P*2047L/2200) + /** @endcond */ + ExcitVolt = 2000*0.8*pCalCfg->fRcal/RtiaVal; + WgAmpWord = ((uint32_t)(ExcitVolt/2200*2047*2)+1)>>1; /* Assign value with rounding (0.5 LSB error) */ + if(WgAmpWord > __MAXVOLT_AMP_CODE) + WgAmpWord = __MAXVOLT_AMP_CODE; + /** + * Determine the best ADC PGA gain for both RCAL and RTIA voltage measurement. + */ + { + float RtiaVolt, RcalVolt, temp; + ExcitVolt = WgAmpWord*2000.0f/2047; /* 2000mVpp -->ExcitVolt in Peak to Peak unit */ + RtiaVolt = ExcitVolt/(pCalCfg->fRcal + 100)*RtiaVal; + RcalVolt = RtiaVolt/RtiaVal*pCalCfg->fRcal; + /* The input range of ADC is 1.5Vp, we calculate how much gain we need */ + temp = 3000.0f/RcalVolt; + if(temp >= 9.0f) ADCPgaGainRcal = ADCPGA_9; + else if(temp >= 4.0f) ADCPgaGainRcal = ADCPGA_4; + else if(temp >= 2.0f) ADCPgaGainRcal = ADCPGA_2; + else if(temp >= 1.5f) ADCPgaGainRcal = ADCPGA_1P5; + else ADCPgaGainRcal = ADCPGA_1; + temp = 3000.0f/RtiaVolt; + if(temp >= 9.0f) ADCPgaGainRtia = ADCPGA_9; + else if(temp >= 4.0f) ADCPgaGainRtia = ADCPGA_4; + else if(temp >= 2.0f) ADCPgaGainRtia = ADCPGA_2; + else if(temp >= 1.5f) ADCPgaGainRtia = ADCPGA_1P5; + else ADCPgaGainRtia = ADCPGA_1; + GainRatio = ADCPGAGainTable[ADCPgaGainRtia]/ADCPGAGainTable[ADCPgaGainRcal]; + } + reg_afecon = AD5940_ReadReg(REG_AFE_AFECON); + /* INTC configuration */ + INTCCfg = AD5940_INTCGetCfg(AFEINTC_1); + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_DFTRDY|AFEINTSRC_SINC2RDY, bTRUE); /* Enable SINC2 Interrupt in INTC1 */ + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Init all to disable state */ + /* Configure reference system */ + __AD5940_ReferenceON(); + /* Configure DSP */ + AD5940_StructInit(&dsp_cfg, sizeof(dsp_cfg)); + dsp_cfg.ADCFilterCfg.ADCAvgNum = ADCAVGNUM_16; /* Don't care because it's disabled */ + dsp_cfg.ADCFilterCfg.ADCRate = bADCClk32MHzMode?ADCRATE_1P6MHZ:ADCRATE_800KHZ; + dsp_cfg.ADCFilterCfg.ADCSinc2Osr = pCalCfg->ADCSinc2Osr; + dsp_cfg.ADCFilterCfg.ADCSinc3Osr = pCalCfg->ADCSinc3Osr; + dsp_cfg.ADCFilterCfg.BpNotch = bTRUE; + dsp_cfg.ADCFilterCfg.BpSinc3 = bFALSE; + dsp_cfg.ADCFilterCfg.Sinc2NotchEnable = bTRUE; + memcpy(&dsp_cfg.DftCfg, &pCalCfg->DftCfg, sizeof(pCalCfg->DftCfg)); + AD5940_DSPCfgS(&dsp_cfg); + /* Configure LP Loop */ + AD5940_StructInit(&lp_loop, sizeof(lp_loop)); + /* Configure LP Amplifies(LPPA and LPTIA). We won't use LP-PA */ + lp_loop.LpDacCfg.LpdacSel = (pCalCfg->LpAmpSel == LPAMP0)?LPDAC0:LPDAC1; + lp_loop.LpDacCfg.DacData12Bit = 0x800; /* Controlled by WG */ + lp_loop.LpDacCfg.DacData6Bit = 32; /* middle scale value */ + lp_loop.LpDacCfg.DataRst =bFALSE; /* Do not keep DATA registers at reset status */ + lp_loop.LpDacCfg.LpDacSW = LPDACSW_VBIAS2LPPA|LPDACSW_VZERO2HSTIA; + lp_loop.LpDacCfg.LpDacRef = LPDACREF_2P5; /* Select internal 2.5V reference */ + lp_loop.LpDacCfg.LpDacSrc = LPDACSRC_WG; /* The LPDAC data comes from WG not MMR in this case */ + lp_loop.LpDacCfg.LpDacVbiasMux = LPDACVBIAS_6BIT; /* Connect Vbias signal to 6Bit LPDAC output */ + lp_loop.LpDacCfg.LpDacVzeroMux = LPDACVZERO_12BIT; /* Connect Vzero signal to 12bit LPDAC output */ + lp_loop.LpDacCfg.PowerEn = bTRUE; /* Power up LPDAC */ + + lp_loop.LpAmpCfg.LpAmpSel = pCalCfg->LpAmpSel; + lp_loop.LpAmpCfg.LpAmpPwrMod = pCalCfg->LpAmpPwrMod; /* Set low power amplifiers to normal power mode */ + lp_loop.LpAmpCfg.LpPaPwrEn = bTRUE; /* Enable LP PA(potential-stat amplifier) power */ + lp_loop.LpAmpCfg.LpTiaPwrEn = bTRUE; /* Enable LPTIA*/ + lp_loop.LpAmpCfg.LpTiaRload = LPTIARLOAD_100R; + lp_loop.LpAmpCfg.LpTiaRtia = pCalCfg->LpTiaRtia; + lp_loop.LpAmpCfg.LpTiaRf = LPTIARF_OPEN; + lp_loop.LpAmpCfg.LpTiaSW = LPTIASW(6)|LPTIASW(8)|(pCalCfg->bWithCtia==bTRUE?LPTIASW(5)/*|LPTIASW(9)*/:0); + AD5940_LPLoopCfgS(&lp_loop); + /* Configure HS Loop */ + AD5940_StructInit(&hs_loop, sizeof(hs_loop)); + /* Take care of HSTIA, we need to disconnect internal RTIA because it connects to Tswitch directly. */ + hs_loop.HsTiaCfg.DiodeClose = bFALSE; + hs_loop.HsTiaCfg.HstiaBias = (pCalCfg->LpAmpSel == LPAMP0)?HSTIABIAS_VZERO0:HSTIABIAS_VZERO1; + hs_loop.HsTiaCfg.HstiaCtia = 31; + hs_loop.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_OPEN; + hs_loop.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_OPEN; + hs_loop.HsTiaCfg.HstiaDe1Rload = HSTIADERLOAD_OPEN; + hs_loop.HsTiaCfg.HstiaDe1Rtia = HSTIADERTIA_OPEN; + hs_loop.HsTiaCfg.HstiaRtiaSel = HSTIARTIA_200; + /* Configure HSDAC */ + hs_loop.HsDacCfg.ExcitBufGain = 0; + hs_loop.HsDacCfg.HsDacGain = 0; /* Don't care */ + hs_loop.HsDacCfg.HsDacUpdateRate = 255; /* Lowest for LPDAC */ + + hs_loop.SWMatCfg.Dswitch = SWD_RCAL0|((pCalCfg->LpAmpSel == LPAMP0)?SWD_SE0:SWD_SE1); + hs_loop.SWMatCfg.Pswitch = SWP_RCAL0; + hs_loop.SWMatCfg.Nswitch = SWN_RCAL1; + hs_loop.SWMatCfg.Tswitch = SWT_TRTIA|SWT_RCAL1; + if(bDCMode) + { + int32_t time_out = -1; /* Always wait. */ + int32_t offset_rcal, offset_rtia; + /* Configure WG */ + hs_loop.WgCfg.WgType = WGTYPE_MMR; + hs_loop.WgCfg.WgCode = WgAmpWord; /* Amplitude word is exactly the maximum DC voltage we could use */ + hs_loop.WgCfg.GainCalEn = bFALSE; /* We don't have calibration value for LPDAC, so we don't use it. */ + hs_loop.WgCfg.OffsetCalEn = bFALSE; + AD5940_HSLoopCfgS(&hs_loop); + AD5940_WGDACCodeS(WgAmpWord + 0x800); + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR|AFECTRL_WG|AFECTRL_ADCPWR, bTRUE); /* Apply voltage to loop and turn on ADC */ + /* Do offset measurement */ + pSWCfg->Dswitch = SWD_RCAL0;//|SWD_SE0; /* Disconnect SE0 for now to measure the offset voltage. */ + pSWCfg->Pswitch = SWP_RCAL0; + pSWCfg->Nswitch = SWN_RCAL1; + pSWCfg->Tswitch = SWT_TRTIA|SWT_RCAL1; + AD5940_SWMatrixCfgS(pSWCfg); + AD5940_Delay10us(1000); /* Wait some time here. */ + /* Measure RCAL channel voltage offset */ + pADCBaseCfg->ADCMuxN = ADCMUXN_N_NODE; + pADCBaseCfg->ADCMuxP = ADCMUXP_P_NODE; + pADCBaseCfg->ADCPga = ADCPgaGainRcal; + AD5940_ADCBaseCfgS(pADCBaseCfg); + AD5940_Delay10us(50); /* Wait some time here. */ + offset_rcal = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + /* Measure RTIA channel voltage offset */ + if(pCalCfg->LpAmpSel == LPAMP0) + { + pADCBaseCfg->ADCMuxN = ADCMUXN_LPTIA0_N; + pADCBaseCfg->ADCMuxP = ADCMUXP_LPTIA0_P; + }else + { + pADCBaseCfg->ADCMuxN = ADCMUXN_LPTIA1_N; + pADCBaseCfg->ADCMuxP = ADCMUXP_LPTIA1_P; + } + pADCBaseCfg->ADCPga = ADCPgaGainRtia; + AD5940_ADCBaseCfgS(pADCBaseCfg); + AD5940_Delay10us(50); /* Wait some time here. */ + offset_rtia = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + /* Connect LPTIA loop, let current flow to RTIA. */ + pSWCfg->Dswitch = SWD_RCAL0|((pCalCfg->LpAmpSel == LPAMP0)?SWD_SE0:SWD_SE1); + pSWCfg->Pswitch = SWP_RCAL0; + pSWCfg->Nswitch = SWN_RCAL1; + pSWCfg->Tswitch = SWT_TRTIA|SWT_RCAL1; + AD5940_SWMatrixCfgS(pSWCfg); + AD5940_Delay10us(1000); /* Wait some time here. */ + /* Measure RCAL */ + pADCBaseCfg = &dsp_cfg.ADCBaseCfg; + pADCBaseCfg->ADCMuxN = ADCMUXN_N_NODE; + pADCBaseCfg->ADCMuxP = ADCMUXP_P_NODE; + pADCBaseCfg->ADCPga = ADCPgaGainRcal; + AD5940_ADCBaseCfgS(pADCBaseCfg); + AD5940_Delay10us(50); /* Wait some time here. */ + DftRcal.Real = (int32_t)__AD5940_TakeMeasurement(&time_out)- offset_rcal; + DftRcal.Image = 0; + /* Measure RTIA */ + if(pCalCfg->LpAmpSel == LPAMP0) + { + pADCBaseCfg->ADCMuxN = ADCMUXN_LPTIA0_N; + pADCBaseCfg->ADCMuxP = ADCMUXP_LPTIA0_P; + }else + { + pADCBaseCfg->ADCMuxN = ADCMUXN_LPTIA1_N; + pADCBaseCfg->ADCMuxP = ADCMUXP_LPTIA1_P; + } + pADCBaseCfg->ADCPga = ADCPgaGainRtia; + AD5940_ADCBaseCfgS(pADCBaseCfg); + AD5940_Delay10us(50); /* Wait some time here. */ + DftRtia.Real = (int32_t)__AD5940_TakeMeasurement(&time_out)- offset_rtia; + DftRtia.Image = 0; + } + else + { + hs_loop.WgCfg.SinCfg.SinAmplitudeWord = WgAmpWord; + hs_loop.WgCfg.SinCfg.SinFreqWord = AD5940_WGFreqWordCal(pCalCfg->fFreq, pCalCfg->SysClkFreq); + hs_loop.WgCfg.SinCfg.SinOffsetWord = 0; + hs_loop.WgCfg.SinCfg.SinPhaseWord = 0; + hs_loop.WgCfg.WgCode = 0; + hs_loop.WgCfg.WgType = WGTYPE_SIN; + hs_loop.WgCfg.GainCalEn = bFALSE; /* disable it */ + hs_loop.WgCfg.OffsetCalEn = bFALSE; + AD5940_HSLoopCfgS(&hs_loop); + AD5940_INTCClrFlag(AFEINTSRC_DFTRDY); + + AD5940_AFECtrlS(AFECTRL_HSTIAPWR|AFECTRL_INAMPPWR, bTRUE); + AD5940_Delay10us(100); /* Wait for loop stable. */ + pADCBaseCfg = &dsp_cfg.ADCBaseCfg; + /* DFT on RCAL */ + pADCBaseCfg->ADCMuxN = ADCMUXN_N_NODE; + pADCBaseCfg->ADCMuxP = ADCMUXP_P_NODE; + pADCBaseCfg->ADCPga = ADCPgaGainRcal; + AD5940_ADCBaseCfgS(pADCBaseCfg); + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_WG, bTRUE); + AD5940_Delay10us(25); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT, bTRUE); + /* Wait until DFT ready */ + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_DFTRDY) == bFALSE); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT|AFECTRL_WG|AFECTRL_ADCPWR, bFALSE); /* Stop ADC convert and DFT */ + AD5940_INTCClrFlag(AFEINTSRC_DFTRDY); + DftRcal.Real = AD5940_ReadAfeResult(AFERESULT_DFTREAL); + DftRcal.Image = AD5940_ReadAfeResult(AFERESULT_DFTIMAGE); + /* DFT on RTIA */ + if(pCalCfg->LpAmpSel == LPAMP0) + { + pADCBaseCfg->ADCMuxN = ADCMUXN_LPTIA0_N; + pADCBaseCfg->ADCMuxP = ADCMUXP_LPTIA0_P; + }else + { + pADCBaseCfg->ADCMuxN = ADCMUXN_LPTIA1_N; + pADCBaseCfg->ADCMuxP = ADCMUXP_LPTIA1_P; + } + pADCBaseCfg->ADCPga = ADCPgaGainRtia; + AD5940_ADCBaseCfgS(pADCBaseCfg); + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_WG, bTRUE); + AD5940_Delay10us(25); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT, bTRUE); + /* Wait until DFT ready */ + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_DFTRDY) == bFALSE); + AD5940_AFECtrlS(AFECTRL_ADCCNV|AFECTRL_DFT|AFECTRL_WG|AFECTRL_ADCPWR, bFALSE); /* Stop ADC convert and DFT */ + AD5940_INTCClrFlag(AFEINTSRC_DFTRDY); + DftRtia.Real = AD5940_ReadAfeResult(AFERESULT_DFTREAL); + DftRtia.Image = AD5940_ReadAfeResult(AFERESULT_DFTIMAGE); + if(DftRcal.Real&(1L<<17)) + DftRcal.Real |= 0xfffc0000; + if(DftRcal.Image&(1L<<17)) + DftRcal.Image |= 0xfffc0000; + if(DftRtia.Real&(1L<<17)) + DftRtia.Real |= 0xfffc0000; + if(DftRtia.Image&(1L<<17)) + DftRtia.Image |= 0xfffc0000; + } + /* + The impedance engine inside of AD594x give us Real part and Imaginary part of DFT. Due to technology used, the Imaginary + part in register is the opposite number. So we add a negative sign on the Imaginary part of results. + */ + DftRtia.Image = -DftRtia.Image; + DftRcal.Image = -DftRcal.Image; + + fImpCar_Type res; + /* RTIA = (DftRtia.Real, DftRtia.Image)/(DftRcal.Real, DftRcal.Image)*fRcal */ + res = AD5940_ComplexDivInt(&DftRtia, &DftRcal); + res.Real *= pCalCfg->fRcal/GainRatio; + res.Image *= pCalCfg->fRcal/GainRatio; + if(pCalCfg->bPolarResult == bFALSE) + { + ((fImpCar_Type*)pResult)->Real = res.Real; + ((fImpCar_Type*)pResult)->Image = res.Image; + } + else + { + ((fImpPol_Type*)pResult)->Magnitude = AD5940_ComplexMag(&res); + ((fImpPol_Type*)pResult)->Phase = AD5940_ComplexPhase(&res); + } + + /* Restore INTC1 DFT configure */ + if(INTCCfg&AFEINTSRC_DFTRDY); + else + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_DFTRDY, bFALSE); /* Disable DFT Interrupt */ + if(INTCCfg&AFEINTSRC_SINC2RDY); + else + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bFALSE); /* Disable SINC2 Interrupt */ + AD5940_WriteReg(REG_AFE_AFECON, reg_afecon); /* Restore AFECON register */ + /* Open all switches in switch-matrix */ + hs_loop.SWMatCfg.Dswitch = SWD_OPEN; + hs_loop.SWMatCfg.Pswitch = SWP_OPEN; + hs_loop.SWMatCfg.Nswitch = SWN_OPEN; + hs_loop.SWMatCfg.Tswitch = SWT_OPEN; + AD5940_SWMatrixCfgS(&hs_loop.SWMatCfg); + + return AD5940ERR_OK; +} + + +/** + * @brief calibrate HSDAC output voltage using ADC. + * @note It acutally calibrates voltage output of excitation buffer. + * @param pCalCfg: pointer to configuration structure + * @return return AD5940ERR_OK if succeeded. +*/ +AD5940Err AD5940_HSDACCal(HSDACCal_Type *pCalCfg) +{ + ADCBaseCfg_Type adc_base; + ADCFilterCfg_Type adc_filter; + HSLoopCfg_Type hsloop_cfg; + LPLoopCfg_Type lploop_cfg; + + /* LSB_Numerator and LSB_Denometer are used to calculate + the codes to write to calibration registers depending on + which calibration register is used + There are LSB_Numerator ADC LSBs in + LSB_Denominator DAC Calibration LSBs*/ + int32_t LSB_Numerator; + int32_t LEB_Denominator; + int32_t time_out; + int32_t ADCCode; + uint32_t HSDACCode = 0x800; /* Mid scale DAC */ + + uint32_t regaddr_offset; + uint32_t ADCPGA_Sel; + BoolFlag bHPMode; + + if(pCalCfg == NULL) return AD5940ERR_NULLP; + if(pCalCfg->ExcitBufGain > 1) return AD5940ERR_PARA; + if(pCalCfg->HsDacGain > 1) return AD5940ERR_PARA; + + bHPMode = pCalCfg->AfePwrMode == AFEPWR_HP?bTRUE:bFALSE; + + switch(pCalCfg->ExcitBufGain) + { + case EXCITBUFGAIN_2: + regaddr_offset = bHPMode?REG_AFE_DACOFFSETHP:REG_AFE_DACOFFSET; + if(pCalCfg->HsDacGain == HSDACGAIN_0P2) + { + LSB_Numerator = 40; + LEB_Denominator = 14; + ADCPGA_Sel = ADCPGA_4; + } + else + { + LSB_Numerator = 7; + LEB_Denominator = 2; + ADCPGA_Sel = ADCPGA_1; + } + break; + case EXCITBUFGAIN_0P25: + regaddr_offset = bHPMode?REG_AFE_DACOFFSETATTENHP:REG_AFE_DACOFFSETATTEN; + if(pCalCfg->HsDacGain == HSDACGAIN_0P2) + { + LSB_Numerator = 5; + LEB_Denominator = 14; + } + else + { + LSB_Numerator = 25; + LEB_Denominator = 14; + } + ADCPGA_Sel = ADCPGA_4; + break; + default: + return AD5940ERR_PARA; + } + + /* Turn On References*/ + __AD5940_ReferenceON(); + /* Step0.0 Initialize ADC filters ADCRawData-->SINC3-->SINC2+NOTCH. Use SIN2 data for calibration-->Lower noise */ + adc_filter.ADCSinc3Osr = pCalCfg->ADCSinc3Osr; + adc_filter.ADCSinc2Osr = pCalCfg->ADCSinc2Osr; /* 800KSPS/4/1333 = 150SPS */ + adc_filter.ADCAvgNum = ADCAVGNUM_2; /* Don't care about it. Average function is only used for DFT */ + adc_filter.ADCRate = bHPMode?ADCRATE_1P6MHZ:ADCRATE_800KHZ; /* If ADC clock is 32MHz, then set it to ADCRATE_1P6MHZ. Default is 16MHz, use ADCRATE_800KHZ. */ + adc_filter.BpNotch = bTRUE; /* SINC2+Notch is one block, when bypass notch filter, we can get fresh data from SINC2 filter. */ + adc_filter.BpSinc3 = bFALSE; /* We use SINC3 filter. */ + adc_filter.Sinc2NotchEnable = bTRUE; /* Enable the SINC2+Notch block. You can also use function AD5940_AFECtrlS */ + AD5940_ADCFilterCfgS(&adc_filter); + /* Step0.1 Initialize ADC basic function */ + adc_base.ADCMuxP = ADCMUXP_P_NODE; + adc_base.ADCMuxN = ADCMUXN_N_NODE; + adc_base.ADCPga = ADCPGA_Sel; + AD5940_ADCBaseCfgS(&adc_base); + + /* Step0.2 Configure LPDAC to connect VZERO to HSTIA */ + lploop_cfg.LpDacCfg.LpdacSel = LPDAC0; + lploop_cfg.LpDacCfg.DacData12Bit = 0x7C0; + lploop_cfg.LpDacCfg.DacData6Bit = 0x1F; + lploop_cfg.LpDacCfg.DataRst = bFALSE; + lploop_cfg.LpDacCfg.LpDacRef = LPDACREF_2P5; + lploop_cfg.LpDacCfg.LpDacSrc = LPDACSRC_MMR; + lploop_cfg.LpDacCfg.LpDacVzeroMux = LPDACVZERO_6BIT; + lploop_cfg.LpDacCfg.LpDacVbiasMux = LPDACVBIAS_12BIT; + lploop_cfg.LpDacCfg.PowerEn = bTRUE; + lploop_cfg.LpDacCfg.LpDacSW = LPDACSW_VBIAS2LPPA|LPDACSW_VBIAS2PIN|LPDACSW_VZERO2HSTIA; + AD5940_LPLoopCfgS(&lploop_cfg); + + /* Step0.3 Configure HSLOOP */ + hsloop_cfg.HsDacCfg.ExcitBufGain = pCalCfg->ExcitBufGain; + hsloop_cfg.HsDacCfg.HsDacGain = pCalCfg->HsDacGain; + hsloop_cfg.HsDacCfg.HsDacUpdateRate = bHPMode?0x7:0x1B; + hsloop_cfg.HsTiaCfg.DiodeClose = bFALSE; + hsloop_cfg.HsTiaCfg.HstiaBias = HSTIABIAS_VZERO0; + hsloop_cfg.HsTiaCfg.HstiaCtia = 8; + hsloop_cfg.HsTiaCfg.HstiaDeRload = HSTIADERLOAD_OPEN; + hsloop_cfg.HsTiaCfg.HstiaDeRtia = HSTIADERTIA_OPEN; + hsloop_cfg.HsTiaCfg.HstiaDe1Rload = HSTIADERLOAD_OPEN; + hsloop_cfg.HsTiaCfg.HstiaDe1Rtia = HSTIADERTIA_OPEN; + hsloop_cfg.HsTiaCfg.HstiaRtiaSel = HSTIARTIA_200; + hsloop_cfg.SWMatCfg.Dswitch = SWD_RCAL0; + hsloop_cfg.SWMatCfg.Pswitch = SWP_RCAL0; + hsloop_cfg.SWMatCfg.Nswitch = SWN_RCAL1; + hsloop_cfg.SWMatCfg.Tswitch = SWT_TRTIA|SWT_RCAL1; + hsloop_cfg.WgCfg.GainCalEn = bTRUE; + hsloop_cfg.WgCfg.OffsetCalEn = bTRUE; + hsloop_cfg.WgCfg.WgType = WGTYPE_MMR; + hsloop_cfg.WgCfg.WgCode = HSDACCode; + AD5940_HSLoopCfgS(&hsloop_cfg); + /* Step0.4 Turn ON reference and ADC power, and DAC power and DAC reference. We use DAC 1.8V reference to calibrate ADC. */ + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Disable all */ + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_HPREFPWR|AFECTRL_DACREFPWR|AFECTRL_HSDACPWR|AFECTRL_SINC2NOTCH|\ + AFECTRL_EXTBUFPWR|AFECTRL_INAMPPWR|AFECTRL_HSTIAPWR|AFECTRL_WG, bTRUE); + AD5940_Delay10us(25); /* Wait 250us for reference power up */ + /* Step0.5 INTC configure and open calibration lock */ + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bTRUE); /* Enable SINC2 Interrupt in INTC1 */ + AD5940_WriteReg(REG_AFE_CALDATLOCK, KEY_CALDATLOCK); /* Unlock KEY */ + /* Reset Offset register before calibration */ + AD5940_WriteReg(regaddr_offset, 0); + /* Update HSDACDAT after resetting calibration register */ + AD5940_WriteReg(REG_AFE_HSDACDAT, 0x800); + /* Step1: Do offset calibration. */ + { + int32_t ExpectedCode = 0x8000; /* Ideal ADC output */ + AD5940_Delay10us(10); + time_out = 1000; /* Reset time out counter */ + ADCCode = __AD5940_TakeMeasurement(&time_out); +#ifdef ADI_DEBUG + ADI_Print("Voltage before cal: %f \n", AD5940_ADCCode2Volt(ADCCode, ADCPGA_Sel, 1.82)); +#endif + + if(time_out == 0) goto DACCALERROR_TIMEOUT; /* Time out error. */ + ADCCode = ADCCode - ExpectedCode; + ADCCode = (((ADCCode)*LEB_Denominator)/LSB_Numerator); + if(ADCCode>0) + ADCCode = 0xFFF - ADCCode; + else + ADCCode = -ADCCode; + AD5940_WriteReg(regaddr_offset, ADCCode); + AD5940_Delay10us(10); + AD5940_WriteReg(REG_AFE_HSDACDAT, 0x800); + AD5940_Delay10us(10); +#ifdef ADI_DEBUG + ADCCode = __AD5940_TakeMeasurement(&time_out); + ADI_Print("Voltage after cal: %f \n", AD5940_ADCCode2Volt(ADCCode, ADCPGA_Sel, 1.82)); +#endif + } + AD5940_WriteReg(REG_AFE_CALDATLOCK, 0); /* Lock KEY */ + return AD5940ERR_OK; +DACCALERROR_TIMEOUT: + AD5940_ADCConvtCtrlS(bFALSE); /* Stop conversion */ + AD5940_WriteReg(REG_AFE_CALDATLOCK, 0); /* Lock KEY */ + return AD5940ERR_TIMEOUT; +} + +/** + * @brief Use ADC to measure LPDAC offset and gain factor. + * @note Assume ADC is accurate enough or accurate than LPDAC at least. + * @param pCalCfg: pointer to structure. + * @param pResult: the pointer to save calibration result. + * @return AD5940ERR_OK if succeed. + *LPDACCal() function is added in ad5940.c only to suggest an optional LPDAC calibration sequence. + *It is not verified by ADI software team and user may use it at own risk. + +**/ +AD5940Err AD5940_LPDACCal(LPDACCal_Type *pCalCfg, LPDACPara_Type *pResult) +{ + AD5940Err error = AD5940ERR_OK; + LPDACCfg_Type LpDacCfg; + ADCBaseCfg_Type adc_base; + ADCFilterCfg_Type adc_filter; + + int32_t time_out; + uint32_t INTCCfg; + int32_t ADCCode, ADCCodeVref1p1; + BoolFlag bADCClk32MHzMode; + + if(pCalCfg == NULL) return AD5940ERR_NULLP; + if(pResult == NULL) return AD5940ERR_NULLP; + if(pCalCfg->AdcClkFreq > (32000000*0.8)) + bADCClk32MHzMode = bTRUE; + + /* Step0: Do initialization */ + /* Turn on AD5940 references in case it's disabled. */ + __AD5940_ReferenceON(); + LpDacCfg.LpdacSel = pCalCfg->LpdacSel; + LpDacCfg.DacData12Bit = 0; + LpDacCfg.DacData6Bit = 0; + LpDacCfg.DataRst = bFALSE; + LpDacCfg.LpDacRef = LPDACREF_2P5; + LpDacCfg.LpDacSrc = LPDACSRC_MMR; + LpDacCfg.LpDacSW = LPDACSW_VBIAS2PIN|LPDACSW_VZERO2PIN; + LpDacCfg.LpDacVbiasMux = LPDACVBIAS_12BIT; + LpDacCfg.LpDacVzeroMux = LPDACVZERO_6BIT; + LpDacCfg.PowerEn = bTRUE; + AD5940_LPDACCfgS(&LpDacCfg); + + /* Initialize ADC filters ADCRawData-->SINC3-->SINC2+NOTCH. Use SIN2 data for calibration-->Lower noise */ + adc_filter.ADCSinc3Osr = pCalCfg->ADCSinc3Osr; + adc_filter.ADCSinc2Osr = pCalCfg->ADCSinc2Osr; /* 800KSPS/4/1333 = 150SPS */ + adc_filter.ADCAvgNum = ADCAVGNUM_2; /* Don't care about it. Average function is only used for DFT */ + adc_filter.ADCRate = bADCClk32MHzMode?ADCRATE_1P6MHZ:ADCRATE_800KHZ; /* If ADC clock is 32MHz, then set it to ADCRATE_1P6MHZ. Default is 16MHz, use ADCRATE_800KHZ. */ + adc_filter.BpNotch = bTRUE; /* SINC2+Notch is one block, when bypass notch filter, we can get fresh data from SINC2 filter. */ + adc_filter.BpSinc3 = bFALSE; /* We use SINC3 filter. */ + adc_filter.Sinc2NotchEnable = bTRUE; /* Enable the SINC2+Notch block. You can also use function AD5940_AFECtrlS */ + AD5940_ADCFilterCfgS(&adc_filter); + /* Initialize ADC MUx and PGA */ + adc_base.ADCMuxP = ADCMUXP_AGND; + adc_base.ADCMuxN = ADCMUXN_VSET1P1; + adc_base.ADCPga = ADCPGA_1; + AD5940_ADCBaseCfgS(&adc_base); + /* Turn ON ADC and its reference. And SINC2. */ + AD5940_AFECtrlS(AFECTRL_ALL, bFALSE); /* Disable all firstly, we only enable things we use */ + AD5940_AFECtrlS(AFECTRL_ADCPWR|AFECTRL_HPREFPWR|AFECTRL_SINC2NOTCH, bTRUE); + AD5940_Delay10us(25); /* Wait 250us for reference power up */ + /* INTC configure and open calibration lock */ + INTCCfg = AD5940_INTCGetCfg(AFEINTC_1); + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bTRUE); /* Enable SINC2 Interrupt in INTC1 */ + /* Step1: Measure internal 1.1V reference. */ + { + //AD5940_ADCMuxCfgS(ADCMUXP_AGND, ADCMUXN_VSET1P1); + time_out = pCalCfg->TimeOut10us; /* Reset time out counter */ + ADCCodeVref1p1 = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + if(time_out == 0) + { + error = AD5940ERR_TIMEOUT; + goto LPDACCALERROR; + } /* Time out error. */ + /* Equation1: ADCCodeVref1p1 = AGND - Vref1p1 */ + } + /* Step2: Do offset measurement. */ + { + /* Equation2': ADCCode = Vbias0/1 - Vref1p1 */ + AD5940_LPDACWriteS(0,0); /* Set LPDAC output voltage to 0.2V(zero code) */ + if(pCalCfg->SettleTime10us > 0) + AD5940_Delay10us(pCalCfg->SettleTime10us); /* Delay nx10us */ + if(pCalCfg->LpdacSel == LPDAC0) + AD5940_ADCMuxCfgS(ADCMUXP_VBIAS0, ADCMUXN_VREF1P1); /* Vbias0 is routed to 12BIT LPDAC */ + else + AD5940_ADCMuxCfgS(ADCMUXP_VBIAS1, ADCMUXN_VREF1P1); /* Vbias1 is routed to 12BIT LPDAC */ + + AD5940_Delay10us(5); /* Delay 50us */ + time_out = pCalCfg->TimeOut10us; /* Reset time out counter */ + ADCCode = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + if(time_out == 0) + { + error = AD5940ERR_TIMEOUT; + goto LPDACCALERROR; + } /* Time out error. */ + /* Calculate the offset voltage using Equation2 - Equation1 */ + ADCCode -= ADCCodeVref1p1; /* Get the code of Vbias0-AGND. Then calculate the offset voltage in mV. */ + pResult->bC2V_DAC12B = ADCCode*pCalCfg->ADCRefVolt*1e3f/32768*1.835f/1.82f; /*mV unit*/ + /* Measure 6BIT DAC output(Vzero0/1) */ + if(pCalCfg->LpdacSel == LPDAC0) + AD5940_ADCMuxCfgS(ADCMUXP_VZERO0, ADCMUXN_VREF1P1); /* Vbias0 is routed to 12BIT LPDAC */ + else + AD5940_ADCMuxCfgS(ADCMUXP_VZERO1, ADCMUXN_VREF1P1); /* Vbias1 is routed to 12BIT LPDAC */ + AD5940_Delay10us(5); /* Delay 50us */ + time_out = pCalCfg->TimeOut10us; /* Reset time out counter */ + ADCCode = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + if(time_out == 0) + { + error = AD5940ERR_TIMEOUT; + goto LPDACCALERROR; + } /* Time out error. */ + /* Calculate the offset voltage */ + ADCCode -= ADCCodeVref1p1; /* Get the code of Vbias0-AGND. Then calculate the offset voltage in mV. */ + pResult->bC2V_DAC6B = ADCCode*pCalCfg->ADCRefVolt*1e3f/32768*1.835f/1.82f; /*mV unit*/ + } + /* Step3: Do gain measurement */ + { + /* Equation2: ADCCode = Vbias0 - Vref1p1 */ + AD5940_LPDACWriteS(0xfff,0x3f); /* Set LPDAC output voltage to 2.4V(zero code) */ + if(pCalCfg->SettleTime10us > 0) + AD5940_Delay10us(pCalCfg->SettleTime10us); /* Delay nx10us */ + if(pCalCfg->LpdacSel == LPDAC0) + AD5940_ADCMuxCfgS(ADCMUXP_VBIAS0, ADCMUXN_VREF1P1); /* Vbias0 is routed to 12BIT LPDAC */ + else + AD5940_ADCMuxCfgS(ADCMUXP_VBIAS1, ADCMUXN_VREF1P1); /* Vbias1 is routed to 12BIT LPDAC */ + AD5940_Delay10us(5); /* Delay 50us */ + time_out = pCalCfg->TimeOut10us; /* Reset time out counter */ + ADCCode = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + if(time_out == 0) + { + error = AD5940ERR_TIMEOUT; + goto LPDACCALERROR; + } /* Time out error. */ + /* Calculate the offset voltage */ + ADCCode -= ADCCodeVref1p1; /* Get the code of Vbias0-AGND. Then calculate the gain factor 'k'. */ + pResult->kC2V_DAC12B = (ADCCode*pCalCfg->ADCRefVolt*1e3f/32768*1.835f/1.82f - pResult->bC2V_DAC12B)/0xfff;/*mV unit*/ + /* Measure 6BIT DAC output(Vzero0) */ + if(pCalCfg->LpdacSel == LPDAC0) + AD5940_ADCMuxCfgS(ADCMUXP_VZERO0, ADCMUXN_VREF1P1); /* Vbias0 is routed to 12BIT LPDAC */ + else + AD5940_ADCMuxCfgS(ADCMUXP_VZERO1, ADCMUXN_VREF1P1); /* Vbias1 is routed to 12BIT LPDAC */ + AD5940_Delay10us(5); /* Delay 50us */ + time_out = pCalCfg->TimeOut10us; /* Reset time out counter */ + ADCCode = __AD5940_TakeMeasurement(&time_out); /* Turn on ADC to get one valid data and then turn off ADC. */ + if(time_out == 0) + { + error = AD5940ERR_TIMEOUT; + goto LPDACCALERROR; + } /* Time out error. */ + /* Calculate the offset voltage */ + ADCCode -= ADCCodeVref1p1; /* Get the code of Vbias0-AGND. Then calculate the offset voltage in mV. */ + pResult->kC2V_DAC6B = (ADCCode*pCalCfg->ADCRefVolt*1e3f/32768*1.835f/1.82f - pResult->bC2V_DAC6B)/0x3f;/*mV unit*/ + } + /* Step4: calculate the parameters for voltage to code calculation. */ + pResult->kV2C_DAC12B = 1/pResult->kC2V_DAC12B; + pResult->bV2C_DAC12B = -pResult->bC2V_DAC12B/pResult->kC2V_DAC12B; + pResult->kV2C_DAC6B = 1/pResult->kC2V_DAC6B; + pResult->bV2C_DAC6B = -pResult->bC2V_DAC6B/pResult->kC2V_DAC6B; + /* Restore INTC1 SINC2 configure */ + if(INTCCfg&AFEINTSRC_SINC2RDY); + else + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_SINC2RDY, bFALSE); /* Disable SINC2 Interrupt */ + /* Done */ + return AD5940ERR_OK; + +LPDACCALERROR: + AD5940_ADCConvtCtrlS(bFALSE); /* Stop conversion */ + return error; +} + +/** + * @brief Use system clock to measure LFOSC frequency. + * @note Set system clock to external crystal to get a better measurement accuracy. + * This function use 3 sequences and the start address is specified by parameter. + * @param pCfg: pointer to structure. + * @param pFreq: Pointer to a variable that used to store frequency in Hz. + * @return AD5940ERR_OK if succeed. +**/ +AD5940Err AD5940_LFOSCMeasure(LFOSCMeasure_Type *pCfg, float *pFreq) /* Measure current LFOSC frequency. */ +{ + /** + * @code + * Sleep wakeup timer running... + * -SLP----WKP----SLP----WKP----SLP----WKP + * --|-----|-------------|-------------|------------Trigger sequencer when Wakeup Timer over. + * --------|SEQA---------|SEQB----------------------Execute SeqA then SeqB + * ---------|InitT--------|StopT--------------------SeqA start timer and SeqB trigger interrupt so MCU read back current count + * ------------------------|INT--------------------- + * -----------------------------------------|Read---We read SEQTIMEOUT register here + * ---------|-----TimerCount----------------|------- + * ---------|--------------|---TimerCount2--|-------We change SeqB to reset timer so we measure how much time needed for MCU to read back SEQTIMEOUT register(TimerCount2) + * @endcode + * **/ + uint32_t TimerCount, TimerCount2; + SEQCfg_Type seq_cfg, seq_cfg_backup; + SEQInfo_Type seqinfo; + WUPTCfg_Type wupt_cfg; + uint32_t INTCCfg; + uint32_t WuptPeriod; + + static const uint32_t SeqA[]= + { + SEQ_TOUT(0x3fffffff), /* Set time-out timer. It will always run until disable Sequencer by SPI interface. */ + }; + static const uint32_t SeqB[]= + { + /** + * Interrupt flag AFEINTSRC_ENDSEQ will be set after this command. So We can inform MCU to read back + * current timer value. MCU will need some additional time to read back time count. + * So we use SeqB to measure how much time needed for MCU to read back + * */ + SEQ_STOP(), + }; + static const uint32_t SeqBB[]= + { + SEQ_TOUT(0x3fffffff), /* Re-Set time-out timer, so we can measure the time needed for MCU to read out Timer Count register. */ + SEQ_STOP(), /* Interrupt flag AFEINTSRC_ENDSEQ will be set here */ + }; + + if(pCfg == NULL) return AD5940ERR_NULLP; + if(pFreq == NULL) return AD5940ERR_NULLP; + if(pCfg->CalDuration < 1.0f) + return AD5940ERR_PARA; + AD5940_SEQGetCfg(&seq_cfg_backup); + INTCCfg = AD5940_INTCGetCfg(AFEINTC_1); + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_ENDSEQ, bTRUE); + AD5940_INTCClrFlag(AFEINTSRC_ALLINT); + + seq_cfg.SeqMemSize = SEQMEMSIZE_2KB; /* 2kB SRAM is used for sequencer */ + seq_cfg.SeqBreakEn = bFALSE; + seq_cfg.SeqIgnoreEn = bFALSE; + seq_cfg.SeqCntCRCClr = bFALSE; + seq_cfg.SeqEnable = bTRUE; + seq_cfg.SeqWrTimer = 0; + AD5940_SEQCfg(&seq_cfg); /* Enable sequencer */ + + seqinfo.pSeqCmd = SeqA; + seqinfo.SeqId = SEQID_0; + seqinfo.SeqLen = SEQ_LEN(SeqA); + seqinfo.SeqRamAddr = pCfg->CalSeqAddr; + seqinfo.WriteSRAM = bTRUE; + AD5940_SEQInfoCfg(&seqinfo); + seqinfo.SeqId = SEQID_1; + seqinfo.SeqRamAddr = pCfg->CalSeqAddr + SEQ_LEN(SeqA) ; + seqinfo.SeqLen = SEQ_LEN(SeqB); + seqinfo.pSeqCmd = SeqB; + AD5940_SEQInfoCfg(&seqinfo); /* Configure sequence0 and sequence1 with command SeqA and SeqB */ + + wupt_cfg.WuptEn = bFALSE; + wupt_cfg.WuptOrder[0] = SEQID_0; + wupt_cfg.WuptOrder[1] = SEQID_1; + wupt_cfg.WuptEndSeq = WUPTENDSEQ_B; + wupt_cfg.SeqxWakeupTime[0] = 4; /* Don't care. >4 is acceptable */ + wupt_cfg.SeqxSleepTime[0] = (uint32_t)((pCfg->CalDuration)*32 + 0.5f) - 1 - 4; + wupt_cfg.SeqxWakeupTime[1] = 4-1; + wupt_cfg.SeqxSleepTime[1] = 0xffffffff; /* Don't care */ + WuptPeriod = (wupt_cfg.SeqxSleepTime[0]+1) + (wupt_cfg.SeqxWakeupTime[1]+1); + AD5940_WUPTCfg(&wupt_cfg); + + AD5940_INTCClrFlag(AFEINTSRC_ENDSEQ); + AD5940_WUPTCtrl(bTRUE); + + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_ENDSEQ) == bFALSE); + TimerCount = AD5940_SEQTimeOutRd(); + + AD5940_WUPTCtrl(bFALSE); + AD5940_WUPTTime(SEQID_0, 4, 4); /* Set it to minimum value because we don't care about sequence0 now. We only want to measure how much time MCU will need to read register */ + seqinfo.SeqId = SEQID_1; + seqinfo.SeqRamAddr = pCfg->CalSeqAddr + SEQ_LEN(SeqA) ; + seqinfo.SeqLen = SEQ_LEN(SeqBB); + seqinfo.pSeqCmd = SeqBB; + seqinfo.WriteSRAM = bTRUE; + AD5940_SEQInfoCfg(&seqinfo); + AD5940_SEQCtrlS(bTRUE); /* Enable Sequencer again */ + + AD5940_INTCClrFlag(AFEINTSRC_ENDSEQ); + AD5940_WUPTCtrl(bTRUE); + while(AD5940_INTCTestFlag(AFEINTC_1, AFEINTSRC_ENDSEQ) == bFALSE); + TimerCount2 = AD5940_SEQTimeOutRd(); + AD5940_INTCTestFlag(AFEINTC_0, AFEINTSRC_ENDSEQ); + + AD5940_WUPTCtrl(bFALSE); + AD5940_SEQCfg(&seq_cfg_backup); /* restore sequencer configuration */ + AD5940_INTCCfg(AFEINTC_1, AFEINTSRC_ENDSEQ, (INTCCfg&AFEINTSRC_ENDSEQ)?bTRUE:bFALSE); /* Restore interrupt configuration */ + AD5940_INTCClrFlag(AFEINTSRC_ENDSEQ); + //printf("Time duration:%d ", (TimerCount2 - TimerCount)); + *pFreq = pCfg->SystemClkFreq*WuptPeriod/(TimerCount2 - TimerCount); + return AD5940ERR_OK; +} + +/** + * @} Calibration + * @} Calibration_Block +*/ + +/** + * @} AD5940_Functions + * @} AD5940_Library +*/ \ No newline at end of file diff --git a/examples/rp2040_port/test/ad5940.h b/examples/rp2040_port/test/ad5940.h new file mode 100644 index 0000000..bbf55ad --- /dev/null +++ b/examples/rp2040_port/test/ad5940.h @@ -0,0 +1,6242 @@ +/** + * @file ad5940.h + * @brief AD5940 library. This file contains all AD5940 library functions. + * @author ADI + * @date March 2019 + * @par Revision History: + * + * Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. + * + * This software is proprietary to Analog Devices, Inc. and its licensors. + * By using this software you agree to the terms of the associated + * Analog Devices Software License Agreement. + **/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef _AD5940_H_ +#define _AD5940_H_ +#include "math.h" +#include "stdio.h" +#include "string.h" +/** @addtogroup AD5940_Library + * @{ + */ + +/** + * Select the correct chip. + * Recommend to define this in your compiler. + * */ +// #define CHIPSEL_M355 /**< ADuCM355 */ +// #define CHIPSEL_594X /**< AD5940 or AD5941 */ + +/* library version number */ +#define AD5940LIB_VER_MAJOR 0 /**< Major number */ +#define AD5940LIB_VER_MINOR 2 /**< Minor number */ +#define AD5940LIB_VER_PATCH 1 /**< Path number */ +#define AD5940LIB_VER \ + (AD5940LIB_VER_MAJOR << 16) | (AD5940LIB_VER_MINOR << 8) | \ + (AD5940LIB_VER_PATCH) + +#define ADI_DEBUG /**< Comment this line to remove debug info. */ + +#ifdef ADI_DEBUG +#define ADI_Print printf /**< Select the method to print out debug message */ +#endif + +#if defined(CHIPSEL_M355) && defined(CHIPSEL_594X) +#error Please select the correct chip by define CHIPSEL_M355 or CHIPSEL_594X. +#endif + +#ifndef CHIPSEL_594X +#define CHIPSEL_594X +#endif + +#if !defined(CHIPSEL_M355) && !defined(CHIPSEL_594X) +#error Please select the correct chip by define CHIPSEL_M355 or CHIPSEL_594X. +#endif + +/** + * @cond + * @defgroup AD5940RegistersBitfields + * @brief All AD5940 registers and bitfields definition. + * @{ + */ +// #if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +// #endif /* _LANGUAGE_C */ + +#ifndef __ADI_GENERATED_DEF_HEADERS__ +#define __ADI_GENERATED_DEF_HEADERS__ 1 +#endif + +#define __ADI_HAS_AGPIO__ 1 +#define __ADI_HAS_ALLON__ 1 +#define __ADI_HAS_INTC__ 1 +#define __ADI_HAS_AFECON__ 1 +#define __ADI_HAS_WUPTMR__ 1 +#define __ADI_HAS_AFE__ 1 + +/* ============================================================================================================================ + GPIO + ============================================================================================================================ + */ + +/* ============================================================================================================================ + AGPIO + ============================================================================================================================ + */ +#define REG_AGPIO_GP0CON_RESET 0x00000000 /* Reset Value for GP0CON */ +#define REG_AGPIO_GP0CON 0x00000000 /* AGPIO GPIO Port 0 Configuration */ +#define REG_AGPIO_GP0OEN_RESET 0x00000000 /* Reset Value for GP0OEN */ +#define REG_AGPIO_GP0OEN 0x00000004 /* AGPIO GPIO Port 0 Output Enable */ +#define REG_AGPIO_GP0PE_RESET 0x00000000 /* Reset Value for GP0PE */ +#define REG_AGPIO_GP0PE \ + 0x00000008 /* AGPIO GPIO Port 0 Pullup/Pulldown Enable */ +#define REG_AGPIO_GP0IEN_RESET 0x00000000 /* Reset Value for GP0IEN */ +#define REG_AGPIO_GP0IEN 0x0000000C /* AGPIO GPIO Port 0 Input Path Enable */ +#define REG_AGPIO_GP0IN_RESET 0x00000000 /* Reset Value for GP0IN */ +#define REG_AGPIO_GP0IN \ + 0x00000010 /* AGPIO GPIO Port 0 Registered Data Input */ +#define REG_AGPIO_GP0OUT_RESET 0x00000000 /* Reset Value for GP0OUT */ +#define REG_AGPIO_GP0OUT 0x00000014 /* AGPIO GPIO Port 0 Data Output */ +#define REG_AGPIO_GP0SET_RESET 0x00000000 /* Reset Value for GP0SET */ +#define REG_AGPIO_GP0SET 0x00000018 /* AGPIO GPIO Port 0 Data Out Set */ +#define REG_AGPIO_GP0CLR_RESET 0x00000000 /* Reset Value for GP0CLR */ +#define REG_AGPIO_GP0CLR 0x0000001C /* AGPIO GPIO Port 0 Data Out Clear */ +#define REG_AGPIO_GP0TGL_RESET 0x00000000 /* Reset Value for GP0TGL */ +#define REG_AGPIO_GP0TGL 0x00000020 /* AGPIO GPIO Port 0 Pin Toggle */ + +/* ============================================================================================================================ + AGPIO Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0CON_PIN7CFG 14 /* P0.7 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN6CFG 12 /* P0.6 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN5CFG 10 /* P0.5 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN4CFG 8 /* P0.4 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN3CFG 6 /* P0.3 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN2CFG 4 /* P0.2 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN1CFG 2 /* P0.1 Configuration Bits */ +#define BITP_AGPIO_GP0CON_PIN0CFG 0 /* P0.0 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN7CFG 0x0000C000 /* P0.7 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN6CFG 0x00003000 /* P0.6 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN5CFG 0x00000C00 /* P0.5 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN4CFG 0x00000300 /* P0.4 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN3CFG 0x000000C0 /* P0.3 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN2CFG 0x00000030 /* P0.2 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN1CFG 0x0000000C /* P0.1 Configuration Bits */ +#define BITM_AGPIO_GP0CON_PIN0CFG 0x00000003 /* P0.0 Configuration Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0OEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0OEN_OEN 0 /* Pin Output Drive Enable */ +#define BITM_AGPIO_GP0OEN_OEN 0x000000FF /* Pin Output Drive Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0PE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0PE_PE 0 /* Pin Pull Enable */ +#define BITM_AGPIO_GP0PE_PE 0x000000FF /* Pin Pull Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0IEN_IEN 0 /* Input Path Enable */ +#define BITM_AGPIO_GP0IEN_IEN 0x000000FF /* Input Path Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0IN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0IN_IN 0 /* Registered Data Input */ +#define BITM_AGPIO_GP0IN_IN 0x000000FF /* Registered Data Input */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0OUT_OUT 0 /* Data Out */ +#define BITM_AGPIO_GP0OUT_OUT 0x000000FF /* Data Out */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0SET_SET 0 /* Set the Output HIGH */ +#define BITM_AGPIO_GP0SET_SET 0x000000FF /* Set the Output HIGH */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0CLR_CLR 0 /* Set the Output LOW */ +#define BITM_AGPIO_GP0CLR_CLR 0x000000FF /* Set the Output LOW */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPIO_GP0TGL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPIO_GP0TGL_TGL 0 /* Toggle the Output */ +#define BITM_AGPIO_GP0TGL_TGL 0x000000FF /* Toggle the Output */ + +/* ============================================================================================================================ + + ============================================================================================================================ + */ + +/* ============================================================================================================================ + AFECON + ============================================================================================================================ + */ +#define REG_AFECON_ADIID_RESET 0x00000000 /* Reset Value for ADIID */ +#define REG_AFECON_ADIID 0x00000400 /* AFECON ADI Identification */ +#define REG_AFECON_CHIPID_RESET 0x00000000 /* Reset Value for CHIPID */ +#define REG_AFECON_CHIPID 0x00000404 /* AFECON Chip Identification */ +#define REG_AFECON_CLKCON0_RESET 0x00000441 /* Reset Value for CLKCON0 */ +#define REG_AFECON_CLKCON0 \ + 0x00000408 /* AFECON Clock Divider Configuration \ + */ +#define REG_AFECON_CLKEN1_RESET 0x000002C0 /* Reset Value for CLKEN1 */ +#define REG_AFECON_CLKEN1 0x00000410 /* AFECON Clock Gate Enable */ +#define REG_AFECON_CLKSEL_RESET 0x00000000 /* Reset Value for CLKSEL */ +#define REG_AFECON_CLKSEL 0x00000414 /* AFECON Clock Select */ +#define REG_AFECON_CLKCON0KEY_RESET \ + 0x00000000 /* Reset Value for CLKCON0KEY */ +#define REG_AFECON_CLKCON0KEY \ + 0x00000420 /* AFECON Enable Clock Division to 8Mhz,4Mhz and 2Mhz */ +#define REG_AFECON_SWRSTCON_RESET \ + 0x00000001 /* Reset Value for SWRSTCON */ +#define REG_AFECON_SWRSTCON 0x00000424 /* AFECON Software Reset */ +#define REG_AFECON_TRIGSEQ_RESET 0x00000000 /* Reset Value for TRIGSEQ */ +#define REG_AFECON_TRIGSEQ 0x00000430 /* AFECON Trigger Sequence */ + +/* ============================================================================================================================ + AFECON Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_ADIID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_ADIID_ADIID 0 /* ADI Identifier. */ +#define BITM_AFECON_ADIID_ADIID 0x0000FFFF /* ADI Identifier. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CHIPID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_CHIPID_PARTID 4 /* Part Identifier */ +#define BITP_AFECON_CHIPID_REVISION 0 /* Silicon Revision Number */ +#define BITM_AFECON_CHIPID_PARTID 0x0000FFF0 /* Part Identifier */ +#define BITM_AFECON_CHIPID_REVISION 0x0000000F /* Silicon Revision Number */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKCON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_CLKCON0_SFFTCLKDIVCNT \ + 10 /* SFFT Clock Divider Configuration */ +#define BITP_AFECON_CLKCON0_ADCCLKDIV 6 /* ADC Clock Divider Configuration */ +#define BITP_AFECON_CLKCON0_SYSCLKDIV \ + 0 /* System Clock Divider Configuration */ +#define BITM_AFECON_CLKCON0_SFFTCLKDIVCNT \ + 0x0000FC00 /* SFFT Clock Divider Configuration */ +#define BITM_AFECON_CLKCON0_ADCCLKDIV \ + 0x000003C0 /* ADC Clock Divider Configuration */ +#define BITM_AFECON_CLKCON0_SYSCLKDIV \ + 0x0000003F /* System Clock Divider Configuration */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKEN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_CLKEN1_GPT1DIS 7 /* GPT1 Clock Enable */ +#define BITP_AFECON_CLKEN1_GPT0DIS 6 /* GPT0 Clock Enable */ +#define BITP_AFECON_CLKEN1_ACLKDIS 5 /* ACLK Clock Enable */ +#define BITM_AFECON_CLKEN1_GPT1DIS 0x00000080 /* GPT1 Clock Enable */ +#define BITM_AFECON_CLKEN1_GPT0DIS 0x00000040 /* GPT0 Clock Enable */ +#define BITM_AFECON_CLKEN1_ACLKDIS 0x00000020 /* ACLK Clock Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKSEL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_CLKSEL_ADCCLKSEL 2 /* Select ADC Clock Source */ +#define BITP_AFECON_CLKSEL_SYSCLKSEL 0 /* Select System Clock Source */ +#define BITM_AFECON_CLKSEL_ADCCLKSEL 0x0000000C /* Select ADC Clock Source */ +#define BITM_AFECON_CLKSEL_SYSCLKSEL \ + 0x00000003 /* Select System Clock Source */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_CLKCON0KEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_CLKCON0KEY_DIVSYSCLK_ULP_EN \ + 0 /* Enable Clock Division to 8Mhz,4Mhz and 2Mhz */ +#define BITM_AFECON_CLKCON0KEY_DIVSYSCLK_ULP_EN \ + 0x0000FFFF /* Enable Clock Division to 8Mhz,4Mhz and 2Mhz */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_SWRSTCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_SWRSTCON_SWRSTL 0 /* Software Reset */ +#define BITM_AFECON_SWRSTCON_SWRSTL 0x0000FFFF /* Software Reset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECON_TRIGSEQ Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECON_TRIGSEQ_TRIG3 3 /* Trigger Sequence 3 */ +#define BITP_AFECON_TRIGSEQ_TRIG2 2 /* Trigger Sequence 2 */ +#define BITP_AFECON_TRIGSEQ_TRIG1 1 /* Trigger Sequence 1 */ +#define BITP_AFECON_TRIGSEQ_TRIG0 0 /* Trigger Sequence 0 */ +#define BITM_AFECON_TRIGSEQ_TRIG3 0x00000008 /* Trigger Sequence 3 */ +#define BITM_AFECON_TRIGSEQ_TRIG2 0x00000004 /* Trigger Sequence 2 */ +#define BITM_AFECON_TRIGSEQ_TRIG1 0x00000002 /* Trigger Sequence 1 */ +#define BITM_AFECON_TRIGSEQ_TRIG0 0x00000001 /* Trigger Sequence 0 */ + +/* ============================================================================================================================ + AFEWDT + ============================================================================================================================ + */ +#define REG_AFEWDT_WDTLD 0x00000900 /* AFEWDT Watchdog Timer Load Value */ +#define REG_AFEWDT_WDTVALS 0x00000904 /* AFEWDT Current Count Value */ +#define REG_AFEWDT_WDTCON \ + 0x00000908 /* AFEWDT Watchdog Timer Control Register */ +#define REG_AFEWDT_WDTCLRI 0x0000090C /* AFEWDT Refresh Watchdog Register */ +#define REG_AFEWDT_WDTSTA 0x00000918 /* AFEWDT Timer Status */ +#define REG_AFEWDT_WDTMINLD 0x0000091C /* AFEWDT Minimum Load Value */ + +/* ============================================================================================================================ + AFEWDT Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTLD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFEWDT_WDTLD_LOAD 0 /* WDT Load Value */ +#define BITM_AFEWDT_WDTLD_LOAD \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* WDT Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTVALS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFEWDT_WDTVALS_CCOUNT 0 /* Current WDT Count Value. */ +#define BITM_AFEWDT_WDTVALS_CCOUNT \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Current WDT Count Value. \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFEWDT_WDTCON_RESERVED_15_11 11 /* RESERVED */ +#define BITP_AFEWDT_WDTCON_WDTIRQEN 10 /* WDT Interrupt Enable */ +#define BITP_AFEWDT_WDTCON_MINLOAD_EN 9 /* Timer Window Control */ +#define BITP_AFEWDT_WDTCON_CLKDIV2 8 /* Clock Source */ +#define BITP_AFEWDT_WDTCON_RESERVED1_7 7 /* Reserved */ +#define BITP_AFEWDT_WDTCON_MDE 6 /* Timer Mode Select */ +#define BITP_AFEWDT_WDTCON_EN 5 /* Timer Enable */ +#define BITP_AFEWDT_WDTCON_PRE 2 /* Prescaler. */ +#define BITP_AFEWDT_WDTCON_IRQ 1 /* WDT Interrupt Enable */ +#define BITP_AFEWDT_WDTCON_PDSTOP 0 /* Power Down Stop Enable */ +#define BITM_AFEWDT_WDTCON_RESERVED_15_11 \ + (_ADI_MSK_3(0x0000F800, 0x0000F800U, uint16_t)) /* RESERVED */ +#define BITM_AFEWDT_WDTCON_WDTIRQEN \ + (_ADI_MSK_3(0x00000400, 0x00000400U, uint16_t)) /* WDT Interrupt Enable */ +#define BITM_AFEWDT_WDTCON_MINLOAD_EN \ + (_ADI_MSK_3(0x00000200, 0x00000200U, uint16_t)) /* Timer Window Control */ +#define BITM_AFEWDT_WDTCON_CLKDIV2 \ + (_ADI_MSK_3(0x00000100, 0x00000100U, uint16_t)) /* Clock Source */ +#define BITM_AFEWDT_WDTCON_RESERVED1_7 \ + (_ADI_MSK_3(0x00000080, 0x00000080U, uint16_t)) /* Reserved */ +#define BITM_AFEWDT_WDTCON_MDE \ + (_ADI_MSK_3(0x00000040, 0x00000040U, uint16_t)) /* Timer Mode Select */ +#define BITM_AFEWDT_WDTCON_EN \ + (_ADI_MSK_3(0x00000020, 0x00000020U, uint16_t)) /* Timer Enable */ +#define BITM_AFEWDT_WDTCON_PRE \ + (_ADI_MSK_3(0x0000000C, 0x0000000CU, uint16_t)) /* Prescaler. */ +#define BITM_AFEWDT_WDTCON_IRQ \ + (_ADI_MSK_3(0x00000002, 0x00000002U, uint16_t)) /* WDT Interrupt Enable */ +#define BITM_AFEWDT_WDTCON_PDSTOP \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* Power Down Stop Enable \ + */ +#define ENUM_AFEWDT_WDTCON_RESET \ + (_ADI_MSK_3(0x00000000, 0x00000000U, \ + uint16_t)) /* IRQ: Watchdog Timer timeout creates a reset. */ +#define ENUM_AFEWDT_WDTCON_INTERRUPT \ + (_ADI_MSK_3(0x00000002, 0x00000002U, \ + uint16_t)) /* IRQ: Watchdog Timer timeout creates an interrupt \ + instead of reset. */ +#define ENUM_AFEWDT_WDTCON_CONTINUE \ + (_ADI_MSK_3(0x00000000, 0x00000000U, \ + uint16_t)) /* PDSTOP: Continue Counting When In Hibernate */ +#define ENUM_AFEWDT_WDTCON_STOP \ + (_ADI_MSK_3(0x00000001, 0x00000001U, \ + uint16_t)) /* PDSTOP: Stop Counter When In Hibernate. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTCLRI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFEWDT_WDTCLRI_CLRWDG 0 /* Refresh Register */ +#define BITM_AFEWDT_WDTCLRI_CLRWDG \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Refresh Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFEWDT_WDTSTA_RESERVED_15_7 7 /* RESERVED */ +#define BITP_AFEWDT_WDTSTA_TMINLD 6 /* WDTMINLD Write Status */ +#define BITP_AFEWDT_WDTSTA_OTPWRDONE 5 /* Reset Type Status */ +#define BITP_AFEWDT_WDTSTA_LOCK 4 /* Lock Status */ +#define BITP_AFEWDT_WDTSTA_CON 3 /* WDTCON Write Status */ +#define BITP_AFEWDT_WDTSTA_TLD 2 /* WDTVAL Write Status */ +#define BITP_AFEWDT_WDTSTA_CLRI 1 /* WDTCLRI Write Status */ +#define BITP_AFEWDT_WDTSTA_IRQ 0 /* WDT Interrupt */ +#define BITM_AFEWDT_WDTSTA_RESERVED_15_7 \ + (_ADI_MSK_3(0x0000FF80, 0x0000FF80U, uint16_t)) /* RESERVED */ +#define BITM_AFEWDT_WDTSTA_TMINLD \ + (_ADI_MSK_3(0x00000040, 0x00000040U, uint16_t)) /* WDTMINLD Write Status */ +#define BITM_AFEWDT_WDTSTA_OTPWRDONE \ + (_ADI_MSK_3(0x00000020, 0x00000020U, uint16_t)) /* Reset Type Status */ +#define BITM_AFEWDT_WDTSTA_LOCK \ + (_ADI_MSK_3(0x00000010, 0x00000010U, uint16_t)) /* Lock Status */ +#define BITM_AFEWDT_WDTSTA_CON \ + (_ADI_MSK_3(0x00000008, 0x00000008U, uint16_t)) /* WDTCON Write Status */ +#define BITM_AFEWDT_WDTSTA_TLD \ + (_ADI_MSK_3(0x00000004, 0x00000004U, uint16_t)) /* WDTVAL Write Status */ +#define BITM_AFEWDT_WDTSTA_CLRI \ + (_ADI_MSK_3(0x00000002, 0x00000002U, uint16_t)) /* WDTCLRI Write Status */ +#define BITM_AFEWDT_WDTSTA_IRQ \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* WDT Interrupt */ +#define ENUM_AFEWDT_WDTSTA_OPEN \ + (_ADI_MSK_3(0x00000000, 0x00000000U, \ + uint16_t)) /* LOCK: Timer Operation Not Locked */ +#define ENUM_AFEWDT_WDTSTA_LOCKED \ + (_ADI_MSK_3(0x00000010, 0x00000010U, \ + uint16_t)) /* LOCK: Timer Enabled and Locked */ +#define ENUM_AFEWDT_WDTSTA_SYNC_COMPLETE \ + (_ADI_MSK_3(0x00000000, 0x00000000U, \ + uint16_t)) /* TLD: Arm and AFE Watchdog Clock Domains WDTLD \ + values match */ +#define ENUM_AFEWDT_WDTSTA_SYNC_IN_PROGRESS \ + (_ADI_MSK_3(0x00000004, 0x00000004U, \ + uint16_t)) /* TLD: Synchronize In Progress */ +#define ENUM_AFEWDT_WDTSTA_CLEARED \ + (_ADI_MSK_3(0x00000000, 0x00000000U, \ + uint16_t)) /* IRQ: Watchdog Timer Interrupt Not Pending */ +#define ENUM_AFEWDT_WDTSTA_PENDING \ + (_ADI_MSK_3(0x00000001, 0x00000001U, \ + uint16_t)) /* IRQ: Watchdog Timer Interrupt Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFEWDT_WDTMINLD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFEWDT_WDTMINLD_MIN_LOAD 0 /* WDT Min Load Value */ +#define BITM_AFEWDT_WDTMINLD_MIN_LOAD \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* WDT Min Load Value */ + +/* ============================================================================================================================ + Wakeup Timer + ============================================================================================================================ + */ + +/* ============================================================================================================================ + WUPTMR + ============================================================================================================================ + */ +#define REG_WUPTMR_CON_RESET 0x00000000 /* Reset Value for CON */ +#define REG_WUPTMR_CON 0x00000800 /* WUPTMR Timer Control */ +#define REG_WUPTMR_SEQORDER_RESET \ + 0x00000000 /* Reset Value for SEQORDER */ +#define REG_WUPTMR_SEQORDER 0x00000804 /* WUPTMR Order Control */ +#define REG_WUPTMR_SEQ0WUPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ0WUPL */ +#define REG_WUPTMR_SEQ0WUPL 0x00000808 /* WUPTMR SEQ0 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ0WUPH_RESET \ + 0x0000000F /* Reset Value for SEQ0WUPH */ +#define REG_WUPTMR_SEQ0WUPH 0x0000080C /* WUPTMR SEQ0 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ0SLEEPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ0SLEEPL */ +#define REG_WUPTMR_SEQ0SLEEPL 0x00000810 /* WUPTMR SEQ0 STimeL (LSB) */ +#define REG_WUPTMR_SEQ0SLEEPH_RESET \ + 0x0000000F /* Reset Value for SEQ0SLEEPH */ +#define REG_WUPTMR_SEQ0SLEEPH 0x00000814 /* WUPTMR SEQ0 STimeH (MSB) */ +#define REG_WUPTMR_SEQ1WUPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ1WUPL */ +#define REG_WUPTMR_SEQ1WUPL 0x00000818 /* WUPTMR SEQ1 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ1WUPH_RESET \ + 0x0000000F /* Reset Value for SEQ1WUPH */ +#define REG_WUPTMR_SEQ1WUPH 0x0000081C /* WUPTMR SEQ1 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ1SLEEPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ1SLEEPL */ +#define REG_WUPTMR_SEQ1SLEEPL 0x00000820 /* WUPTMR SEQ1 STimeL (LSB) */ +#define REG_WUPTMR_SEQ1SLEEPH_RESET \ + 0x0000000F /* Reset Value for SEQ1SLEEPH */ +#define REG_WUPTMR_SEQ1SLEEPH 0x00000824 /* WUPTMR SEQ1 STimeH (MSB) */ +#define REG_WUPTMR_SEQ2WUPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ2WUPL */ +#define REG_WUPTMR_SEQ2WUPL 0x00000828 /* WUPTMR SEQ2 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ2WUPH_RESET \ + 0x0000000F /* Reset Value for SEQ2WUPH */ +#define REG_WUPTMR_SEQ2WUPH 0x0000082C /* WUPTMR SEQ2 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ2SLEEPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ2SLEEPL */ +#define REG_WUPTMR_SEQ2SLEEPL 0x00000830 /* WUPTMR SEQ2 STimeL (LSB) */ +#define REG_WUPTMR_SEQ2SLEEPH_RESET \ + 0x0000000F /* Reset Value for SEQ2SLEEPH */ +#define REG_WUPTMR_SEQ2SLEEPH 0x00000834 /* WUPTMR SEQ2 STimeH (MSB) */ +#define REG_WUPTMR_SEQ3WUPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ3WUPL */ +#define REG_WUPTMR_SEQ3WUPL 0x00000838 /* WUPTMR SEQ3 WTimeL (LSB) */ +#define REG_WUPTMR_SEQ3WUPH_RESET \ + 0x0000000F /* Reset Value for SEQ3WUPH */ +#define REG_WUPTMR_SEQ3WUPH 0x0000083C /* WUPTMR SEQ3 WTimeH (MSB) */ +#define REG_WUPTMR_SEQ3SLEEPL_RESET \ + 0x0000FFFF /* Reset Value for SEQ3SLEEPL */ +#define REG_WUPTMR_SEQ3SLEEPL 0x00000840 /* WUPTMR SEQ3 STimeL (LSB) */ +#define REG_WUPTMR_SEQ3SLEEPH_RESET \ + 0x0000000F /* Reset Value for SEQ3SLEEPH */ +#define REG_WUPTMR_SEQ3SLEEPH 0x00000844 /* WUPTMR SEQ3 STimeH (MSB) */ + +/* ============================================================================================================================ + WUPTMR Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_CON_MSKTRG \ + 6 /* Mark Sequence Trigger from Sleep Wakeup Timer */ +#define BITP_WUPTMR_CON_CLKSEL 4 /* Clock Selection */ +#define BITP_WUPTMR_CON_ENDSEQ 1 /* End Sequence */ +#define BITP_WUPTMR_CON_EN 0 /* Sleep Wake Timer Enable Bit */ +#define BITM_WUPTMR_CON_MSKTRG \ + 0x00000040 /* Mark Sequence Trigger from Sleep Wakeup Timer */ +#define BITM_WUPTMR_CON_CLKSEL 0x00000030 /* Clock Selection */ +#define BITM_WUPTMR_CON_ENDSEQ 0x0000000E /* End Sequence */ +#define BITM_WUPTMR_CON_EN 0x00000001 /* Sleep Wake Timer Enable Bit */ +#define ENUM_WUPTMR_CON_SWT32K0 0x00000000 /* CLKSEL: Internal 32kHz OSC */ +#define ENUM_WUPTMR_CON_SWTEXT0 0x00000010 /* CLKSEL: External Clock */ +#define ENUM_WUPTMR_CON_SWT32K 0x00000020 /* CLKSEL: Internal 32kHz OSC */ +#define ENUM_WUPTMR_CON_SWTEXT 0x00000030 /* CLKSEL: External Clock */ +#define ENUM_WUPTMR_CON_ENDSEQA \ + 0x00000000 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqA And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQB \ + 0x00000002 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqB And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQC \ + 0x00000004 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqC And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQD \ + 0x00000006 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqD And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQE \ + 0x00000008 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqE And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQF \ + 0x0000000A /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqF And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQG \ + 0x0000000C /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqG And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_ENDSEQH \ + 0x0000000E /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqH And Then Go \ + Back To SeqA */ +#define ENUM_WUPTMR_CON_SWTEN 0x00000000 /* EN: Enable Sleep Wakeup Timer */ +#define ENUM_WUPTMR_CON_SWTDIS \ + 0x00000001 /* EN: Disable Sleep Wakeup Timer \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQORDER Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQORDER_SEQH 14 /* SEQH Config */ +#define BITP_WUPTMR_SEQORDER_SEQG 12 /* SEQG Config */ +#define BITP_WUPTMR_SEQORDER_SEQF 10 /* SEQF Config */ +#define BITP_WUPTMR_SEQORDER_SEQE 8 /* SEQE Config */ +#define BITP_WUPTMR_SEQORDER_SEQD 6 /* SEQD Config */ +#define BITP_WUPTMR_SEQORDER_SEQC 4 /* SEQC Config */ +#define BITP_WUPTMR_SEQORDER_SEQB 2 /* SEQB Config */ +#define BITP_WUPTMR_SEQORDER_SEQA 0 /* SEQA Config */ +#define BITM_WUPTMR_SEQORDER_SEQH 0x0000C000 /* SEQH Config */ +#define BITM_WUPTMR_SEQORDER_SEQG 0x00003000 /* SEQG Config */ +#define BITM_WUPTMR_SEQORDER_SEQF 0x00000C00 /* SEQF Config */ +#define BITM_WUPTMR_SEQORDER_SEQE 0x00000300 /* SEQE Config */ +#define BITM_WUPTMR_SEQORDER_SEQD 0x000000C0 /* SEQD Config */ +#define BITM_WUPTMR_SEQORDER_SEQC 0x00000030 /* SEQC Config */ +#define BITM_WUPTMR_SEQORDER_SEQB 0x0000000C /* SEQB Config */ +#define BITM_WUPTMR_SEQORDER_SEQA 0x00000003 /* SEQA Config */ +#define ENUM_WUPTMR_SEQORDER_SEQH0 0x00000000 /* SEQH: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQH1 0x00004000 /* SEQH: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQH2 0x00008000 /* SEQH: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQH3 0x0000C000 /* SEQH: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG0 0x00000000 /* SEQG: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG1 0x00001000 /* SEQG: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG2 0x00002000 /* SEQG: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQG3 0x00003000 /* SEQG: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF0 0x00000000 /* SEQF: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF1 0x00000400 /* SEQF: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF2 0x00000800 /* SEQF: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQF3 0x00000C00 /* SEQF: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE0 0x00000000 /* SEQE: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE1 0x00000100 /* SEQE: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE2 0x00000200 /* SEQE: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQE3 0x00000300 /* SEQE: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD0 0x00000000 /* SEQD: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD1 0x00000040 /* SEQD: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD2 0x00000080 /* SEQD: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQD3 0x000000C0 /* SEQD: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC0 0x00000000 /* SEQC: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC1 0x00000010 /* SEQC: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC2 0x00000020 /* SEQC: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQC3 0x00000030 /* SEQC: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB0 0x00000000 /* SEQB: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB1 0x00000004 /* SEQB: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB2 0x00000008 /* SEQB: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQB3 0x0000000C /* SEQB: Fill SEQ3 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA0 0x00000000 /* SEQA: Fill SEQ0 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA1 0x00000001 /* SEQA: Fill SEQ1 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA2 0x00000002 /* SEQA: Fill SEQ2 In */ +#define ENUM_WUPTMR_SEQORDER_SEQA3 0x00000003 /* SEQA: Fill SEQ3 In */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ0WUPL_WAKEUPTIME0 0 /* Sequence 0 Sleep Period */ +#define BITM_WUPTMR_SEQ0WUPL_WAKEUPTIME0 \ + 0x0000FFFF /* Sequence 0 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ0WUPH_WAKEUPTIME0 0 /* Sequence 0 Sleep Period */ +#define BITM_WUPTMR_SEQ0WUPH_WAKEUPTIME0 \ + 0x0000000F /* Sequence 0 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ0SLEEPL_SLEEPTIME0 0 /* Sequence 0 Active Period */ +#define BITM_WUPTMR_SEQ0SLEEPL_SLEEPTIME0 \ + 0x0000FFFF /* Sequence 0 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ0SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ0SLEEPH_SLEEPTIME0 0 /* Sequence 0 Active Period */ +#define BITM_WUPTMR_SEQ0SLEEPH_SLEEPTIME0 \ + 0x0000000F /* Sequence 0 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ1WUPL_WAKEUPTIME 0 /* Sequence 1 Sleep Period */ +#define BITM_WUPTMR_SEQ1WUPL_WAKEUPTIME \ + 0x0000FFFF /* Sequence 1 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ1WUPH_WAKEUPTIME 0 /* Sequence 1 Sleep Period */ +#define BITM_WUPTMR_SEQ1WUPH_WAKEUPTIME \ + 0x0000000F /* Sequence 1 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ1SLEEPL_SLEEPTIME1 0 /* Sequence 1 Active Period */ +#define BITM_WUPTMR_SEQ1SLEEPL_SLEEPTIME1 \ + 0x0000FFFF /* Sequence 1 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ1SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ1SLEEPH_SLEEPTIME1 0 /* Sequence 1 Active Period */ +#define BITM_WUPTMR_SEQ1SLEEPH_SLEEPTIME1 \ + 0x0000000F /* Sequence 1 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ2WUPL_WAKEUPTIME2 0 /* Sequence 2 Sleep Period */ +#define BITM_WUPTMR_SEQ2WUPL_WAKEUPTIME2 \ + 0x0000FFFF /* Sequence 2 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ2WUPH_WAKEUPTIME2 0 /* Sequence 2 Sleep Period */ +#define BITM_WUPTMR_SEQ2WUPH_WAKEUPTIME2 \ + 0x0000000F /* Sequence 2 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ2SLEEPL_SLEEPTIME2 0 /* Sequence 2 Active Period */ +#define BITM_WUPTMR_SEQ2SLEEPL_SLEEPTIME2 \ + 0x0000FFFF /* Sequence 2 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ2SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ2SLEEPH_SLEEPTIME2 0 /* Sequence 2 Active Period */ +#define BITM_WUPTMR_SEQ2SLEEPH_SLEEPTIME2 \ + 0x0000000F /* Sequence 2 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3WUPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ3WUPL_WAKEUPTIME3 0 /* Sequence 3 Sleep Period */ +#define BITM_WUPTMR_SEQ3WUPL_WAKEUPTIME3 \ + 0x0000FFFF /* Sequence 3 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3WUPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ3WUPH_WAKEUPTIME3 0 /* Sequence 3 Sleep Period */ +#define BITM_WUPTMR_SEQ3WUPH_WAKEUPTIME3 \ + 0x0000000F /* Sequence 3 Sleep Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3SLEEPL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ3SLEEPL_SLEEPTIME3 0 /* Sequence 3 Active Period */ +#define BITM_WUPTMR_SEQ3SLEEPL_SLEEPTIME3 \ + 0x0000FFFF /* Sequence 3 Active Period */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WUPTMR_SEQ3SLEEPH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_WUPTMR_SEQ3SLEEPH_SLEEPTIME3 0 /* Sequence 3 Active Period */ +#define BITM_WUPTMR_SEQ3SLEEPH_SLEEPTIME3 \ + 0x0000000F /* Sequence 3 Active Period */ + +/* ============================================================================================================================ + Always On Register + ============================================================================================================================ + */ + +/* ============================================================================================================================ + ALLON + ============================================================================================================================ + */ +#define REG_ALLON_PWRMOD_RESET 0x00000001 /* Reset Value for PWRMOD */ +#define REG_ALLON_PWRMOD 0x00000A00 /* ALLON Power Modes */ +#define REG_ALLON_PWRKEY_RESET 0x00000000 /* Reset Value for PWRKEY */ +#define REG_ALLON_PWRKEY 0x00000A04 /* ALLON Key Protection for PWRMOD */ +#define REG_ALLON_OSCKEY_RESET 0x00000000 /* Reset Value for OSCKEY */ +#define REG_ALLON_OSCKEY 0x00000A0C /* ALLON Key Protection for OSCCON */ +#define REG_ALLON_OSCCON_RESET 0x00000003 /* Reset Value for OSCCON */ +#define REG_ALLON_OSCCON 0x00000A10 /* ALLON Oscillator Control */ +#define REG_ALLON_TMRCON_RESET 0x00000000 /* Reset Value for TMRCON */ +#define REG_ALLON_TMRCON 0x00000A1C /* ALLON Timer Wakeup Configuration */ +#define REG_ALLON_EI0CON_RESET 0x00000000 /* Reset Value for EI0CON */ +#define REG_ALLON_EI0CON \ + 0x00000A20 /* ALLON External Interrupt Configuration 0 */ +#define REG_ALLON_EI1CON_RESET 0x00000000 /* Reset Value for EI1CON */ +#define REG_ALLON_EI1CON \ + 0x00000A24 /* ALLON External Interrupt Configuration 1 */ +#define REG_ALLON_EI2CON_RESET 0x00000000 /* Reset Value for EI2CON */ +#define REG_ALLON_EI2CON \ + 0x00000A28 /* ALLON External Interrupt Configuration 2 */ +#define REG_ALLON_EICLR_RESET 0x0000C000 /* Reset Value for EICLR */ +#define REG_ALLON_EICLR 0x00000A30 /* ALLON External Interrupt Clear */ +#define REG_ALLON_RSTSTA_RESET 0x00000000 /* Reset Value for RSTSTA */ +#define REG_ALLON_RSTSTA 0x00000A40 /* ALLON Reset Status */ +#define REG_ALLON_RSTCONKEY_RESET \ + 0x00000000 /* Reset Value for RSTCONKEY */ +#define REG_ALLON_RSTCONKEY \ + 0x00000A5C /* ALLON Key Protection for RSTCON Register */ +#define REG_ALLON_LOSCTST_RESET 0x0000008F /* Reset Value for LOSCTST */ +#define REG_ALLON_LOSCTST 0x00000A6C /* ALLON Internal LF Oscillator Test */ +#define REG_ALLON_CLKEN0_RESET 0x00000004 /* Reset Value for CLKEN0 */ +#define REG_ALLON_CLKEN0 0x00000A70 /* ALLON 32KHz Peripheral Clock Enable */ + +/* ============================================================================================================================ + ALLON Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_PWRMOD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_PWRMOD_RAMRETEN 15 /* Retention for RAM */ +#define BITP_ALLON_PWRMOD_ADCRETEN \ + 14 /* Keep ADC Power Switch on in Hibernate */ +#define BITP_ALLON_PWRMOD_SEQSLPEN 3 /* Auto Sleep by Sequencer Command */ +#define BITP_ALLON_PWRMOD_TMRSLPEN 2 /* Auto Sleep by Sleep Wakeup Timer */ +#define BITP_ALLON_PWRMOD_PWRMOD 0 /* Power Mode Control Bits */ +#define BITM_ALLON_PWRMOD_RAMRETEN 0x00008000 /* Retention for RAM */ +#define BITM_ALLON_PWRMOD_ADCRETEN \ + 0x00004000 /* Keep ADC Power Switch on in Hibernate */ +#define BITM_ALLON_PWRMOD_SEQSLPEN \ + 0x00000008 /* Auto Sleep by Sequencer Command */ +#define BITM_ALLON_PWRMOD_TMRSLPEN \ + 0x00000004 /* Auto Sleep by Sleep Wakeup Timer */ +#define BITM_ALLON_PWRMOD_PWRMOD 0x00000003 /* Power Mode Control Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_PWRKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_PWRKEY_PWRKEY 0 /* PWRMOD Key Register */ +#define BITM_ALLON_PWRKEY_PWRKEY 0x0000FFFF /* PWRMOD Key Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_OSCKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_OSCKEY_OSCKEY 0 /* Oscillator Control Key Register. */ +#define BITM_ALLON_OSCKEY_OSCKEY \ + 0x0000FFFF /* Oscillator Control Key Register. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_OSCCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_OSCCON_HFXTALOK 10 /* Status of HFXTAL Oscillator */ +#define BITP_ALLON_OSCCON_HFOSCOK 9 /* Status of HFOSC Oscillator */ +#define BITP_ALLON_OSCCON_LFOSCOK 8 /* Status of LFOSC Oscillator */ +#define BITP_ALLON_OSCCON_HFXTALEN \ + 2 /* High Frequency Crystal Oscillator Enable */ +#define BITP_ALLON_OSCCON_HFOSCEN \ + 1 /* High Frequency Internal Oscillator Enable */ +#define BITP_ALLON_OSCCON_LFOSCEN \ + 0 /* Low Frequency Internal Oscillator Enable */ +#define BITM_ALLON_OSCCON_HFXTALOK \ + 0x00000400 /* Status of HFXTAL Oscillator \ + */ +#define BITM_ALLON_OSCCON_HFOSCOK 0x00000200 /* Status of HFOSC Oscillator */ +#define BITM_ALLON_OSCCON_LFOSCOK 0x00000100 /* Status of LFOSC Oscillator */ +#define BITM_ALLON_OSCCON_HFXTALEN \ + 0x00000004 /* High Frequency Crystal Oscillator Enable */ +#define BITM_ALLON_OSCCON_HFOSCEN \ + 0x00000002 /* High Frequency Internal Oscillator Enable */ +#define BITM_ALLON_OSCCON_LFOSCEN \ + 0x00000001 /* Low Frequency Internal Oscillator Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_TMRCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_TMRCON_TMRINTEN 0 /* Enable Wakeup Timer */ +#define BITM_ALLON_TMRCON_TMRINTEN 0x00000001 /* Enable Wakeup Timer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EI0CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_EI0CON_IRQ3EN 15 /* External Interrupt 3 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ3MDE \ + 12 /* External Interrupt 3 Mode Registers \ + */ +#define BITP_ALLON_EI0CON_IRQ2EN 11 /* External Interrupt 2 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ2MDE 8 /* External Interrupt 2 Mode Registers */ +#define BITP_ALLON_EI0CON_IRQ1EN 7 /* External Interrupt 1 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ1MDE 4 /* External Interrupt 1 Mode Registers */ +#define BITP_ALLON_EI0CON_IRQ0EN 3 /* External Interrupt 0 Enable Bit */ +#define BITP_ALLON_EI0CON_IRQ0MDE 0 /* External Interrupt 0 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ3EN \ + 0x00008000 /* External Interrupt 3 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ3MDE \ + 0x00007000 /* External Interrupt 3 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ2EN \ + 0x00000800 /* External Interrupt 2 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ2MDE \ + 0x00000700 /* External Interrupt 2 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ1EN \ + 0x00000080 /* External Interrupt 1 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ1MDE \ + 0x00000070 /* External Interrupt 1 Mode Registers */ +#define BITM_ALLON_EI0CON_IRQ0EN \ + 0x00000008 /* External Interrupt 0 Enable Bit */ +#define BITM_ALLON_EI0CON_IRQ0MDE \ + 0x00000007 /* External Interrupt 0 Mode Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EI1CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_EI1CON_IRQ7EN 15 /* External Interrupt 7 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ7MDE \ + 12 /* External Interrupt 7 Mode Registers \ + */ +#define BITP_ALLON_EI1CON_IRQ6EN 11 /* External Interrupt 6 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ6MDE 8 /* External Interrupt 6 Mode Registers */ +#define BITP_ALLON_EI1CON_IRQ5EN 7 /* External Interrupt 5 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ5MDE 4 /* External Interrupt 5 Mode Registers */ +#define BITP_ALLON_EI1CON_IRQ4EN 3 /* External Interrupt 4 Enable Bit */ +#define BITP_ALLON_EI1CON_IRQ4MDE 0 /* External Interrupt 4 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ7EN \ + 0x00008000 /* External Interrupt 7 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ7MDE \ + 0x00007000 /* External Interrupt 7 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ6EN \ + 0x00000800 /* External Interrupt 6 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ6MDE \ + 0x00000700 /* External Interrupt 6 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ5EN \ + 0x00000080 /* External Interrupt 5 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ5MDE \ + 0x00000070 /* External Interrupt 5 Mode Registers */ +#define BITM_ALLON_EI1CON_IRQ4EN \ + 0x00000008 /* External Interrupt 4 Enable Bit */ +#define BITM_ALLON_EI1CON_IRQ4MDE \ + 0x00000007 /* External Interrupt 4 Mode Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EI2CON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_EI2CON_BUSINTEN 3 /* BUS Interrupt Detection Enable Bit */ +#define BITP_ALLON_EI2CON_BUSINTMDE \ + 0 /* BUS Interrupt Detection Mode Registers */ +#define BITM_ALLON_EI2CON_BUSINTEN \ + 0x00000008 /* BUS Interrupt Detection Enable Bit */ +#define BITM_ALLON_EI2CON_BUSINTMDE \ + 0x00000007 /* BUS Interrupt Detection Mode Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_EICLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_EICLR_AUTCLRBUSEN \ + 15 /* Enable Auto Clear of Bus Interrupt */ +#define BITP_ALLON_EICLR_BUSINT 8 /* BUS Interrupt */ +#define BITM_ALLON_EICLR_AUTCLRBUSEN \ + 0x00008000 /* Enable Auto Clear of Bus Interrupt */ +#define BITM_ALLON_EICLR_BUSINT 0x00000100 /* BUS Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_RSTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_RSTSTA_PINSWRST 4 /* Software Reset Pin */ +#define BITP_ALLON_RSTSTA_MMRSWRST 3 /* MMR Software Reset */ +#define BITP_ALLON_RSTSTA_WDRST 2 /* Watchdog Timeout */ +#define BITP_ALLON_RSTSTA_EXTRST 1 /* External Reset */ +#define BITP_ALLON_RSTSTA_POR 0 /* Power-on Reset */ +#define BITM_ALLON_RSTSTA_PINSWRST 0x00000010 /* Software Reset Pin */ +#define BITM_ALLON_RSTSTA_MMRSWRST 0x00000008 /* MMR Software Reset */ +#define BITM_ALLON_RSTSTA_WDRST 0x00000004 /* Watchdog Timeout */ +#define BITM_ALLON_RSTSTA_EXTRST 0x00000002 /* External Reset */ +#define BITM_ALLON_RSTSTA_POR 0x00000001 /* Power-on Reset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_RSTCONKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_RSTCONKEY_KEY 0 /* Reset Control Key Register */ +#define BITM_ALLON_RSTCONKEY_KEY 0x0000FFFF /* Reset Control Key Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_LOSCTST Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_LOSCTST_TRIM 0 /* Trim Caps to Adjust Frequency. */ +#define BITM_ALLON_LOSCTST_TRIM \ + 0x0000000F /* Trim Caps to Adjust Frequency. \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ALLON_CLKEN0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_ALLON_CLKEN0_TIACHPDIS 2 /* TIA Chop Clock Disable */ +#define BITP_ALLON_CLKEN0_SLPWUTDIS 1 /* Sleep/Wakeup Timer Clock Disable */ +#define BITP_ALLON_CLKEN0_WDTDIS 0 /* Watch Dog Timer Clock Disable */ +#define BITM_ALLON_CLKEN0_TIACHPDIS 0x00000004 /* TIA Chop Clock Disable */ +#define BITM_ALLON_CLKEN0_SLPWUTDIS \ + 0x00000002 /* Sleep/Wakeup Timer Clock Disable */ +#define BITM_ALLON_CLKEN0_WDTDIS \ + 0x00000001 /* Watch Dog Timer Clock Disable \ + */ + +/* ============================================================================================================================ + General Purpose Timer + ============================================================================================================================ + */ + +/* ============================================================================================================================ + AGPT0 + ============================================================================================================================ + */ +#define REG_AGPT0_LD0 0x00000D00 /* AGPT0 16-bit Load Value Register. */ +#define REG_AGPT0_VAL0 0x00000D04 /* AGPT0 16-Bit Timer Value Register. */ +#define REG_AGPT0_CON0 0x00000D08 /* AGPT0 Control Register. */ +#define REG_AGPT0_CLRI0 0x00000D0C /* AGPT0 Clear Interrupt Register. */ +#define REG_AGPT0_CAP0 0x00000D10 /* AGPT0 Capture Register. */ +#define REG_AGPT0_ALD0 \ + 0x00000D14 /* AGPT0 16-Bit Load Value, Asynchronous. \ + */ +#define REG_AGPT0_AVAL0 \ + 0x00000D18 /* AGPT0 16-Bit Timer Value, Asynchronous Register. */ +#define REG_AGPT0_STA0 0x00000D1C /* AGPT0 Status Register. */ +#define REG_AGPT0_PWMCON0 0x00000D20 /* AGPT0 PWM Control Register. */ +#define REG_AGPT0_PWMMAT0 0x00000D24 /* AGPT0 PWM Match Value Register. */ +#define REG_AGPT0_INTEN 0x00000D28 /* AGPT0 Interrupt Enable */ + +/* ============================================================================================================================ + AGPT0 Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_LD0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_LD0_LOAD 0 /* Load Value */ +#define BITM_AGPT0_LD0_LOAD \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_VAL0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_VAL0_VAL 0 /* Current Count */ +#define BITM_AGPT0_VAL0_VAL \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Current Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_CON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_CON0_SYNCBYP 15 /* Synchronization Bypass */ +#define BITP_AGPT0_CON0_RSTEN 14 /* Counter and Prescale Reset Enable */ +#define BITP_AGPT0_CON0_EVTEN 13 /* Event Select */ +#define BITP_AGPT0_CON0_EVENT 8 /* Event Select Range */ +#define BITP_AGPT0_CON0_RLD 7 /* Reload Control */ +#define BITP_AGPT0_CON0_CLK 5 /* Clock Select */ +#define BITP_AGPT0_CON0_ENABLE 4 /* Timer Enable */ +#define BITP_AGPT0_CON0_MOD 3 /* Timer Mode */ +#define BITP_AGPT0_CON0_UP 2 /* Count up */ +#define BITP_AGPT0_CON0_PRE 0 /* Prescaler */ +#define BITM_AGPT0_CON0_SYNCBYP \ + (_ADI_MSK_3(0x00008000, 0x00008000U, uint16_t)) /* Synchronization Bypass \ + */ +#define BITM_AGPT0_CON0_RSTEN \ + (_ADI_MSK_3(0x00004000, 0x00004000U, \ + uint16_t)) /* Counter and Prescale Reset Enable */ +#define BITM_AGPT0_CON0_EVTEN \ + (_ADI_MSK_3(0x00002000, 0x00002000U, uint16_t)) /* Event Select */ +#define BITM_AGPT0_CON0_EVENT \ + (_ADI_MSK_3(0x00001F00, 0x00001F00U, uint16_t)) /* Event Select Range */ +#define BITM_AGPT0_CON0_RLD \ + (_ADI_MSK_3(0x00000080, 0x00000080U, uint16_t)) /* Reload Control */ +#define BITM_AGPT0_CON0_CLK \ + (_ADI_MSK_3(0x00000060, 0x00000060U, uint16_t)) /* Clock Select */ +#define BITM_AGPT0_CON0_ENABLE \ + (_ADI_MSK_3(0x00000010, 0x00000010U, uint16_t)) /* Timer Enable */ +#define BITM_AGPT0_CON0_MOD \ + (_ADI_MSK_3(0x00000008, 0x00000008U, uint16_t)) /* Timer Mode */ +#define BITM_AGPT0_CON0_UP \ + (_ADI_MSK_3(0x00000004, 0x00000004U, uint16_t)) /* Count up */ +#define BITM_AGPT0_CON0_PRE \ + (_ADI_MSK_3(0x00000003, 0x00000003U, uint16_t)) /* Prescaler */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_CLRI0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_CLRI0_CAP 1 /* Clear Captured Event Interrupt */ +#define BITP_AGPT0_CLRI0_TMOUT 0 /* Clear Timeout Interrupt */ +#define BITM_AGPT0_CLRI0_CAP \ + (_ADI_MSK_3(0x00000002, 0x00000002U, \ + uint16_t)) /* Clear Captured Event Interrupt */ +#define BITM_AGPT0_CLRI0_TMOUT \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* Clear Timeout Interrupt \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_CAP0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_CAP0_CAP 0 /* 16-bit Captured Value */ +#define BITM_AGPT0_CAP0_CAP \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* 16-bit Captured Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_ALD0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_ALD0_ALOAD 0 /* Load Value, Asynchronous */ +#define BITM_AGPT0_ALD0_ALOAD \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Load Value, Asynchronous \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_AVAL0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_AVAL0_AVAL 0 /* Counter Value */ +#define BITM_AGPT0_AVAL0_AVAL \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Counter Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_STA0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_STA0_RSTCNT 8 /* Counter Reset Occurring */ +#define BITP_AGPT0_STA0_PDOK 7 /* Clear Interrupt Register Synchronization */ +#define BITP_AGPT0_STA0_BUSY 6 /* Timer Busy */ +#define BITP_AGPT0_STA0_CAP 1 /* Capture Event Pending */ +#define BITP_AGPT0_STA0_TMOUT 0 /* Timeout Event Occurred */ +#define BITM_AGPT0_STA0_RSTCNT \ + (_ADI_MSK_3(0x00000100, 0x00000100U, uint16_t)) /* Counter Reset Occurring \ + */ +#define BITM_AGPT0_STA0_PDOK \ + (_ADI_MSK_3(0x00000080, 0x00000080U, \ + uint16_t)) /* Clear Interrupt Register Synchronization */ +#define BITM_AGPT0_STA0_BUSY \ + (_ADI_MSK_3(0x00000040, 0x00000040U, uint16_t)) /* Timer Busy */ +#define BITM_AGPT0_STA0_CAP \ + (_ADI_MSK_3(0x00000002, 0x00000002U, uint16_t)) /* Capture Event Pending */ +#define BITM_AGPT0_STA0_TMOUT \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* Timeout Event Occurred \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_PWMCON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_PWMCON0_IDLE 1 /* PWM Idle State */ +#define BITP_AGPT0_PWMCON0_MATCHEN 0 /* PWM Match Enabled */ +#define BITM_AGPT0_PWMCON0_IDLE \ + (_ADI_MSK_3(0x00000002, 0x00000002U, uint16_t)) /* PWM Idle State */ +#define BITM_AGPT0_PWMCON0_MATCHEN \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* PWM Match Enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_PWMMAT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_PWMMAT0_MATCHVAL 0 /* PWM Match Value */ +#define BITM_AGPT0_PWMMAT0_MATCHVAL \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* PWM Match Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT0_INTEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT0_INTEN_INTEN 0 /* Interrupt Enable */ +#define BITM_AGPT0_INTEN_INTEN \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* Interrupt Enable */ + +/* ============================================================================================================================ + General Purpose Timer + ============================================================================================================================ + */ + +/* ============================================================================================================================ + AGPT1 + ============================================================================================================================ + */ +#define REG_AGPT1_LD1 0x00000E00 /* AGPT1 16-bit Load Value Register */ +#define REG_AGPT1_VAL1 0x00000E04 /* AGPT1 16-bit Timer Value Register */ +#define REG_AGPT1_CON1 0x00000E08 /* AGPT1 Control Register */ +#define REG_AGPT1_CLRI1 0x00000E0C /* AGPT1 Clear Interrupt Register */ +#define REG_AGPT1_CAP1 0x00000E10 /* AGPT1 Capture Register */ +#define REG_AGPT1_ALD1 \ + 0x00000E14 /* AGPT1 16-bit Load Value, Asynchronous Register */ +#define REG_AGPT1_AVAL1 \ + 0x00000E18 /* AGPT1 16-bit Timer Value, Asynchronous Register */ +#define REG_AGPT1_STA1 0x00000E1C /* AGPT1 Status Register */ +#define REG_AGPT1_PWMCON1 0x00000E20 /* AGPT1 PWM Control Register */ +#define REG_AGPT1_PWMMAT1 0x00000E24 /* AGPT1 PWM Match Value Register */ +#define REG_AGPT1_INTEN1 0x00000E28 /* AGPT1 Interrupt Enable */ + +/* ============================================================================================================================ + AGPT1 Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_LD1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_LD1_LOAD 0 /* Load Value */ +#define BITM_AGPT1_LD1_LOAD \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_VAL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_VAL1_VAL 0 /* Current Count */ +#define BITM_AGPT1_VAL1_VAL \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Current Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_CON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_CON1_SYNCBYP 15 /* Synchronization Bypass */ +#define BITP_AGPT1_CON1_RSTEN 14 /* Counter and Prescale Reset Enable */ +#define BITP_AGPT1_CON1_EVENTEN 13 /* Event Select */ +#define BITP_AGPT1_CON1_EVENT 8 /* Event Select Range */ +#define BITP_AGPT1_CON1_RLD 7 /* Reload Control */ +#define BITP_AGPT1_CON1_CLK 5 /* Clock Select */ +#define BITP_AGPT1_CON1_ENABLE 4 /* Timer Enable */ +#define BITP_AGPT1_CON1_MOD 3 /* Timer Mode */ +#define BITP_AGPT1_CON1_UP 2 /* Count up */ +#define BITP_AGPT1_CON1_PRE 0 /* Prescaler */ +#define BITM_AGPT1_CON1_SYNCBYP \ + (_ADI_MSK_3(0x00008000, 0x00008000U, uint16_t)) /* Synchronization Bypass \ + */ +#define BITM_AGPT1_CON1_RSTEN \ + (_ADI_MSK_3(0x00004000, 0x00004000U, \ + uint16_t)) /* Counter and Prescale Reset Enable */ +#define BITM_AGPT1_CON1_EVENTEN \ + (_ADI_MSK_3(0x00002000, 0x00002000U, uint16_t)) /* Event Select */ +#define BITM_AGPT1_CON1_EVENT \ + (_ADI_MSK_3(0x00001F00, 0x00001F00U, uint16_t)) /* Event Select Range */ +#define BITM_AGPT1_CON1_RLD \ + (_ADI_MSK_3(0x00000080, 0x00000080U, uint16_t)) /* Reload Control */ +#define BITM_AGPT1_CON1_CLK \ + (_ADI_MSK_3(0x00000060, 0x00000060U, uint16_t)) /* Clock Select */ +#define BITM_AGPT1_CON1_ENABLE \ + (_ADI_MSK_3(0x00000010, 0x00000010U, uint16_t)) /* Timer Enable */ +#define BITM_AGPT1_CON1_MOD \ + (_ADI_MSK_3(0x00000008, 0x00000008U, uint16_t)) /* Timer Mode */ +#define BITM_AGPT1_CON1_UP \ + (_ADI_MSK_3(0x00000004, 0x00000004U, uint16_t)) /* Count up */ +#define BITM_AGPT1_CON1_PRE \ + (_ADI_MSK_3(0x00000003, 0x00000003U, uint16_t)) /* Prescaler */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_CLRI1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_CLRI1_CAP 1 /* Clear Captured Event Interrupt */ +#define BITP_AGPT1_CLRI1_TMOUT 0 /* Clear Timeout Interrupt */ +#define BITM_AGPT1_CLRI1_CAP \ + (_ADI_MSK_3(0x00000002, 0x00000002U, \ + uint16_t)) /* Clear Captured Event Interrupt */ +#define BITM_AGPT1_CLRI1_TMOUT \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* Clear Timeout Interrupt \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_CAP1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_CAP1_CAP 0 /* 16-bit Captured Value. */ +#define BITM_AGPT1_CAP1_CAP \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* 16-bit Captured Value. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_ALD1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_ALD1_ALOAD 0 /* Load Value, Asynchronous */ +#define BITM_AGPT1_ALD1_ALOAD \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Load Value, Asynchronous \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_AVAL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_AVAL1_AVAL 0 /* Counter Value */ +#define BITM_AGPT1_AVAL1_AVAL \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* Counter Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_STA1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_STA1_RSTCNT 8 /* Counter Reset Occurring */ +#define BITP_AGPT1_STA1_PDOK 7 /* Clear Interrupt Register Synchronization */ +#define BITP_AGPT1_STA1_BUSY 6 /* Timer Busy */ +#define BITP_AGPT1_STA1_CAP 1 /* Capture Event Pending */ +#define BITP_AGPT1_STA1_TMOUT 0 /* Timeout Event Occurred */ +#define BITM_AGPT1_STA1_RSTCNT \ + (_ADI_MSK_3(0x00000100, 0x00000100U, uint16_t)) /* Counter Reset Occurring \ + */ +#define BITM_AGPT1_STA1_PDOK \ + (_ADI_MSK_3(0x00000080, 0x00000080U, \ + uint16_t)) /* Clear Interrupt Register Synchronization */ +#define BITM_AGPT1_STA1_BUSY \ + (_ADI_MSK_3(0x00000040, 0x00000040U, uint16_t)) /* Timer Busy */ +#define BITM_AGPT1_STA1_CAP \ + (_ADI_MSK_3(0x00000002, 0x00000002U, uint16_t)) /* Capture Event Pending */ +#define BITM_AGPT1_STA1_TMOUT \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* Timeout Event Occurred \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_PWMCON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_PWMCON1_IDLE 1 /* PWM Idle State. */ +#define BITP_AGPT1_PWMCON1_MATCHEN 0 /* PWM Match Enabled. */ +#define BITM_AGPT1_PWMCON1_IDLE \ + (_ADI_MSK_3(0x00000002, 0x00000002U, uint16_t)) /* PWM Idle State. */ +#define BITM_AGPT1_PWMCON1_MATCHEN \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* PWM Match Enabled. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_PWMMAT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_PWMMAT1_MATCHVAL 0 /* PWM Match Value */ +#define BITM_AGPT1_PWMMAT1_MATCHVAL \ + (_ADI_MSK_3(0x0000FFFF, 0x0000FFFF, int16_t)) /* PWM Match Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AGPT1_INTEN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AGPT1_INTEN1_INTEN 0 /* Interrupt Enable */ +#define BITM_AGPT1_INTEN1_INTEN \ + (_ADI_MSK_3(0x00000001, 0x00000001U, uint16_t)) /* Interrupt Enable */ + +/* ============================================================================================================================ + CRC Accelerator + ============================================================================================================================ + */ + +/* ============================================================================================================================ + AFECRC + ============================================================================================================================ + */ +#define REG_AFECRC_CTL 0x00001000 /* AFECRC CRC Control Register */ +#define REG_AFECRC_IPDATA 0x00001004 /* AFECRC Data Input. */ +#define REG_AFECRC_RESULT 0x00001008 /* AFECRC CRC Residue */ +#define REG_AFECRC_POLY 0x0000100C /* AFECRC CRC Reduction Polynomial */ +#define REG_AFECRC_IPBITS 0x00001010 /* AFECRC Input Data Bits */ +#define REG_AFECRC_IPBYTE 0x00001014 /* AFECRC Input Data Byte */ +#define REG_AFECRC_CRC_SIG_COMP \ + 0x00001020 /* AFECRC CRC Signature Compare Data Input. */ +#define REG_AFECRC_CRCINTEN \ + 0x00001024 /* AFECRC CRC Error Interrupt Enable Bit */ +#define REG_AFECRC_INTSTA \ + 0x00001028 /* AFECRC CRC Error Interrupt Status Bit */ + +/* ============================================================================================================================ + AFECRC Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_CTL_REVID 28 /* Revision ID */ +#define BITP_AFECRC_CTL_MON_EN \ + 9 /* Enable Apb32/Apb16 to Get Address/Data for CRC Calculation */ +#define BITP_AFECRC_CTL_W16SWP 4 /* Word16 Swap Enabled. */ +#define BITP_AFECRC_CTL_BYTMIRR 3 /* Byte Mirroring. */ +#define BITP_AFECRC_CTL_BITMIRR 2 /* Bit Mirroring. */ +#define BITP_AFECRC_CTL_LSBFIRST 1 /* LSB First Calculation Order */ +#define BITP_AFECRC_CTL_EN 0 /* CRC Peripheral Enable */ +#define BITM_AFECRC_CTL_REVID \ + (_ADI_MSK_3(0xF0000000, 0xF0000000UL, uint32_t)) /* Revision ID */ +#define BITM_AFECRC_CTL_MON_EN \ + (_ADI_MSK_3(0x00000200, 0x00000200UL, \ + uint32_t)) /* Enable Apb32/Apb16 to Get Address/Data for CRC \ + Calculation */ +#define BITM_AFECRC_CTL_W16SWP \ + (_ADI_MSK_3(0x00000010, 0x00000010UL, uint32_t)) /* Word16 Swap Enabled. */ +#define BITM_AFECRC_CTL_BYTMIRR \ + (_ADI_MSK_3(0x00000008, 0x00000008UL, uint32_t)) /* Byte Mirroring. */ +#define BITM_AFECRC_CTL_BITMIRR \ + (_ADI_MSK_3(0x00000004, 0x00000004UL, uint32_t)) /* Bit Mirroring. */ +#define BITM_AFECRC_CTL_LSBFIRST \ + (_ADI_MSK_3(0x00000002, 0x00000002UL, \ + uint32_t)) /* LSB First Calculation Order */ +#define BITM_AFECRC_CTL_EN \ + (_ADI_MSK_3(0x00000001, 0x00000001UL, uint32_t)) /* CRC Peripheral Enable \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_IPDATA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_IPDATA_VALUE 0 /* Data Input. */ +#define BITM_AFECRC_IPDATA_VALUE \ + (_ADI_MSK_3(0xFFFFFFFF, 0xFFFFFFFF, int32_t)) /* Data Input. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_RESULT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_RESULT_VALUE 0 /* CRC Residue */ +#define BITM_AFECRC_RESULT_VALUE \ + (_ADI_MSK_3(0xFFFFFFFF, 0xFFFFFFFF, int32_t)) /* CRC Residue */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_POLY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_POLY_VALUE 0 /* CRC Reduction Polynomial */ +#define BITM_AFECRC_POLY_VALUE \ + (_ADI_MSK_3(0xFFFFFFFF, 0xFFFFFFFFUL, \ + uint32_t)) /* CRC Reduction Polynomial */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_IPBITS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_IPBITS_DATA_BITS 0 /* Input Data Bits. */ +#define BITM_AFECRC_IPBITS_DATA_BITS \ + (_ADI_MSK_3(0x000000FF, 0x000000FFU, uint8_t)) /* Input Data Bits. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_IPBYTE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_IPBYTE_DATA_BYTE 0 /* Input Data Byte. */ +#define BITM_AFECRC_IPBYTE_DATA_BYTE \ + (_ADI_MSK_3(0x000000FF, 0x000000FFU, uint8_t)) /* Input Data Byte. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_CRC_SIG_COMP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_CRC_SIG_COMP_CRC_SIG \ + 0 /* CRC Signature Compare Data Input. */ +#define BITM_AFECRC_CRC_SIG_COMP_CRC_SIG \ + (_ADI_MSK_3(0xFFFFFFFF, 0xFFFFFFFFUL, \ + uint32_t)) /* CRC Signature Compare Data Input. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_CRCINTEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_CRCINTEN_RESERVED_31_1 1 /* Reserved */ +#define BITP_AFECRC_CRCINTEN_CRC_ERR_EN \ + 0 /* CRC Error Interrupt Enable Bit \ + */ +#define BITM_AFECRC_CRCINTEN_RESERVED_31_1 \ + (_ADI_MSK_3(0xFFFFFFFE, 0xFFFFFFFEUL, uint32_t)) /* Reserved */ +#define BITM_AFECRC_CRCINTEN_CRC_ERR_EN \ + (_ADI_MSK_3(0x00000001, 0x00000001UL, \ + uint32_t)) /* CRC Error Interrupt Enable Bit */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFECRC_INTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFECRC_INTSTA_CRC_ERR_ST 0 /* CRC Error Interrupt Status Bit */ +#define BITM_AFECRC_INTSTA_CRC_ERR_ST \ + (_ADI_MSK_3(0x00000001, 0x00000001UL, \ + uint32_t)) /* CRC Error Interrupt Status Bit */ + +/* ============================================================================================================================ + + ============================================================================================================================ + */ + +/* ============================================================================================================================ + AFE + ============================================================================================================================ + */ +#define REG_AFE_AFECON_RESET 0x00080000 /* Reset Value for AFECON */ +#define REG_AFE_AFECON 0x00002000 /* AFE AFE Configuration */ +#define REG_AFE_SEQCON_RESET 0x00000002 /* Reset Value for SEQCON */ +#define REG_AFE_SEQCON 0x00002004 /* AFE Sequencer Configuration */ +#define REG_AFE_FIFOCON_RESET 0x00001010 /* Reset Value for FIFOCON */ +#define REG_AFE_FIFOCON 0x00002008 /* AFE FIFOs Configuration */ +#define REG_AFE_SWCON_RESET 0x0000FFFF /* Reset Value for SWCON */ +#define REG_AFE_SWCON 0x0000200C /* AFE Switch Matrix Configuration */ +#define REG_AFE_HSDACCON_RESET 0x0000001E /* Reset Value for HSDACCON */ +#define REG_AFE_HSDACCON 0x00002010 /* AFE High Speed DAC Configuration */ +#define REG_AFE_WGCON_RESET 0x00000030 /* Reset Value for WGCON */ +#define REG_AFE_WGCON 0x00002014 /* AFE Waveform Generator Configuration */ +#define REG_AFE_WGDCLEVEL1_RESET \ + 0x00000000 /* Reset Value for WGDCLEVEL1 */ +#define REG_AFE_WGDCLEVEL1 \ + 0x00002018 /* AFE Waveform Generator - Trapezoid DC Level 1 */ +#define REG_AFE_WGDCLEVEL2_RESET \ + 0x00000000 /* Reset Value for WGDCLEVEL2 */ +#define REG_AFE_WGDCLEVEL2 \ + 0x0000201C /* AFE Waveform Generator - Trapezoid DC Level 2 */ +#define REG_AFE_WGDELAY1_RESET 0x00000000 /* Reset Value for WGDELAY1 */ +#define REG_AFE_WGDELAY1 \ + 0x00002020 /* AFE Waveform Generator - Trapezoid Delay 1 Time */ +#define REG_AFE_WGSLOPE1_RESET 0x00000000 /* Reset Value for WGSLOPE1 */ +#define REG_AFE_WGSLOPE1 \ + 0x00002024 /* AFE Waveform Generator - Trapezoid Slope 1 Time */ +#define REG_AFE_WGDELAY2_RESET 0x00000000 /* Reset Value for WGDELAY2 */ +#define REG_AFE_WGDELAY2 \ + 0x00002028 /* AFE Waveform Generator - Trapezoid Delay 2 Time */ +#define REG_AFE_WGSLOPE2_RESET 0x00000000 /* Reset Value for WGSLOPE2 */ +#define REG_AFE_WGSLOPE2 \ + 0x0000202C /* AFE Waveform Generator - Trapezoid Slope 2 Time */ +#define REG_AFE_WGFCW_RESET 0x00000000 /* Reset Value for WGFCW */ +#define REG_AFE_WGFCW \ + 0x00002030 /* AFE Waveform Generator - Sinusoid Frequency Control Word */ +#define REG_AFE_WGPHASE_RESET 0x00000000 /* Reset Value for WGPHASE */ +#define REG_AFE_WGPHASE \ + 0x00002034 /* AFE Waveform Generator - Sinusoid Phase Offset */ +#define REG_AFE_WGOFFSET_RESET 0x00000000 /* Reset Value for WGOFFSET */ +#define REG_AFE_WGOFFSET \ + 0x00002038 /* AFE Waveform Generator - Sinusoid Offset */ +#define REG_AFE_WGAMPLITUDE_RESET \ + 0x00000000 /* Reset Value for WGAMPLITUDE */ +#define REG_AFE_WGAMPLITUDE \ + 0x0000203C /* AFE Waveform Generator - Sinusoid Amplitude */ +#define REG_AFE_ADCFILTERCON_RESET \ + 0x00000301 /* Reset Value for ADCFILTERCON */ +#define REG_AFE_ADCFILTERCON \ + 0x00002044 /* AFE ADC Output Filters Configuration */ +#define REG_AFE_HSDACDAT_RESET 0x00000800 /* Reset Value for HSDACDAT */ +#define REG_AFE_HSDACDAT 0x00002048 /* AFE HS DAC Code */ +#define REG_AFE_LPREFBUFCON_RESET \ + 0x00000000 /* Reset Value for LPREFBUFCON */ +#define REG_AFE_LPREFBUFCON 0x00002050 /* AFE LPREF_BUF_CON */ +#define REG_AFE_SYNCEXTDEVICE_RESET \ + 0x00000000 /* Reset Value for SYNCEXTDEVICE */ +#define REG_AFE_SYNCEXTDEVICE 0x00002054 /* AFE SYNC External Devices */ +#define REG_AFE_SEQCRC_RESET 0x00000001 /* Reset Value for SEQCRC */ +#define REG_AFE_SEQCRC 0x00002060 /* AFE Sequencer CRC Value */ +#define REG_AFE_SEQCNT_RESET 0x00000000 /* Reset Value for SEQCNT */ +#define REG_AFE_SEQCNT 0x00002064 /* AFE Sequencer Command Count */ +#define REG_AFE_SEQTIMEOUT_RESET \ + 0x00000000 /* Reset Value for SEQTIMEOUT */ +#define REG_AFE_SEQTIMEOUT 0x00002068 /* AFE Sequencer Timeout Counter */ +#define REG_AFE_DATAFIFORD_RESET \ + 0x00000000 /* Reset Value for DATAFIFORD */ +#define REG_AFE_DATAFIFORD 0x0000206C /* AFE Data FIFO Read */ +#define REG_AFE_CMDFIFOWRITE_RESET \ + 0x00000000 /* Reset Value for CMDFIFOWRITE */ +#define REG_AFE_CMDFIFOWRITE 0x00002070 /* AFE Command FIFO Write */ +#define REG_AFE_ADCDAT_RESET 0x00000000 /* Reset Value for ADCDAT */ +#define REG_AFE_ADCDAT 0x00002074 /* AFE ADC Raw Result */ +#define REG_AFE_DFTREAL_RESET 0x00000000 /* Reset Value for DFTREAL */ +#define REG_AFE_DFTREAL 0x00002078 /* AFE DFT Result, Real Part */ +#define REG_AFE_DFTIMAG_RESET 0x00000000 /* Reset Value for DFTIMAG */ +#define REG_AFE_DFTIMAG 0x0000207C /* AFE DFT Result, Imaginary Part */ +#define REG_AFE_SINC2DAT_RESET 0x00000000 /* Reset Value for SINC2DAT */ +#define REG_AFE_SINC2DAT 0x00002080 /* AFE Supply Rejection Filter Result */ +#define REG_AFE_TEMPSENSDAT_RESET \ + 0x00000000 /* Reset Value for TEMPSENSDAT */ +#define REG_AFE_TEMPSENSDAT 0x00002084 /* AFE Temperature Sensor Result */ +#define REG_AFE_AFEGENINTSTA_RESET \ + 0x00000000 /* Reset Value for AFEGENINTSTA */ +#define REG_AFE_AFEGENINTSTA 0x0000209C /* AFE Analog Generation Interrupt */ +#define REG_AFE_ADCMIN_RESET 0x00000000 /* Reset Value for ADCMIN */ +#define REG_AFE_ADCMIN 0x000020A8 /* AFE ADC Minimum Value Check */ +#define REG_AFE_ADCMINSM_RESET 0x00000000 /* Reset Value for ADCMINSM */ +#define REG_AFE_ADCMINSM 0x000020AC /* AFE ADCMIN Hysteresis Value */ +#define REG_AFE_ADCMAX_RESET 0x00000000 /* Reset Value for ADCMAX */ +#define REG_AFE_ADCMAX 0x000020B0 /* AFE ADC Maximum Value Check */ +#define REG_AFE_ADCMAXSMEN_RESET \ + 0x00000000 /* Reset Value for ADCMAXSMEN */ +#define REG_AFE_ADCMAXSMEN 0x000020B4 /* AFE ADCMAX Hysteresis Value */ +#define REG_AFE_ADCDELTA_RESET 0x00000000 /* Reset Value for ADCDELTA */ +#define REG_AFE_ADCDELTA 0x000020B8 /* AFE ADC Delta Value */ +#define REG_AFE_HPOSCCON_RESET 0x00000024 /* Reset Value for HPOSCCON */ +#define REG_AFE_HPOSCCON 0x000020BC /* AFE HPOSC Configuration */ +#define REG_AFE_DFTCON_RESET 0x00000090 /* Reset Value for DFTCON */ +#define REG_AFE_DFTCON 0x000020D0 /* AFE AFE DSP Configuration */ +#define REG_AFE_LPTIASW1 \ + 0x000020E0 /* AFE ULPTIA Switch Configuration for Channel 1 */ +#define REG_AFE_LPTIASW0_RESET 0x00000000 /* Reset Value for LPTIASW0 */ +#define REG_AFE_LPTIACON1 0x000020E8 /* AFE ULPTIA Control Bits Channel 1 */ +#define REG_AFE_LPTIASW0 \ + 0x000020E4 /* AFE ULPTIA Switch Configuration for Channel 0 */ +#define REG_AFE_LPTIACON0_RESET \ + 0x00000003 /* Reset Value for LPTIACON0 \ + */ +#define REG_AFE_LPTIACON0 0x000020EC /* AFE ULPTIA Control Bits Channel 0 */ +#define REG_AFE_HSRTIACON_RESET \ + 0x0000000F /* Reset Value for HSRTIACON \ + */ +#define REG_AFE_HSRTIACON 0x000020F0 /* AFE High Power RTIA Configuration */ +#define REG_AFE_DE1RESCON \ + 0x000020F4 /* AFE DE1 HSTIA Resistors Configuration */ +#define REG_AFE_DE0RESCON_RESET \ + 0x000000FF /* Reset Value for DE0RESCON \ + */ +#define REG_AFE_DE0RESCON \ + 0x000020F8 /* AFE DE0 HSTIA Resistors Configuration */ +#define REG_AFE_HSTIACON_RESET 0x00000000 /* Reset Value for HSTIACON */ +#define REG_AFE_HSTIACON 0x000020FC /* AFE HSTIA Amplifier Configuration */ +#define REG_AFE_LPMODEKEY_RESET \ + 0x00000000 /* Reset Value for LPMODEKEY \ + */ +#define REG_AFE_LPMODEKEY 0x0000210C /* AFE LP Mode AFE Control Lock */ +#define REG_AFE_LPMODECLKSEL_RESET \ + 0x00000000 /* Reset Value for LPMODECLKSEL */ +#define REG_AFE_LPMODECLKSEL 0x00002110 /* AFE LFSYSCLKEN */ +#define REG_AFE_LPMODECON_RESET \ + 0x00000102 /* Reset Value for LPMODECON \ + */ +#define REG_AFE_LPMODECON 0x00002114 /* AFE LPMODECON */ +#define REG_AFE_SEQSLPLOCK_RESET \ + 0x00000000 /* Reset Value for SEQSLPLOCK */ +#define REG_AFE_SEQSLPLOCK 0x00002118 /* AFE Sequencer Sleep Control Lock */ +#define REG_AFE_SEQTRGSLP_RESET \ + 0x00000000 /* Reset Value for SEQTRGSLP \ + */ +#define REG_AFE_SEQTRGSLP 0x0000211C /* AFE Sequencer Trigger Sleep */ +#define REG_AFE_LPDACDAT0_RESET \ + 0x00000000 /* Reset Value for LPDACDAT0 \ + */ +#define REG_AFE_LPDACDAT0 0x00002120 /* AFE LPDAC Data-out */ +#define REG_AFE_LPDACSW0_RESET 0x00000000 /* Reset Value for LPDACSW0 */ +#define REG_AFE_LPDACSW0 0x00002124 /* AFE LPDAC0 Switch Control */ +#define REG_AFE_LPDACCON0_RESET \ + 0x00000002 /* Reset Value for LPDACCON0 \ + */ +#define REG_AFE_LPDACCON0 0x00002128 /* AFE LPDAC Control Bits */ +#define REG_AFE_LPDACDAT1 0x0000212C /* AFE Low Power DAC1 data register */ +#define REG_AFE_LPDACSW1 \ + 0x00002130 /* AFE Control register for switches to LPDAC1 */ +#define REG_AFE_LPDACCON1 0x00002134 /* AFE ULP_DACCON1 */ +#define REG_AFE_DSWFULLCON_RESET \ + 0x00000000 /* Reset Value for DSWFULLCON */ +#define REG_AFE_DSWFULLCON \ + 0x00002150 /* AFE Switch Matrix Full Configuration (D) */ +#define REG_AFE_NSWFULLCON_RESET \ + 0x00000000 /* Reset Value for NSWFULLCON */ +#define REG_AFE_NSWFULLCON \ + 0x00002154 /* AFE Switch Matrix Full Configuration (N) */ +#define REG_AFE_PSWFULLCON_RESET \ + 0x00000000 /* Reset Value for PSWFULLCON */ +#define REG_AFE_PSWFULLCON \ + 0x00002158 /* AFE Switch Matrix Full Configuration (P) */ +#define REG_AFE_TSWFULLCON_RESET \ + 0x00000000 /* Reset Value for TSWFULLCON */ +#define REG_AFE_TSWFULLCON \ + 0x0000215C /* AFE Switch Matrix Full Configuration (T) */ +#define REG_AFE_TEMPSENS_RESET 0x00000000 /* Reset Value for TEMPSENS */ +#define REG_AFE_TEMPSENS 0x00002174 /* AFE Temp Sensor Configuration */ +#define REG_AFE_BUFSENCON_RESET \ + 0x00000037 /* Reset Value for BUFSENCON \ + */ +#define REG_AFE_BUFSENCON 0x00002180 /* AFE HP and LP Buffer Control */ +#define REG_AFE_ADCCON_RESET 0x00000000 /* Reset Value for ADCCON */ +#define REG_AFE_ADCCON 0x000021A8 /* AFE ADC Configuration */ +#define REG_AFE_DSWSTA_RESET 0x00000000 /* Reset Value for DSWSTA */ +#define REG_AFE_DSWSTA 0x000021B0 /* AFE Switch Matrix Status (D) */ +#define REG_AFE_PSWSTA_RESET 0x00006000 /* Reset Value for PSWSTA */ +#define REG_AFE_PSWSTA 0x000021B4 /* AFE Switch Matrix Status (P) */ +#define REG_AFE_NSWSTA_RESET 0x00000C00 /* Reset Value for NSWSTA */ +#define REG_AFE_NSWSTA 0x000021B8 /* AFE Switch Matrix Status (N) */ +#define REG_AFE_TSWSTA_RESET 0x00000000 /* Reset Value for TSWSTA */ +#define REG_AFE_TSWSTA 0x000021BC /* AFE Switch Matrix Status (T) */ +#define REG_AFE_STATSVAR_RESET 0x00000000 /* Reset Value for STATSVAR */ +#define REG_AFE_STATSVAR 0x000021C0 /* AFE Variance Output */ +#define REG_AFE_STATSCON_RESET 0x00000000 /* Reset Value for STATSCON */ +#define REG_AFE_STATSCON 0x000021C4 /* AFE Statistics Control */ +#define REG_AFE_STATSMEAN_RESET \ + 0x00000000 /* Reset Value for STATSMEAN \ + */ +#define REG_AFE_STATSMEAN 0x000021C8 /* AFE Statistics Mean Output */ +#define REG_AFE_SEQ0INFO_RESET 0x00000000 /* Reset Value for SEQ0INFO */ +#define REG_AFE_SEQ0INFO 0x000021CC /* AFE Sequence 0 Info */ +#define REG_AFE_SEQ2INFO_RESET 0x00000000 /* Reset Value for SEQ2INFO */ +#define REG_AFE_SEQ2INFO 0x000021D0 /* AFE Sequence 2 Info */ +#define REG_AFE_CMDFIFOWADDR_RESET \ + 0x00000000 /* Reset Value for CMDFIFOWADDR */ +#define REG_AFE_CMDFIFOWADDR 0x000021D4 /* AFE Command FIFO Write Address */ +#define REG_AFE_CMDDATACON_RESET \ + 0x00000410 /* Reset Value for CMDDATACON */ +#define REG_AFE_CMDDATACON 0x000021D8 /* AFE Command Data Control */ +#define REG_AFE_DATAFIFOTHRES_RESET \ + 0x00000000 /* Reset Value for DATAFIFOTHRES */ +#define REG_AFE_DATAFIFOTHRES 0x000021E0 /* AFE Data FIFO Threshold */ +#define REG_AFE_SEQ3INFO_RESET 0x00000000 /* Reset Value for SEQ3INFO */ +#define REG_AFE_SEQ3INFO 0x000021E4 /* AFE Sequence 3 Info */ +#define REG_AFE_SEQ1INFO_RESET 0x00000000 /* Reset Value for SEQ1INFO */ +#define REG_AFE_SEQ1INFO 0x000021E8 /* AFE Sequence 1 Info */ +#define REG_AFE_REPEATADCCNV_RESET \ + 0x00000160 /* Reset Value for REPEATADCCNV */ +#define REG_AFE_REPEATADCCNV 0x000021F0 /* AFE REPEAT ADC Conversions */ +#define REG_AFE_FIFOCNTSTA_RESET \ + 0x00000000 /* Reset Value for FIFOCNTSTA */ +#define REG_AFE_FIFOCNTSTA \ + 0x00002200 /* AFE CMD and DATA FIFO INTERNAL DATA COUNT */ +#define REG_AFE_CALDATLOCK_RESET \ + 0x00000000 /* Reset Value for CALDATLOCK */ +#define REG_AFE_CALDATLOCK 0x00002230 /* AFE Calibration Data Lock */ +#define REG_AFE_ADCOFFSETHSTIA_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETHSTIA */ +#define REG_AFE_ADCOFFSETHSTIA \ + 0x00002234 /* AFE ADC Offset Calibration High Speed TIA Channel */ +#define REG_AFE_ADCGAINTEMPSENS0_RESET \ + 0x00004000 /* Reset Value for ADCGAINTEMPSENS0 */ +#define REG_AFE_ADCGAINTEMPSENS0 \ + 0x00002238 /* AFE ADC Gain Calibration Temp Sensor Channel */ +#define REG_AFE_ADCOFFSETTEMPSENS0_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETTEMPSENS0 */ +#define REG_AFE_ADCOFFSETTEMPSENS0 \ + 0x0000223C /* AFE ADC Offset Calibration Temp Sensor Channel 0 */ +#define REG_AFE_ADCGAINGN1_RESET \ + 0x00004000 /* Reset Value for ADCGAINGN1 */ +#define REG_AFE_ADCGAINGN1 \ + 0x00002240 /* AFE ADCPGAGN1: ADC Gain Calibration Auxiliary Input Channel \ + */ +#define REG_AFE_ADCOFFSETGN1_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETGN1 */ +#define REG_AFE_ADCOFFSETGN1 \ + 0x00002244 /* AFE ADC Offset Calibration Auxiliary Channel (PGA Gain=1) */ +#define REG_AFE_DACGAIN_RESET 0x00000800 /* Reset Value for DACGAIN */ +#define REG_AFE_DACGAIN 0x00002260 /* AFE DACGAIN */ +#define REG_AFE_DACOFFSETATTEN_RESET \ + 0x00000000 /* Reset Value for DACOFFSETATTEN */ +#define REG_AFE_DACOFFSETATTEN \ + 0x00002264 /* AFE DAC Offset with Attenuator Enabled (LP Mode) */ +#define REG_AFE_DACOFFSET_RESET \ + 0x00000000 /* Reset Value for DACOFFSET \ + */ +#define REG_AFE_DACOFFSET \ + 0x00002268 /* AFE DAC Offset with Attenuator Disabled (LP Mode) */ +#define REG_AFE_ADCGAINGN1P5_RESET \ + 0x00004000 /* Reset Value for ADCGAINGN1P5 */ +#define REG_AFE_ADCGAINGN1P5 \ + 0x00002270 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA \ + Gain=1.5) */ +#define REG_AFE_ADCGAINGN2_RESET \ + 0x00004000 /* Reset Value for ADCGAINGN2 */ +#define REG_AFE_ADCGAINGN2 \ + 0x00002274 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=2) \ + */ +#define REG_AFE_ADCGAINGN4_RESET \ + 0x00004000 /* Reset Value for ADCGAINGN4 */ +#define REG_AFE_ADCGAINGN4 \ + 0x00002278 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=4) \ + */ +#define REG_AFE_ADCPGAOFFSETCANCEL_RESET \ + 0x00000000 /* Reset Value for ADCPGAOFFSETCANCEL */ +#define REG_AFE_ADCPGAOFFSETCANCEL \ + 0x00002280 /* AFE ADC Offset Cancellation (Optional) */ +#define REG_AFE_ADCGNHSTIA_RESET \ + 0x00004000 /* Reset Value for ADCGNHSTIA */ +#define REG_AFE_ADCGNHSTIA \ + 0x00002284 /* AFE ADC Gain Calibration for HS TIA Channel */ +#define REG_AFE_ADCOFFSETLPTIA0_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETLPTIA0 */ +#define REG_AFE_ADCOFFSETLPTIA0 \ + 0x00002288 /* AFE ADC Offset Calibration ULP-TIA0 Channel */ +#define REG_AFE_ADCGNLPTIA0_RESET \ + 0x00004000 /* Reset Value for ADCGNLPTIA0 */ +#define REG_AFE_ADCGNLPTIA0 \ + 0x0000228C /* AFE ADC GAIN Calibration for LP TIA0 Channel */ +#define REG_AFE_ADCPGAGN4OFCAL_RESET \ + 0x00004000 /* Reset Value for ADCPGAGN4OFCAL */ +#define REG_AFE_ADCPGAGN4OFCAL \ + 0x00002294 /* AFE ADC Gain Calibration with DC Cancellation(PGA G=4) */ +#define REG_AFE_ADCGAINGN9_RESET \ + 0x00004000 /* Reset Value for ADCGAINGN9 */ +#define REG_AFE_ADCGAINGN9 \ + 0x00002298 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=9) \ + */ +#define REG_AFE_ADCOFFSETEMPSENS1_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETEMPSENS1 */ +#define REG_AFE_ADCOFFSETEMPSENS1 \ + 0x000022A8 /* AFE ADC Offset Calibration Temp Sensor Channel 1 */ +#define REG_AFE_ADCGAINDIOTEMPSENS_RESET \ + 0x00004000 /* Reset Value for ADCGAINDIOTEMPSENS */ +#define REG_AFE_ADCGAINDIOTEMPSENS \ + 0x000022AC /* AFE ADC Gain Calibration Diode Temperature Sensor Channel */ +#define REG_AFE_DACOFFSETATTENHP_RESET \ + 0x00000000 /* Reset Value for DACOFFSETATTENHP */ +#define REG_AFE_DACOFFSETATTENHP \ + 0x000022B8 /* AFE DAC Offset with Attenuator Enabled (HP Mode) */ +#define REG_AFE_DACOFFSETHP_RESET \ + 0x00000000 /* Reset Value for DACOFFSETHP */ +#define REG_AFE_DACOFFSETHP \ + 0x000022BC /* AFE DAC Offset with Attenuator Disabled (HP Mode) */ +#define REG_AFE_ADCGNLPTIA1_RESET \ + 0x00004000 /* Reset Value for ADCGNLPTIA1 */ +#define REG_AFE_ADCOFFSETLPTIA1 \ + 0x000022C0 /* AFE ADC Offset Calibration ULP-TIA0 Channel */ +#define REG_AFE_ADCGNLPTIA1 \ + 0x000022C4 /* AFE ADC GAIN Calibration for LP TIA1 Channel */ +#define REG_AFE_ADCOFFSETGN2_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETGN2 */ +#define REG_AFE_ADCOFFSETGN2 \ + 0x000022C8 /* AFE Offset Calibration Auxiliary Channel (PGA Gain =2) */ +#define REG_AFE_ADCOFFSETGN1P5_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETGN1P5 */ +#define REG_AFE_ADCOFFSETGN1P5 \ + 0x000022CC /* AFE Offset Calibration Auxiliary Channel (PGA Gain =1.5) */ +#define REG_AFE_ADCOFFSETGN9_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETGN9 */ +#define REG_AFE_ADCOFFSETGN9 \ + 0x000022D0 /* AFE Offset Calibration Auxiliary Channel (PGA Gain =9) */ +#define REG_AFE_ADCOFFSETGN4_RESET \ + 0x00000000 /* Reset Value for ADCOFFSETGN4 */ +#define REG_AFE_ADCOFFSETGN4 \ + 0x000022D4 /* AFE Offset Calibration Auxiliary Channel (PGA Gain =4) */ +#define REG_AFE_PMBW_RESET 0x00088800 /* Reset Value for PMBW */ +#define REG_AFE_PMBW 0x000022F0 /* AFE Power Mode Configuration */ +#define REG_AFE_SWMUX_RESET 0x00000000 /* Reset Value for SWMUX */ +#define REG_AFE_SWMUX 0x0000235C /* AFE Switch Mux for ECG */ +#define REG_AFE_AFE_TEMPSEN_DIO_RESET \ + 0x00020000 /* Reset Value for AFE_TEMPSEN_DIO */ +#define REG_AFE_AFE_TEMPSEN_DIO 0x00002374 /* AFE AFE_TEMPSEN_DIO */ +#define REG_AFE_ADCBUFCON_RESET \ + 0x005F3D00 /* Reset Value for ADCBUFCON \ + */ +#define REG_AFE_ADCBUFCON 0x0000238C /* AFE Configure ADC Input Buffer */ + +/* ============================================================================================================================ + AFE Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_AFECON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_AFECON_DACBUFEN 21 /* Enable DC DAC Buffer */ +#define BITP_AFE_AFECON_DACREFEN 20 /* High Speed DAC Reference Enable */ +#define BITP_AFE_AFECON_ALDOILIMITEN \ + 19 /* Analog LDO Current Limiting Enable */ +#define BITP_AFE_AFECON_SINC2EN 16 /* ADC Output 50/60Hz Filter Enable */ +#define BITP_AFE_AFECON_DFTEN 15 /* DFT Hardware Accelerator Enable */ +#define BITP_AFE_AFECON_WAVEGENEN 14 /* Waveform Generator Enable */ +#define BITP_AFE_AFECON_TEMPCONVEN 13 /* ADC Temp Sensor Convert Enable */ +#define BITP_AFE_AFECON_TEMPSENSEN \ + 12 /* ADC Temperature Sensor Channel Enable */ +#define BITP_AFE_AFECON_TIAEN 11 /* High Power TIA Enable */ +#define BITP_AFE_AFECON_INAMPEN 10 /* Enable Excitation Amplifier */ +#define BITP_AFE_AFECON_EXBUFEN 9 /* Enable Excitation Buffer */ +#define BITP_AFE_AFECON_ADCCONVEN 8 /* ADC Conversion Start Enable */ +#define BITP_AFE_AFECON_ADCEN 7 /* ADC Power Enable */ +#define BITP_AFE_AFECON_DACEN 6 /* High Power DAC Enable */ +#define BITP_AFE_AFECON_HPREFDIS 5 /* Disable High Power Reference */ +#define BITM_AFE_AFECON_DACBUFEN 0x00200000 /* Enable DC DAC Buffer */ +#define BITM_AFE_AFECON_DACREFEN \ + 0x00100000 /* High Speed DAC Reference Enable */ +#define BITM_AFE_AFECON_ALDOILIMITEN \ + 0x00080000 /* Analog LDO Current Limiting Enable */ +#define BITM_AFE_AFECON_SINC2EN \ + 0x00010000 /* ADC Output 50/60Hz Filter Enable */ +#define BITM_AFE_AFECON_DFTEN \ + 0x00008000 /* DFT Hardware Accelerator Enable \ + */ +#define BITM_AFE_AFECON_WAVEGENEN 0x00004000 /* Waveform Generator Enable */ +#define BITM_AFE_AFECON_TEMPCONVEN \ + 0x00002000 /* ADC Temp Sensor Convert Enable */ +#define BITM_AFE_AFECON_TEMPSENSEN \ + 0x00001000 /* ADC Temperature Sensor Channel Enable */ +#define BITM_AFE_AFECON_TIAEN 0x00000800 /* High Power TIA Enable */ +#define BITM_AFE_AFECON_INAMPEN 0x00000400 /* Enable Excitation Amplifier */ +#define BITM_AFE_AFECON_EXBUFEN 0x00000200 /* Enable Excitation Buffer */ +#define BITM_AFE_AFECON_ADCCONVEN \ + 0x00000100 /* ADC Conversion Start Enable \ + */ +#define BITM_AFE_AFECON_ADCEN 0x00000080 /* ADC Power Enable */ +#define BITM_AFE_AFECON_DACEN 0x00000040 /* High Power DAC Enable */ +#define BITM_AFE_AFECON_HPREFDIS \ + 0x00000020 /* Disable High Power Reference \ + */ +#define ENUM_AFE_AFECON_OFF 0x00000000 /* DACEN: High Power DAC Disabled */ +#define ENUM_AFE_AFECON_ON 0x00000040 /* DACEN: High Power DAC Enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQCON_SEQWRTMR 8 /* Timer for Sequencer Write Commands */ +#define BITP_AFE_SEQCON_SEQHALT 4 /* Halt Seq */ +#define BITP_AFE_SEQCON_SEQHALTFIFOEMPTY 1 /* Halt Sequencer If Empty */ +#define BITP_AFE_SEQCON_SEQEN 0 /* Enable Sequencer */ +#define BITM_AFE_SEQCON_SEQWRTMR \ + 0x0000FF00 /* Timer for Sequencer Write Commands */ +#define BITM_AFE_SEQCON_SEQHALT 0x00000010 /* Halt Seq */ +#define BITM_AFE_SEQCON_SEQHALTFIFOEMPTY \ + 0x00000002 /* Halt Sequencer If Empty */ +#define BITM_AFE_SEQCON_SEQEN 0x00000001 /* Enable Sequencer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_FIFOCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_FIFOCON_DATAFIFOSRCSEL \ + 13 /* Selects the Source for the Data FIFO. */ +#define BITP_AFE_FIFOCON_DATAFIFOEN 11 /* Data FIFO Enable. */ +#define BITM_AFE_FIFOCON_DATAFIFOSRCSEL \ + 0x0000E000 /* Selects the Source for the Data FIFO. */ +#define BITM_AFE_FIFOCON_DATAFIFOEN 0x00000800 /* Data FIFO Enable. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SWCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SWCON_T11CON 19 /* Control of T[11] */ +#define BITP_AFE_SWCON_T10CON 18 /* Control of T[10] */ +#define BITP_AFE_SWCON_T9CON 17 /* Control of T[9] */ +#define BITP_AFE_SWCON_SWSOURCESEL 16 /* Switch Control Select */ +#define BITP_AFE_SWCON_TMUXCON 12 /* Control of T Switch MUX. */ +#define BITP_AFE_SWCON_NMUXCON 8 /* Control of N Switch MUX */ +#define BITP_AFE_SWCON_PMUXCON 4 /* Control of P Switch MUX */ +#define BITP_AFE_SWCON_DMUXCON 0 /* Control of D Switch MUX */ +#define BITM_AFE_SWCON_T11CON 0x00080000 /* Control of T[11] */ +#define BITM_AFE_SWCON_T10CON 0x00040000 /* Control of T[10] */ +#define BITM_AFE_SWCON_T9CON 0x00020000 /* Control of T[9] */ +#define BITM_AFE_SWCON_SWSOURCESEL 0x00010000 /* Switch Control Select */ +#define BITM_AFE_SWCON_TMUXCON 0x0000F000 /* Control of T Switch MUX. */ +#define BITM_AFE_SWCON_NMUXCON 0x00000F00 /* Control of N Switch MUX */ +#define BITM_AFE_SWCON_PMUXCON 0x000000F0 /* Control of P Switch MUX */ +#define BITM_AFE_SWCON_DMUXCON 0x0000000F /* Control of D Switch MUX */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSDACCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_HSDACCON_INAMPGNMDE \ + 12 /* Excitation Amplifier Gain Control \ + */ +#define BITP_AFE_HSDACCON_RATE 1 /* DAC Update Rate */ +#define BITP_AFE_HSDACCON_ATTENEN 0 /* PGA Stage Gain Attenuation */ +#define BITM_AFE_HSDACCON_INAMPGNMDE \ + 0x00001000 /* Excitation Amplifier Gain Control */ +#define BITM_AFE_HSDACCON_RATE 0x000001FE /* DAC Update Rate */ +#define BITM_AFE_HSDACCON_ATTENEN 0x00000001 /* PGA Stage Gain Attenuation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGCON_DACGAINCAL 5 /* Bypass DAC Gain */ +#define BITP_AFE_WGCON_DACOFFSETCAL 4 /* Bypass DAC Offset */ +#define BITP_AFE_WGCON_TYPESEL 1 /* Selects the Type of Waveform */ +#define BITP_AFE_WGCON_TRAPRSTEN \ + 0 /* Resets the Trapezoid Waveform Generator */ +#define BITM_AFE_WGCON_DACGAINCAL 0x00000020 /* Bypass DAC Gain */ +#define BITM_AFE_WGCON_DACOFFSETCAL 0x00000010 /* Bypass DAC Offset */ +#define BITM_AFE_WGCON_TYPESEL 0x00000006 /* Selects the Type of Waveform */ +#define BITM_AFE_WGCON_TRAPRSTEN \ + 0x00000001 /* Resets the Trapezoid Waveform Generator */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDCLEVEL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGDCLEVEL1_TRAPDCLEVEL1 \ + 0 /* DC Level 1 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDCLEVEL1_TRAPDCLEVEL1 \ + 0x00000FFF /* DC Level 1 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDCLEVEL2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGDCLEVEL2_TRAPDCLEVEL2 \ + 0 /* DC Level 2 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDCLEVEL2_TRAPDCLEVEL2 \ + 0x00000FFF /* DC Level 2 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDELAY1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGDELAY1_DELAY1 \ + 0 /* Delay 1 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDELAY1_DELAY1 \ + 0x000FFFFF /* Delay 1 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGSLOPE1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGSLOPE1_SLOPE1 \ + 0 /* Slope 1 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGSLOPE1_SLOPE1 \ + 0x000FFFFF /* Slope 1 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGDELAY2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGDELAY2_DELAY2 \ + 0 /* Delay 2 Value for Trapezoid Waveform Generation */ +#define BITM_AFE_WGDELAY2_DELAY2 \ + 0x000FFFFF /* Delay 2 Value for Trapezoid Waveform Generation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGSLOPE2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGSLOPE2_SLOPE2 \ + 0 /* Slope 2 Value for Trapezoid Waveform Generation. */ +#define BITM_AFE_WGSLOPE2_SLOPE2 \ + 0x000FFFFF /* Slope 2 Value for Trapezoid Waveform Generation. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGFCW Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGFCW_SINEFCW \ + 0 /* Sinusoid Generator Frequency Control Word */ +#define BITM_AFE_WGFCW_SINEFCW \ + 0x00FFFFFF /* Sinusoid Generator Frequency Control Word */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGPHASE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGPHASE_SINEOFFSET 0 /* Sinusoid Phase Offset */ +#define BITM_AFE_WGPHASE_SINEOFFSET 0x000FFFFF /* Sinusoid Phase Offset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGOFFSET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGOFFSET_SINEOFFSET 0 /* Sinusoid Offset */ +#define BITM_AFE_WGOFFSET_SINEOFFSET 0x00000FFF /* Sinusoid Offset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_WGAMPLITUDE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_WGAMPLITUDE_SINEAMPLITUDE 0 /* Sinusoid Amplitude */ +#define BITM_AFE_WGAMPLITUDE_SINEAMPLITUDE \ + 0x000007FF /* Sinusoid Amplitude \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCFILTERCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCFILTERCON_AVRGNUM 14 /* Number of Samples Averaged */ +#define BITP_AFE_ADCFILTERCON_SINC3OSR 12 /* SINC3 OSR */ +#define BITP_AFE_ADCFILTERCON_SINC2OSR 8 /* SINC2 OSR */ +#define BITP_AFE_ADCFILTERCON_AVRGEN 7 /* Average Function Enable */ +#define BITP_AFE_ADCFILTERCON_SINC3BYP 6 /* SINC3 Filter Bypass */ +#define BITP_AFE_ADCFILTERCON_LPFBYPEN 4 /* 50/60Hz Low Pass Filter */ +#define BITP_AFE_ADCFILTERCON_ADCCLK 0 /* ADC Data Rate */ +#define BITM_AFE_ADCFILTERCON_AVRGNUM \ + 0x0000C000 /* Number of Samples Averaged */ +#define BITM_AFE_ADCFILTERCON_SINC3OSR 0x00003000 /* SINC3 OSR */ +#define BITM_AFE_ADCFILTERCON_SINC2OSR 0x00000F00 /* SINC2 OSR */ +#define BITM_AFE_ADCFILTERCON_AVRGEN 0x00000080 /* Average Function Enable */ +#define BITM_AFE_ADCFILTERCON_SINC3BYP 0x00000040 /* SINC3 Filter Bypass */ +#define BITM_AFE_ADCFILTERCON_LPFBYPEN \ + 0x00000010 /* 50/60Hz Low Pass Filter \ + */ +#define BITM_AFE_ADCFILTERCON_ADCCLK 0x00000001 /* ADC Data Rate */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSDACDAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_HSDACDAT_DACDAT 0 /* DAC Code */ +#define BITM_AFE_HSDACDAT_DACDAT 0x00000FFF /* DAC Code */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPREFBUFCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPREFBUFCON_BOOSTCURRENT \ + 2 /* Set: Drive 2 Dac ;Unset Drive 1 Dac, and Save Power */ +#define BITP_AFE_LPREFBUFCON_LPBUF2P5DIS \ + 1 /* Low Power Bandgap's Output Buffer */ +#define BITP_AFE_LPREFBUFCON_LPREFDIS \ + 0 /* Set This Bit Will Power Down Low Power Bandgap */ +#define BITM_AFE_LPREFBUFCON_BOOSTCURRENT \ + 0x00000004 /* Set: Drive 2 Dac ;Unset Drive 1 Dac, and Save Power */ +#define BITM_AFE_LPREFBUFCON_LPBUF2P5DIS \ + 0x00000002 /* Low Power Bandgap's Output Buffer */ +#define BITM_AFE_LPREFBUFCON_LPREFDIS \ + 0x00000001 /* Set This Bit Will Power Down Low Power Bandgap */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SYNCEXTDEVICE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SYNCEXTDEVICE_SYNC 0 /* As Output Data of GPIO */ +#define BITM_AFE_SYNCEXTDEVICE_SYNC 0x000000FF /* As Output Data of GPIO */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQCRC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQCRC_CRC 0 /* Sequencer Command CRC Value. */ +#define BITM_AFE_SEQCRC_CRC 0x000000FF /* Sequencer Command CRC Value. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQCNT_COUNT 0 /* Sequencer Command Count */ +#define BITM_AFE_SEQCNT_COUNT 0x0000FFFF /* Sequencer Command Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQTIMEOUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQTIMEOUT_TIMEOUT \ + 0 /* Current Value of the Sequencer Timeout Counter. */ +#define BITM_AFE_SEQTIMEOUT_TIMEOUT \ + 0x3FFFFFFF /* Current Value of the Sequencer Timeout Counter. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DATAFIFORD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DATAFIFORD_DATAFIFOOUT 0 /* Data FIFO Read */ +#define BITM_AFE_DATAFIFORD_DATAFIFOOUT 0x0000FFFF /* Data FIFO Read */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CMDFIFOWRITE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_CMDFIFOWRITE_CMDFIFOIN 0 /* Command FIFO Write. */ +#define BITM_AFE_CMDFIFOWRITE_CMDFIFOIN 0xFFFFFFFF /* Command FIFO Write. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCDAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCDAT_DATA 0 /* ADC Result */ +#define BITM_AFE_ADCDAT_DATA 0x0000FFFF /* ADC Result */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DFTREAL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DFTREAL_DATA 0 /* DFT Real */ +#define BITM_AFE_DFTREAL_DATA 0x0003FFFF /* DFT Real */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DFTIMAG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DFTIMAG_DATA 0 /* DFT Imaginary */ +#define BITM_AFE_DFTIMAG_DATA 0x0003FFFF /* DFT Imaginary */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SINC2DAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SINC2DAT_DATA 0 /* LPF Result */ +#define BITM_AFE_SINC2DAT_DATA 0x0000FFFF /* LPF Result */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TEMPSENSDAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_TEMPSENSDAT_DATA 0 /* Temp Sensor */ +#define BITM_AFE_TEMPSENSDAT_DATA 0x0000FFFF /* Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_AFEGENINTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ3 3 /* Custom IRQ 3. */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ2 2 /* Custom IRQ 2 */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ1 1 /* Custom IRQ 1. */ +#define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ0 0 /* Custom IRQ 0 */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ3 0x00000008 /* Custom IRQ 3. */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ2 0x00000004 /* Custom IRQ 2 */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ1 0x00000002 /* Custom IRQ 1. */ +#define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ0 0x00000001 /* Custom IRQ 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMIN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCMIN_MINVAL 0 /* ADC Minimum Value Threshold */ +#define BITM_AFE_ADCMIN_MINVAL 0x0000FFFF /* ADC Minimum Value Threshold */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMINSM Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCMINSM_MINCLRVAL 0 /* ADCMIN Hysteresis Value */ +#define BITM_AFE_ADCMINSM_MINCLRVAL 0x0000FFFF /* ADCMIN Hysteresis Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMAX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCMAX_MAXVAL 0 /* ADC Max Threshold */ +#define BITM_AFE_ADCMAX_MAXVAL 0x0000FFFF /* ADC Max Threshold */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCMAXSMEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCMAXSMEN_MAXSWEN 0 /* ADCMAX Hysteresis Value */ +#define BITM_AFE_ADCMAXSMEN_MAXSWEN 0x0000FFFF /* ADCMAX Hysteresis Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCDELTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCDELTA_DELTAVAL \ + 0 /* ADCDAT Code Differences Limit Option \ + */ +#define BITM_AFE_ADCDELTA_DELTAVAL \ + 0x0000FFFF /* ADCDAT Code Differences Limit Option */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HPOSCCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_HPOSCCON_CLK32MHZEN 2 /* 16M/32M Output Selector Signal. */ +#define BITM_AFE_HPOSCCON_CLK32MHZEN \ + 0x00000004 /* 16M/32M Output Selector Signal. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DFTCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DFTCON_DFTINSEL 20 /* DFT Input Select */ +#define BITP_AFE_DFTCON_DFTNUM 4 /* ADC Samples Used */ +#define BITP_AFE_DFTCON_HANNINGEN 0 /* Hanning Window Enable */ +#define BITM_AFE_DFTCON_DFTINSEL 0x00300000 /* DFT Input Select */ +#define BITM_AFE_DFTCON_DFTNUM 0x000000F0 /* ADC Samples Used */ +#define BITM_AFE_DFTCON_HANNINGEN 0x00000001 /* Hanning Window Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIASW1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPTIASW1_TIABIASSEL 13 /* TIA SW13 Control. Active High */ +#define BITP_AFE_LPTIASW1_PABIASSEL 12 /* TIA SW12 Control. Active High */ +#define BITP_AFE_LPTIASW1_TIASWCON 0 /* TIA SW[11:0] Control */ +#define BITM_AFE_LPTIASW1_TIABIASSEL \ + (_ADI_MSK_3(0x00002000, 0x00002000UL, \ + uint32_t)) /* TIA SW13 Control. Active High */ +#define BITM_AFE_LPTIASW1_PABIASSEL \ + (_ADI_MSK_3(0x00001000, 0x00001000UL, \ + uint32_t)) /* TIA SW12 Control. Active High */ +#define BITM_AFE_LPTIASW1_TIASWCON \ + (_ADI_MSK_3(0x00000FFF, 0x00000FFFUL, uint32_t)) /* TIA SW[11:0] Control */ +#define ENUM_AFE_LPTIASW1_CAPA_LP \ + (_ADI_MSK_3(0x00000014, 0x00000014UL, \ + uint32_t)) /* TIASWCON: CAPA test with LP TIA */ +#define ENUM_AFE_LPTIASW1_NORM \ + (_ADI_MSK_3(0x0000002C, 0x0000002CUL, \ + uint32_t)) /* TIASWCON: Normal work mode */ +#define ENUM_AFE_LPTIASW1_DIO \ + (_ADI_MSK_3(0x0000002D, 0x0000002DUL, \ + uint32_t)) /* TIASWCON: Normal work mode with back-back diode \ + enabled. */ +#define ENUM_AFE_LPTIASW1_SHORTSW \ + (_ADI_MSK_3( \ + 0x0000002E, 0x0000002EUL, \ + uint32_t)) /* TIASWCON: Work mode with short switch protection */ +#define ENUM_AFE_LPTIASW1_LOWNOISE \ + (_ADI_MSK_3(0x0000006C, 0x0000006CUL, \ + uint32_t)) /* TIASWCON: Work mode, vzero-vbias=0. */ +#define ENUM_AFE_LPTIASW1_CAPA_RAMP_H \ + (_ADI_MSK_3(0x00000094, 0x00000094UL, \ + uint32_t)) /* TIASWCON: CAPA test or Ramp test with HP TIA */ +#define ENUM_AFE_LPTIASW1_BUFDIS \ + (_ADI_MSK_3(0x00000180, 0x00000180UL, \ + uint32_t)) /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW1_BUFEN \ + (_ADI_MSK_3(0x000001A4, 0x000001A4UL, \ + uint32_t)) /* TIASWCON: Set PA/TIA as unity gain buffer. \ + Connect amp's output to CE1 & RC11. */ +#define ENUM_AFE_LPTIASW1_TWOLEAD \ + (_ADI_MSK_3(0x0000042C, 0x0000042CUL, \ + uint32_t)) /* TIASWCON: Two lead sensor, set PA as unity gain \ + buffer. */ +#define ENUM_AFE_LPTIASW1_BUFEN2 \ + (_ADI_MSK_3(0x000004A4, 0x000004A4UL, \ + uint32_t)) /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW1_SESHORTRE \ + (_ADI_MSK_3(0x00000800, 0x00000800UL, \ + uint32_t)) /* TIASWCON: Close SW11 - Short SE1 to RE1, */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIASW0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPTIASW0_RECAL 15 /* TIA SW15 Control. Active High */ +#define BITP_AFE_LPTIASW0_VZEROSHARE 14 /* TIA SW14 Control. Active High */ +#define BITP_AFE_LPTIASW0_TIABIASSEL 13 /* TIA SW13 Control. Active High */ +#define BITP_AFE_LPTIASW0_PABIASSEL 12 /* TIA SW12 Control. Active High */ +#define BITP_AFE_LPTIASW0_TIASWCON 0 /* TIA SW[11:0] Control */ +#define BITM_AFE_LPTIASW0_RECAL \ + 0x00008000 /* TIA SW15 Control. Active High \ + */ +#define BITM_AFE_LPTIASW0_VZEROSHARE \ + 0x00004000 /* TIA SW14 Control. Active High */ +#define BITM_AFE_LPTIASW0_TIABIASSEL \ + 0x00002000 /* TIA SW13 Control. Active High */ +#define BITM_AFE_LPTIASW0_PABIASSEL \ + 0x00001000 /* TIA SW12 Control. Active High */ +#define BITM_AFE_LPTIASW0_TIASWCON 0x00000FFF /* TIA SW[11:0] Control */ +#define ENUM_AFE_LPTIASW0_11 0x00000014 /* TIASWCON: CAPA test with LP TIA */ +#define ENUM_AFE_LPTIASW0_NORM 0x0000002C /* TIASWCON: Normal work mode */ +#define ENUM_AFE_LPTIASW0_DIO \ + 0x0000002D /* TIASWCON: Normal work mode with back-back diode enabled. */ +#define ENUM_AFE_LPTIASW0_SHORTSW \ + 0x0000002E /* TIASWCON: Work mode with short switch protection */ +#define ENUM_AFE_LPTIASW0_LOWNOISE \ + 0x0000006C /* TIASWCON: Work mode, vzero-vbias=0. */ +#define ENUM_AFE_LPTIASW0_1 \ + 0x00000094 /* TIASWCON: CAPA test or Ramp test with HP TIA */ +#define ENUM_AFE_LPTIASW0_BUFDIS \ + 0x00000180 /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW0_BUFEN \ + 0x000001A4 /* TIASWCON: Set PA/TIA as unity gain buffer. Connect amp's \ + output to CE0 & RC01. */ +#define ENUM_AFE_LPTIASW0_TWOLEAD \ + 0x0000042C /* TIASWCON: Two lead sensor, set PA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW0_BUFEN2 \ + 0x000004A4 /* TIASWCON: Set PA/TIA as unity gain buffer. */ +#define ENUM_AFE_LPTIASW0_SESHORTRE \ + 0x00000800 /* TIASWCON: Close SW11 - Short SE0 to RE0. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIACON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPTIACON1_CHOPEN 16 /* Chopping Enable */ +#define BITP_AFE_LPTIACON1_TIARF 13 /* Set LPF Resistor */ +#define BITP_AFE_LPTIACON1_TIARL 10 /* Set RLOAD */ +#define BITP_AFE_LPTIACON1_TIAGAIN 5 /* Set RTIA Gain Resistor */ +#define BITP_AFE_LPTIACON1_IBOOST 3 /* Current Boost Control */ +#define BITP_AFE_LPTIACON1_HALFPWR 2 /* Half Power Mode Select */ +#define BITP_AFE_LPTIACON1_PAPDEN 1 /* PA Power Down */ +#define BITP_AFE_LPTIACON1_TIAPDEN 0 /* TIA Power Down */ +#define BITM_AFE_LPTIACON1_CHOPEN \ + (_ADI_MSK_3(0x00030000, 0x00030000UL, uint32_t)) /* Chopping Enable */ +#define BITM_AFE_LPTIACON1_TIARF \ + (_ADI_MSK_3(0x0000E000, 0x0000E000UL, uint32_t)) /* Set LPF Resistor */ +#define BITM_AFE_LPTIACON1_TIARL \ + (_ADI_MSK_3(0x00001C00, 0x00001C00UL, uint32_t)) /* Set RLOAD */ +#define BITM_AFE_LPTIACON1_TIAGAIN \ + (_ADI_MSK_3(0x000003E0, 0x000003E0UL, uint32_t)) /* Set RTIA Gain Resistor \ + */ +#define BITM_AFE_LPTIACON1_IBOOST \ + (_ADI_MSK_3(0x00000018, 0x00000018UL, uint32_t)) /* Current Boost Control \ + */ +#define BITM_AFE_LPTIACON1_HALFPWR \ + (_ADI_MSK_3(0x00000004, 0x00000004UL, uint32_t)) /* Half Power Mode Select \ + */ +#define BITM_AFE_LPTIACON1_PAPDEN \ + (_ADI_MSK_3(0x00000002, 0x00000002UL, uint32_t)) /* PA Power Down */ +#define BITM_AFE_LPTIACON1_TIAPDEN \ + (_ADI_MSK_3(0x00000001, 0x00000001UL, uint32_t)) /* TIA Power Down */ +#define ENUM_AFE_LPTIACON1_DISCONRF \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, \ + uint32_t)) /* TIARF: Disconnect TIA output from LPF pin */ +#define ENUM_AFE_LPTIACON1_BYPRF \ + (_ADI_MSK_3(0x00002000, 0x00002000UL, uint32_t)) /* TIARF: Bypass resistor \ + */ +#define ENUM_AFE_LPTIACON1_RF20K \ + (_ADI_MSK_3(0x00004000, 0x00004000UL, uint32_t)) /* TIARF: 20k Ohm */ +#define ENUM_AFE_LPTIACON1_RF100K \ + (_ADI_MSK_3(0x00006000, 0x00006000UL, uint32_t)) /* TIARF: 100k Ohm */ +#define ENUM_AFE_LPTIACON1_RF200K \ + (_ADI_MSK_3(0x00008000, 0x00008000UL, uint32_t)) /* TIARF: 200k Ohm */ +#define ENUM_AFE_LPTIACON1_RF400K \ + (_ADI_MSK_3(0x0000A000, 0x0000A000UL, uint32_t)) /* TIARF: 400k Ohm */ +#define ENUM_AFE_LPTIACON1_RF600K \ + (_ADI_MSK_3(0x0000C000, 0x0000C000UL, uint32_t)) /* TIARF: 600k Ohm */ +#define ENUM_AFE_LPTIACON1_RF1MOHM \ + (_ADI_MSK_3(0x0000E000, 0x0000E000UL, uint32_t)) /* TIARF: 1Meg Ohm */ +#define ENUM_AFE_LPTIACON1_RL0 \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, uint32_t)) /* TIARL: 0 ohm */ +#define ENUM_AFE_LPTIACON1_RL10 \ + (_ADI_MSK_3(0x00000400, 0x00000400UL, uint32_t)) /* TIARL: 10 ohm */ +#define ENUM_AFE_LPTIACON1_RL30 \ + (_ADI_MSK_3(0x00000800, 0x00000800UL, uint32_t)) /* TIARL: 30 ohm */ +#define ENUM_AFE_LPTIACON1_RL50 \ + (_ADI_MSK_3(0x00000C00, 0x00000C00UL, uint32_t)) /* TIARL: 50 ohm */ +#define ENUM_AFE_LPTIACON1_RL100 \ + (_ADI_MSK_3(0x00001000, 0x00001000UL, uint32_t)) /* TIARL: 100 ohm */ +#define ENUM_AFE_LPTIACON1_RL1P6K \ + (_ADI_MSK_3(0x00001400, 0x00001400UL, uint32_t)) /* TIARL: 1.6kohm */ +#define ENUM_AFE_LPTIACON1_RL3P1K \ + (_ADI_MSK_3(0x00001800, 0x00001800UL, uint32_t)) /* TIARL: 3.1kohm */ +#define ENUM_AFE_LPTIACON1_RL3P5K \ + (_ADI_MSK_3(0x00001C00, 0x00001C00UL, uint32_t)) /* TIARL: 3.6kohm */ +#define ENUM_AFE_LPTIACON1_DISCONTIA \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, \ + uint32_t)) /* TIAGAIN: Disconnect TIA Gain resistor */ +#define ENUM_AFE_LPTIACON1_TIAGAIN200 \ + (_ADI_MSK_3(0x00000020, 0x00000020UL, uint32_t)) /* TIAGAIN: 200 Ohm */ +#define ENUM_AFE_LPTIACON1_TIAGAIN1K \ + (_ADI_MSK_3(0x00000040, 0x00000040UL, uint32_t)) /* TIAGAIN: 1k ohm */ +#define ENUM_AFE_LPTIACON1_TIAGAIN2K \ + (_ADI_MSK_3(0x00000060, 0x00000060UL, uint32_t)) /* TIAGAIN: 2k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN3K \ + (_ADI_MSK_3(0x00000080, 0x00000080UL, uint32_t)) /* TIAGAIN: 3k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN4K \ + (_ADI_MSK_3(0x000000A0, 0x000000A0UL, uint32_t)) /* TIAGAIN: 4k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN6K \ + (_ADI_MSK_3(0x000000C0, 0x000000C0UL, uint32_t)) /* TIAGAIN: 6k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN8K \ + (_ADI_MSK_3(0x000000E0, 0x000000E0UL, uint32_t)) /* TIAGAIN: 8k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN10K \ + (_ADI_MSK_3(0x00000100, 0x00000100UL, uint32_t)) /* TIAGAIN: 10k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN12K \ + (_ADI_MSK_3(0x00000120, 0x00000120UL, uint32_t)) /* TIAGAIN: 12k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN16K \ + (_ADI_MSK_3(0x00000140, 0x00000140UL, uint32_t)) /* TIAGAIN: 16k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN20K \ + (_ADI_MSK_3(0x00000160, 0x00000160UL, uint32_t)) /* TIAGAIN: 20k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN24K \ + (_ADI_MSK_3(0x00000180, 0x00000180UL, uint32_t)) /* TIAGAIN: 24k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN30K \ + (_ADI_MSK_3(0x000001A0, 0x000001A0UL, uint32_t)) /* TIAGAIN: 30k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN32K \ + (_ADI_MSK_3(0x000001C0, 0x000001C0UL, uint32_t)) /* TIAGAIN: 32k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN40K \ + (_ADI_MSK_3(0x000001E0, 0x000001E0UL, uint32_t)) /* TIAGAIN: 40k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN48K \ + (_ADI_MSK_3(0x00000200, 0x00000200UL, uint32_t)) /* TIAGAIN: 48k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN64K \ + (_ADI_MSK_3(0x00000220, 0x00000220UL, uint32_t)) /* TIAGAIN: 64k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN85K \ + (_ADI_MSK_3(0x00000240, 0x00000240UL, uint32_t)) /* TIAGAIN: 85k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN96K \ + (_ADI_MSK_3(0x00000260, 0x00000260UL, uint32_t)) /* TIAGAIN: 96k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN100K \ + (_ADI_MSK_3(0x00000280, 0x00000280UL, uint32_t)) /* TIAGAIN: 100k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN120K \ + (_ADI_MSK_3(0x000002A0, 0x000002A0UL, uint32_t)) /* TIAGAIN: 120k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN128K \ + (_ADI_MSK_3(0x000002C0, 0x000002C0UL, uint32_t)) /* TIAGAIN: 128k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN160K \ + (_ADI_MSK_3(0x000002E0, 0x000002E0UL, uint32_t)) /* TIAGAIN: 160k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN196K \ + (_ADI_MSK_3(0x00000300, 0x00000300UL, uint32_t)) /* TIAGAIN: 196k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN256K \ + (_ADI_MSK_3(0x00000320, 0x00000320UL, uint32_t)) /* TIAGAIN: 256k */ +#define ENUM_AFE_LPTIACON1_TIAGAIN512K \ + (_ADI_MSK_3(0x00000340, 0x00000340UL, uint32_t)) /* TIAGAIN: 512k */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPTIACON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPTIACON0_CHOPEN 16 /* Chopping Enable */ +#define BITP_AFE_LPTIACON0_TIARF 13 /* Set LPF Resistor */ +#define BITP_AFE_LPTIACON0_TIARL 10 /* Set RLOAD */ +#define BITP_AFE_LPTIACON0_TIAGAIN 5 /* Set RTIA */ +#define BITP_AFE_LPTIACON0_IBOOST 3 /* Current Boost Control */ +#define BITP_AFE_LPTIACON0_HALFPWR 2 /* Half Power Mode Select */ +#define BITP_AFE_LPTIACON0_PAPDEN 1 /* PA Power Down */ +#define BITP_AFE_LPTIACON0_TIAPDEN 0 /* TIA Power Down */ +#define BITM_AFE_LPTIACON0_CHOPEN 0x00030000 /* Chopping Enable */ +#define BITM_AFE_LPTIACON0_TIARF 0x0000E000 /* Set LPF Resistor */ +#define BITM_AFE_LPTIACON0_TIARL 0x00001C00 /* Set RLOAD */ +#define BITM_AFE_LPTIACON0_TIAGAIN 0x000003E0 /* Set RTIA */ +#define BITM_AFE_LPTIACON0_IBOOST 0x00000018 /* Current Boost Control */ +#define BITM_AFE_LPTIACON0_HALFPWR 0x00000004 /* Half Power Mode Select */ +#define BITM_AFE_LPTIACON0_PAPDEN 0x00000002 /* PA Power Down */ +#define BITM_AFE_LPTIACON0_TIAPDEN 0x00000001 /* TIA Power Down */ +#define ENUM_AFE_LPTIACON0_DISCONRF \ + 0x00000000 /* TIARF: Disconnect TIA output from LPF pin */ +#define ENUM_AFE_LPTIACON0_BYPRF 0x00002000 /* TIARF: Bypass resistor */ +#define ENUM_AFE_LPTIACON0_RF20K 0x00004000 /* TIARF: 20k Ohm */ +#define ENUM_AFE_LPTIACON0_RF100K 0x00006000 /* TIARF: 100k Ohm */ +#define ENUM_AFE_LPTIACON0_RF200K 0x00008000 /* TIARF: 200k Ohm */ +#define ENUM_AFE_LPTIACON0_RF400K 0x0000A000 /* TIARF: 400k Ohm */ +#define ENUM_AFE_LPTIACON0_RF600K 0x0000C000 /* TIARF: 600k Ohm */ +#define ENUM_AFE_LPTIACON0_RF1MOHM 0x0000E000 /* TIARF: 1Meg Ohm */ +#define ENUM_AFE_LPTIACON0_RL0 0x00000000 /* TIARL: 0 ohm */ +#define ENUM_AFE_LPTIACON0_RL10 0x00000400 /* TIARL: 10 ohm */ +#define ENUM_AFE_LPTIACON0_RL30 0x00000800 /* TIARL: 30 ohm */ +#define ENUM_AFE_LPTIACON0_RL50 0x00000C00 /* TIARL: 50 ohm */ +#define ENUM_AFE_LPTIACON0_RL100 0x00001000 /* TIARL: 100 ohm */ +#define ENUM_AFE_LPTIACON0_RL1P6K 0x00001400 /* TIARL: 1.6kohm */ +#define ENUM_AFE_LPTIACON0_RL3P1K 0x00001800 /* TIARL: 3.1kohm */ +#define ENUM_AFE_LPTIACON0_RL3P5K 0x00001C00 /* TIARL: 3.6kohm */ +#define ENUM_AFE_LPTIACON0_DISCONTIA \ + 0x00000000 /* TIAGAIN: Disconnect TIA Gain resistor */ +#define ENUM_AFE_LPTIACON0_TIAGAIN200 0x00000020 /* TIAGAIN: 200 Ohm */ +#define ENUM_AFE_LPTIACON0_TIAGAIN1K 0x00000040 /* TIAGAIN: 1k ohm */ +#define ENUM_AFE_LPTIACON0_TIAGAIN2K 0x00000060 /* TIAGAIN: 2k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN3K 0x00000080 /* TIAGAIN: 3k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN4K 0x000000A0 /* TIAGAIN: 4k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN6K 0x000000C0 /* TIAGAIN: 6k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN8K 0x000000E0 /* TIAGAIN: 8k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN10K 0x00000100 /* TIAGAIN: 10k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN12K 0x00000120 /* TIAGAIN: 12k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN16K 0x00000140 /* TIAGAIN: 16k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN20K 0x00000160 /* TIAGAIN: 20k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN24K 0x00000180 /* TIAGAIN: 24k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN30K 0x000001A0 /* TIAGAIN: 30k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN32K 0x000001C0 /* TIAGAIN: 32k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN40K 0x000001E0 /* TIAGAIN: 40k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN48K 0x00000200 /* TIAGAIN: 48k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN64K 0x00000220 /* TIAGAIN: 64k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN85K 0x00000240 /* TIAGAIN: 85k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN96K 0x00000260 /* TIAGAIN: 96k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN100K 0x00000280 /* TIAGAIN: 100k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN120K 0x000002A0 /* TIAGAIN: 120k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN128K 0x000002C0 /* TIAGAIN: 128k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN160K 0x000002E0 /* TIAGAIN: 160k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN196K 0x00000300 /* TIAGAIN: 196k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN256K 0x00000320 /* TIAGAIN: 256k */ +#define ENUM_AFE_LPTIACON0_TIAGAIN512K 0x00000340 /* TIAGAIN: 512k */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSRTIACON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_HSRTIACON_CTIACON \ + 5 /* Configure Capacitor in Parallel with RTIA */ +#define BITP_AFE_HSRTIACON_TIASW6CON 4 /* SW6 Control */ +#define BITP_AFE_HSRTIACON_RTIACON 0 /* Configure General RTIA Value */ +#define BITM_AFE_HSRTIACON_CTIACON \ + 0x00001FE0 /* Configure Capacitor in Parallel with RTIA */ +#define BITM_AFE_HSRTIACON_TIASW6CON 0x00000010 /* SW6 Control */ +#define BITM_AFE_HSRTIACON_RTIACON \ + 0x0000000F /* Configure General RTIA Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DE1RESCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DE1RESCON_DE1RCON 0 /* DE1 RLOAD RTIA Setting */ +#define BITM_AFE_DE1RESCON_DE1RCON \ + (_ADI_MSK_3(0x000000FF, 0x000000FFUL, uint32_t)) /* DE1 RLOAD RTIA Setting \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DE0RESCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DE0RESCON_DE0RCON 0 /* DE0 RLOAD RTIA Setting */ +#define BITM_AFE_DE0RESCON_DE0RCON 0x000000FF /* DE0 RLOAD RTIA Setting */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_HSTIACON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_HSTIACON_VBIASSEL 0 /* Select HSTIA Positive Input */ +#define BITM_AFE_HSTIACON_VBIASSEL \ + 0x00000003 /* Select HSTIA Positive Input \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACDCBUFCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DACDCBUFCON_CHANSEL 1 /* DAC DC Channel Selection */ +#define BITP_AFE_DACDCBUFCON_RESERVED_0 0 /* Reserved */ +#define BITM_AFE_DACDCBUFCON_CHANSEL \ + (_ADI_MSK_3(0x00000002, 0x00000002UL, \ + uint32_t)) /* DAC DC Channel Selection */ +#define BITM_AFE_DACDCBUFCON_RESERVED_0 \ + (_ADI_MSK_3(0x00000001, 0x00000001UL, uint32_t)) /* Reserved */ +#define ENUM_AFE_DACDCBUFCON_CHAN0 \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, \ + uint32_t)) /* CHANSEL: ULPDAC0 Sets DC level */ +#define ENUM_AFE_DACDCBUFCON_CHAN1 \ + (_ADI_MSK_3(0x00000002, 0x00000002UL, \ + uint32_t)) /* CHANSEL: ULPDAC1 Sets DC level */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPMODEKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPMODEKEY_KEY 0 /* LP Key */ +#define BITM_AFE_LPMODEKEY_KEY 0x000FFFFF /* LP Key */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPMODECLKSEL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPMODECLKSEL_LFSYSCLKEN \ + 0 /* Enable Switching System Clock to 32KHz by Sequencer */ +#define BITM_AFE_LPMODECLKSEL_LFSYSCLKEN \ + 0x00000001 /* Enable Switching System Clock to 32KHz by Sequencer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPMODECON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPMODECON_ALDOEN \ + 8 /* Set High to Power Down of Analog LDO \ + */ +#define BITP_AFE_LPMODECON_V1P1HPADCEN \ + 7 /* Set High to Enable 1.1V HP CM Buffer */ +#define BITP_AFE_LPMODECON_V1P8HPADCEN \ + 6 /* Set High to Enable HP 1.8V Reference Buffer */ +#define BITP_AFE_LPMODECON_PTATEN \ + 5 /* Set to High to Generate Ptat Current Bias */ +#define BITP_AFE_LPMODECON_ZTATEN \ + 4 /* Set High to Generate Ztat Current Bias */ +#define BITP_AFE_LPMODECON_REPEATADCCNVEN_P \ + 3 /* Set High to Enable Repeat ADC Conversion */ +#define BITP_AFE_LPMODECON_ADCCONVEN \ + 2 /* Set High to Enable ADC Conversion \ + */ +#define BITP_AFE_LPMODECON_HPREFDIS \ + 1 /* Set High to Power Down HP Reference \ + */ +#define BITP_AFE_LPMODECON_HFOSCPD \ + 0 /* Set High to Power Down HP Power Oscillator */ +#define BITM_AFE_LPMODECON_ALDOEN \ + 0x00000100 /* Set High to Power Down of Analog LDO */ +#define BITM_AFE_LPMODECON_V1P1HPADCEN \ + 0x00000080 /* Set High to Enable 1.1V HP CM Buffer */ +#define BITM_AFE_LPMODECON_V1P8HPADCEN \ + 0x00000040 /* Set High to Enable HP 1.8V Reference Buffer */ +#define BITM_AFE_LPMODECON_PTATEN \ + 0x00000020 /* Set to High to Generate Ptat Current Bias */ +#define BITM_AFE_LPMODECON_ZTATEN \ + 0x00000010 /* Set High to Generate Ztat Current Bias */ +#define BITM_AFE_LPMODECON_REPEATADCCNVEN_P \ + 0x00000008 /* Set High to Enable Repeat ADC Conversion */ +#define BITM_AFE_LPMODECON_ADCCONVEN \ + 0x00000004 /* Set High to Enable ADC Conversion */ +#define BITM_AFE_LPMODECON_HPREFDIS \ + 0x00000002 /* Set High to Power Down HP Reference */ +#define BITM_AFE_LPMODECON_HFOSCPD \ + 0x00000001 /* Set High to Power Down HP Power Oscillator */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQSLPLOCK Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQSLPLOCK_SEQ_SLP_PW 0 /* Password for SLPBYSEQ Register */ +#define BITM_AFE_SEQSLPLOCK_SEQ_SLP_PW \ + 0x000FFFFF /* Password for SLPBYSEQ Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQTRGSLP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQTRGSLP_TRGSLP 0 /* Trigger Sleep by Sequencer */ +#define BITM_AFE_SEQTRGSLP_TRGSLP 0x00000001 /* Trigger Sleep by Sequencer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACDAT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPDACDAT0_DACIN6 12 /* 6BITVAL, 1LSB=34.375mV */ +#define BITP_AFE_LPDACDAT0_DACIN12 0 /* 12BITVAL, 1LSB=537uV */ +#define BITM_AFE_LPDACDAT0_DACIN6 0x0003F000 /* 6BITVAL, 1LSB=34.375mV */ +#define BITM_AFE_LPDACDAT0_DACIN12 0x00000FFF /* 12BITVAL, 1LSB=537uV */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACSW0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPDACSW0_LPMODEDIS 5 /* Switch Control */ +#define BITP_AFE_LPDACSW0_LPDACSW 0 /* LPDAC0 Switches Matrix */ +#define BITM_AFE_LPDACSW0_LPMODEDIS 0x00000020 /* Switch Control */ +#define BITM_AFE_LPDACSW0_LPDACSW 0x0000001F /* LPDAC0 Switches Matrix */ +#define ENUM_AFE_LPDACSW0_DACCONBIT5 \ + 0x00000000 /* LPMODEDIS: REG_AFE_LPDACDAT0 Switch controlled by \ + REG_AFE_LPDACDAT0CON0 bit 5 */ +#define ENUM_AFE_LPDACSW0_OVRRIDE \ + 0x00000020 /* LPMODEDIS: REG_AFE_LPDACDAT0 Switches override */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACCON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPDACCON0_WAVETYPE 6 /* LPDAC Data Source */ +#define BITP_AFE_LPDACCON0_DACMDE 5 /* LPDAC0 Switch Settings */ +#define BITP_AFE_LPDACCON0_VZEROMUX 4 /* VZERO MUX Select */ +#define BITP_AFE_LPDACCON0_VBIASMUX 3 /* VBIAS MUX Select */ +#define BITP_AFE_LPDACCON0_REFSEL 2 /* Reference Select Bit */ +#define BITP_AFE_LPDACCON0_PWDEN 1 /* LPDAC0 Power Down */ +#define BITP_AFE_LPDACCON0_RSTEN 0 /* Enable Writes to REG_AFE_LPDACDAT00 */ +#define BITM_AFE_LPDACCON0_WAVETYPE 0x00000040 /* LPDAC Data Source */ +#define BITM_AFE_LPDACCON0_DACMDE 0x00000020 /* LPDAC0 Switch Settings */ +#define BITM_AFE_LPDACCON0_VZEROMUX 0x00000010 /* VZERO MUX Select */ +#define BITM_AFE_LPDACCON0_VBIASMUX 0x00000008 /* VBIAS MUX Select */ +#define BITM_AFE_LPDACCON0_REFSEL 0x00000004 /* Reference Select Bit */ +#define BITM_AFE_LPDACCON0_PWDEN 0x00000002 /* LPDAC0 Power Down */ +#define BITM_AFE_LPDACCON0_RSTEN \ + 0x00000001 /* Enable Writes to REG_AFE_LPDACDAT00 */ +#define ENUM_AFE_LPDACCON0_MMR \ + 0x00000000 /* WAVETYPE: Direct from REG_AFE_LPDACDAT0DAT0 */ +#define ENUM_AFE_LPDACCON0_WAVEGEN \ + 0x00000040 /* WAVETYPE: Waveform generator */ +#define ENUM_AFE_LPDACCON0_NORM \ + 0x00000000 /* DACMDE: REG_AFE_LPDACDAT00 switches set for normal mode */ +#define ENUM_AFE_LPDACCON0_DIAG \ + 0x00000020 /* DACMDE: REG_AFE_LPDACDAT00 switches set for Diagnostic mode \ + */ +#define ENUM_AFE_LPDACCON0_BITS6 0x00000000 /* VZEROMUX: VZERO 6BIT */ +#define ENUM_AFE_LPDACCON0_BITS12 0x00000010 /* VZEROMUX: VZERO 12BIT */ +#define ENUM_AFE_LPDACCON0_12BIT 0x00000000 /* VBIASMUX: Output 12Bit */ +#define ENUM_AFE_LPDACCON0_EN 0x00000008 /* VBIASMUX: output 6Bit */ +#define ENUM_AFE_LPDACCON0_ULPREF 0x00000000 /* REFSEL: ULP2P5V Ref */ +#define ENUM_AFE_LPDACCON0_AVDD 0x00000004 /* REFSEL: AVDD Reference */ +#define ENUM_AFE_LPDACCON0_PWREN \ + 0x00000000 /* PWDEN: REG_AFE_LPDACDAT00 Powered On */ +#define ENUM_AFE_LPDACCON0_PWRDIS \ + 0x00000002 /* PWDEN: REG_AFE_LPDACDAT00 Powered Off */ +#define ENUM_AFE_LPDACCON0_WRITEDIS \ + 0x00000000 /* RSTEN: Disable REG_AFE_LPDACDAT00 Writes */ +#define ENUM_AFE_LPDACCON0_WRITEEN \ + 0x00000001 /* RSTEN: Enable REG_AFE_LPDACDAT00 Writes */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACDAT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPDACDAT1_DACIN6 12 /* 6BITVAL, 1LSB=34.375mV */ +#define BITP_AFE_LPDACDAT1_DACIN12 0 /* 12BITVAL, 1LSB=537uV */ +#define BITM_AFE_LPDACDAT1_DACIN6 \ + (_ADI_MSK_3(0x0003F000, 0x0003F000UL, uint32_t)) /* 6BITVAL, 1LSB=34.375mV \ + */ +#define BITM_AFE_LPDACDAT1_DACIN12 \ + (_ADI_MSK_3(0x00000FFF, 0x00000FFFUL, uint32_t)) /* 12BITVAL, 1LSB=537uV */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACSW1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPDACSW1_LPMODEDIS 5 /* Switch Control */ +#define BITP_AFE_LPDACSW1_LPDACSW 0 /* ULPDAC0 Switches Matrix */ +#define BITM_AFE_LPDACSW1_LPMODEDIS \ + (_ADI_MSK_3(0x00000020, 0x00000020UL, uint32_t)) /* Switch Control */ +#define BITM_AFE_LPDACSW1_LPDACSW \ + (_ADI_MSK_3(0x0000001F, 0x0000001FUL, \ + uint32_t)) /* ULPDAC0 Switches Matrix */ +#define ENUM_AFE_LPDACSW1_DACCONBIT5 \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, \ + uint32_t)) /* LPMODEDIS: ULPDAC Switch controlled by ULPDACCON1 \ + bit 5 */ +#define ENUM_AFE_LPDACSW1_OVRRIDE \ + (_ADI_MSK_3(0x00000020, 0x00000020UL, \ + uint32_t)) /* LPMODEDIS: ULPDAC Switches override */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_LPDACCON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_LPDACCON1_WAVETYPE 6 /* DAC Input Source */ +#define BITP_AFE_LPDACCON1_DACMDE 5 /* LPDAC1 Switch Settings */ +#define BITP_AFE_LPDACCON1_VZEROMUX 4 /* VZEROOUT */ +#define BITP_AFE_LPDACCON1_VBIASMUX 3 /* BITSEL */ +#define BITP_AFE_LPDACCON1_REFSEL 2 /* REFSEL */ +#define BITP_AFE_LPDACCON1_PWDEN 1 /* ULPDAC0 Power */ +#define BITP_AFE_LPDACCON1_RSTEN 0 /* Enable Writes to ULPDAC1 */ +#define BITM_AFE_LPDACCON1_WAVETYPE \ + (_ADI_MSK_3(0x00000040, 0x00000040UL, uint32_t)) /* DAC Input Source */ +#define BITM_AFE_LPDACCON1_DACMDE \ + (_ADI_MSK_3(0x00000020, 0x00000020UL, uint32_t)) /* LPDAC1 Switch Settings \ + */ +#define BITM_AFE_LPDACCON1_VZEROMUX \ + (_ADI_MSK_3(0x00000010, 0x00000010UL, uint32_t)) /* VZEROOUT */ +#define BITM_AFE_LPDACCON1_VBIASMUX \ + (_ADI_MSK_3(0x00000008, 0x00000008UL, uint32_t)) /* BITSEL */ +#define BITM_AFE_LPDACCON1_REFSEL \ + (_ADI_MSK_3(0x00000004, 0x00000004UL, uint32_t)) /* REFSEL */ +#define BITM_AFE_LPDACCON1_PWDEN \ + (_ADI_MSK_3(0x00000002, 0x00000002UL, uint32_t)) /* ULPDAC0 Power */ +#define BITM_AFE_LPDACCON1_RSTEN \ + (_ADI_MSK_3(0x00000001, 0x00000001UL, \ + uint32_t)) /* Enable Writes to ULPDAC1 */ +#define ENUM_AFE_LPDACCON1_NORM \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, \ + uint32_t)) /* DACMDE: ULPDAC1 switches set for normal mode */ +#define ENUM_AFE_LPDACCON1_DIAG \ + (_ADI_MSK_3( \ + 0x00000020, 0x00000020UL, \ + uint32_t)) /* DACMDE: ULPDAC1 switches set for Diagnostic mode */ +#define ENUM_AFE_LPDACCON1_BITS6 \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, uint32_t)) /* VZEROMUX: VZERO 6BIT */ +#define ENUM_AFE_LPDACCON1_BITS12 \ + (_ADI_MSK_3(0x00000010, 0x00000010UL, uint32_t)) /* VZEROMUX: VZERO 12BIT \ + */ +#define ENUM_AFE_LPDACCON1_DIS \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, uint32_t)) /* VBIASMUX: 12BIT Output \ + */ +#define ENUM_AFE_LPDACCON1_EN \ + (_ADI_MSK_3(0x00000008, 0x00000008UL, uint32_t)) /* VBIASMUX: 6BIT Output \ + */ +#define ENUM_AFE_LPDACCON1_ULPREF \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, uint32_t)) +#define ENUM_AFE_LPDACCON1_AVDD (_ADI_MSK_3(0x00000004, 0x00000004UL, uint32_t)) +#define ENUM_AFE_LPDACCON1_PWREN \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, \ + uint32_t)) /* PWDEN: ULPDAC1 Powered On */ +#define ENUM_AFE_LPDACCON1_PWRDIS \ + (_ADI_MSK_3(0x00000002, 0x00000002UL, \ + uint32_t)) /* PWDEN: ULPDAC1 Powered Off */ +#define ENUM_AFE_LPDACCON1_WRITEDIS \ + (_ADI_MSK_3(0x00000000, 0x00000000UL, \ + uint32_t)) /* RSTEN: Disable ULPDAC1 Writes */ +#define ENUM_AFE_LPDACCON1_WRITEEN \ + (_ADI_MSK_3(0x00000001, 0x00000001UL, \ + uint32_t)) /* RSTEN: Enable ULPDAC1 Writes */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DSWFULLCON_D8 7 /* Control of D8 Switch. */ +#define BITP_AFE_DSWFULLCON_D7 6 /* Control of D7 Switch. */ +#define BITP_AFE_DSWFULLCON_D6 5 /* Control of D6 Switch. */ +#define BITP_AFE_DSWFULLCON_D5 4 /* Control of D5 Switch. */ +#define BITP_AFE_DSWFULLCON_D4 3 /* Control of D4 Switch. */ +#define BITP_AFE_DSWFULLCON_D3 2 /* Control of D3 Switch. */ +#define BITP_AFE_DSWFULLCON_D2 1 /* Control of D2 Switch. */ +#define BITP_AFE_DSWFULLCON_DR0 0 /* Control of Dr0 Switch. */ +#define BITM_AFE_DSWFULLCON_D8 0x00000080 /* Control of D8 Switch. */ +#define BITM_AFE_DSWFULLCON_D7 0x00000040 /* Control of D7 Switch. */ +#define BITM_AFE_DSWFULLCON_D6 0x00000020 /* Control of D6 Switch. */ +#define BITM_AFE_DSWFULLCON_D5 0x00000010 /* Control of D5 Switch. */ +#define BITM_AFE_DSWFULLCON_D4 0x00000008 /* Control of D4 Switch. */ +#define BITM_AFE_DSWFULLCON_D3 0x00000004 /* Control of D3 Switch. */ +#define BITM_AFE_DSWFULLCON_D2 0x00000002 /* Control of D2 Switch. */ +#define BITM_AFE_DSWFULLCON_DR0 0x00000001 /* Control of Dr0 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_NSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_NSWFULLCON_NL2 11 /* Control of NL2 Switch. */ +#define BITP_AFE_NSWFULLCON_NL 10 /* Control of NL Switch. */ +#define BITP_AFE_NSWFULLCON_NR1 \ + 9 /* Control of Nr1 Switch. Set Will Close Nr1, Unset Open */ +#define BITP_AFE_NSWFULLCON_N9 \ + 8 /* Control of N9 Switch. Set Will Close N9, Unset Open */ +#define BITP_AFE_NSWFULLCON_N8 \ + 7 /* Control of N8 Switch. Set Will Close N8, Unset Open */ +#define BITP_AFE_NSWFULLCON_N7 \ + 6 /* Control of N7 Switch. Set Will Close N7, Unset Open */ +#define BITP_AFE_NSWFULLCON_N6 \ + 5 /* Control of N6 Switch. Set Will Close N6, Unset Open */ +#define BITP_AFE_NSWFULLCON_N5 \ + 4 /* Control of N5 Switch. Set Will Close N5, Unset Open */ +#define BITP_AFE_NSWFULLCON_N4 \ + 3 /* Control of N4 Switch. Set Will Close N4, Unset Open */ +#define BITP_AFE_NSWFULLCON_N3 \ + 2 /* Control of N3 Switch. Set Will Close N3, Unset Open */ +#define BITP_AFE_NSWFULLCON_N2 \ + 1 /* Control of N2 Switch. Set Will Close N2, Unset Open */ +#define BITP_AFE_NSWFULLCON_N1 \ + 0 /* Control of N1 Switch. Set Will Close N1, Unset Open */ +#define BITM_AFE_NSWFULLCON_NL2 0x00000800 /* Control of NL2 Switch. */ +#define BITM_AFE_NSWFULLCON_NL 0x00000400 /* Control of NL Switch. */ +#define BITM_AFE_NSWFULLCON_NR1 \ + 0x00000200 /* Control of Nr1 Switch. Set Will Close Nr1, Unset Open */ +#define BITM_AFE_NSWFULLCON_N9 \ + 0x00000100 /* Control of N9 Switch. Set Will Close N9, Unset Open */ +#define BITM_AFE_NSWFULLCON_N8 \ + 0x00000080 /* Control of N8 Switch. Set Will Close N8, Unset Open */ +#define BITM_AFE_NSWFULLCON_N7 \ + 0x00000040 /* Control of N7 Switch. Set Will Close N7, Unset Open */ +#define BITM_AFE_NSWFULLCON_N6 \ + 0x00000020 /* Control of N6 Switch. Set Will Close N6, Unset Open */ +#define BITM_AFE_NSWFULLCON_N5 \ + 0x00000010 /* Control of N5 Switch. Set Will Close N5, Unset Open */ +#define BITM_AFE_NSWFULLCON_N4 \ + 0x00000008 /* Control of N4 Switch. Set Will Close N4, Unset Open */ +#define BITM_AFE_NSWFULLCON_N3 \ + 0x00000004 /* Control of N3 Switch. Set Will Close N3, Unset Open */ +#define BITM_AFE_NSWFULLCON_N2 \ + 0x00000002 /* Control of N2 Switch. Set Will Close N2, Unset Open */ +#define BITM_AFE_NSWFULLCON_N1 \ + 0x00000001 /* Control of N1 Switch. Set Will Close N1, Unset Open */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_PSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_PSWFULLCON_PL2 14 /* PL2 Switch Control */ +#define BITP_AFE_PSWFULLCON_PL 13 /* PL Switch Control */ +#define BITP_AFE_PSWFULLCON_P12 \ + 11 /* Control of P12 Switch. Set Will Close P12, Unset Open */ +#define BITP_AFE_PSWFULLCON_P11 \ + 10 /* Control of P11 Switch. Set Will Close P11, Unset Open */ +#define BITP_AFE_PSWFULLCON_P10 9 /* P10 Switch Control */ +#define BITP_AFE_PSWFULLCON_P9 \ + 8 /* Control of P9 Switch. Set Will Close P9, Unset Open */ +#define BITP_AFE_PSWFULLCON_P8 \ + 7 /* Control of P8 Switch. Set Will Close P8, Unset Open */ +#define BITP_AFE_PSWFULLCON_P7 \ + 6 /* Control of P7 Switch. Set Will Close P7, Unset Open */ +#define BITP_AFE_PSWFULLCON_P6 \ + 5 /* Control of P6 Switch. Set Will Close P6, Unset Open */ +#define BITP_AFE_PSWFULLCON_P5 \ + 4 /* Control of P5 Switch. Set Will Close P5, Unset Open */ +#define BITP_AFE_PSWFULLCON_P4 \ + 3 /* Control of P4 Switch. Set Will Close P4, Unset Open */ +#define BITP_AFE_PSWFULLCON_P3 \ + 2 /* Control of P3 Switch. Set Will Close P3, Unset Open */ +#define BITP_AFE_PSWFULLCON_P2 \ + 1 /* Control of P2 Switch. Set Will Close P2, Unset Open */ +#define BITP_AFE_PSWFULLCON_PR0 0 /* PR0 Switch Control */ +#define BITM_AFE_PSWFULLCON_PL2 0x00004000 /* PL2 Switch Control */ +#define BITM_AFE_PSWFULLCON_PL 0x00002000 /* PL Switch Control */ +#define BITM_AFE_PSWFULLCON_P12 \ + 0x00000800 /* Control of P12 Switch. Set Will Close P12, Unset Open */ +#define BITM_AFE_PSWFULLCON_P11 \ + 0x00000400 /* Control of P11 Switch. Set Will Close P11, Unset Open */ +#define BITM_AFE_PSWFULLCON_P10 0x00000200 /* P10 Switch Control */ +#define BITM_AFE_PSWFULLCON_P9 \ + 0x00000100 /* Control of P9 Switch. Set Will Close P9, Unset Open */ +#define BITM_AFE_PSWFULLCON_P8 \ + 0x00000080 /* Control of P8 Switch. Set Will Close P8, Unset Open */ +#define BITM_AFE_PSWFULLCON_P7 \ + 0x00000040 /* Control of P7 Switch. Set Will Close P7, Unset Open */ +#define BITM_AFE_PSWFULLCON_P6 \ + 0x00000020 /* Control of P6 Switch. Set Will Close P6, Unset Open */ +#define BITM_AFE_PSWFULLCON_P5 \ + 0x00000010 /* Control of P5 Switch. Set Will Close P5, Unset Open */ +#define BITM_AFE_PSWFULLCON_P4 \ + 0x00000008 /* Control of P4 Switch. Set Will Close P4, Unset Open */ +#define BITM_AFE_PSWFULLCON_P3 \ + 0x00000004 /* Control of P3 Switch. Set Will Close P3, Unset Open */ +#define BITM_AFE_PSWFULLCON_P2 \ + 0x00000002 /* Control of P2 Switch. Set Will Close P2, Unset Open */ +#define BITM_AFE_PSWFULLCON_PR0 0x00000001 /* PR0 Switch Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TSWFULLCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_TSWFULLCON_TR1 \ + 11 /* Control of Tr1 Switch. Set Will Close Tr1, Unset Open */ +#define BITP_AFE_TSWFULLCON_T11 \ + 10 /* Control of T11 Switch. Set Will Close T11, Unset Open */ +#define BITP_AFE_TSWFULLCON_T10 \ + 9 /* Control of T10 Switch. Set Will Close T10, Unset Open */ +#define BITP_AFE_TSWFULLCON_T9 \ + 8 /* Control of T9 Switch. Set Will Close T9, Unset Open */ +#define BITP_AFE_TSWFULLCON_T7 \ + 6 /* Control of T7 Switch. Set Will Close T7, Unset Open */ +#define BITP_AFE_TSWFULLCON_T5 \ + 4 /* Control of T5 Switch. Set Will Close T5, Unset Open */ +#define BITP_AFE_TSWFULLCON_T4 \ + 3 /* Control of T4 Switch. Set Will Close T4, Unset Open */ +#define BITP_AFE_TSWFULLCON_T3 \ + 2 /* Control of T3 Switch. Set Will Close T3, Unset Open */ +#define BITP_AFE_TSWFULLCON_T2 \ + 1 /* Control of T2 Switch. Set Will Close T2, Unset Open */ +#define BITP_AFE_TSWFULLCON_T1 \ + 0 /* Control of T1 Switch. Set Will Close T1, Unset Open */ +#define BITM_AFE_TSWFULLCON_TR1 \ + 0x00000800 /* Control of Tr1 Switch. Set Will Close Tr1, Unset Open */ +#define BITM_AFE_TSWFULLCON_T11 \ + 0x00000400 /* Control of T11 Switch. Set Will Close T11, Unset Open */ +#define BITM_AFE_TSWFULLCON_T10 \ + 0x00000200 /* Control of T10 Switch. Set Will Close T10, Unset Open */ +#define BITM_AFE_TSWFULLCON_T9 \ + 0x00000100 /* Control of T9 Switch. Set Will Close T9, Unset Open */ +#define BITM_AFE_TSWFULLCON_T7 \ + 0x00000040 /* Control of T7 Switch. Set Will Close T7, Unset Open */ +#define BITM_AFE_TSWFULLCON_T5 \ + 0x00000010 /* Control of T5 Switch. Set Will Close T5, Unset Open */ +#define BITM_AFE_TSWFULLCON_T4 \ + 0x00000008 /* Control of T4 Switch. Set Will Close T4, Unset Open */ +#define BITM_AFE_TSWFULLCON_T3 \ + 0x00000004 /* Control of T3 Switch. Set Will Close T3, Unset Open */ +#define BITM_AFE_TSWFULLCON_T2 \ + 0x00000002 /* Control of T2 Switch. Set Will Close T2, Unset Open */ +#define BITM_AFE_TSWFULLCON_T1 \ + 0x00000001 /* Control of T1 Switch. Set Will Close T1, Unset Open */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TEMPSENS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_TEMPSENS_CHOPFRESEL 2 /* Chop Mode Frequency Setting */ +#define BITP_AFE_TEMPSENS_CHOPCON 1 /* Temp Sensor Chop Mode */ +#define BITP_AFE_TEMPSENS_ENABLE 0 /* Unused */ +#define BITM_AFE_TEMPSENS_CHOPFRESEL \ + 0x0000000C /* Chop Mode Frequency Setting */ +#define BITM_AFE_TEMPSENS_CHOPCON 0x00000002 /* Temp Sensor Chop Mode */ +#define BITM_AFE_TEMPSENS_ENABLE 0x00000001 /* Unused */ +#define ENUM_AFE_TEMPSENS_DIS 0x00000000 /* CHOPCON: Disable chop */ +#define ENUM_AFE_TEMPSENS_EN 0x00000002 /* CHOPCON: Enable chop */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_BUFSENCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_BUFSENCON_V1P8THERMSTEN 8 /* Buffered Reference Output */ +#define BITP_AFE_BUFSENCON_V1P1LPADCCHGDIS \ + 6 /* Controls Decoupling Cap Discharge Switch */ +#define BITP_AFE_BUFSENCON_V1P1LPADCEN 5 /* ADC 1.1V LP Buffer */ +#define BITP_AFE_BUFSENCON_V1P1HPADCEN 4 /* Enable 1.1V HP CM Buffer */ +#define BITP_AFE_BUFSENCON_V1P8HPADCCHGDIS \ + 3 /* Controls Decoupling Cap Discharge Switch */ +#define BITP_AFE_BUFSENCON_V1P8LPADCEN 2 /* ADC 1.8V LP Reference Buffer */ +#define BITP_AFE_BUFSENCON_V1P8HPADCILIMITEN \ + 1 /* HP ADC Input Current Limit \ + */ +#define BITP_AFE_BUFSENCON_V1P8HPADCEN 0 /* HP 1.8V Reference Buffer */ +#define BITM_AFE_BUFSENCON_V1P8THERMSTEN \ + 0x00000100 /* Buffered Reference Output */ +#define BITM_AFE_BUFSENCON_V1P1LPADCCHGDIS \ + 0x00000040 /* Controls Decoupling Cap Discharge Switch */ +#define BITM_AFE_BUFSENCON_V1P1LPADCEN 0x00000020 /* ADC 1.1V LP Buffer */ +#define BITM_AFE_BUFSENCON_V1P1HPADCEN \ + 0x00000010 /* Enable 1.1V HP CM Buffer */ +#define BITM_AFE_BUFSENCON_V1P8HPADCCHGDIS \ + 0x00000008 /* Controls Decoupling Cap Discharge Switch */ +#define BITM_AFE_BUFSENCON_V1P8LPADCEN \ + 0x00000004 /* ADC 1.8V LP Reference Buffer */ +#define BITM_AFE_BUFSENCON_V1P8HPADCILIMITEN \ + 0x00000002 /* HP ADC Input Current Limit */ +#define BITM_AFE_BUFSENCON_V1P8HPADCEN \ + 0x00000001 /* HP 1.8V Reference Buffer */ +#define ENUM_AFE_BUFSENCON_DIS \ + 0x00000000 /* V1P8THERMSTEN: Disable 1.8V Buffered Reference output */ +#define ENUM_AFE_BUFSENCON_EN \ + 0x00000100 /* V1P8THERMSTEN: Enable 1.8V Buffered Reference output */ +#define ENUM_AFE_BUFSENCON_ENCHRG \ + 0x00000000 /* V1P1LPADCCHGDIS: Open switch \ + */ +#define ENUM_AFE_BUFSENCON_DISCHRG \ + 0x00000040 /* V1P1LPADCCHGDIS: Close Switch */ +#define ENUM_AFE_BUFSENCON_DISABLE \ + 0x00000000 /* V1P1LPADCEN: Disable ADC 1.8V LP Reference Buffer */ +#define ENUM_AFE_BUFSENCON_ENABLE \ + 0x00000020 /* V1P1LPADCEN: Enable ADC 1.8V LP Reference Buffer */ +#define ENUM_AFE_BUFSENCON_OFF \ + 0x00000000 /* V1P1HPADCEN: Disable 1.1V HP Common Mode Buffer */ +#define ENUM_AFE_BUFSENCON_ON \ + 0x00000010 /* V1P1HPADCEN: Enable 1.1V HP Common Mode Buffer */ +#define ENUM_AFE_BUFSENCON_OPEN 0x00000000 /* V1P8HPADCCHGDIS: Open switch */ +#define ENUM_AFE_BUFSENCON_CLOSED \ + 0x00000008 /* V1P8HPADCCHGDIS: Close Switch */ +#define ENUM_AFE_BUFSENCON_LPADCREF_DIS \ + 0x00000000 /* V1P8LPADCEN: Disable LP 1.8V Reference Buffer */ +#define ENUM_AFE_BUFSENCON_LPADCREF_EN \ + 0x00000004 /* V1P8LPADCEN: Enable LP 1.8V Reference Buffer */ +#define ENUM_AFE_BUFSENCON_LIMIT_DIS \ + 0x00000000 /* V1P8HPADCILIMITEN: Disable buffer Current Limit */ +#define ENUM_AFE_BUFSENCON_LIMIT_EN \ + 0x00000002 /* V1P8HPADCILIMITEN: Enable buffer Current Limit */ +#define ENUM_AFE_BUFSENCON_HPBUF_DIS \ + 0x00000000 /* V1P8HPADCEN: Disable 1.8V HP ADC Reference Buffer */ +#define ENUM_AFE_BUFSENCON_HPBUF_EN \ + 0x00000001 /* V1P8HPADCEN: Enable 1.8V HP ADC Reference Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCCON_GNPGA 16 /* PGA Gain Setup */ +#define BITP_AFE_ADCCON_GNOFSELPGA 15 /* Internal Offset/Gain Cancellation */ +#define BITP_AFE_ADCCON_GNOFFSEL 13 /* Obsolete */ +#define BITP_AFE_ADCCON_MUXSELN 8 /* Select Negative Input */ +#define BITP_AFE_ADCCON_MUXSELP 0 /* Select Positive Input */ +#define BITM_AFE_ADCCON_GNPGA 0x00070000 /* PGA Gain Setup */ +#define BITM_AFE_ADCCON_GNOFSELPGA \ + 0x00008000 /* Internal Offset/Gain Cancellation */ +#define BITM_AFE_ADCCON_GNOFFSEL 0x00006000 /* Obsolete */ +#define BITM_AFE_ADCCON_MUXSELN 0x00001F00 /* Select Negative Input */ +#define BITM_AFE_ADCCON_MUXSELP 0x0000003F /* Select Positive Input */ +#define ENUM_AFE_ADCCON_RESERVED 0x00000011 /* MUXSELP: Reserved */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DSWSTA_D8STA 7 /* Status of D8 Switch. */ +#define BITP_AFE_DSWSTA_D7STA 6 /* Status of D7 Switch. */ +#define BITP_AFE_DSWSTA_D6STA 5 /* Status of D6 Switch. */ +#define BITP_AFE_DSWSTA_D5STA 4 /* Status of D5 Switch. */ +#define BITP_AFE_DSWSTA_D4STA 3 /* Status of D4 Switch. */ +#define BITP_AFE_DSWSTA_D3STA 2 /* Status of D3 Switch. */ +#define BITP_AFE_DSWSTA_D2STA 1 /* Status of D2 Switch. */ +#define BITP_AFE_DSWSTA_D1STA 0 /* Status of Dr0 Switch. */ +#define BITM_AFE_DSWSTA_D8STA 0x00000080 /* Status of D8 Switch. */ +#define BITM_AFE_DSWSTA_D7STA 0x00000040 /* Status of D7 Switch. */ +#define BITM_AFE_DSWSTA_D6STA 0x00000020 /* Status of D6 Switch. */ +#define BITM_AFE_DSWSTA_D5STA 0x00000010 /* Status of D5 Switch. */ +#define BITM_AFE_DSWSTA_D4STA 0x00000008 /* Status of D4 Switch. */ +#define BITM_AFE_DSWSTA_D3STA 0x00000004 /* Status of D3 Switch. */ +#define BITM_AFE_DSWSTA_D2STA 0x00000002 /* Status of D2 Switch. */ +#define BITM_AFE_DSWSTA_D1STA 0x00000001 /* Status of Dr0 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_PSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_PSWSTA_PL2STA 14 /* PL Switch Control */ +#define BITP_AFE_PSWSTA_PLSTA 13 /* PL Switch Control */ +#define BITP_AFE_PSWSTA_P13STA 12 /* Status of P13 Switch. */ +#define BITP_AFE_PSWSTA_P12STA 11 /* Status of P12 Switch. */ +#define BITP_AFE_PSWSTA_P11STA 10 /* Status of P11 Switch. */ +#define BITP_AFE_PSWSTA_P10STA 9 /* Status of P10 Switch. */ +#define BITP_AFE_PSWSTA_P9STA 8 /* Status of P9 Switch. */ +#define BITP_AFE_PSWSTA_P8STA 7 /* Status of P8 Switch. */ +#define BITP_AFE_PSWSTA_P7STA 6 /* Status of P7 Switch. */ +#define BITP_AFE_PSWSTA_P6STA 5 /* Status of P6 Switch. */ +#define BITP_AFE_PSWSTA_P5STA 4 /* Status of P5 Switch. */ +#define BITP_AFE_PSWSTA_P4STA 3 /* Status of P4 Switch. */ +#define BITP_AFE_PSWSTA_P3STA 2 /* Status of P3 Switch. */ +#define BITP_AFE_PSWSTA_P2STA 1 /* Status of P2 Switch. */ +#define BITP_AFE_PSWSTA_PR0STA 0 /* PR0 Switch Control */ +#define BITM_AFE_PSWSTA_PL2STA 0x00004000 /* PL Switch Control */ +#define BITM_AFE_PSWSTA_PLSTA 0x00002000 /* PL Switch Control */ +#define BITM_AFE_PSWSTA_P13STA 0x00001000 /* Status of P13 Switch. */ +#define BITM_AFE_PSWSTA_P12STA 0x00000800 /* Status of P12 Switch. */ +#define BITM_AFE_PSWSTA_P11STA 0x00000400 /* Status of P11 Switch. */ +#define BITM_AFE_PSWSTA_P10STA 0x00000200 /* Status of P10 Switch. */ +#define BITM_AFE_PSWSTA_P9STA 0x00000100 /* Status of P9 Switch. */ +#define BITM_AFE_PSWSTA_P8STA 0x00000080 /* Status of P8 Switch. */ +#define BITM_AFE_PSWSTA_P7STA 0x00000040 /* Status of P7 Switch. */ +#define BITM_AFE_PSWSTA_P6STA 0x00000020 /* Status of P6 Switch. */ +#define BITM_AFE_PSWSTA_P5STA 0x00000010 /* Status of P5 Switch. */ +#define BITM_AFE_PSWSTA_P4STA 0x00000008 /* Status of P4 Switch. */ +#define BITM_AFE_PSWSTA_P3STA 0x00000004 /* Status of P3 Switch. */ +#define BITM_AFE_PSWSTA_P2STA 0x00000002 /* Status of P2 Switch. */ +#define BITM_AFE_PSWSTA_PR0STA 0x00000001 /* PR0 Switch Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_NSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_NSWSTA_NL2STA 11 /* Status of NL2 Switch. */ +#define BITP_AFE_NSWSTA_NLSTA 10 /* Status of NL Switch. */ +#define BITP_AFE_NSWSTA_NR1STA 9 /* Status of NR1 Switch. */ +#define BITP_AFE_NSWSTA_N9STA 8 /* Status of N9 Switch. */ +#define BITP_AFE_NSWSTA_N8STA 7 /* Status of N8 Switch. */ +#define BITP_AFE_NSWSTA_N7STA 6 /* Status of N7 Switch. */ +#define BITP_AFE_NSWSTA_N6STA 5 /* Status of N6 Switch. */ +#define BITP_AFE_NSWSTA_N5STA 4 /* Status of N5 Switch. */ +#define BITP_AFE_NSWSTA_N4STA 3 /* Status of N4 Switch. */ +#define BITP_AFE_NSWSTA_N3STA 2 /* Status of N3 Switch. */ +#define BITP_AFE_NSWSTA_N2STA 1 /* Status of N2 Switch. */ +#define BITP_AFE_NSWSTA_N1STA 0 /* Status of N1 Switch. */ +#define BITM_AFE_NSWSTA_NL2STA 0x00000800 /* Status of NL2 Switch. */ +#define BITM_AFE_NSWSTA_NLSTA 0x00000400 /* Status of NL Switch. */ +#define BITM_AFE_NSWSTA_NR1STA 0x00000200 /* Status of NR1 Switch. */ +#define BITM_AFE_NSWSTA_N9STA 0x00000100 /* Status of N9 Switch. */ +#define BITM_AFE_NSWSTA_N8STA 0x00000080 /* Status of N8 Switch. */ +#define BITM_AFE_NSWSTA_N7STA 0x00000040 /* Status of N7 Switch. */ +#define BITM_AFE_NSWSTA_N6STA 0x00000020 /* Status of N6 Switch. */ +#define BITM_AFE_NSWSTA_N5STA 0x00000010 /* Status of N5 Switch. */ +#define BITM_AFE_NSWSTA_N4STA 0x00000008 /* Status of N4 Switch. */ +#define BITM_AFE_NSWSTA_N3STA 0x00000004 /* Status of N3 Switch. */ +#define BITM_AFE_NSWSTA_N2STA 0x00000002 /* Status of N2 Switch. */ +#define BITM_AFE_NSWSTA_N1STA 0x00000001 /* Status of N1 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_TSWSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_TSWSTA_TR1STA 11 /* Status of TR1 Switch. */ +#define BITP_AFE_TSWSTA_T11STA 10 /* Status of T11 Switch. */ +#define BITP_AFE_TSWSTA_T10STA 9 /* Status of T10 Switch. */ +#define BITP_AFE_TSWSTA_T9STA 8 /* Status of T9 Switch. */ +#define BITP_AFE_TSWSTA_T8STA 7 /* Status of T8 Switch. */ +#define BITP_AFE_TSWSTA_T7STA 6 /* Status of T7 Switch. */ +#define BITP_AFE_TSWSTA_T6STA 5 /* Status of T6 Switch. */ +#define BITP_AFE_TSWSTA_T5STA 4 /* Status of T5 Switch. */ +#define BITP_AFE_TSWSTA_T4STA 3 /* Status of T4 Switch. */ +#define BITP_AFE_TSWSTA_T3STA 2 /* Status of T3 Switch. */ +#define BITP_AFE_TSWSTA_T2STA 1 /* Status of T2 Switch. */ +#define BITP_AFE_TSWSTA_T1STA 0 /* Status of T1 Switch. */ +#define BITM_AFE_TSWSTA_TR1STA 0x00000800 /* Status of TR1 Switch. */ +#define BITM_AFE_TSWSTA_T11STA 0x00000400 /* Status of T11 Switch. */ +#define BITM_AFE_TSWSTA_T10STA 0x00000200 /* Status of T10 Switch. */ +#define BITM_AFE_TSWSTA_T9STA 0x00000100 /* Status of T9 Switch. */ +#define BITM_AFE_TSWSTA_T8STA 0x00000080 /* Status of T8 Switch. */ +#define BITM_AFE_TSWSTA_T7STA 0x00000040 /* Status of T7 Switch. */ +#define BITM_AFE_TSWSTA_T6STA 0x00000020 /* Status of T6 Switch. */ +#define BITM_AFE_TSWSTA_T5STA 0x00000010 /* Status of T5 Switch. */ +#define BITM_AFE_TSWSTA_T4STA 0x00000008 /* Status of T4 Switch. */ +#define BITM_AFE_TSWSTA_T3STA 0x00000004 /* Status of T3 Switch. */ +#define BITM_AFE_TSWSTA_T2STA 0x00000002 /* Status of T2 Switch. */ +#define BITM_AFE_TSWSTA_T1STA 0x00000001 /* Status of T1 Switch. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_STATSVAR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_STATSVAR_VARIANCE 0 /* Statistical Variance Value */ +#define BITM_AFE_STATSVAR_VARIANCE \ + 0x7FFFFFFF /* Statistical Variance Value \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_STATSCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_STATSCON_STDDEV 7 /* Standard Deviation Configuration */ +#define BITP_AFE_STATSCON_SAMPLENUM 4 /* Sample Size */ +#define BITP_AFE_STATSCON_RESRVED 1 /* Reserved */ +#define BITP_AFE_STATSCON_STATSEN 0 /* Statistics Enable */ +#define BITM_AFE_STATSCON_STDDEV \ + 0x00000F80 /* Standard Deviation Configuration */ +#define BITM_AFE_STATSCON_SAMPLENUM 0x00000070 /* Sample Size */ +#define BITM_AFE_STATSCON_RESRVED 0x0000000E /* Reserved */ +#define BITM_AFE_STATSCON_STATSEN 0x00000001 /* Statistics Enable */ +#define ENUM_AFE_STATSCON_DIS 0x00000000 /* STATSEN: Disable Statistics */ +#define ENUM_AFE_STATSCON_EN 0x00000001 /* STATSEN: Enable Statistics */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_STATSMEAN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_STATSMEAN_MEAN 0 /* Mean Output */ +#define BITM_AFE_STATSMEAN_MEAN 0x0000FFFF /* Mean Output */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ0INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQ0INFO_LEN 16 /* SEQ0 Instruction Number */ +#define BITP_AFE_SEQ0INFO_ADDR 0 /* SEQ0 Start Address */ +#define BITM_AFE_SEQ0INFO_LEN 0x07FF0000 /* SEQ0 Instruction Number */ +#define BITM_AFE_SEQ0INFO_ADDR 0x000007FF /* SEQ0 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ2INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQ2INFO_LEN 16 /* SEQ2 Instruction Number */ +#define BITP_AFE_SEQ2INFO_ADDR 0 /* SEQ2 Start Address */ +#define BITM_AFE_SEQ2INFO_LEN 0x07FF0000 /* SEQ2 Instruction Number */ +#define BITM_AFE_SEQ2INFO_ADDR 0x000007FF /* SEQ2 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CMDFIFOWADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_CMDFIFOWADDR_WADDR 0 /* Write Address */ +#define BITM_AFE_CMDFIFOWADDR_WADDR 0x000007FF /* Write Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CMDDATACON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_CMDDATACON_DATAMEMMDE 9 /* Data FIFO Mode Select */ +#define BITP_AFE_CMDDATACON_DATA_MEM_SEL 6 /* Data FIFO Size Select */ +#define BITP_AFE_CMDDATACON_CMDMEMMDE \ + 3 /* This is Command Fifo Mode Register */ +#define BITP_AFE_CMDDATACON_CMD_MEM_SEL 0 /* Command Memory Select */ +#define BITM_AFE_CMDDATACON_DATAMEMMDE 0x00000E00 /* Data FIFO Mode Select */ +#define BITM_AFE_CMDDATACON_DATA_MEM_SEL \ + 0x000001C0 /* Data FIFO Size Select \ + */ +#define BITM_AFE_CMDDATACON_CMDMEMMDE \ + 0x00000038 /* This is Command Fifo Mode Register */ +#define BITM_AFE_CMDDATACON_CMD_MEM_SEL \ + 0x00000007 /* Command Memory Select \ + */ +#define ENUM_AFE_CMDDATACON_DFIFO 0x00000400 /* DATAMEMMDE: FIFO MODE */ +#define ENUM_AFE_CMDDATACON_DSTM 0x00000600 /* DATAMEMMDE: STREAM MODE */ +#define ENUM_AFE_CMDDATACON_DMEM32B \ + 0x00000000 /* DATA_MEM_SEL: 32B_1 Local Memory */ +#define ENUM_AFE_CMDDATACON_DMEM2K 0x00000040 /* DATA_MEM_SEL: 2K_2 SRAM */ +#define ENUM_AFE_CMDDATACON_DMEM4K 0x00000080 /* DATA_MEM_SEL: 2K_2~1 SRAM */ +#define ENUM_AFE_CMDDATACON_DMEM6K 0x000000C0 /* DATA_MEM_SEL: 2K_2~0 SRAM */ +#define ENUM_AFE_CMDDATACON_CMEM 0x00000008 /* CMDMEMMDE: MEMORY MODE */ +#define ENUM_AFE_CMDDATACON_CFIFO 0x00000010 /* CMDMEMMDE: FIFO MODE */ +#define ENUM_AFE_CMDDATACON_CSTM 0x00000018 /* CMDMEMMDE: STREAM MODE */ +#define ENUM_AFE_CMDDATACON_CMEM32B \ + 0x00000000 /* CMD_MEM_SEL: 32B_0 Local Memory */ +#define ENUM_AFE_CMDDATACON_CMEM2K 0x00000001 /* CMD_MEM_SEL: 2K_0 SRAM */ +#define ENUM_AFE_CMDDATACON_CMEM4K 0x00000002 /* CMD_MEM_SEL: 2K_0~1 SRAM */ +#define ENUM_AFE_CMDDATACON_CMEM6K 0x00000003 /* CMD_MEM_SEL: 2K_0~2 SRAM */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DATAFIFOTHRES Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DATAFIFOTHRES_HIGHTHRES 16 /* High Threshold */ +#define BITM_AFE_DATAFIFOTHRES_HIGHTHRES 0x07FF0000 /* High Threshold */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ3INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQ3INFO_LEN 16 /* SEQ3 Instruction Number */ +#define BITP_AFE_SEQ3INFO_ADDR 0 /* SEQ3 Start Address */ +#define BITM_AFE_SEQ3INFO_LEN 0x07FF0000 /* SEQ3 Instruction Number */ +#define BITM_AFE_SEQ3INFO_ADDR 0x000007FF /* SEQ3 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SEQ1INFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SEQ1INFO_LEN 16 /* SEQ1 Instruction Number */ +#define BITP_AFE_SEQ1INFO_ADDR 0 /* SEQ1 Start Address */ +#define BITM_AFE_SEQ1INFO_LEN 0x07FF0000 /* SEQ1 Instruction Number */ +#define BITM_AFE_SEQ1INFO_ADDR 0x000007FF /* SEQ1 Start Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_REPEATADCCNV Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_REPEATADCCNV_NUM 4 /* Repeat Value */ +#define BITP_AFE_REPEATADCCNV_EN 0 /* Enable Repeat ADC Conversions */ +#define BITM_AFE_REPEATADCCNV_NUM 0x00000FF0 /* Repeat Value */ +#define BITM_AFE_REPEATADCCNV_EN \ + 0x00000001 /* Enable Repeat ADC Conversions \ + */ +#define ENUM_AFE_REPEATADCCNV_DIS \ + 0x00000000 /* EN: Disable Repeat ADC Conversions */ +#define ENUM_AFE_REPEATADCCNV_EN \ + 0x00000001 /* EN: Enable Repeat ADC Conversions */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_FIFOCNTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_FIFOCNTSTA_DATAFIFOCNTSTA \ + 16 /* Current Number of Words in the Data FIFO */ +#define BITM_AFE_FIFOCNTSTA_DATAFIFOCNTSTA \ + 0x07FF0000 /* Current Number of Words in the Data FIFO */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_CALDATLOCK Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_CALDATLOCK_KEY \ + 0 /* Password for Calibration Data Registers \ + */ +#define BITM_AFE_CALDATLOCK_KEY \ + 0xFFFFFFFF /* Password for Calibration Data Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETHSTIA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETHSTIA_VALUE 0 /* HSTIA Offset Calibration */ +#define BITM_AFE_ADCOFFSETHSTIA_VALUE \ + 0x00007FFF /* HSTIA Offset Calibration \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINTEMPSENS0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGAINTEMPSENS0_VALUE \ + 0 /* Gain Calibration Temp Sensor Channel */ +#define BITM_AFE_ADCGAINTEMPSENS0_VALUE \ + 0x00007FFF /* Gain Calibration Temp Sensor Channel */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETTEMPSENS0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETTEMPSENS0_VALUE \ + 0 /* Offset Calibration Temp Sensor */ +#define BITM_AFE_ADCOFFSETTEMPSENS0_VALUE \ + 0x00007FFF /* Offset Calibration Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGAINGN1_VALUE 0 /* Gain Calibration PGA Gain 1x */ +#define BITM_AFE_ADCGAINGN1_VALUE \ + 0x00007FFF /* Gain Calibration PGA Gain 1x \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETGN1_VALUE 0 /* Offset Calibration Gain1 */ +#define BITM_AFE_ADCOFFSETGN1_VALUE 0x00007FFF /* Offset Calibration Gain1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACGAIN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DACGAIN_VALUE 0 /* HS DAC Gain Correction Factor */ +#define BITM_AFE_DACGAIN_VALUE 0x00000FFF /* HS DAC Gain Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSETATTEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DACOFFSETATTEN_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSETATTEN_VALUE \ + 0x00000FFF /* DAC Offset Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DACOFFSET_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSET_VALUE \ + 0x00000FFF /* DAC Offset Correction Factor \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN1P5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGAINGN1P5_VALUE 0 /* Gain Calibration PGA Gain 1.5x */ +#define BITM_AFE_ADCGAINGN1P5_VALUE \ + 0x00007FFF /* Gain Calibration PGA Gain 1.5x */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGAINGN2_VALUE 0 /* Gain Calibration PGA Gain 2x */ +#define BITM_AFE_ADCGAINGN2_VALUE \ + 0x00007FFF /* Gain Calibration PGA Gain 2x \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGAINGN4_VALUE 0 /* Gain Calibration PGA Gain 4x */ +#define BITM_AFE_ADCGAINGN4_VALUE \ + 0x00007FFF /* Gain Calibration PGA Gain 4x \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCPGAOFFSETCANCEL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCPGAOFFSETCANCEL_OFFSETCANCEL 0 /* Offset Cancellation */ +#define BITM_AFE_ADCPGAOFFSETCANCEL_OFFSETCANCEL \ + 0x00007FFF /* Offset Cancellation */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGNHSTIA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGNHSTIA_VALUE \ + 0 /* Gain Error Calibration HS TIA Channel \ + */ +#define BITM_AFE_ADCGNHSTIA_VALUE \ + 0x00007FFF /* Gain Error Calibration HS TIA Channel */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETLPTIA0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETLPTIA0_VALUE \ + 0 /* Offset Calibration for ULP-TIA0 \ + */ +#define BITM_AFE_ADCOFFSETLPTIA0_VALUE \ + 0x00007FFF /* Offset Calibration for ULP-TIA0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGNLPTIA0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGNLPTIA0_VALUE 0 /* Gain Error Calibration ULPTIA0 */ +#define BITM_AFE_ADCGNLPTIA0_VALUE \ + 0x00007FFF /* Gain Error Calibration ULPTIA0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCPGAGN4OFCAL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCPGAGN4OFCAL_ADCGAINAUX 0 /* DC Calibration Gain=4 */ +#define BITM_AFE_ADCPGAGN4OFCAL_ADCGAINAUX \ + 0x00007FFF /* DC Calibration Gain=4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINGN9 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGAINGN9_VALUE 0 /* Gain Calibration PGA Gain 9x */ +#define BITM_AFE_ADCGAINGN9_VALUE \ + 0x00007FFF /* Gain Calibration PGA Gain 9x \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETEMPSENS1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETEMPSENS1_VALUE \ + 0 /* Offset Calibration Temp Sensor \ + */ +#define BITM_AFE_ADCOFFSETEMPSENS1_VALUE \ + 0x00007FFF /* Offset Calibration Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGAINDIOTEMPSENS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGAINDIOTEMPSENS_VALUE \ + 0 /* Gain Calibration for Diode Temp Sensor */ +#define BITM_AFE_ADCGAINDIOTEMPSENS_VALUE \ + 0x00007FFF /* Gain Calibration for Diode Temp Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSETATTENHP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DACOFFSETATTENHP_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSETATTENHP_VALUE \ + 0x00000FFF /* DAC Offset Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_DACOFFSETHP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_DACOFFSETHP_VALUE 0 /* DAC Offset Correction Factor */ +#define BITM_AFE_DACOFFSETHP_VALUE \ + 0x00000FFF /* DAC Offset Correction Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETLPTIA1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETLPTIA1_VALUE \ + 0 /* Offset Calibration for ULP-TIA1 \ + */ +#define BITM_AFE_ADCOFFSETLPTIA1_VALUE \ + (_ADI_MSK_3(0x00007FFF, 0x00007FFFUL, \ + uint32_t)) /* Offset Calibration for ULP-TIA1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCGNLPTIA1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCGNLPTIA1_ULPTIA1GN 0 /* Gain Calibration ULP-TIA1 */ +#define BITM_AFE_ADCGNLPTIA1_ULPTIA1GN \ + 0x00007FFF /* Gain Calibration ULP-TIA1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETGN2_VALUE \ + 0 /* Offset Calibration Auxiliary Channel (PGA Gain =2) */ +#define BITM_AFE_ADCOFFSETGN2_VALUE \ + 0x00007FFF /* Offset Calibration Auxiliary Channel (PGA Gain =2) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN1P5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETGN1P5_VALUE 0 /* Offset Calibration Gain1.5 */ +#define BITM_AFE_ADCOFFSETGN1P5_VALUE \ + 0x00007FFF /* Offset Calibration Gain1.5 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN9 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETGN9_VALUE 0 /* Offset Calibration Gain9 */ +#define BITM_AFE_ADCOFFSETGN9_VALUE 0x00007FFF /* Offset Calibration Gain9 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCOFFSETGN4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCOFFSETGN4_VALUE 0 /* Offset Calibration Gain4 */ +#define BITM_AFE_ADCOFFSETGN4_VALUE 0x00007FFF /* Offset Calibration Gain4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_PMBW Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_PMBW_SYSBW 2 /* Configure System Bandwidth */ +#define BITP_AFE_PMBW_SYSHP \ + 0 /* Set High Speed DAC and ADC in High Power Mode */ +#define BITM_AFE_PMBW_SYSBW 0x0000000C /* Configure System Bandwidth */ +#define BITM_AFE_PMBW_SYSHP \ + 0x00000001 /* Set High Speed DAC and ADC in High Power Mode */ +#define ENUM_AFE_PMBW_BWNA \ + 0x00000000 /* SYSBW: no action for system configuration */ +#define ENUM_AFE_PMBW_BW50 0x00000004 /* SYSBW: 50kHz -3dB bandwidth */ +#define ENUM_AFE_PMBW_BW100 0x00000008 /* SYSBW: 100kHz -3dB bandwidth */ +#define ENUM_AFE_PMBW_BW250 0x0000000C /* SYSBW: 250kHz -3dB bandwidth */ +#define ENUM_AFE_PMBW_LP 0x00000000 /* SYSHP: LP mode */ +#define ENUM_AFE_PMBW_HP 0x00000001 /* SYSHP: HP mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_SWMUX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_SWMUX_CMMUX 3 /* CM Resistor Select for Ain2, Ain3 */ +#define BITM_AFE_SWMUX_CMMUX \ + 0x00000008 /* CM Resistor Select for Ain2, Ain3 \ + */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_AFE_TEMPSEN_DIO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_AFE_TEMPSEN_DIO_TSDIO_PD 17 /* Power Down Control */ +#define BITP_AFE_AFE_TEMPSEN_DIO_TSDIO_EN 16 /* Test Signal Enable */ +#define BITP_AFE_AFE_TEMPSEN_DIO_TSDIO_CON 0 /* Bias Current Selection */ +#define BITM_AFE_AFE_TEMPSEN_DIO_TSDIO_PD 0x00020000 /* Power Down Control */ +#define BITM_AFE_AFE_TEMPSEN_DIO_TSDIO_EN 0x00010000 /* Test Signal Enable */ +#define BITM_AFE_AFE_TEMPSEN_DIO_TSDIO_CON \ + 0x0000FFFF /* Bias Current Selection */ + +/* ------------------------------------------------------------------------------------------------------------------------- + AFE_ADCBUFCON Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_AFE_ADCBUFCON_AMPDIS 4 /* Disable OpAmp. */ +#define BITP_AFE_ADCBUFCON_CHOPDIS 0 /* Disable Chop */ +#define BITM_AFE_ADCBUFCON_AMPDIS 0x000001F0 /* Disable OpAmp. */ +#define BITM_AFE_ADCBUFCON_CHOPDIS 0x0000000F /* Disable Chop */ + +/* ============================================================================================================================ + Interrupt Controller Register Map + ============================================================================================================================ + */ + +/* ============================================================================================================================ + INTC + ============================================================================================================================ + */ +#define REG_INTC_INTCPOL_RESET 0x00000000 /* Reset Value for INTCPOL */ +#define REG_INTC_INTCPOL 0x00003000 /* INTC Interrupt Polarity Register */ +#define REG_INTC_INTCCLR_RESET 0x00000000 /* Reset Value for INTCCLR */ +#define REG_INTC_INTCCLR 0x00003004 /* INTC Interrupt Clear Register */ +#define REG_INTC_INTCSEL0_RESET 0x00002000 /* Reset Value for INTCSEL0 */ +#define REG_INTC_INTCSEL0 0x00003008 /* INTC INT0 Select Register */ +#define REG_INTC_INTCSEL1_RESET 0x00000000 /* Reset Value for INTCSEL1 */ +#define REG_INTC_INTCSEL1 0x0000300C /* INTC INT1 Select Register */ +#define REG_INTC_INTCFLAG0_RESET \ + 0x00000000 /* Reset Value for INTCFLAG0 */ +#define REG_INTC_INTCFLAG0 0x00003010 /* INTC INT0 FLAG Register */ +#define REG_INTC_INTCFLAG1_RESET \ + 0x00000000 /* Reset Value for INTCFLAG1 */ +#define REG_INTC_INTCFLAG1 0x00003014 /* INTC INT1 FLAG Register */ + +/* ============================================================================================================================ + INTC Register BitMasks, Positions & Enumerations + ============================================================================================================================ + */ +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCPOL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_INTC_INTCPOL_INTPOL 0 +#define BITM_INTC_INTCPOL_INTPOL 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCCLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_INTC_INTCCLR_INTCLR31 31 +#define BITP_INTC_INTCCLR_INTCLR30 30 +#define BITP_INTC_INTCCLR_INTCLR29 29 +#define BITP_INTC_INTCCLR_INTCLR28 28 +#define BITP_INTC_INTCCLR_INTCLR27 27 +#define BITP_INTC_INTCCLR_INTCLR26 26 +#define BITP_INTC_INTCCLR_INTCLR25 25 +#define BITP_INTC_INTCCLR_INTCLR24 24 +#define BITP_INTC_INTCCLR_INTCLR23 23 +#define BITP_INTC_INTCCLR_INTCLR22 22 +#define BITP_INTC_INTCCLR_INTCLR21 21 +#define BITP_INTC_INTCCLR_INTCLR20 20 +#define BITP_INTC_INTCCLR_INTCLR19 19 +#define BITP_INTC_INTCCLR_INTCLR18 18 +#define BITP_INTC_INTCCLR_INTCLR17 17 +#define BITP_INTC_INTCCLR_INTCLR16 16 +#define BITP_INTC_INTCCLR_INTCLR15 15 +#define BITP_INTC_INTCCLR_INTCLR14 14 +#define BITP_INTC_INTCCLR_INTCLR13 13 +#define BITP_INTC_INTCCLR_INTCLR12 12 /* Custom IRQ 3. Write 1 to clear. */ +#define BITP_INTC_INTCCLR_INTCLR11 11 /* Custom IRQ 2. Write 1 to clear. */ +#define BITP_INTC_INTCCLR_INTCLR10 10 /* Custom IRQ 1. Write 1 to clear. */ +#define BITP_INTC_INTCCLR_INTCLR9 9 /* Custom IRQ 0. Write 1 to clear */ +#define BITP_INTC_INTCCLR_INTCLR8 8 +#define BITP_INTC_INTCCLR_INTCLR7 7 +#define BITP_INTC_INTCCLR_INTCLR6 6 +#define BITP_INTC_INTCCLR_INTCLR5 5 +#define BITP_INTC_INTCCLR_INTCLR4 4 +#define BITP_INTC_INTCCLR_INTCLR3 3 +#define BITP_INTC_INTCCLR_INTCLR2 2 +#define BITP_INTC_INTCCLR_INTCLR1 1 +#define BITP_INTC_INTCCLR_INTCLR0 0 +#define BITM_INTC_INTCCLR_INTCLR31 0x80000000 +#define BITM_INTC_INTCCLR_INTCLR30 0x40000000 +#define BITM_INTC_INTCCLR_INTCLR29 0x20000000 +#define BITM_INTC_INTCCLR_INTCLR28 0x10000000 +#define BITM_INTC_INTCCLR_INTCLR27 0x08000000 +#define BITM_INTC_INTCCLR_INTCLR26 0x04000000 +#define BITM_INTC_INTCCLR_INTCLR25 0x02000000 +#define BITM_INTC_INTCCLR_INTCLR24 0x01000000 +#define BITM_INTC_INTCCLR_INTCLR23 0x00800000 +#define BITM_INTC_INTCCLR_INTCLR22 0x00400000 +#define BITM_INTC_INTCCLR_INTCLR21 0x00200000 +#define BITM_INTC_INTCCLR_INTCLR20 0x00100000 +#define BITM_INTC_INTCCLR_INTCLR19 0x00080000 +#define BITM_INTC_INTCCLR_INTCLR18 0x00040000 +#define BITM_INTC_INTCCLR_INTCLR17 0x00020000 +#define BITM_INTC_INTCCLR_INTCLR16 0x00010000 +#define BITM_INTC_INTCCLR_INTCLR15 0x00008000 +#define BITM_INTC_INTCCLR_INTCLR14 0x00004000 +#define BITM_INTC_INTCCLR_INTCLR13 0x00002000 +#define BITM_INTC_INTCCLR_INTCLR12 \ + 0x00001000 /* Custom IRQ 3. Write 1 to clear. */ +#define BITM_INTC_INTCCLR_INTCLR11 \ + 0x00000800 /* Custom IRQ 2. Write 1 to clear. */ +#define BITM_INTC_INTCCLR_INTCLR10 \ + 0x00000400 /* Custom IRQ 1. Write 1 to clear. */ +#define BITM_INTC_INTCCLR_INTCLR9 \ + 0x00000200 /* Custom IRQ 0. Write 1 to clear */ +#define BITM_INTC_INTCCLR_INTCLR8 0x00000100 +#define BITM_INTC_INTCCLR_INTCLR7 0x00000080 +#define BITM_INTC_INTCCLR_INTCLR6 0x00000040 +#define BITM_INTC_INTCCLR_INTCLR5 0x00000020 +#define BITM_INTC_INTCCLR_INTCLR4 0x00000010 +#define BITM_INTC_INTCCLR_INTCLR3 0x00000008 +#define BITM_INTC_INTCCLR_INTCLR2 0x00000004 +#define BITM_INTC_INTCCLR_INTCLR1 0x00000002 +#define BITM_INTC_INTCCLR_INTCLR0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCSEL0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_INTC_INTCSEL0_INTSEL31 31 +#define BITP_INTC_INTCSEL0_INTSEL30 30 +#define BITP_INTC_INTCSEL0_INTSEL29 29 +#define BITP_INTC_INTCSEL0_INTSEL28 28 +#define BITP_INTC_INTCSEL0_INTSEL27 27 +#define BITP_INTC_INTCSEL0_INTSEL26 26 +#define BITP_INTC_INTCSEL0_INTSEL25 25 +#define BITP_INTC_INTCSEL0_INTSEL24 24 +#define BITP_INTC_INTCSEL0_INTSEL23 23 +#define BITP_INTC_INTCSEL0_INTSEL22 22 +#define BITP_INTC_INTCSEL0_INTSEL21 21 +#define BITP_INTC_INTCSEL0_INTSEL20 20 +#define BITP_INTC_INTCSEL0_INTSEL19 19 +#define BITP_INTC_INTCSEL0_INTSEL18 18 +#define BITP_INTC_INTCSEL0_INTSEL17 17 +#define BITP_INTC_INTCSEL0_INTSEL16 16 +#define BITP_INTC_INTCSEL0_INTSEL15 15 +#define BITP_INTC_INTCSEL0_INTSEL14 14 +#define BITP_INTC_INTCSEL0_INTSEL13 13 +#define BITP_INTC_INTCSEL0_INTSEL12 12 /* Custom IRQ 3 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL11 11 /* Custom IRQ 2 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL10 10 /* Custom IRQ 1 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL9 9 /* Custom IRQ 0 Enable */ +#define BITP_INTC_INTCSEL0_INTSEL8 8 +#define BITP_INTC_INTCSEL0_INTSEL7 7 +#define BITP_INTC_INTCSEL0_INTSEL6 6 +#define BITP_INTC_INTCSEL0_INTSEL5 5 +#define BITP_INTC_INTCSEL0_INTSEL4 4 +#define BITP_INTC_INTCSEL0_INTSEL3 3 +#define BITP_INTC_INTCSEL0_INTSEL2 2 +#define BITP_INTC_INTCSEL0_INTSEL1 1 +#define BITP_INTC_INTCSEL0_INTSEL0 0 +#define BITM_INTC_INTCSEL0_INTSEL31 0x80000000 +#define BITM_INTC_INTCSEL0_INTSEL30 0x40000000 +#define BITM_INTC_INTCSEL0_INTSEL29 0x20000000 +#define BITM_INTC_INTCSEL0_INTSEL28 0x10000000 +#define BITM_INTC_INTCSEL0_INTSEL27 0x08000000 +#define BITM_INTC_INTCSEL0_INTSEL26 0x04000000 +#define BITM_INTC_INTCSEL0_INTSEL25 0x02000000 +#define BITM_INTC_INTCSEL0_INTSEL24 0x01000000 +#define BITM_INTC_INTCSEL0_INTSEL23 0x00800000 +#define BITM_INTC_INTCSEL0_INTSEL22 0x00400000 +#define BITM_INTC_INTCSEL0_INTSEL21 0x00200000 +#define BITM_INTC_INTCSEL0_INTSEL20 0x00100000 +#define BITM_INTC_INTCSEL0_INTSEL19 0x00080000 +#define BITM_INTC_INTCSEL0_INTSEL18 0x00040000 +#define BITM_INTC_INTCSEL0_INTSEL17 0x00020000 +#define BITM_INTC_INTCSEL0_INTSEL16 0x00010000 +#define BITM_INTC_INTCSEL0_INTSEL15 0x00008000 +#define BITM_INTC_INTCSEL0_INTSEL14 0x00004000 +#define BITM_INTC_INTCSEL0_INTSEL13 0x00002000 +#define BITM_INTC_INTCSEL0_INTSEL12 0x00001000 /* Custom IRQ 3 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL11 0x00000800 /* Custom IRQ 2 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL10 0x00000400 /* Custom IRQ 1 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL9 0x00000200 /* Custom IRQ 0 Enable */ +#define BITM_INTC_INTCSEL0_INTSEL8 0x00000100 +#define BITM_INTC_INTCSEL0_INTSEL7 0x00000080 +#define BITM_INTC_INTCSEL0_INTSEL6 0x00000040 +#define BITM_INTC_INTCSEL0_INTSEL5 0x00000020 +#define BITM_INTC_INTCSEL0_INTSEL4 0x00000010 +#define BITM_INTC_INTCSEL0_INTSEL3 0x00000008 +#define BITM_INTC_INTCSEL0_INTSEL2 0x00000004 +#define BITM_INTC_INTCSEL0_INTSEL1 0x00000002 +#define BITM_INTC_INTCSEL0_INTSEL0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCSEL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_INTC_INTCSEL1_INTSEL31 31 +#define BITP_INTC_INTCSEL1_INTSEL30 30 +#define BITP_INTC_INTCSEL1_INTSEL29 29 +#define BITP_INTC_INTCSEL1_INTSEL28 28 +#define BITP_INTC_INTCSEL1_INTSEL27 27 +#define BITP_INTC_INTCSEL1_INTSEL26 26 +#define BITP_INTC_INTCSEL1_INTSEL25 25 +#define BITP_INTC_INTCSEL1_INTSEL24 24 +#define BITP_INTC_INTCSEL1_INTSEL23 23 +#define BITP_INTC_INTCSEL1_INTSEL22 22 +#define BITP_INTC_INTCSEL1_INTSEL21 21 +#define BITP_INTC_INTCSEL1_INTSEL20 20 +#define BITP_INTC_INTCSEL1_INTSEL19 19 +#define BITP_INTC_INTCSEL1_INTSEL18 18 +#define BITP_INTC_INTCSEL1_INTSEL17 17 +#define BITP_INTC_INTCSEL1_INTSEL16 16 +#define BITP_INTC_INTCSEL1_INTSEL15 15 +#define BITP_INTC_INTCSEL1_INTSEL14 14 +#define BITP_INTC_INTCSEL1_INTSEL13 13 +#define BITP_INTC_INTCSEL1_INTSEL12 12 /* Custom IRQ 3 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL11 11 /* Custom IRQ 2 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL10 10 /* Custom IRQ 1 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL9 9 /* Custom IRQ 0 Enable */ +#define BITP_INTC_INTCSEL1_INTSEL8 8 +#define BITP_INTC_INTCSEL1_INTSEL7 7 +#define BITP_INTC_INTCSEL1_INTSEL6 6 +#define BITP_INTC_INTCSEL1_INTSEL5 5 +#define BITP_INTC_INTCSEL1_INTSEL4 4 +#define BITP_INTC_INTCSEL1_INTSEL3 3 +#define BITP_INTC_INTCSEL1_INTSEL2 2 +#define BITP_INTC_INTCSEL1_INTSEL1 1 +#define BITP_INTC_INTCSEL1_INTSEL0 0 +#define BITM_INTC_INTCSEL1_INTSEL31 0x80000000 +#define BITM_INTC_INTCSEL1_INTSEL30 0x40000000 +#define BITM_INTC_INTCSEL1_INTSEL29 0x20000000 +#define BITM_INTC_INTCSEL1_INTSEL28 0x10000000 +#define BITM_INTC_INTCSEL1_INTSEL27 0x08000000 +#define BITM_INTC_INTCSEL1_INTSEL26 0x04000000 +#define BITM_INTC_INTCSEL1_INTSEL25 0x02000000 +#define BITM_INTC_INTCSEL1_INTSEL24 0x01000000 +#define BITM_INTC_INTCSEL1_INTSEL23 0x00800000 +#define BITM_INTC_INTCSEL1_INTSEL22 0x00400000 +#define BITM_INTC_INTCSEL1_INTSEL21 0x00200000 +#define BITM_INTC_INTCSEL1_INTSEL20 0x00100000 +#define BITM_INTC_INTCSEL1_INTSEL19 0x00080000 +#define BITM_INTC_INTCSEL1_INTSEL18 0x00040000 +#define BITM_INTC_INTCSEL1_INTSEL17 0x00020000 +#define BITM_INTC_INTCSEL1_INTSEL16 0x00010000 +#define BITM_INTC_INTCSEL1_INTSEL15 0x00008000 +#define BITM_INTC_INTCSEL1_INTSEL14 0x00004000 +#define BITM_INTC_INTCSEL1_INTSEL13 0x00002000 +#define BITM_INTC_INTCSEL1_INTSEL12 0x00001000 /* Custom IRQ 3 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL11 0x00000800 /* Custom IRQ 2 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL10 0x00000400 /* Custom IRQ 1 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL9 0x00000200 /* Custom IRQ 0 Enable */ +#define BITM_INTC_INTCSEL1_INTSEL8 0x00000100 +#define BITM_INTC_INTCSEL1_INTSEL7 0x00000080 +#define BITM_INTC_INTCSEL1_INTSEL6 0x00000040 +#define BITM_INTC_INTCSEL1_INTSEL5 0x00000020 +#define BITM_INTC_INTCSEL1_INTSEL4 0x00000010 +#define BITM_INTC_INTCSEL1_INTSEL3 0x00000008 +#define BITM_INTC_INTCSEL1_INTSEL2 0x00000004 +#define BITM_INTC_INTCSEL1_INTSEL1 0x00000002 +#define BITM_INTC_INTCSEL1_INTSEL0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCFLAG0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_INTC_INTCFLAG0_FLAG31 31 +#define BITP_INTC_INTCFLAG0_FLAG30 30 +#define BITP_INTC_INTCFLAG0_FLAG29 29 +#define BITP_INTC_INTCFLAG0_FLAG28 28 +#define BITP_INTC_INTCFLAG0_FLAG27 27 +#define BITP_INTC_INTCFLAG0_FLAG26 26 +#define BITP_INTC_INTCFLAG0_FLAG25 25 +#define BITP_INTC_INTCFLAG0_FLAG24 24 +#define BITP_INTC_INTCFLAG0_FLAG23 23 +#define BITP_INTC_INTCFLAG0_FLAG22 22 +#define BITP_INTC_INTCFLAG0_FLAG21 21 +#define BITP_INTC_INTCFLAG0_FLAG20 20 +#define BITP_INTC_INTCFLAG0_FLAG19 19 +#define BITP_INTC_INTCFLAG0_FLAG18 18 +#define BITP_INTC_INTCFLAG0_FLAG17 17 +#define BITP_INTC_INTCFLAG0_FLAG16 16 +#define BITP_INTC_INTCFLAG0_FLAG15 15 +#define BITP_INTC_INTCFLAG0_FLAG14 14 +#define BITP_INTC_INTCFLAG0_FLAG13 13 +#define BITP_INTC_INTCFLAG0_FLAG12 12 /* Custom IRQ 3 Status */ +#define BITP_INTC_INTCFLAG0_FLAG11 11 /* Custom IRQ 2 Status */ +#define BITP_INTC_INTCFLAG0_FLAG10 10 /* Custom IRQ 1 Status */ +#define BITP_INTC_INTCFLAG0_FLAG9 9 /* Custom IRQ 0 Status */ +#define BITP_INTC_INTCFLAG0_FLAG8 8 /* Variance IRQ status. */ +#define BITP_INTC_INTCFLAG0_FLAG7 7 +#define BITP_INTC_INTCFLAG0_FLAG6 6 +#define BITP_INTC_INTCFLAG0_FLAG5 5 +#define BITP_INTC_INTCFLAG0_FLAG4 4 +#define BITP_INTC_INTCFLAG0_FLAG3 3 +#define BITP_INTC_INTCFLAG0_FLAG2 2 +#define BITP_INTC_INTCFLAG0_FLAG1 1 +#define BITP_INTC_INTCFLAG0_FLAG0 0 +#define BITM_INTC_INTCFLAG0_FLAG31 0x80000000 +#define BITM_INTC_INTCFLAG0_FLAG30 0x40000000 +#define BITM_INTC_INTCFLAG0_FLAG29 0x20000000 +#define BITM_INTC_INTCFLAG0_FLAG28 0x10000000 +#define BITM_INTC_INTCFLAG0_FLAG27 0x08000000 +#define BITM_INTC_INTCFLAG0_FLAG26 0x04000000 +#define BITM_INTC_INTCFLAG0_FLAG25 0x02000000 +#define BITM_INTC_INTCFLAG0_FLAG24 0x01000000 +#define BITM_INTC_INTCFLAG0_FLAG23 0x00800000 +#define BITM_INTC_INTCFLAG0_FLAG22 0x00400000 +#define BITM_INTC_INTCFLAG0_FLAG21 0x00200000 +#define BITM_INTC_INTCFLAG0_FLAG20 0x00100000 +#define BITM_INTC_INTCFLAG0_FLAG19 0x00080000 +#define BITM_INTC_INTCFLAG0_FLAG18 0x00040000 +#define BITM_INTC_INTCFLAG0_FLAG17 0x00020000 +#define BITM_INTC_INTCFLAG0_FLAG16 0x00010000 +#define BITM_INTC_INTCFLAG0_FLAG15 0x00008000 +#define BITM_INTC_INTCFLAG0_FLAG14 0x00004000 +#define BITM_INTC_INTCFLAG0_FLAG13 0x00002000 +#define BITM_INTC_INTCFLAG0_FLAG12 0x00001000 /* Custom IRQ 3 Status */ +#define BITM_INTC_INTCFLAG0_FLAG11 0x00000800 /* Custom IRQ 2 Status */ +#define BITM_INTC_INTCFLAG0_FLAG10 0x00000400 /* Custom IRQ 1 Status */ +#define BITM_INTC_INTCFLAG0_FLAG9 0x00000200 /* Custom IRQ 0 Status */ +#define BITM_INTC_INTCFLAG0_FLAG8 0x00000100 /* Variance IRQ status. */ +#define BITM_INTC_INTCFLAG0_FLAG7 0x00000080 +#define BITM_INTC_INTCFLAG0_FLAG6 0x00000040 +#define BITM_INTC_INTCFLAG0_FLAG5 0x00000020 +#define BITM_INTC_INTCFLAG0_FLAG4 0x00000010 +#define BITM_INTC_INTCFLAG0_FLAG3 0x00000008 +#define BITM_INTC_INTCFLAG0_FLAG2 0x00000004 +#define BITM_INTC_INTCFLAG0_FLAG1 0x00000002 +#define BITM_INTC_INTCFLAG0_FLAG0 0x00000001 + +/* ------------------------------------------------------------------------------------------------------------------------- + INTC_INTCFLAG1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- + */ +#define BITP_INTC_INTCFLAG1_FLAG31 31 +#define BITP_INTC_INTCFLAG1_FLAG30 30 +#define BITP_INTC_INTCFLAG1_FLAG29 29 +#define BITP_INTC_INTCFLAG1_FLAG28 28 +#define BITP_INTC_INTCFLAG1_FLAG27 27 +#define BITP_INTC_INTCFLAG1_FLAG26 26 +#define BITP_INTC_INTCFLAG1_FLAG25 25 +#define BITP_INTC_INTCFLAG1_FLAG24 24 +#define BITP_INTC_INTCFLAG1_FLAG23 23 +#define BITP_INTC_INTCFLAG1_FLAG22 22 +#define BITP_INTC_INTCFLAG1_FLAG21 21 +#define BITP_INTC_INTCFLAG1_FLAG20 20 +#define BITP_INTC_INTCFLAG1_FLAG19 19 +#define BITP_INTC_INTCFLAG1_FLAG18 18 +#define BITP_INTC_INTCFLAG1_FLAG17 17 +#define BITP_INTC_INTCFLAG1_FLAG16 16 +#define BITP_INTC_INTCFLAG1_FLAG15 15 +#define BITP_INTC_INTCFLAG1_FLAG14 14 +#define BITP_INTC_INTCFLAG1_FLAG13 13 +#define BITP_INTC_INTCFLAG1_FLAG12 12 /* Custom IRQ 3 Status */ +#define BITP_INTC_INTCFLAG1_FLAG11 11 /* Custom IRQ 2 Status */ +#define BITP_INTC_INTCFLAG1_FLAG10 10 /* Custom IRQ 1 Status */ +#define BITP_INTC_INTCFLAG1_FLAG9 9 /* Custom IRQ 0 Status */ +#define BITP_INTC_INTCFLAG1_FLAG8 8 /* Variance IRQ status. */ +#define BITP_INTC_INTCFLAG1_FLAG7 7 +#define BITP_INTC_INTCFLAG1_FLAG6 6 +#define BITP_INTC_INTCFLAG1_FLAG5 5 +#define BITP_INTC_INTCFLAG1_FLAG4 4 +#define BITP_INTC_INTCFLAG1_FLAG3 3 +#define BITP_INTC_INTCFLAG1_FLAG2 2 +#define BITP_INTC_INTCFLAG1_FLAG1 1 +#define BITP_INTC_INTCFLAG1_FLAG0 0 +#define BITM_INTC_INTCFLAG1_FLAG31 0x80000000 +#define BITM_INTC_INTCFLAG1_FLAG30 0x40000000 +#define BITM_INTC_INTCFLAG1_FLAG29 0x20000000 +#define BITM_INTC_INTCFLAG1_FLAG28 0x10000000 +#define BITM_INTC_INTCFLAG1_FLAG27 0x08000000 +#define BITM_INTC_INTCFLAG1_FLAG26 0x04000000 +#define BITM_INTC_INTCFLAG1_FLAG25 0x02000000 +#define BITM_INTC_INTCFLAG1_FLAG24 0x01000000 +#define BITM_INTC_INTCFLAG1_FLAG23 0x00800000 +#define BITM_INTC_INTCFLAG1_FLAG22 0x00400000 +#define BITM_INTC_INTCFLAG1_FLAG21 0x00200000 +#define BITM_INTC_INTCFLAG1_FLAG20 0x00100000 +#define BITM_INTC_INTCFLAG1_FLAG19 0x00080000 +#define BITM_INTC_INTCFLAG1_FLAG18 0x00040000 +#define BITM_INTC_INTCFLAG1_FLAG17 0x00020000 +#define BITM_INTC_INTCFLAG1_FLAG16 0x00010000 +#define BITM_INTC_INTCFLAG1_FLAG15 0x00008000 +#define BITM_INTC_INTCFLAG1_FLAG14 0x00004000 +#define BITM_INTC_INTCFLAG1_FLAG13 0x00002000 +#define BITM_INTC_INTCFLAG1_FLAG12 0x00001000 /* Custom IRQ 3 Status */ +#define BITM_INTC_INTCFLAG1_FLAG11 0x00000800 /* Custom IRQ 2 Status */ +#define BITM_INTC_INTCFLAG1_FLAG10 0x00000400 /* Custom IRQ 1 Status */ +#define BITM_INTC_INTCFLAG1_FLAG9 0x00000200 /* Custom IRQ 0 Status */ +#define BITM_INTC_INTCFLAG1_FLAG8 0x00000100 /* Variance IRQ status. */ +#define BITM_INTC_INTCFLAG1_FLAG7 0x00000080 +#define BITM_INTC_INTCFLAG1_FLAG6 0x00000040 +#define BITM_INTC_INTCFLAG1_FLAG5 0x00000020 +#define BITM_INTC_INTCFLAG1_FLAG4 0x00000010 +#define BITM_INTC_INTCFLAG1_FLAG3 0x00000008 +#define BITM_INTC_INTCFLAG1_FLAG2 0x00000004 +#define BITM_INTC_INTCFLAG1_FLAG1 0x00000002 +#define BITM_INTC_INTCFLAG1_FLAG0 0x00000001 +/** + * @} AD5940RegistersBitfields + * @endcond + * */ + +/** + * @addtogroup SPI_Block + * @{ + * @defgroup SPI_Block_Const + * @{ + * + */ +#define SPICMD_SETADDR \ + 0x20 /**< set the register address that is going to operate. */ +#define SPICMD_READREG 0x6d /**< command to read register */ +#define SPICMD_WRITEREG 0x2d /**< command to write register */ +#define SPICMD_READFIFO 0x5f /**< command to read FIFO */ +/** + * @} SPI_Block_Const + * @} SPI_Block + */ + +/** + * @addtogroup AFE_Control + * @{ + * */ + +/** + * @defgroup AFE_Control_Const + * @{ + * */ + +/** + * @defgroup AFEINTC_Const + * @brief AD5940 has two interrupt controller INTC0 and INTC1. Both of them have + * ability to generate interrupt signal from GPIO. + * @{ + * */ +/* AFE Interrupt controller selection */ +#define AFEINTC_0 0 /**< Interrupt controller 0 */ +#define AFEINTC_1 1 /**< Interrupt controller 1 */ +/** @} */ + +/** + * @defgroup AFEINTC_SRC_Const + * @brief Interrupt source selection. These sources are defined as bit mask. + * They are available for register INTCCLR, INTCSEL0/1, INTCFLAG0/1 + * @{ + * */ +#define AFEINTSRC_ADCRDY 0x00000001 /**< Bit0, ADC Result Ready Status */ +#define AFEINTSRC_DFTRDY 0x00000002 /**< Bit1, DFT Result Ready Status */ +#define AFEINTSRC_SINC2RDY \ + 0x00000004 /**< Bit2, SINC2/Low Pass Filter Result Status */ +#define AFEINTSRC_TEMPRDY 0x00000008 /**< Bit3, Temp Sensor Result Ready */ +#define AFEINTSRC_ADCMINERR 0x00000010 /**< Bit4, ADC Minimum Value */ +#define AFEINTSRC_ADCMAXERR 0x00000020 /**< Bit5, ADC Maximum Value */ +#define AFEINTSRC_ADCDIFFERR 0x00000040 /**< Bit6, ADC Delta Ready */ +#define AFEINTSRC_MEANRDY 0x00000080 /**< Bit7, Mean Result Ready */ +#define AFEINTSRC_VARRDY 0x00000100 /**< Bit8, Variance Result Ready */ +#define AFEINTSRC_CUSTOMINT0 \ + 0x00000200 /**< Bit9, Custom interrupt source 0. It happens when \ + **sequencer** writes 1 to register AFEGENINTSTA.BIT0 */ +#define AFEINTSRC_CUSTOMINT1 \ + 0x00000400 /**< Bit10, Custom interrupt source 1. It happens when \ + **sequencer** writes 1 to register AFEGENINTSTA.BIT1*/ +#define AFEINTSRC_CUSTOMINT2 \ + 0x00000800 /**< Bit11, Custom interrupt source 2. It happens when \ + **sequencer** writes 1 to register AFEGENINTSTA.BIT2 */ +#define AFEINTSRC_CUSTOMINT3 \ + 0x00001000 /**< Bit12, Custom interrupt source 3. It happens when \ + **sequencer** writes 1 to register AFEGENINTSTA.BIT3 */ +#define AFEINTSRC_BOOTLDDONE 0x00002000 /**< Bit13, OTP Boot Loading Done */ +#define AFEINTSRC_WAKEUP 0x00004000 /**< Bit14, AFE Woken up*/ +#define AFEINTSRC_ENDSEQ 0x00008000 /**< Bit15, End of Sequence Interrupt. */ +#define AFEINTSRC_SEQTIMEOUT \ + 0x00010000 /**< Bit16, Sequencer Timeout Command Finished. */ +#define AFEINTSRC_SEQTIMEOUTERR \ + 0x00020000 /**< Bit17, Sequencer Timeout Command Error. */ +#define AFEINTSRC_CMDFIFOFULL \ + 0x00040000 /**< Bit18, Command FIFO Full Interrupt. */ +#define AFEINTSRC_CMDFIFOEMPTY 0x00080000 /**< Bit19, Command FIFO Empty */ +#define AFEINTSRC_CMDFIFOTHRESH \ + 0x00100000 /**< Bit20, Command FIFO Threshold Interrupt. */ +#define AFEINTSRC_CMDFIFOOF \ + 0x00200000 /**< Bit21, Command FIFO Overflow Interrupt. */ +#define AFEINTSRC_CMDFIFOUF \ + 0x00400000 /**< Bit22, Command FIFO Underflow Interrupt. */ +#define AFEINTSRC_DATAFIFOFULL \ + 0x00800000 /**< Bit23, Data FIFO Full Interrupt. */ +#define AFEINTSRC_DATAFIFOEMPTY 0x01000000 /**< Bit24, Data FIFO Empty */ +#define AFEINTSRC_DATAFIFOTHRESH \ + 0x02000000 /**< Bit25, Data FIFO Threshold Interrupt. */ +#define AFEINTSRC_DATAFIFOOF \ + 0x04000000 /**< Bit26, Data FIFO Overflow Interrupt. */ +#define AFEINTSRC_DATAFIFOUF \ + 0x08000000 /**< Bit27, Data FIFO Underflow Interrupt. */ +#define AFEINTSRC_WDTIRQ 0x10000000 /**< Bit28, WDT Timeout Interrupt. */ +#define AFEINTSRC_CRC_OUTLIER \ + 0x20000000 /**< Bit29, CRC interrupt for M355, Outlier Int for AD5940 */ +#define AFEINTSRC_GPT0INT_SLPWUT \ + 0x40000000 /**< Bit30, Gneral Pupose Timer0 IRQ for M355. Sleep or Wakeup \ + Tiemr timeout for AD5940*/ +#define AFEINTSRC_GPT1INT_TRYBRK \ + 0x80000000 /**< Bit31, Gneral Pupose Timer1 IRQ for M355. Tried to Break \ + IRQ for AD5940*/ +#define AFEINTSRC_ALLINT 0xffffffff /**< mask of all interrupt */ +/** @} */ + +/** + * @defgroup AFEPWR_Const + * @brief AFE power mode. + * @details It will set the whole analog system power mode include HSDAC, + * Excitation Buffer, HSTIA, ADC front-buffer etc. + * @{ + */ +#define AFEPWR_LP \ + 0 /**< Set AFE to Low Power mode. For signal <80kHz, use it. */ +#define AFEPWR_HP \ + 1 /**< Set AFE to High Power mode. For signal >80kHz, use it. */ +/** + * @} + */ + +/** + * @defgroup AFEBW_Const + * @brief AFE system bandwidth. + * @details It will set the whole analog bandwidth include HSDAC, Excitation + * Buffer, HSTIA, ADC front-buffer etc. + * @{ + */ +#define AFEBW_AUTOSET \ + 0 /**< Set the bandwidth automatically based on WGFCW frequency word. */ +#define AFEBW_50KHZ 1 /**< 50kHZ system bandwidth(DAC/ADC) */ +#define AFEBW_100KHZ 2 /**< 100kHZ system bandwidth(DAC/ADC) */ +#define AFEBW_250KHZ 3 /**< 250kHZ system bandwidth(DAC/ADC) */ +/** + * @} + */ + +/** + * @defgroup AFECTRL_Const + * @brief AFE Control signal set. Bit masks for register AFECON. + * @details This is all the available control signal for function @ref + * AD5940_AFECtrlS + * @warning Bit field in register AFECON has some opposite meaning as below + * definitions. We use all positive word here like HPREF instead of HPREFDIS. + * This set is only used in function @ref AD5940_AFECtrlS, the second parameter + * decides whether enable it or disable it. + * @{ + */ +#define AFECTRL_HPREFPWR (1L << 5) /**< High power reference on-off control */ +#define AFECTRL_HSDACPWR (1L << 6) /**< High speed DAC on-off control */ +#define AFECTRL_ADCPWR (1L << 7) /**< ADC power on-off control */ +#define AFECTRL_ADCCNV (1L << 8) /**< Start ADC convert enable */ +#define AFECTRL_EXTBUFPWR (1L << 9) /**< Excitation buffer power control */ +#define AFECTRL_INAMPPWR \ + (1L << 10) /**< Excitation loop input amplifier before P/N node power \ + control */ +#define AFECTRL_HSTIAPWR \ + (1L << 11) /**< High speed TIA amplifier power control */ +#define AFECTRL_TEMPSPWR (1L << 12) /**< Temperature sensor power */ +#define AFECTRL_TEMPCNV (1L << 13) /**< Start Temperature sensor convert */ +#define AFECTRL_WG (1L << 14) /**< Waveform generator on-off control */ +#define AFECTRL_DFT (1L << 15) /**< DFT engine on-off control */ +#define AFECTRL_SINC2NOTCH (1L << 16) /**< SIN2+Notch block on-off control */ +#define AFECTRL_ALDOLIMIT (1L << 19) /**< ALDO current limit on-off control */ +#define AFECTRL_DACREFPWR \ + (1L << 20) /**< DAC reference buffer power control \ + */ +#define AFECTRL_DCBUFPWR \ + (1L << 21) /**< Excitation loop DC offset buffer sourced from LPDAC power \ + control */ +#define AFECTRL_ALL 0x39ffe0 /**< All control signals */ +/** + * @} + */ + +/** + * @defgroup LPMODECTRL_Const + * @brief LP Control signal(bit mask) for register LPMODECON + * @details This is all the available control signal for function @ref + * AD5940_LPModeCtrlS + * @warning Bit field in register LPMODECON has some opposite meaning as below + * definitions. We use all positive word here like HPREFPWR instead of HPREFDIS. + * This set is only used in function @ref AD5940_AFECtrlS, the second parameter + * decides whether enable or disable selected block(s). + * @{ + */ +#define LPMODECTRL_HFOSCEN \ + (1 << 0) /**< Enable internal HFOSC. Note: the register defination is set \ + this bit to 1 to disable it. */ +#define LPMODECTRL_HPREFPWR \ + (1 << 1) /**< High power reference power EN. Note: the register defination \ + is set this bit to 1 to disable it. */ +#define LPMODECTRL_ADCCNV (1 << 2) /**< Start ADC convert enable */ +#define LPMODECTRL_REPEATEN \ + (1 << 3) /**< Enable repeat convert function. This will enable ADC power \ + automatically */ +#define LPMODECTRL_GLBBIASZ \ + (1 << 4) /**< Enable Global ZTAT bias. Disable it to save more power */ +#define LPMODECTRL_GLBBIASP \ + (1 << 5) /**< Enable Global PTAT bias. Disable it to save more power */ +#define LPMODECTRL_BUFHP1P8V (1 << 6) /**< High power 1.8V reference buffer */ +#define LPMODECTRL_BUFHP1P1V (1 << 7) /**< High power 1.1V reference buffer */ +#define LPMODECTRL_ALDOPWR \ + (1 << 8) /**< Enable ALDO. Note: register defination is set this bit to 1 to \ + disable ALDO. */ +#define LPMODECTRL_ALL 0x1ff /**< All Control signal Or'ed together*/ +#define LPMODECTRL_NONE 0 /**< No blocks selected */ +/** @} */ + +/** + * @defgroup AFERESULT_Const + * @brief The available AFE results type. Used for function @ref + * AD5940_ReadAfeResult + * @{ + */ +#define AFERESULT_SINC3 0 /**< SINC3 result */ +#define AFERESULT_SINC2 1 /**< SINC2+NOTCH result */ +#define AFERESULT_TEMPSENSOR 2 /**< Temperature sensor result */ +#define AFERESULT_DFTREAL 3 /**< DFT Real result */ +#define AFERESULT_DFTIMAGE 4 /**< DFT Imaginary result */ +#define AFERESULT_STATSMEAN 5 /**< Statistic Mean result */ +#define AFERESULT_STATSVAR 6 /**< Statistic Variance result */ +/** @} */ + +/** + * @} AFE_Control_Const + * @} AFE_Control + * */ + +/** + * @addtogroup High_Speed_Loop + * @{ + * @defgroup High_Speed_Loop_Const + * @{ + */ + +/** + * @defgroup Switch_Matrix_Block_Const + * @{ + * @defgroup SWD_Const + * @brief Switch D set. This is bit mask for register DSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type + * The bit masks can be OR'ed together. For example + * - `SWD_AIN1|SWD_RCAL0` means close SWD_AIN1 and SWD_RCAL0 in same + * time, and open all other D switches. + * - `SWD_AIN2` means close SWD_AIN2 and open all other D switches. + * @{ + */ +#define SWD_OPEN (0 << 0) /**< Open all D switch. */ +#define SWD_RCAL0 (1 << 0) /**< pin RCAL0 */ +#define SWD_AIN1 (1 << 1) /**< Pin AIN1 */ +#define SWD_AIN2 (1 << 2) /**< Pin AIN2 */ +#define SWD_AIN3 (1 << 3) /**< Pin AIN3 */ +#define SWD_CE0 (1 << 4) /**< Pin CE0 */ +#define SWD_CE1 (1 << 5) /**< CE1 in ADuCM355 */ +#define SWD_AFE1 (1 << 5) /**< AFE1 in AD594x */ +#define SWD_SE0 (1 << 6) /**< Pin SE0 */ +#define SWD_SE1 (1 << 7) /**< SE1 in ADuCM355 */ +#define SWD_AFE3 (1 << 7) /**< AFE3 in AD594x */ +/** @} */ + +/** + * @defgroup SWP_Const + * @brief Switch P set. This is bit mask for register PSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type. + * The bit masks can be OR'ed together. For example + * - `SWP_RCAL0|SWP_AIN1` means close SWP_RCAL0 and SWP_AIN1 in same + * time, and open all other P switches. + * - `SWP_SE0` means close SWP_SE0 and open all other P switches. + * @{ + */ +#define SWP_OPEN 0 /**< Open all P switches */ +#define SWP_RCAL0 (1 << 0) /**< Pin RCAL0 */ +#define SWP_AIN1 (1 << 1) /**< Pin AIN1 */ +#define SWP_AIN2 (1 << 2) /**< Pin AIN2 */ +#define SWP_AIN3 (1 << 3) /**< Pin AIN3 */ +#define SWP_RE0 (1 << 4) /**< Pin RE0 */ +#define SWP_RE1 (1 << 5) /**< RE1 in ADuCM355 */ +#define SWP_AFE2 (1 << 5) /**< AFE2 in AD5940 */ +#define SWP_SE0 (1 << 6) /**< Pin SE0 */ +#define SWP_DE0 (1 << 7) /**< Pin DE0 */ +#define SWP_SE1 (1 << 8) /**< SE1 in ADuCM355 */ +#define SWP_AFE3 (1 << 8) /**< AFE3 in AD5940 */ +#define SWP_DE1 (1 << 9) /**< ADuCM355 Only. */ +#define SWP_CE0 (1 << 10) /**< Pin CE0 */ +#define SWP_CE1 (1 << 11) /**< CE1 in ADuCM355 */ +#define SWP_AFE1 (1 << 11) /**< AFE1 in AD5940 */ +#define SWP_PL (1 << 13) /**< Internal PL switch */ +#define SWP_PL2 (1 << 14) /**< Internal PL2 switch */ +/** @} */ + +/** + * @defgroup SWN_Const + * @brief Switch N set. This is bit mask for register NSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type. + * The bit masks can be OR'ed together. For example + * - `SWN_RCAL0|SWN_AIN1` means close SWN_RCAL0 and SWN_AIN1 in same + * time, and open all other N switches. + * - `SWN_SE0` means close SWN_SE0 and open all other N switches. + * @{ + */ +#define SWN_OPEN 0 /**< Open all N switches */ +#define SWN_RCAL1 (1 << 9) /**< Pin RCAL1 */ +#define SWN_AIN0 (1 << 0) /**< Pin AIN0 */ +#define SWN_AIN1 (1 << 1) /**< Pin AIN1 */ +#define SWN_AIN2 (1 << 2) /**< Pin AIN2 */ +#define SWN_AIN3 (1 << 3) /**< Pin AIN3 */ +#define SWN_SE0LOAD \ + (1 << 4) /**< SE0_LOAD is different from PIN SE0. It's the point after \ + 100Ohm load resistor */ +#define SWN_DE0LOAD (1 << 5) /**< DE0_Load is after Rload resistor */ +#define SWN_SE1LOAD (1 << 6) /**< SE1_LOAD in ADuCM355 */ +#define SWN_AFE3LOAD (1 << 6) /**< AFE3LOAD in ADuCM355 */ +#define SWN_DE1LOAD (1 << 7) /**< ADuCM355 Only*/ +#define SWN_SE0 (1 << 8) /**< SE0 here means the PIN SE0. */ +#define SWN_NL (1 << 10) /**< Internal NL switch */ +#define SWN_NL2 (1 << 11) /**< Internal NL2 switch */ +/** @} */ + +/** + * @defgroup SWT_Const + * @brief Switch T set. This is bit mask for register TSWFULLCON. + * @details + * It's used to initialize structure @ref SWMatrixCfg_Type. + * The bit masks can be OR'ed together. For example + * - SWT_RCAL0|SWT_AIN1 means close SWT_RCAL0 and SWT_AIN1 in same + * time, and open all other T switches. + * - SWT_SE0LOAD means close SWT_SE0LOAD and open all other T switches. + * @{ + */ +#define SWT_OPEN 0 /**< Open all T switches */ +#define SWT_RCAL1 (1 << 11) /**< Pin RCAL1 */ +#define SWT_AIN0 (1 << 0) /**< Pin AIN0 */ +#define SWT_AIN1 (1 << 1) /**< Pin AIN1 */ +#define SWT_AIN2 (1 << 2) /**< Pin AIN2 */ +#define SWT_AIN3 (1 << 3) /**< Pin AIN3 */ +#define SWT_SE0LOAD \ + (1 << 4) /**< SE0_LOAD is different from PIN SE0. It's the point after \ + 100Ohm load resistor */ +#define SWT_DE0 (1 << 5) /**< DE0 pin. */ +#define SWT_SE1LOAD (1 << 6) /**< SE1_LOAD on ADuCM355*/ +#define SWT_AFE3LOAD (1 << 6) /**< AFE3_LOAD on ADuCM355*/ +#define SWT_DE1 (1 << 7) /**< ADuCM355 Only*/ +#define SWT_TRTIA (1 << 8) /**< T9 switch. Connect RTIA to T matrix */ +#define SWT_DE0LOAD \ + (1 << 9) /**< DE0Load is the position after Rload Resisor \ + */ +#define SWT_DE1LOAD \ + (1 << 10) /**< DE1Load is the position after Rload Resisor */ +/** @} */ + +/** @} Switch_Matrix_Block_Const */ + +/** + * @defgroup Waveform_Generator_Block_Const + * @{ + */ +/** + * @defgroup WGTYPE_Const + * @brief Waveform generator signal type + * @{ + */ +#define WGTYPE_MMR 0 /**< Direct write to DAC using register */ +#define WGTYPE_SIN 2 /**< Sine wave generator */ +#define WGTYPE_TRAPZ 3 /**< Trapezoid generator */ +/** @} */ +/** @} Waveform_Generator_Block_Const */ + +/** + * @defgroup HSDAC_Block_Const + * @{ + */ +/* Excitation buffer gain selection */ +/** + * @defgroup EXCITBUFGAIN_Const + * @{ + */ +#define EXCITBUFGAIN_2 0 /**< Excitation buffer gain is x2 */ +#define EXCITBUFGAIN_0P25 1 /**< Excitation buffer gain is x1/4 */ +/** @} */ + +/** + * @defgroup HSDACGAIN_Const + * @{ + */ +/* HSDAC PGA Gain selection(DACCON.BIT0) */ +#define HSDACGAIN_1 0 /**< Gain is x1 */ +#define HSDACGAIN_0P2 1 /**< Gain is x1/5 */ +/** @} */ +/** @} */ // HSDAC_Block_Const + +/** + * @defgroup HSTIA_Block_Const + * @{ + * */ +/* HSTIA Amplifier Positive Input selection */ + +/** + * @defgroup HSTIABIAS_Const + * @warning When select Vzero0 as bias, close LPDAC switch + * @{ + */ +#define HSTIABIAS_1P1 \ + 0 /**< Internal 1.1V common voltage from internal 1.1V reference buffer */ +#define HSTIABIAS_VZERO0 1 /**< From LPDAC0 Vzero0 output */ +#define HSTIABIAS_VZERO1 \ + 2 /**< From LPDAC1 Vzero1 output. Only available on ADuCM355. */ +/** @} */ + +/* HSTIA Internal RTIA selection */ + +/** + * @defgroup HSTIARTIA_Const + * @{ + */ +#define HSTIARTIA_200 0 /**< HSTIA Internal RTIA resistor 200 */ +#define HSTIARTIA_1K 1 /**< HSTIA Internal RTIA resistor 1K */ +#define HSTIARTIA_5K 2 /**< HSTIA Internal RTIA resistor 5K */ +#define HSTIARTIA_10K 3 /**< HSTIA Internal RTIA resistor 10K */ +#define HSTIARTIA_20K 4 /**< HSTIA Internal RTIA resistor 20K */ +#define HSTIARTIA_40K 5 /**< HSTIA Internal RTIA resistor 40K */ +#define HSTIARTIA_80K 6 /**< HSTIA Internal RTIA resistor 80K */ +#define HSTIARTIA_160K 7 /**< HSTIA Internal RTIA resistor 160K */ +#define HSTIARTIA_OPEN 8 /**< Open internal resistor */ +/** @} */ + +/** + * @defgroup HSTIADERTIA_Const + * @{ + */ +#define HSTIADERTIA_50 0 /**< 50Ohm Settings depends on RLOAD resistor. */ +#define HSTIADERTIA_100 1 /**< 100Ohm Settings depends on RLOAD resistor.*/ +#define HSTIADERTIA_200 2 /**< 200Ohm Settings depends on RLOAD resistor.*/ +#define HSTIADERTIA_1K 3 /**< set bit[7:3] to 0x0b(11) */ +#define HSTIADERTIA_5K 4 /**< set bit[7:3] to 0x0c(12) */ +#define HSTIADERTIA_10K 5 /**< set bit[7:3] to 0x0d(13) */ +#define HSTIADERTIA_20K 6 /**< set bit[7:3] to 0x0e(14) */ +#define HSTIADERTIA_40K 7 /**< set bit[7:3] to 0x0f(15) */ +#define HSTIADERTIA_80K 8 /**< set bit[7:3] to 0x10(16) */ +#define HSTIADERTIA_160K 9 /**< set bit[7:3] to 0x11(17) */ +#define HSTIADERTIA_TODE \ + 10 /**< short HSTIA output to DE0 pin. set bit[7:3] to 0x12(18) */ +#define HSTIADERTIA_OPEN \ + 11 /**< Default state is set to OPEN RTIA by setting bit[7:3] to 0x1f */ +/** @} */ + +/* HSTIA DE0 Terminal internal RLOAD selection */ +/** + * @defgroup HSTIADERLOAD_Const + * @{ + */ +#define HSTIADERLOAD_0R 0 /**< set bit[2:0] to 0x00 */ +#define HSTIADERLOAD_10R 1 /**< set bit[2:0] to 0x01 */ +#define HSTIADERLOAD_30R 2 /**< set bit[2:0] to 0x02 */ +#define HSTIADERLOAD_50R 3 /**< set bit[2:0] to 0x03 */ +#define HSTIADERLOAD_100R 4 /**< set bit[2:0] to 0x04 */ +#define HSTIADERLOAD_OPEN \ + 5 /**< RLOAD open means open switch between HSTIA negative input and Rload \ + resistor().Default state is OPEN RLOAD by setting \ + HSTIARES03CON[2:0] to 0x5, 0x6 or 0x7 */ +/** @} */ + +/** + * @defgroup HSTIAPWRMOE_Const + * @{ + */ +#define HSTIAPWRMOE_LP 0 /**< HSTIA in LP mode */ +#define HSTIAPWRMOE_HP 1 /**< HSTIA in HP mode */ +/** @} */ + +/** @} HSTIA_Block_Const */ +/** + * @} High_Speed_Loop_Const + * @} High_Speed_Loop + */ + +/** + * @addtogroup Low_Power_Loop + * Low power includes low power DAC and two low power amplifiers(PA and TIA) + * @{ + * @defgroup Low_Power_Loop_Const + * The constant used in Low power loop. + * @{ + */ + +/** + * @defgroup LPDAC_Block_Const + * @{ + * */ +/** + * @defgroup LPDAC_Const + * Select which LPDAC is accessing. + * @note This parameter must be configured correctly + * @{ + */ +#define LPDAC0 0 /**< LPDAC0 */ +#define LPDAC1 1 /**< LPDAC1, ADuCM355 Only */ +/** @} */ +/** + * @defgroup LPDACSRC_Const + * LPDAC data source selection. Either from MMR or from waveform generator. + * @{ + */ +#define LPDACSRC_MMR 0 /**< Get data from register REG_AFE_LPDACDAT0DATA0 */ +#define LPDACSRC_WG 1 /**< Get data from waveform generator */ +/** @} */ + +/** + * @defgroup LPDACSW_Const + * @brief LPDAC switch settings + * @{ + */ +#define LPDACSW_VBIAS2LPPA \ + 0x10 /**< switch between LPDAC Vbias output and LPPA(low power PA(Potential \ + Amplifier)) */ +#define LPDACSW_VBIAS2PIN \ + 0x08 /**< Switch between LPDAC Vbias output and Vbias pin */ +#define LPDACSW_VZERO2LPTIA \ + 0x04 /**< Switch between LPDAC Vzero output and LPTIA positive input */ +#define LPDACSW_VZERO2PIN \ + 0x02 /**< Switch between LPDAC Vzero output and Vzero pin */ +#define LPDACSW_VZERO2HSTIA \ + 0x01 /**< Switch between LPDAC Vzero output and HSTIA positive input MUX */ +/** @} */ + +/** + * @defgroup LPDACVZERO_Const + * @brief Vzero MUX selection + * @{ + */ +#define LPDACVZERO_6BIT 0 /**< Connect Vzero to 6bit LPDAC output */ +#define LPDACVZERO_12BIT 1 /**< Connect Vzero to 12bit LPDAC output */ +/** @} */ + +/** + * @defgroup LPDACVBIAS_Const + * @brief Vbias MUX selection + * @{ + */ +#define LPDACVBIAS_6BIT 1 /**< Connect Vbias to 6bit LPDAC output */ +#define LPDACVBIAS_12BIT 0 /**< Connect Vbias to 12bit LPDAC output */ +/** @} */ + +/** + * @defgroup LPDACREF_Const + * @brief LPDAC reference selection + * @{ + */ +#define LPDACREF_2P5 0 /**< Internal 2.5V reference */ +#define LPDACREF_AVDD 1 /**< Use AVDD as reference */ +/** @} */ + +/** @} */ // LPDAC_Block_Const + +/** + * @defgroup LPAMP_Block_Const + * @brief Low power amplifies include potential-state amplifier(PA in short) and + * TIA. + * @{ + * */ + +/** + * @defgroup LPTIA_Const + * @brief LPTIA selecion + * @{ + * */ +#define LPTIA0 0 /**< LPTIA0 */ +#define LPTIA1 1 /**< LPTIA1, ADuCM355 Only */ +/** @} */ + +/** + * @defgroup LPTIARF_Const + * @brief LPTIA LPF Resistor selection + * @{ + * */ +#define LPTIARF_OPEN 0 /**< Disconnect Rf resistor */ +#define LPTIARF_SHORT 1 /**< Bypass Rf resistor */ +#define LPTIARF_20K 2 /**< 20kOhm Rf */ +#define LPTIARF_100K 3 /**< Rf resistor 100kOhm */ +#define LPTIARF_200K 4 /**< Rf resistor 200kOhm */ +#define LPTIARF_400K 5 /**< Rf resistor 400kOhm */ +#define LPTIARF_600K 6 /**< Rf resistor 600kOhm */ +#define LPTIARF_1M 7 /**< Rf resistor 1MOhm */ +/** @} */ + +/** + * @defgroup LPTIARLOAD_Const + * @brief LPTIA Rload Selection + * @{ + */ +#define LPTIARLOAD_SHORT 0 /**< 0Ohm Rload */ +#define LPTIARLOAD_10R 1 /**< 10Ohm Rload */ +#define LPTIARLOAD_30R 2 /**< Rload resistor 30Ohm */ +#define LPTIARLOAD_50R 3 /**< Rload resistor 50Ohm */ +#define LPTIARLOAD_100R 4 /**< Rload resistor 100Ohm */ +#define LPTIARLOAD_1K6 5 /**< Only available when RTIA setting >= 2KOHM */ +#define LPTIARLOAD_3K1 6 /**< Only available when RTIA setting >= 4KOHM */ +#define LPTIARLOAD_3K6 7 /**< Only available when RTIA setting >= 4KOHM */ +/** @} */ + +/** + * @defgroup LPTIARTIA_Const + * @brief LPTIA RTIA Selection + * @note The real RTIA resistor value dependents on Rload settings. + * @{ + */ +#define LPTIARTIA_OPEN 0 /**< Disconnect LPTIA Internal RTIA */ +#define LPTIARTIA_200R 1 /**< 200Ohm Internal RTIA */ +#define LPTIARTIA_1K 2 /**< 1KOHM */ +#define LPTIARTIA_2K 3 /**< 2KOHM */ +#define LPTIARTIA_3K 4 /**< 3KOHM */ +#define LPTIARTIA_4K 5 /**< 4KOHM */ +#define LPTIARTIA_6K 6 /**< 6KOHM */ +#define LPTIARTIA_8K 7 /**< 8KOHM */ +#define LPTIARTIA_10K 8 /**< 10KOHM */ +#define LPTIARTIA_12K 9 /**< 12KOHM */ +#define LPTIARTIA_16K 10 /**< 16KOHM */ +#define LPTIARTIA_20K 11 /**< 20KOHM */ +#define LPTIARTIA_24K 12 /**< 24KOHM */ +#define LPTIARTIA_30K 13 /**< 30KOHM */ +#define LPTIARTIA_32K 14 /**< 32KOHM */ +#define LPTIARTIA_40K 15 /**< 40KOHM */ +#define LPTIARTIA_48K 16 /**< 48KOHM */ +#define LPTIARTIA_64K 17 /**< 64KOHM */ +#define LPTIARTIA_85K 18 /**< 85KOHM */ +#define LPTIARTIA_96K 19 /**< 96KOHM */ +#define LPTIARTIA_100K 20 /**< 100KOHM */ +#define LPTIARTIA_120K 21 /**< 120KOHM */ +#define LPTIARTIA_128K 22 /**< 128KOHM */ +#define LPTIARTIA_160K 23 /**< 160KOHM */ +#define LPTIARTIA_196K 24 /**< 196KOHM */ +#define LPTIARTIA_256K 25 /**< 256KOHM */ +#define LPTIARTIA_512K 26 /**< 512KOHM */ +/** @} */ + +/** + * @defgroup LPAMP_Const + * LPAMP selecion. On AD594x, only LPAMP0 is available. + * @note This parameter must be configured correctly. + * @{ + * */ +#define LPAMP0 \ + 0 /**< LPAMP0, AMP include both LPTIA and Potentio-stat amplifiers */ +#define LPAMP1 1 /**< LPAMP1, ADuCM355 Only */ +/** @} */ + +/** + * @defgroup LPAMPPWR_Const + * @brief Low power amplifier(PA and TIA) power mode selection. + * @{ + */ +#define LPAMPPWR_NORM 0 /**< Normal Power mode */ +#define LPAMPPWR_BOOST1 1 /**< Boost power to level 1 */ +#define LPAMPPWR_BOOST2 2 /**< Boost power to level 2 */ +#define LPAMPPWR_BOOST3 3 /**< Boost power to level 3 */ +#define LPAMPPWR_HALF 4 /**< Put PA and TIA in half power mode */ +/** @} */ + +#define LPTIASW(n) \ + (1L << n) /**< LPTIA switch control. Use this macro to set LpTiaSW field of \ + @ref LPAmpCfg_Type */ + +/** + * @} LPAMP_Block_Const + * @} Low_Power_Loop_Const + * @} Low_Power_Loop + * + * */ + +/** + * @addtogroup DSP_Block + * DSP block include signal chain from raw ADC data to various filters, DFT + * engine and Statistic Functions etc. + * @{ + * @defgroup DSP_Block_Const + * @{ + * @defgroup ADC_Block_Const + * @{ + */ + +/** + * @defgroup ADCPGA_Const + * @brief ADC PGA Selection + * @note Only gain 1.5 is factory calibrated. + * @{ + */ +#define ADCPGA_1 0 /**< ADC PGA Gain of 1 */ +#define ADCPGA_1P5 1 /**< ADC PGA Gain of 1.5 */ +#define ADCPGA_2 2 /**< ADC PGA Gain of 2 */ +#define ADCPGA_4 3 /**< ADC PGA Gain of 4 */ +#define ADCPGA_9 4 /**< ADC PGA Gain of 9 */ +#define IS_ADCPGA(pga) (((pga) == ADCPGA_1) ||\ + (pga) == ADCPGA_1P5) ||\ + (pga) == ADCPGA_2) ||\ + (pga) == ADCPGA_4) ||\ + (pga) == ADCPGA_9)) +/** + * @} + * */ + +/** + * @defgroup ADCMUXP_Const + * @brief ADC Channel P Configuration + * @{ + */ +#define ADCMUXP_FLOAT 0x0 /**< float */ +#define ADCMUXP_HSTIA_P 0x1 /**< output of HSTIA */ +#define ADCMUXP_AIN0 0x4 /**< pin AIN0 */ +#define ADCMUXP_AIN1 0x5 /**< pin AIN1 */ +#define ADCMUXP_AIN2 0x6 /**< pin AIN2 */ +#define ADCMUXP_AIN3 0x7 /**< pin AIN3 */ +#define ADCMUXP_AVDD_2 0x8 /**< AVDD/2 */ +#define ADCMUXP_DVDD_2 0x9 /**< DVDD/2 */ +#define ADCMUXP_AVDDREG \ + 0xA /**< AVDD internal regulator output. It's around 1.8V */ +#define ADCMUXP_TEMPP 0xB /**< Internal temperature output postive terminal */ +#define ADCMUXP_VSET1P1 0xC /**< Internal 1.1V bias voltage */ +#define ADCMUXP_VDE0 0xD /**< Voltage of DE0 pin */ +#define ADCMUXP_VSE0 0xE /**< Voltage of SE0 pin */ +#define ADCMUXP_VSE1 0xF /**< Voltage of SE1 pin on ADuCM355 */ +#define ADCMUXP_VAFE3 0xF /**< Voltage of AFE3 pin on AD5940. */ +#define ADCMUXP_VREF2P5 \ + 0x10 /**< 1.25V. The internal 2.5V reference buffer output divided by 2. */ +#define ADCMUXP_VREF1P8DAC \ + 0x12 /**< HSDAC 1.8V internal reference. It's only available when both \ + AFECON.BIT20 and AFECON.BIT6 are set. */ +#define ADCMUXP_TEMPN \ + 0x13 /**< Internal temperature output negative terminal \ + */ +#define ADCMUXP_AIN4 0x14 /**< Voltage of AIN4/LPF0 pin */ +#define ADCMUXP_AIN5 0x15 /**< Voltage of AIN5 pin */ +#define ADCMUXP_AIN6 0x16 /**< Voltage of AIN6 pin, not available on AD5941 */ +#define ADCMUXP_VZERO0 0x17 /**< Voltage of Vzero0 pin */ +#define ADCMUXP_VBIAS0 0x18 /**< Voltage of Vbias0 pin */ +#define ADCMUXP_VCE0 0x19 /**< Pin CE0 */ +#define ADCMUXP_VRE0 0x1A /**< Pin RE0 */ +#define ADCMUXP_VZERO1 0x1B /**< Voltage of Vzero1 pin on ADuCM355 */ +#define ADCMUXP_VAFE4 0x1B /**< Voltage of AFE4 pin on AD5940. */ +#define ADCMUXP_VBIAS1 0x1C /**< Voltage of Vbias1 pin */ +#define ADCMUXP_VCE1 0x1D /**< Voltage of CE1 pin on ADuCM355. */ +#define ADCMUXP_VAFE1 0x1D /**< Voltage of AFE1 pin on AD5940. */ +#define ADCMUXP_VRE1 0x1E /**< Voltage of RE1 pin on ADuCM355. */ +#define ADCMUXP_VAFE2 0x1E /**< Voltage of AFE2 pin on AD5940. */ +#define ADCMUXP_VCE0_2 0x1F /**< VCE0 divide by 2 */ +#define ADCMUXP_VCE1_2 0x20 /**< VCE1 divide by 2 */ +#define ADCMUXP_LPTIA0_P 0x21 /**< Output of LPTIA0 */ +#define ADCMUXP_LPTIA1_P 0x22 /**< Output of LPTIA1 */ +#define ADCMUXP_AGND 0x23 /**< Internal AGND node */ +#define ADCMUXP_P_NODE \ + 0x24 /**< Buffered voltage of excitation buffer P node. */ +#define ADCMUXP_IOVDD_2 0x27 /**< IOVDD/2 */ +/**@}*/ + +/** + * @defgroup ADCMUXN_Const + * @brief ADC Channel N Configuration + * @{ + */ +#define ADCMUXN_FLOAT 0x0 /**< float */ +#define ADCMUXN_HSTIA_N 0x1 /**< HSTIA negative input node. */ +#define ADCMUXN_LPTIA0_N 0x2 /**< LPTIA0 negative input node. */ +#define ADCMUXN_LPTIA1_N 0x3 /**< LPTIA1 negative input node. */ +#define ADCMUXN_AIN0 0x4 /**< Pin AIN0 */ +#define ADCMUXN_AIN1 0x5 /**< Pin AIN1 */ +#define ADCMUXN_AIN2 0x6 /**< Pin AIN2 */ +#define ADCMUXN_AIN3 0x7 /**< Pin AIN3 */ +#define ADCMUXN_VSET1P1 0x8 /**< Internal 1.11V reference */ +#define ADCMUXN_VREF1P1 \ + 0x8 /**< Internal 1.11V reference, same as ADCMUXN_VSET1P1 */ +#define ADCMUXN_TEMPN 0xB /**< Temperature sensor output. */ +#define ADCMUXN_AIN4 0xC /**< AIN4 */ +#define ADCMUXN_AIN5 0xD /**< AIN5 */ +#define ADCMUXN_AIN6 0xE /**< AIN6 */ +#define ADCMUXN_VZERO0 0x10 /**< pin Vzero0 */ +#define ADCMUXN_VBIAS0 0x11 /**< pin Vbias0 */ +#define ADCMUXN_VZERO1 0x12 /**< pin Vzero1 */ +#define ADCMUXN_AFE4 0x12 /**< Pin AFE4 on AD5940. */ +#define ADCMUXN_VBIAS1 0x13 /**< pin Vbias1 */ +#define ADCMUXN_N_NODE \ + 0x14 /**< Buffered voltage of excitation buffer N node. */ +/** @} */ + +/** + * @defgroup ADCRATE_Const + * @brief ADC Current Sample Rate. If ADC clock is 32MHz, set it to + * ADCRATE_1P6MHZ. Otherwise, set it to ADCRATE_800KHZ. + * @{ + */ +#define ADCRATE_800KHZ \ + 1 /**< ADC input clock is 16MHz, sample rate is 800kHz \ + */ +#define ADCRATE_1P6MHZ \ + 0 /**< ADC input clock is 32MHz, sample rate is 1.6MHz \ + */ +#define IS_ADCRATE(rate) (((rate) == ADCRATE_800KHZ) ||\ + (rate) == ADCRATE_1P6MHZ)) +/** @} */ + +/** + * @defgroup ADCSINC3OSR_Const + * @brief ADC SINC3 Filter OSR. 2, 4 is recommended value. 5 is not recommended. + * @{ + */ +#define ADCSINC3OSR_2 2 /**< ADC SINC3 OSR 2 */ +#define ADCSINC3OSR_4 1 /**< ADC SINC3 OSR 4 */ +#define ADCSINC3OSR_5 0 /**< ADC SINC3 OSR 5 */ +#define IS_ADCSINC3OSR(osr) (((osr) == ADCSINC3OSR_2) ||\ + (osr) == ADCSINC3OSR_4) ||\ + (osr) == ADCSINC3OSR_5)) /**< checker of ADCSINC3OSR */ +/** @} */ + +/** + * @defgroup ADCSINC2OSR_Const + * @brief ADC SINC2 Filter OSR. + * @{ + */ +#define ADCSINC2OSR_22 0 /**< ADC SINC2 OSR 22 */ +#define ADCSINC2OSR_44 1 /**< ADC SINC2 OSR 44 */ +#define ADCSINC2OSR_89 2 /**< ADC SINC2 OSR 89 */ +#define ADCSINC2OSR_178 3 /**< ADC SINC2 OSR 178 */ +#define ADCSINC2OSR_267 4 /**< ADC SINC2 OSR 267 */ +#define ADCSINC2OSR_533 5 /**< ADC SINC2 OSR 533 */ +#define ADCSINC2OSR_640 6 /**< ADC SINC2 OSR 640 */ +#define ADCSINC2OSR_667 7 /**< ADC SINC2 OSR 667 */ +#define ADCSINC2OSR_800 8 /**< ADC SINC2 OSR 800 */ +#define ADCSINC2OSR_889 9 /**< ADC SINC2 OSR 889 */ +#define ADCSINC2OSR_1067 10 /**< ADC SINC2 OSR 1067 */ +#define ADCSINC2OSR_1333 11 /**< ADC SINC2 OSR 1333 */ +#define IS_ADCSINC2OSR(osr) (((osr) == ADCSINC2OSR_22) ||\ + (osr) == ADCSINC2OSR_44) ||\ + (osr) == ADCSINC2OSR_89) ||\ + (osr) == ADCSINC2OSR_178) ||\ + (osr) == ADCSINC2OSR_267) ||\ + (osr) == ADCSINC2OSR_533) ||\ + (osr) == ADCSINC2OSR_640) ||\ + (osr) == ADCSINC2OSR_667) ||\ + (osr) == ADCSINC2OSR_800) ||\ + (osr) == ADCSINC2OSR_889) ||\ + (osr) == ADCSINC2OSR_1067) ||\ + (osr) == ADCSINC2OSR_1333)) /**< checker of ADCSINC2OSR */ +/** @} */ + +/** + * @defgroup ADCAVGNUM_Const + * @brief ADC Average filter for DFT. The average block locates after SINC3 + * filter. The output of average filter is directly feed into DFT block. + * @warning Once average filter is enabled, DFT source is automatically changed + * to averaged data. + * @{ + */ +#define ADCAVGNUM_2 0 /**< Take 2 input to do average. */ +#define ADCAVGNUM_4 1 /**< Take 4 input to do average. */ +#define ADCAVGNUM_8 2 /**< Take 8 input to do average. */ +#define ADCAVGNUM_16 3 /**< Take 16 input to do average. */ +#define IS_ADCAVGNUM(num) (((num) == ADCAVGNUM_2) ||\ + (num) == ADCAVGNUM_4) ||\ + (num) == ADCAVGNUM_8) ||\ + (num) == ADCAVGNUM_16)) /**< checker of ADCAVGNUM macro */ +/** @} */ + +/** @} ADC_Block_Const */ + +/** + * @defgroup DFT_Block_Const + * @{ + * */ + +/** + * @defgroup DFTSRC_Const + * @brief DFT source selection. When average function is enabled, DFT source + * automatically switch to average output. + * @{ + * */ +#define DFTSRC_SINC2NOTCH \ + 0 /**< SINC2+Notch filter block output. Bypass Notch to use SINC2 data */ +#define DFTSRC_SINC3 1 /**< SINC3 filter */ +#define DFTSRC_ADCRAW 2 /**< Raw ADC data */ +#define DFTSRC_AVG 3 /**< Average output of SINC3. */ +/** @} */ + +/** + * @defgroup DFTNUM_Const + * @brief DFT number selection. + * @{ + * */ +#define DFTNUM_4 0 /**< 4 Point */ +#define DFTNUM_8 1 /**< 8 Point */ +#define DFTNUM_16 2 /**< 16 Point */ +#define DFTNUM_32 3 /**< 32 Point */ +#define DFTNUM_64 4 /**< 64 Point */ +#define DFTNUM_128 5 /**< 128 Point */ +#define DFTNUM_256 6 /**< 256 Point */ +#define DFTNUM_512 7 /**< 512 Point */ +#define DFTNUM_1024 8 /**< 1024 Point */ +#define DFTNUM_2048 9 /**< 2048 Point */ +#define DFTNUM_4096 10 /**< 4096 Point */ +#define DFTNUM_8192 11 /**< 8192 Point */ +#define DFTNUM_16384 12 /**< 16384 Point */ +/** @} */ + +/** + * @} DFT_Block_Const + */ + +/** + * @defgroup Statistic_Block_Const + * @{ + */ +/** + * @defgroup STATSAMPLE_Const + * @brief The statistic module sample size. It decides how much data is used to + * do calculation. + * @{ + */ +#define STATSAMPLE_128 0 /**< Sample size 128 */ +#define STATSAMPLE_64 1 /**< Sample size 64 */ +#define STATSAMPLE_32 2 /**< Sample size 32 */ +#define STATSAMPLE_16 3 /**< Sample size 16 */ +#define STATSAMPLE_8 4 /**< Sample size 8 */ +/** @} */ + +/* Statistic standard deviation configure */ +/** + * @defgroup STATDEV_Const + * @brief The standard deviation configure + * @{ + */ +#define STATDEV_1 1 /**< Used for check outlier of ADC result */ +#define STATDEV_4 4 /**< Used for check outlier of ADC result */ +#define STATDEV_9 9 /**< Used for check outlier of ADC result */ +#define STATDEV_16 16 /**< Used for check outlier of ADC result */ +#define STATDEV_25 25 /**< Used for check outlier of ADC result */ +/** @} */ + +/** + * @} Statistic_Block_Const + * @} DSP_Block_Const + * @} DSP_Block + * + */ + +/** + * @addtogroup Sequencer_FIFO + * @{ + * @defgroup Sequencer_FIFO_Const + * @brief This block includes sequencer and FIFO related all parameters. + * @{ + */ + +/** + * @defgroup SEQID_Const + * @{ + */ +#define SEQID_0 0 /**< Sequence0 */ +#define SEQID_1 1 /**< Sequence1 */ +#define SEQID_2 2 /**< Sequence2 */ +#define SEQID_3 3 /**< Sequence3 */ +/** @} */ + +/** + * @defgroup SEQID_Const + * @brief Sequencer memory size. SRAM is shared between FIFO and Sequencer + * @warning The total available SRAM is 6kB. It's shared by FIFO and sequencer. + * @{ + */ +#define SEQMEMSIZE_32B \ + 0 /**< The selfbuild in 32Byte for sequencer. All 6kB SRAM can be used for \ + data FIFO */ +#define SEQMEMSIZE_2KB \ + 1 /**< Sequencer use 2kB. The reset 4kB can be used for data FIFO */ +#define SEQMEMSIZE_4KB 2 /**< 4kB for Sequencer. 2kB for data FIFO */ +#define SEQMEMSIZE_6KB \ + 3 /**< All 6kB for Sequencer. Build in 32Bytes memory can be used for data \ + FIFO */ +/** @} */ + +/* Mode of GPIO detecting used for triggering sequence */ +/** + * @defgroup SEQPINTRIGMODE_Const + * @{ + */ +#define SEQPINTRIGMODE_RISING 0 /**< Rising edge */ +#define SEQPINTRIGMODE_FALLING 1 /**< Falling edge */ +#define SEQPINTRIGMODE_BOTHEDGE 2 /**< Rising or falling */ +#define SEQPINTRIGMODE_HIGHL 3 /**< High level */ +#define SEQPINTRIGMODE_LOWL 4 /**< Low level */ +/** @} */ + +/* Sequencer helper */ +/** + * @defgroup Sequencer_Helper + * @{ + */ + +/* Three kinds of sequencer commands: wait, time-out, write */ +/* Decoded by BIT[31:30] */ +/** + * Wait command. Wait some clocks-code Command Code: 'b00 + * @warning Maximum wait time is 0x3fff_ffff/System clock. + */ +#define SEQ_WAIT(ClkNum) (0x00000000 | ((uint32_t)(ClkNum) & 0x3fffffff)) + +/** + * Time-Out command. Set time-out count down value. Command Code: 'b01 + * @warning maximum time-out timer value is 0x3fffffff + * */ +#define SEQ_TOUT(ClkNum) (0x40000000 | ((uint32_t)(ClkNum) & 0x3fffffff)) + +/** + * Write register command. Command Code: 'b10 or 'b11 + * @warning Address range is 0x2000 to 0x21FF. Data is limited to 24bit width. + * */ +#define SEQ_WR(addr, data) \ + (0x80000000 | (((((uint32_t)(addr)) >> 2) & 0x7f) << 24) | \ + (((uint32_t)(data)) & 0xffffff)) + +/* Some commands used frequently */ +#define SEQ_NOP() \ + SEQ_WAIT(0) /**< SEQ_NOP is just a simple wait command that wait one system \ + clock */ +#define SEQ_HALT() \ + SEQ_WR(REG_AFE_SEQCON, 0x12) /**< Can halt sequencer. Used for debug */ +#define SEQ_STOP() \ + SEQ_WR(REG_AFE_SEQCON, 0x00) /**< Disable sequencer, this will generate End \ + of Sequence interrupt */ + +#define SEQ_SLP() \ + SEQ_WR(REG_AFE_SEQTRGSLP, 1) /**< Trigger sleep. If sleep is allowed, AFE \ + will go to sleep/hibernate mode */ + +#define SEQ_INT0() \ + SEQ_WR(REG_AFE_AFEGENINTSTA, (1L << 0)) /**< Generate custom interrupt 0 */ +#define SEQ_INT1() \ + SEQ_WR(REG_AFE_AFEGENINTSTA, (1L << 1)) /**< Generate custom interrupt 1 */ +#define SEQ_INT2() \ + SEQ_WR(REG_AFE_AFEGENINTSTA, (1L << 2)) /**< Generate custom interrupt 2 */ +#define SEQ_INT3() \ + SEQ_WR(REG_AFE_AFEGENINTSTA, (1L << 3)) /**< Generate custom interrupt 3 */ + +/* Helper to calculate sequence length in array */ +#define SEQ_LEN(n) \ + (sizeof(n) / 4) /**< Calculate how many commands are in sepecified array. */ +/** @} */ // Sequencer_Helper + +/* FIFO */ +/** + * @defgroup FIFOMODE_Const + * @{ + */ +#define FIFOMODE_FIFO \ + 2 /**< Standard FIFO mode. If FIFO is full, reject all comming data and put \ + FIFO to fault state, report interrupt if enabled */ +#define FIFOMODE_STREAM \ + 3 /**< Stream mode. If FIFO is full, discard older data. Report FIFO full \ + interrupt if enabled */ +/** @} */ + +/** + * @defgroup FIFOSRC_Const + * @{ + */ +#define FIFOSRC_SINC3 0 /**< SINC3 data */ +#define FIFOSRC_DFT 2 /**< DFT real and imaginary part */ +#define FIFOSRC_SINC2NOTCH \ + 3 /**< SINC2+NOTCH block. Notch can be bypassed, so SINC2 data can be feed \ + to FIFO */ +#define FIFOSRC_VAR 4 /**< Statistic variarance output */ +#define FIFOSRC_MEAN 5 /**< Statistic mean output */ +/** @} */ + +/** + * @defgroup FIFO_Helper + * @{ + */ +/** + * Method to identify FIFO channel ID: + * [31:25][24:23][22:16][15:0] + * [ ECC ][SEQID][CH_ID][DATA] + * + * CH_ID: [22:16] 7bit in total: + * xxxxx_xx + * 11111_xx : DFT results + * 11110_xx : Mean of statistic block + * 11101_xx : Variance of statistic block + * 1xxxx_xx : Notch filter result, where xxx_xx is the ADC MUX P + * settings(6bits of reg ADCCON[5:0]). 0xxxx_xx : SINC3 filter result, where + * xxx_xx is the ADC MUX P settings(6bits of reg ADCCON[5:0]). + */ +#define FIFO_SEQID(data) \ + ((((uint32_t)data) >> 23) & 0x3) /**< Return seqid of this FIFO result */ +#define FIFO_ECC(data) \ + ((((uint32_t)data) >> 25) & 0x7f) /**< Return ECC of this FIFO result */ +#define FIFO_CHANID(data) \ + ((((uint32_t)data) >> 16) & 0x7f) /**< Return Channel ID */ +#define FIFOCHANID_MUXP(data) \ + ((((uint32_t)data) >> 16) & 0x3f) /**< Return the ADC MUXP selection */ + +#define ISCHANID_DFT(data) \ + ((((((uint32_t)data) >> 18) & 0x1f) == 0x1f) \ + ? bTRUE \ + : bFALSE) /**< If the channel id is DFT */ +#define ISCHANID_MEAN(data) \ + ((((((uint32_t)data) >> 18) & 0x1f) == 0x1e) \ + ? bTRUE \ + : bFALSE) /**< If the channel id is MEAN */ +#define ISCHANID_VAR(data) \ + ((((((uint32_t)data) >> 18) & 0x1f) == 0x1d) \ + ? bTRUE \ + : bFALSE) /**< If the channel id is Variance */ +#define ISCHANID_SINC3(data) \ + ((((((uint32_t)data) >> 18) & 0x1f) < 0x10) \ + ? bTRUE \ + : bFALSE) /**< If the channel id is SINC3 */ +#define ISCHANID_NOTCH(data) \ + ((((((uint32_t)data) >> 18) & 0x1f) >= 0x10) && \ + (((((uint32_t)data >> 18) & 0x1f) < 0x1d) \ + ? bTRUE \ + : bFALSE)) /**< If the channel id is Notch */ +/** @} */ + +/** + * @defgroup FIFOSIZE_Const + * @brief Set FIFO size. + * @warning The total available SRAM is 6kB. It's shared by FIFO and sequencer. + * @{ + */ +#define FIFOSIZE_32B \ + 0 /**< The selfbuild in 32Byte for data FIFO. All 6kB SRAM for sequencer */ +#define FIFOSIZE_2KB \ + 1 /**< DATA FIFO use 2kB. The reset 4kB is used for sequencer */ +#define FIFOSIZE_4KB 2 /**< 4kB for Data FIFO. 2kB for sequencer */ +#define FIFOSIZE_6KB \ + 3 /**< All 6kB for Data FIFO. Build in 32Bytes memory for sequencer */ +/** @} */ + +/* Wake up timer */ +/** + * @defgroup WUPTENDSEQ_Const + * @{ + */ +#define WUPTENDSEQ_A 0 /**< End at slot A */ +#define WUPTENDSEQ_B 1 /**< End at slot B */ +#define WUPTENDSEQ_C 2 /**< End at slot C */ +#define WUPTENDSEQ_D 3 /**< End at slot D */ +#define WUPTENDSEQ_E 4 /**< End at slot E */ +#define WUPTENDSEQ_F 5 /**< End at slot F */ +#define WUPTENDSEQ_G 6 /**< End at slot G */ +#define WUPTENDSEQ_H 7 /**< End at slot H */ +/** @} */ + +/** + * @} End of sequencer_and_FIFO block + * @} Sequencer_FIFO + * */ + +/** + * @addtogroup MISC_Block + * @{ + * @defgroup MISC_Block_Const + * @brief This block includes clock, GPIO, configuration. + * @{ + */ + +/* Helper for calculate clocks needed for various of data type */ +/** + * @defgroup DATATYPE_Const + * @{ + */ +#define DATATYPE_ADCRAW 0 /**< ADC raw data */ +#define DATATYPE_SINC3 1 /**< SINC3 data */ +#define DATATYPE_SINC2 2 /**< SINC2 Data */ +#define DATATYPE_DFT 3 /**< DFT */ +#define DATATYPE_NOTCH \ + 4 /**< Notch filter output. (when notch is not bypassed) */ +// #define DATATYPE_MEAN +/** @} */ + +/** + * @defgroup SLPKEY_Const + * @{ + */ +#define SLPKEY_LOCK 0 /**< any incorrect value will lock the key */ +#define SLPKEY_UNLOCK 0xa47e5 /**< The correct key for register SEQSLPLOCK */ +/** @} */ + +/** + * @defgroup HPOSCOUT_Const + * @brief Set HPOSC output clock frequency, 16MHz or 32MHz. + * @{ + */ +#define HPOSCOUT_32MHZ 0 /**< Configure internal HFOSC output 32MHz clock */ +#define HPOSCOUT_16MHZ 1 /**< 16MHz Clock */ +/** @} */ + +/* GPIO */ +/** + * @defgroup AGPIOPIN_Const + * @brief The pin masks for register GP0OEN, GP0PE, GP0IEN,..., GP0TGL + * @{ + */ +#define AGPIO_Pin0 \ + 0x01 /**< AFE GPIO0, only available on AD5940 and AD5941, not ADuCM355 */ +#define AGPIO_Pin1 \ + 0x02 /**< AFE GPIO1, only available on AD5940 and AD5941, not ADuCM355 */ +#define AGPIO_Pin2 \ + 0x04 /**< AFE GPIO2, only available on AD5940 and AD5941, not ADuCM355 */ +#define AGPIO_Pin3 0x08 /**< AFE GPIO3, only available on AD5941. */ +#define AGPIO_Pin4 0x10 /**< AFE GPIO4, only available on AD5941. */ +#define AGPIO_Pin5 0x20 /**< AFE GPIO5, only available on AD5941. */ +#define AGPIO_Pin6 0x40 /**< AFE GPIO6, only available on AD5941. */ +#define AGPIO_Pin7 0x80 /**< AFE GPIO7, only available on AD5941. */ +/** @} */ + +/** + * @defgroup GP0FUNC_Const + * @{ + */ +#define GP0_INT 0 /**< Interrupt Controller 0 output */ +#define GP0_TRIG 1 /**< Sequence0 trigger */ +#define GP0_SYNC 2 /**< Use Sequencer to controll GP0 output level */ +#define GP0_GPIO 3 /**< Normal GPIO function */ +/** @} */ + +/** + * @defgroup GP1FUNC_Const + * @{ + */ +#define GP1_GPIO (0 << 2) /**< Normal GPIO function */ +#define GP1_TRIG (1 << 2) /**< Sequence1 trigger */ +#define GP1_SYNC (2 << 2) /**< Use Sequencer to controll GP1 output level */ +#define GP1_SLEEP (3 << 2) /**< Internal Sleep Signal */ +/** @} */ + +/** + * @defgroup GP2FUNC_Const + * @{ + */ +#define GP2_PORB (0 << 4) /**< Internal Power ON reset signal */ +#define GP2_TRIG (1 << 4) /**< Sequence1 trigger */ +#define GP2_SYNC (2 << 4) /**< Use Sequencer to controll GP2 output level */ +#define GP2_EXTCLK (3 << 4) /**< External Clock input(32kHz/16MHz/32MHz) */ +/** @} */ + +/** + * @defgroup GP3FUNC_Const + * @{ + */ +#define GP3_GPIO (0 << 6) /**< Normal GPIO function */ +#define GP3_TRIG (1 << 6) /**< Sequence3 trigger */ +#define GP3_SYNC (2 << 6) /**< Use Sequencer to controll GP3 output level */ +#define GP3_INT0 (3 << 6) /**< Interrupt Controller 0 output */ +/** @} */ + +/** + * @defgroup GP4FUNC_Const + * @note GP4 (Not available on AD5941) + * @{ + */ +#define GP4_GPIO (0 << 8) /**< Normal GPIO function */ +#define GP4_TRIG (1 << 8) /**< Sequence0 trigger */ +#define GP4_SYNC (2 << 8) /**< Use Sequencer to controll GP4 output level */ +#define GP4_INT1 (3 << 8) /**< Interrupt Controller 1 output */ +/** @} */ + +/** + * @defgroup GP5FUNC_Const + * @note GP5 (Not available on AD5941) + * @{ + */ +#define GP5_GPIO (0 << 10) /**< Internal Power ON reset signal */ +#define GP5_TRIG (1 << 10) /**< Sequence1 trigger */ +#define GP5_SYNC (2 << 10) /**< Use Sequencer to controll GP5 output level */ +#define GP5_EXTCLK (3 << 10) /**< External Clock input(32kHz/16MHz/32MHz) */ +/** @} */ + +/** + * @defgroup GP6FUNC_Const + * @note GP6 (Not available on AD5941) + * @{ + */ +#define GP6_GPIO (0 << 12) /**< Normal GPIO function */ +#define GP6_TRIG (1 << 12) /**< Sequence2 trigger */ +#define GP6_SYNC (2 << 12) /**< Use Sequencer to controll GP6 output level */ +#define GP6_INT0 (3 << 12) /**< Interrupt Controller 0 output */ +/** @} */ + +/** + * @defgroup GP7FUNC_Const + * @note GP7 (Not available on AD5941) + * @{ + */ +#define GP7_GPIO (0 << 14) /**< Normal GPIO function */ +#define GP7_TRIG (1 << 14) /**< Sequence2 trigger */ +#define GP7_SYNC (2 << 14) /**< Use Sequencer to controll GP7 output level */ +#define GP7_INT (3 << 14) /**< Interrupt Controller 1 output */ +/** @} */ + +// LPModeClk +/** + * @defgroup LPMODECLK_Const + * @{ + */ +#define LPMODECLK_HFOSC 0 /**< Use HFOSC 16MHz/32MHz clock as system clock */ +#define LPMODECLK_LFOSC 1 /**< Use LFOSC 32kHz clock as system clock */ +/** @} */ + +/* Clock */ +/** + * @defgroup SYSCLKSRC_Const + * @brief Select system clock source. The clock must be available. If + * unavailable clock is selected, we can reset AD5940. The system clock should + * be limited to 32MHz. If external clock or XTAL is faster than 16MHz, we use + * system clock divider to ensure it's always in range of 16MHz. + * @warning Maximum SPI clock has relation with system clock. Limit the SPI + * clock to ensure SPI clock is slower than system clock. + * @{ + */ +#define SYSCLKSRC_HFOSC \ + 0 /**< Internal HFOSC. CLock is 16MHz or 32MHz configurable. Set clock \ + divider to ensure system clock is always 16MHz */ +#define SYSCLKSRC_XTAL \ + 1 /**< External crystal. It can be 16MHz or 32MHz.Set clock divider to \ + ensure system clock is always 16MHz */ +#define SYSCLKSRC_LFOSC \ + 2 /**< Internal 32kHz clock. Note the SPI clock also sourced with 32kHz so \ + the register read/write frequency is lower down. */ +#define SYSCLKSRC_EXT 3 /**< External clock from GPIO, AD594x Only */ +/** @} */ + +/** + * @defgroup ADCCLKSRC_Const + * @brief Select ADC clock source. + * The maximum clock is 32MHz. + * @warning The ADC raw data update rate is equal to ADCClock/20. When ADC clock + * is 32MHz, sample rate is 1.6MSPS. The SINC3 filter clock are sourced from ADC + * clock and should be limited to 16MHz. When ADC clock is set to 32MHz. Clear + * bit ADCFILTERCON.BIT0 to enable the SINC3 clock divider. + * @{ + */ +#define ADCCLKSRC_HFOSC \ + 0 /**< Internal HFOSC. 16MHz or 32MHz which is configurable */ +#define ADCCLKSRC_XTAL \ + 1 /**< External crystal. Set ADC clock divider to get either 16MHz or 32MHz \ + clock */ +// #define ADCCLKSRC_LFOSC 2 /**< Do not use */ +#define ADCCLKSRC_EXT \ + 3 /**< External clock from GPIO. Set ADC clock divider to get the clock you \ + want */ +/** @} */ + +/** + * @defgroup ADCCLKDIV_Const + * @brief The divider for ADC clock. ADC clock = ClockSrc/Divider. + * @{ + */ +#define ADCCLKDIV_1 1 /**< Divider ADCClk = ClkSrc/1 */ +#define ADCCLKDIV_2 2 /**< Divider ADCClk = ClkSrc/2 */ +/** @} */ + +/** + * @defgroup SYSCLKDV_Const + * @brief The divider for system clock. System clock = ClockSrc/Divider. + * @{ + */ +#define SYSCLKDIV_1 1 /**< Divider SysClk = ClkSrc/1 */ +#define SYSCLKDIV_2 2 /**< Divider SysClk = ClkSrc/2 */ +/** @} */ + +/** + * @defgroup PGACALTYPE_Const + * @brief Calibration Type + * @{ + */ +#define PGACALTYPE_OFFSET 0 /**< Calibrate offset */ +#define PGACALTYPE_GAIN 1 /**< Calibrate gain */ +#define PGACALTYPE_OFFSETGAIN 2 /**< Calibrate offset and gain */ +/** @} */ + +/** + * @defgroup AD5940ERR_Const + * @brief AD5940 error code used by library and example codes. + * @{ + */ +#define AD5940ERR_OK 0 /**< No error */ +#define AD5940ERR_ERROR -1 /**< General error message */ +#define AD5940ERR_PARA -2 /**< Parameter is illegal */ +#define AD5940ERR_NULLP -3 /**< Null pointer */ +#define AD5940ERR_BUFF -4 /**< Buffer limited. */ +#define AD5940ERR_ADDROR \ + -5 /**< Out of Range. Register address is out of range. */ +#define AD5940ERR_SEQGEN -6 /**< Sequence generator error */ +#define AD5940ERR_SEQREG -7 /**< Register info is not found */ +#define AD5940ERR_SEQLEN -8 /**< Sequence length is too long. */ +#define AD5940ERR_WAKEUP -9 /**< Unable to wakeup AFE in specified time */ +#define AD5940ERR_TIMEOUT -10 /**< Time out error. */ +#define AD5940ERR_CALOR -11 /**< calibration out of range. */ +#define AD5940ERR_APPERROR \ + -100 /**< Used in example code to indicated the application has not been \ + initialized. */ +/** @} */ + +#ifndef NULL +#define NULL (void *)0 /**< Null, if it's not defined. */ +#endif +#define MATH_PI 3.1415926f /**< Pi defination. */ + +#define AD5940_ADIID 0x4144 /**< ADIID is fixed to 0x4144 */ +#define AD5940_CHIPID 0x0000 /**< CHIPID is changing with silicon version */ +#define M355_ADIID 0x4144 /**< ADIID is fixed to 0x4144 */ +#define M355_CHIPID 0x0000 /**< CHIPID is changing with silicon version */ + +#define AD5940_SWRST \ + 0xa158 /**< AD594x only. The value to perform software reset via reigster \ + SWRSTCON */ +#define KEY_OSCCON \ + 0xcb14 /**< key of register OSCCON. The key is auto locked after writing to \ + any other register */ +#define KEY_CALDATLOCK 0xde87a5af /**< Calibration key. */ +#define KEY_LPMODEKEY 0xc59d6 /**< LP mode key */ + +#define PARA_CHECK(n) /** add parameter check, Add DEBUG switch */ + +/** + * @} MISC_Block_Const + * @} MISC_Block + * */ +/** + * @defgroup TypeDefinitions + * @{ + */ + +typedef int32_t AD5940Err; /**< error number defination */ + +/** + * bool definition for ad5940lib. + */ +typedef enum { + bFALSE = 0, + bTRUE = !bFALSE, /**< True and False definition*/ +} BoolFlag; + +typedef struct { + /* ADC/DAC/TIA reference and buffer */ + BoolFlag HpBandgapEn; /**< Enable High power band-gap. Clear bit + AFECON.HPREFDIS will enable Bandgap, while set this + bit will disable bandgap */ + BoolFlag Hp1V8BuffEn; /**< High power 1.8V reference buffer enable */ + BoolFlag Hp1V1BuffEn; /**< High power 1.1V reference buffer enable */ + BoolFlag Lp1V8BuffEn; /**< Low power 1.8V reference buffer enable */ + BoolFlag Lp1V1BuffEn; /**< Low power 1.1V reference buffer enable */ + /* Low bandwidth loop reference and buffer */ + BoolFlag LpBandgapEn; /**< Enable Low power band-gap. */ + BoolFlag LpRefBufEn; /**< Enable the 2.5V low power reference buffer */ + BoolFlag LpRefBoostEn; /**< Boost buffer current */ + /* DAC Reference Buffer */ + BoolFlag HSDACRefEn; /**< Enable DAC reference buffer from HP Bandgap */ + /* Misc. control */ + BoolFlag Hp1V8ThemBuff; /**< Thermal Buffer for internal 1.8V reference to + AIN3 pin */ + BoolFlag + Hp1V8Ilimit; /**< Current limit for High power 1.8V reference buffer */ + BoolFlag + Disc1V8Cap; /**< Discharge 1.8V capacitor. Short external 1.8V decouple + capacitor to ground. Be careful when use this bit */ + BoolFlag + Disc1V1Cap; /**< Discharge 1.1V capacitor. Short external 1.1V decouple + capacitor to ground. Be careful when use this bit */ +} AFERefCfg_Type; + +/** + * @defgroup ADC_BlockType + * @{ + */ + +/** + * Structure for ADC Basic settings include MUX and PGA. + */ +typedef struct { + uint32_t ADCMuxP; /**< ADC Positive input channel selection. select from @ref + ADCMUXP */ + uint32_t ADCMuxN; /**< ADC negative input channel selection. select from @ref + ADCMUXN */ + uint32_t ADCPga; /**< ADC PGA settings, select from @ref ADCPGA */ +} ADCBaseCfg_Type; + +/** + * Structure for ADC filter settings. + */ +typedef struct { + uint32_t ADCSinc3Osr; + uint32_t ADCSinc2Osr; + uint32_t ADCAvgNum; /**< Average filter is enabled when DFT source is @ref + DFTSRC_AVG in function @ref AD5940_DFTCfgS. This + average filter is only used by DFT engine. */ + uint32_t ADCRate; /**< ADC Core sample rate */ + BoolFlag BpNotch; /**< Bypass Notch filter in SINC2+Notch block, so only SINC2 + is used. ADCFILTERCON.BIT4 */ + BoolFlag BpSinc3; /**< Bypass SINC3 Module */ + BoolFlag Sinc3ClkEnable; /**< Enable SINC3 clock */ + BoolFlag Sinc2NotchClkEnable; /**< Enable SINC2+Notch clock */ + BoolFlag Sinc2NotchEnable; /**< Enable SINC2+Notch block */ + BoolFlag DFTClkEnable; /**< Enable DFT clock */ + BoolFlag WGClkEnable; /**< Enable Waveform Generator clock */ +} ADCFilterCfg_Type; +/** @} */ + +/** + * DFT Configuration structure. + */ +typedef struct { + uint32_t DftNum; /**< DFT number */ + uint32_t DftSrc; /**< DFT Source */ + BoolFlag HanWinEn; /**< Enable Hanning window */ +} DFTCfg_Type; + +/** + * ADC digital comparator + */ +typedef struct { + uint16_t ADCMin; /**< The ADC code minimum limit value */ + uint16_t ADCMinHys; + uint16_t ADCMax; /**< The ADC code maximum limit value */ + uint16_t ADCMaxHys; +} ADCDigComp_Type; + +/** + * Statistic function + */ +typedef struct { + uint32_t StatDev; /**< Statistic standard deviation configure */ + uint32_t StatSample; /**< Sample size */ + BoolFlag StatEnable; /**< Set true to enable statistic block */ +} StatCfg_Type; + +/** + * Switch matrix configure */ +typedef struct { + uint32_t Dswitch; /**< D switch settings. Select from @ref SWD_Const*/ + uint32_t Pswitch; /**< P switch settings. Select from @ref SWP_Const */ + uint32_t Nswitch; /**< N switch settings. Select from @ref SWN_Const */ + uint32_t Tswitch; /**< T switch settings. Select from @ref SWT_Const */ +} SWMatrixCfg_Type; + +/** HSTIA Configure */ +typedef struct { + uint32_t HstiaBias; /**< When select Vzero as bias, the related + switch(VZERO2HSTIA) at LPDAC should be closed */ + uint32_t HstiaRtiaSel; /**< RTIA selection @ref HSTIARTIA_Const */ + uint32_t ExtRtia; /**< Value of external RTIA*/ + uint32_t HstiaCtia; /**< Set internal CTIA value from 1 to 32 pF */ + BoolFlag DiodeClose; /**< Close the switch for internal back to back diode */ + uint32_t HstiaDeRtia; /**< DE0 node RTIA selection @ref HSTIADERTIA_Const */ + uint32_t + HstiaDeRload; /**< DE0 node Rload selection @ref HSTIADERLOAD_Const */ + uint32_t HstiaDe1Rtia; /**< (ADuCM355 only, ignored on AD594x)DE1 node RTIA + selection @ref HSTIADERTIA_Const */ + uint32_t HstiaDe1Rload; /**< (ADuCM355 only)DE1 node Rload selection @ref + HSTIADERLOAD_Const */ +} HSTIACfg_Type; + +/** HSDAC Configure */ +typedef struct { + uint32_t ExcitBufGain; /**< Select from EXCITBUFGAIN_2, EXCITBUFGAIN_0P25 */ + uint32_t HsDacGain; /**< Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + uint32_t + HsDacUpdateRate; /**< Divider for DAC update. Available range is 7~255. */ +} HSDACCfg_Type; + +/** LPDAC Configure + * @note The LPDAC structure: + * @code + * Switch to select DAC output to Vzero and Vbias nodes. Vzero and Vbias can + * select from DAC6BIT and DAC12BIT output freely. LPDAC >DAC6BIT ---- Vzero + * LPDACVZERO_12BIT + * \--- Vbias LPDACVBIAS_6BIT + * >DAC12BIT---- Vzero LPDACVZERO_6BIT + * \--- Vbias LPDACVBIAS_12BIT + * Vzero/Vbias switch, controlled by @ref LPDACCfg_Type LpDacSW + * Vzero ------PIN + * \-----LPTIA LPDACSW_VZERO2LPTIA. LPTIA positive input + * \----HSTIA LPDACSW_VZERO2LPAMP. HSTIA positive input. Note, there is + * a MUX on HSTIA positive input pin to select the bias voltage between Vzero + * and 1.1V fixed internal reference. Vbias ------PIN LPDACSW_VBIAS2PIN + * \-----LPAMP LPDACSW_VBIAS2LPAMP positive input. The potential state + * amplifier input, or called LPAMP or PA(potential amplifier). + * @endcode + */ +typedef struct { + uint32_t LpdacSel; /**< Selectr from LPDAC0 or LPDAC1. LPDAC1 is only + available on ADuCM355. */ + uint32_t LpDacSrc; /**< LPDACSRC_MMR or LPDACSRC_WG. Note: HSDAC is always + connects to WG. Disable HSDAC if there is need. */ + uint32_t LpDacVzeroMux; /**< Select which DAC output connects to Vzero. 6Bit + or 12Bit DAC */ + uint32_t LpDacVbiasMux; /**< Select which DAC output connects to Vbias */ + uint32_t LpDacSW; /**< LPDAC switch set. Only available from Si2 */ + uint32_t LpDacRef; /**< Reference selection. Either internal 2.5V LPRef or + AVDD. select from @ref LPDACREF_Const*/ + BoolFlag DataRst; /**< Keep Reset register REG_AFE_LPDACDAT0DATA */ + BoolFlag PowerEn; /**< Power up REG_AFE_LPDACDAT0 */ + uint16_t DacData12Bit; /**< Data for 12bit DAC */ + uint16_t DacData6Bit; /**< Data for 6bit DAC */ +} LPDACCfg_Type; + +/** + * Low power amplifiers(PA and TIA) + */ +typedef struct { + uint32_t LpAmpSel; /**< Select from LPAMP0 and LPAMP1. LPAMP1 is only + available on ADuCM355. */ + uint32_t LpTiaRf; /**< The one order RC filter resistor selection. Select from + @ref LPTIARF_Const */ + uint32_t LpTiaRload; /**< The Rload resistor right in front of LPTIA negative + input terminal. Select from @ref LPTIARLOAD_Const*/ + uint32_t LpTiaRtia; /**< LPTIA RTIA resistor selection. Set it to open(@ref + LPTIARTIA_Const) when use external resistor. */ + uint32_t LpAmpPwrMod; /**< Power mode for LP PA and LPTIA */ + uint32_t + LpTiaSW; /**< Set of switches, using macro LPTIASW() to close switch */ + BoolFlag LpPaPwrEn; /**< Enable(bTRUE) or disable(bFALSE) power of + PA(potential amplifier) */ + BoolFlag LpTiaPwrEn; /**< Enable(bTRUE) or Disable(bFALSE) power of LPTIA + amplifier */ +} LPAmpCfg_Type; + +/** + * @brief Trapezoid Generator parameters + * The definition of the Trapezoid waveform is shown below. Note the Delay and + * Slope are all in clock unit. + * @code + * + * DCLevel2 _________ + * / \ + * / \ + * DCLevel1 _____/ \______ + * | | | | | + * Delay1|S1|Delay2 |S2| Delay1 repeat... + * Where S1 is slope1 and S2 is slop2 + * @endcode + * The DAC update rate from Trapezoid generator is SystemClock/50. The default + * SystemClock is internal HFOSC 16MHz. So the update rate is 320kHz. The time + * parameter specifies in clock number. For example, if Delay1 is set to 10, S1 + * is set 20, the time for Delay1 period is 10/320kHz = 31.25us, and time for S1 + * period is 20/320kHz = 62.5us. + */ +typedef struct { + uint32_t WGTrapzDCLevel1; /**< Trapezoid generator DC level1, this value is + written directly to corresponding register */ + uint32_t WGTrapzDCLevel2; /**< DC level2, similar to DCLevel1 */ + uint32_t WGTrapzDelay1; /**< Trapezoid generator delay 1 */ + uint32_t WGTrapzDelay2; /**< Trapezoid generator delay 2 */ + uint32_t WGTrapzSlope1; /**< Trapezoid generator Slope 1 */ + uint32_t WGTrapzSlope2; /**< Trapezoid generator Slope 2 */ +} WGTrapzCfg_Type; + +/** + * Sin wave generator parameters + */ +typedef struct { + uint32_t SinFreqWord; /**< Frequency word */ + uint32_t SinAmplitudeWord; /**< Amplitude word, range is 0 to 2047. Amplitude + range is 0 to 800mV */ + uint32_t SinOffsetWord; /**< Offset word, range is -2048 to 2047. Offset + voltage range is -800 to +800mV */ + uint32_t SinPhaseWord; /**< the start phase of sine wave. Use to tune start + phase of signal. */ +} WGSinCfg_Type; + +/** + * Waveform generator configuration + */ +typedef struct { + uint32_t WgType; /**< Select from WGTYPE_MMR, WGTYPE_SIN, WGTYPE_TRAPZ. HSDAC + is always connected to WG. */ + BoolFlag GainCalEn; /**< Enable Gain calibration */ + BoolFlag OffsetCalEn; /**< Enable offset calibration */ + WGTrapzCfg_Type TrapzCfg; /**< Configure Trapezoid generator */ + WGSinCfg_Type SinCfg; /**< Configure Sine wave generator */ + uint32_t WgCode; /**< The 12bit data WG will move to DAC data register. */ +} WGCfg_Type; + +/** + * High speed loop configuration + * */ +typedef struct { + SWMatrixCfg_Type SWMatCfg; /**< switch matrix configuration. */ + HSDACCfg_Type HsDacCfg; /**< HSDAC configuration. */ + WGCfg_Type WgCfg; /**< Waveform generator configuration. */ + HSTIACfg_Type HsTiaCfg; /**< HSTIA configuration. */ +} HSLoopCfg_Type; + +/** + * Low power loop Configure + * */ +typedef struct { + LPDACCfg_Type LpDacCfg; /**< LPDAC configuration. @note Must select LPDAC0 or + LPDAC1 in structure. */ + LPAmpCfg_Type LpAmpCfg; /**< LPAMP(LPTIA and PA) configuration. @note Must + select LPAMP0 or LPAMP1 in structure. */ +} LPLoopCfg_Type; + +/** + * DSP Configure + * */ +typedef struct { + ADCBaseCfg_Type ADCBaseCfg; /**< ADC base configuration */ + ADCFilterCfg_Type ADCFilterCfg; /**< ADC filter configuration include + SINC3/SINC2/Notch/Average(for DFT only) */ + ADCDigComp_Type ADCDigCompCfg; /**< ADC digital comparator */ + DFTCfg_Type DftCfg; /**< DFT configuration include data source, DFT number and + Hanning Window */ + StatCfg_Type StatCfg; /**< Statistic block */ +} DSPCfg_Type; + +/** + * GPIO Configure + * */ +typedef struct { + uint32_t FuncSet; /**< AGP0 to AGP7 function sets */ + uint32_t OutputEnSet; /**< AGPIO_Pin0|AGPIO_Pin1|...|AGPIO_Pin7, Enable output + of selected pins, disable other pins */ + uint32_t InputEnSet; /**< Enable input of selected pins, disable other pins */ + uint32_t PullEnSet; /**< Enable pull up or down on selected pin. disable other + pins */ + uint32_t OutVal; /**< Value for GPIOOUT register */ +} AGPIOCfg_Type; + +/** + * FIFO configure + */ +typedef struct { + BoolFlag FIFOEn; /**< Enable DATAFIFO. Disable FIFO will reset FIFO */ + uint32_t FIFOMode; /**< Stream mode or standard FIFO mode */ + uint32_t FIFOSize; /**< How to allocate the internal 6kB SRAM. Data FIFO and + sequencer share all 6kB SRAM */ + uint32_t FIFOSrc; /**< Select which data source will be stored to FIFO */ + uint32_t FIFOThresh; /**< FIFO threshold value, 0 to 1023. Threshold can be + used to generate interrupt so MCU can read back data + before FIFO is full */ +} FIFOCfg_Type; + +/** + * Sequencer configure + */ +typedef struct { + uint32_t SeqMemSize; /**< Sequencer memory size. SRAM is used by both FIFO and + Sequencer. Make sure the total SRAM used is less than + 6kB. */ + BoolFlag SeqEnable; /**< Enable sequencer. Only with valid trigger, sequencer + can run */ + BoolFlag SeqBreakEn; /**< Do not use it */ + BoolFlag SeqIgnoreEn; /**< Do not use it */ + BoolFlag SeqCntCRCClr; /**< Clear sequencer count and CRC */ + uint32_t + SeqWrTimer; /**< Set wait how much clocks after every commands executed */ +} SEQCfg_Type; + +/** + * Sequence info structure + */ +typedef struct { + uint32_t SeqId; /**< The Sequence ID @ref SEQID_Const */ + uint32_t SeqRamAddr; /**< The start address that in AF5940 SRAM */ + uint32_t SeqLen; /**< Sequence length */ + BoolFlag WriteSRAM; /**< Write command to SRAM or not. */ + const uint32_t + *pSeqCmd; /**< Pointer to the sequencer commands that stored in MCU */ +} SEQInfo_Type; + +typedef struct { + uint32_t PinSel; /**< Select which pin are going to be configured. @ref + AGPIOPIN_Const */ + uint32_t SeqPinTrigMode; /**< The pin detect mode. Select from @ref + SEQPINTRIGMODE_Const */ + BoolFlag bEnable; /**< Allow detected pin action to trigger corresponding + sequence. */ +} SeqGpioTrig_Cfg; + +/** + * Wakeup Timer Configure + * */ +typedef struct { + uint32_t WuptEndSeq; /**< end sequence selection @ref WUPTENDSEQ_Const. Wupt + will go back to slot A after this one is executed. */ + uint32_t WuptOrder[8]; /**< The 8 slots for WakeupTimer. Place @ref + SEQID_Const to this array. */ + uint32_t SeqxSleepTime[4]; /**< Time before put AFE to sleep. 0 to + 0x000f_ffff. We normally don't use this feature + and it's disabled in @ref AD5940_Initialize */ + uint32_t SeqxWakeupTime[4]; /**< Time before Wakeup AFE. */ + BoolFlag WuptEn; /**< Timer enable. Once enabled, it starts to run. */ +} WUPTCfg_Type; + +/** + * Clock configure + */ +typedef struct { + uint32_t SysClkSrc; /**< System clock source @ref SYSCLKSRC_Const */ + uint32_t ADCCLkSrc; /**< ADC clock source @ref ADCCLKSRC_Const */ + uint32_t SysClkDiv; /**< System clock divider. Use this to ensure System clock + < 16MHz. */ + uint32_t ADCClkDiv; /**< ADC control clock divider. ADC core clock is + @ADCCLkSrc, but control clock should be <16MHz. */ + BoolFlag HFOSCEn; /**< Enable internal 16MHz/32MHz HFOSC */ + BoolFlag HfOSC32MHzMode; /**< Enable internal HFOSC to output 32MHz */ + BoolFlag LFOSCEn; /**< Enable internal 32kHZ OSC */ + BoolFlag HFXTALEn; /**< Enable XTAL driver */ +} CLKCfg_Type; + +/** + * HSTIA internal RTIA calibration structure + * @note ADC filter settings and DFT should be configured properly based on + * signal frequency. + */ +typedef struct { + float fFreq; /**< Calibration frequency */ + float fRcal; /**< Rcal resistor value in Ohm*/ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + + HSTIACfg_Type HsTiaCfg; /**< HSTIA configuration */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + DFTCfg_Type DftCfg; /**< DFT configuration. */ + uint32_t bPolarResult; /**< bTRUE-Polar coordinate:Return results in Magnitude + and Phase. bFALSE-Cartesian coordinate: Return + results in Real part and Imaginary Part */ +} HSRTIACal_Type; + +/** + * LPTIA internal RTIA calibration structure + */ +typedef struct { + float fFreq; /**< Calibration frequency. Set it to 0.0 for DC calibration */ + float fRcal; /**< Rcal resistor value in Ohm*/ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + + uint32_t LpAmpSel; /**< Select from LPAMP0 and LPAMP1. LPAMP1 is only + available on ADuCM355. */ + BoolFlag bWithCtia; /**< Connect external CTIA or not. */ + uint32_t LpTiaRtia; /**< LPTIA RTIA selection. */ + uint32_t LpAmpPwrMod; /**< Amplifiers power mode setting */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + DFTCfg_Type DftCfg; /**< DFT configuration */ + uint32_t bPolarResult; /**< bTRUE-Polar coordinate:Return results in Magnitude + and Phase. bFALSE-Cartesian coordinate: Return + results in Real part and Imaginary Part */ +} LPRTIACal_Type; + +/** + * HSDAC calibration structure. + */ +typedef struct { + float fRcal; /**< Rcal resistor value in Ohm*/ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + + uint32_t AfePwrMode; /**< Calibrate DAC in High power mode */ + uint32_t ExcitBufGain; /**< Select from EXCITBUFGAIN_2, EXCITBUFGAIN_0P25 */ + uint32_t HsDacGain; /**< Select from HSDACGAIN_1, HSDACGAIN_0P2 */ + + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ +} HSDACCal_Type; + +/** + * LPDAC calibration structure. + */ +typedef struct { + uint32_t + LpdacSel; /**< Select from LPDAC0 and LPDAC1. LPDAC1 is ADuCM355 only. */ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + float ADCRefVolt; /**< ADC reference voltage. Default is 1.82V*/ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC2 OSR settings. */ + int32_t SettleTime10us; /**< Wait how much time after TIA is enabled? */ + int32_t TimeOut10us; /**< ADC converts signal need time. Specify the maximum + time allowed. Timeout in 10us. negative number means + wait no time. */ +} LPDACCal_Type; + +/** + * LPDAC parameters: LPDAC code to voltage transfer function. + * Voltage(mV) = kC2V_DACxB * Code + bC2V_DACxB; + * where x is 12 or 6 represent 12Bit DAC and 6Bit DAC. C2V means code to + * voltage. Code is the data register value for LPDAC. The equation gives real + * output voltage of LPDAC. Similarly, Code(LSB) = kV2C_DACxB * Voltage(mV) + + * bV2C_DACxB; + * + * Apparently, kV2C_DACxB = 1/kC2V_DACxB; + * bV2C_DACxB = -bC2V_DACxB/kC2V_DACxB; + */ +typedef struct { + /* Code to voltage equation parameters */ + float kC2V_DAC12B; /**< the k factor of code to voltage(in mV) transfer + function */ + float bC2V_DAC12B; /**< the offset of code to voltage transfer function. It's + the voltage in mV when code is zero. */ + float kC2V_DAC6B; /**< the k factor for LPDAC 6 bit output. */ + float bC2V_DAC6B; /**< the offset for LPDAC 6 bit output. */ + /* Code to voltage equation parameters */ + float kV2C_DAC12B; /**< the k factor for converting voltage to code for LPDAC + 12bit output. */ + float bV2C_DAC12B; /**< the offset for converting voltage to code for LPDAC + 12bit output. */ + float kV2C_DAC6B; /**< the k factor for converting voltage to code for LPDAC + 6bit output. */ + float bV2C_DAC6B; /**< the offset for converting voltage to code for LPDAC + 6bit output. */ +} LPDACPara_Type; + +/** + * LFOSC frequency measure structure + */ +typedef struct { + uint32_t CalSeqAddr; /**< Sequence start address */ + float CalDuration; /**< Time can be used for calibration in unit of ms. + Recommend to use tens of millisecond like 10ms */ + float SystemClkFreq; /**< System clock frequency. */ +} LFOSCMeasure_Type; + +/** + * ADC PGA calibration type + */ +typedef struct { + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + float VRef1p82; /**< The real voltage of 1.82 reference. Unit is volt. */ + float VRef1p11; /**< The real voltage of 1.1 reference. Unit is volt. */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCPga; /**< Which PGA gain we are going to calibrate? */ + uint32_t PGACalType; /**< Calibrate gain of offset or gain+offset? */ + int32_t TimeOut10us; /**< Timeout in 10us. -1 means no time-out*/ +} ADCPGACal_Type; + +/** + * LPTIA Offset calibration type + */ +typedef struct { + uint32_t LpAmpSel; /**< Select from LPAMP0 and LPAMP1. LPAMP1 is only + available on ADuCM355. */ + float SysClkFreq; /**< The real frequency of system clock */ + float AdcClkFreq; /**< The real frequency of ADC clock */ + uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ + uint32_t ADCPga; /**< PGA Gain selection */ + uint32_t DacData12Bit; /**< 12Bit DAC data */ + uint32_t DacData6Bit; /**< 6Bit DAC data */ + uint32_t LpDacVzeroMux; /**< Vzero is used as LPTIA bias voltage, select + 12Bit/6Bit DAC */ + uint32_t LpAmpPwrMod; /**< LP amplifiers power mode, select from + LPAMPPWR_NORM, LPAMPPWR_BOOSTn*/ + uint32_t LpTiaSW; /**< Switch configuration for LPTIA. Normally for SW(5) and + SW(9).*/ + uint32_t LpTiaRtia; /**< LPTIA RTIA resistor selection. */ + int32_t SettleTime10us; /**< Wait how much time after TIA is enabled? */ + int32_t TimeOut10us; /**< ADC converts signal need time. Specify the maximum + time allowed. Timeout in 10us. negative number means + wait no time. */ +} LPTIAOffsetCal_Type; + +/** + * Structure for calculating how much system clocks needed for specified number + * of data + */ +typedef struct { + uint32_t + DataType; /**< The final data output selection. @ref DATATYPE_Const */ + uint32_t DataCount; /**< How many data you want. */ + uint32_t ADCSinc3Osr; /**< ADC SINC3 filter OSR setting */ + uint32_t ADCSinc2Osr; /**< ADC SINC2 filter OSR setting */ + uint32_t ADCAvgNum; /**< Average number for DFT engine. Only used when data + type is DATATYPE_DFT and DftSrc is DFTSRC_AVG */ + uint32_t + DftSrc; /**< The DFT source. Only used when data type is DATATYPE_DFT */ + uint8_t ADCRate; /**< ADCRate @ref ADCRATE_Const. Only used when data type is + DATATYPE_NOTCH */ + BoolFlag BpNotch; /**< Bypass notch filter or not. Only used when data type is + DATATYPE_DFT and DftSrc is DFTSRC_SINC2NOTCH */ + float RatioSys2AdcClk; /**< Ratio of system clock to ADC clock frequency */ +} ClksCalInfo_Type; + +/** + * Software controlled Sweep Function + * */ +typedef struct { + BoolFlag SweepEn; /**< Software can automatically sweep frequency from + following parameters. Set value to 1 to enable it. */ + float SweepStart; /**< Sweep start frequency. Software will go back to the + start frequency when it reaches SWEEP_STOP */ + float SweepStop; /**< Sweep end frequency. */ + uint32_t SweepPoints; /**< How many points from START to STOP frequency */ + BoolFlag SweepLog; /**< The step is linear or logarithmic. 0: Linear, 1: + Logarithmic*/ + uint32_t SweepIndex; /**< Current position of sweep */ +} SoftSweepCfg_Type; + +/** + * Impedance result in Polar coordinate + */ +typedef struct { + float Magnitude; /**< The magnitude in polar coordinate */ + float Phase; /**< The phase in polar coordinate */ +} fImpPol_Type; // Polar + +/** + * Impedance result in Cartesian coordinate + */ +typedef struct { + float Real; /**< The real part in Cartesian coordinate */ + float Image; /**< The imaginary in Cartesian coordinate */ +} fImpCar_Type; // Cartesian + +/** + * int32_t type Impedance result in Cartesian coordinate + */ +typedef struct { + int32_t Real; /**< The real part in Cartesian coordinate */ + int32_t Image; /**< The real imaginary in Cartesian coordinate */ +} iImpCar_Type; + +/** + * FreqParams_Type - Structure to store optimum filter settings + */ +typedef struct { + BoolFlag HighPwrMode; + uint32_t DftNum; + uint32_t DftSrc; + uint32_t ADCSinc3Osr; + uint32_t ADCSinc2Osr; + uint32_t NumClks; +} FreqParams_Type; + +/** + * @} TypeDefinitions + */ + +/** + * @defgroup Exported_Functions + * @{ + */ +/* 1. Basic SPI functions */ +void AD5940_WriteReg(uint16_t RegAddr, uint32_t RegData); +uint32_t AD5940_ReadReg(uint16_t RegAddr); +void AD5940_FIFORd(uint32_t *pBuffer, uint32_t uiReadCount); + +/* 2. AD5940 Top Control functions */ +void AD5940_Initialize(void); /* Call this function firstly once AD5940 power on + or come from soft reset */ +void AD5940_AFECtrlS(uint32_t AfeCtrlSet, BoolFlag State); +AD5940Err AD5940_LPModeCtrlS(uint32_t EnSet); +void AD5940_AFEPwrBW( + uint32_t AfePwr, + uint32_t AfeBw); /* AFE power mode and system bandwidth control */ +void AD5940_REFCfgS(AFERefCfg_Type *pBufCfg); + +/* 3. High_Speed_Loop Functions */ +void AD5940_HSLoopCfgS(HSLoopCfg_Type *pHsLoopCfg); +void AD5940_SWMatrixCfgS(SWMatrixCfg_Type *pSwMatrix); +void AD5940_HSDacCfgS(HSDACCfg_Type *pHsDacCfg); +AD5940Err AD5940_HSTIACfgS(HSTIACfg_Type *pHsTiaCfg); +void AD5940_HSRTIACfgS(uint32_t HSTIARtia); +void __AD5940_SetDExRTIA(uint32_t DExPin, uint32_t DeRtia, uint32_t DeRload); + +/* 4. Low_Power_Loop Functions*/ +void AD5940_LPLoopCfgS(LPLoopCfg_Type *pLpLoopCfg); +void AD5940_LPDACCfgS(LPDACCfg_Type *pLpDacCfg); +// void AD5940_LPDACWriteS(uint16_t Data12Bit, uint8_t Data6Bit); +void AD5940_LPDAC0WriteS(uint16_t Data12Bit, uint8_t Data6Bit); +void AD5940_LPDAC1WriteS(uint16_t Data12Bit, uint8_t Data6Bit); +void AD5940_LPAMPCfgS(LPAmpCfg_Type *pLpAmpCfg); + +/* 5. DSP_Block_Functions */ +void AD5940_DSPCfgS(DSPCfg_Type *pDSPCfg); +uint32_t AD5940_ReadAfeResult(uint32_t AfeResultSel); +/* 5.1 ADC Block */ +void AD5940_ADCBaseCfgS(ADCBaseCfg_Type *pADCInit); +void AD5940_ADCFilterCfgS(ADCFilterCfg_Type *pFiltCfg); +void AD5940_ADCPowerCtrlS(BoolFlag State); +void AD5940_ADCConvtCtrlS(BoolFlag State); +void AD5940_ADCMuxCfgS(uint32_t ADCMuxP, uint32_t ADCMuxN); +void AD5940_ADCDigCompCfgS(ADCDigComp_Type *pCompCfg); +void AD5940_StatisticCfgS(StatCfg_Type *pStatCfg); +void AD5940_ADCRepeatCfgS(uint32_t Number); +void AD5940_DFTCfgS(DFTCfg_Type *pDftCfg); +/* 5.2 Waveform Generator Block */ +void AD5940_WGCfgS(WGCfg_Type *pWGInit); +AD5940Err AD5940_WGDACCodeS(uint32_t code); /* Directly write DAC Code */ +void AD5940_WGFreqCtrlS(float SinFreqHz, float WGClock); +uint32_t AD5940_WGFreqWordCal(float SinFreqHz, float WGClock); +// uint32_t AD5940_WGAmpWordCal(float Amp, BoolFlag DacGain, BoolFlag +// ExcitGain); + +/* 6. Sequencer_FIFO */ +void AD5940_FIFOCfg(FIFOCfg_Type *pFifoCfg); +AD5940Err +AD5940_FIFOGetCfg(FIFOCfg_Type *pFifoCfg); /* Read back current configuration */ +void AD5940_FIFOCtrlS( + uint32_t FifoSrc, + BoolFlag FifoEn); /* Configure FIFO data source. And disable/enable it.*/ +void AD5940_FIFOThrshSet(uint32_t FIFOThresh); +uint32_t AD5940_FIFOGetCnt(void); /* Get current FIFO count */ +void AD5940_SEQCfg(SEQCfg_Type *pSeqCfg); +AD5940Err +AD5940_SEQGetCfg(SEQCfg_Type *pSeqCfg); /* Read back current configuration */ +void AD5940_SEQCtrlS(BoolFlag SeqEn); +void AD5940_SEQHaltS(void); +void AD5940_SEQMmrTrig(uint32_t SeqId); /* Manually trigger sequence */ +void AD5940_SEQCmdWrite(uint32_t StartAddr, const uint32_t *pCommand, + uint32_t CmdCnt); +void AD5940_SEQInfoCfg(SEQInfo_Type *pSeq); +AD5940Err AD5940_SEQInfoGet(uint32_t SeqId, SEQInfo_Type *pSeqInfo); +void AD5940_SEQGpioCtrlS( + uint32_t GpioSet); /* Sequencer can control GPIO0~7 if the GPIO function is + set to SYNC */ +uint32_t +AD5940_SEQTimeOutRd(void); /* Read back current sequence time out value */ +AD5940Err AD5940_SEQGpioTrigCfg(SeqGpioTrig_Cfg *pSeqGpioTrigCfg); +void AD5940_WUPTCfg(WUPTCfg_Type *pWuptCfg); +void AD5940_WUPTCtrl(BoolFlag Enable); /* Enable or disable Wakeup timer */ +AD5940Err AD5940_WUPTTime(uint32_t SeqId, uint32_t SleepTime, + uint32_t WakeupTime); + +/* 7. MISC_Block */ +/* 7.1 Clock system */ +void AD5940_CLKCfg(CLKCfg_Type *pClkCfg); +void AD5940_HFOSC32MHzCtrl(BoolFlag Mode32MHz); +void AD5940_HPModeEn(BoolFlag Enable); /* Switch system clocks to high power + mode for EIS >80kHz)*/ +/* 7.2 AFE Interrupt */ +void AD5940_INTCCfg(uint32_t AfeIntcSel, uint32_t AFEIntSrc, BoolFlag State); +uint32_t AD5940_INTCGetCfg(uint32_t AfeIntcSel); +void AD5940_INTCClrFlag(uint32_t AfeIntSrcSel); +BoolFlag AD5940_INTCTestFlag( + uint32_t AfeIntcSel, + uint32_t AfeIntSrcSel); /* Check if selected interrupt happened */ +uint32_t +AD5940_INTCGetFlag(uint32_t AfeIntcSel); /* Get current INTC interrupt flag */ +/* 7.3 GPIO */ +void AD5940_AGPIOCfg(AGPIOCfg_Type *pAgpioCfg); +void AD5940_AGPIOFuncCfg(uint32_t uiCfgSet); +void AD5940_AGPIOOen(uint32_t uiPinSet); +void AD5940_AGPIOIen(uint32_t uiPinSet); +uint32_t AD5940_AGPIOIn(void); +void AD5940_AGPIOPen(uint32_t uiPinSet); +void AD5940_AGPIOSet(uint32_t uiPinSet); +void AD5940_AGPIOClr(uint32_t uiPinSet); +void AD5940_AGPIOToggle(uint32_t uiPinSet); + +/* 7.4 LPMODE */ +AD5940Err +AD5940_LPModeEnS(BoolFlag LPModeEn); /* Enable LP mode or disable it. */ +void AD5940_LPModeClkS(uint32_t LPModeClk); +void AD5940_ADCRepeatCfg(uint32_t Number); +/* 7.5 Power */ +void AD5940_SleepKeyCtrlS(uint32_t SlpKey); /* enter the correct key to allow + AFE to enter sleep mode */ +void AD5940_EnterSleepS(void); /* Put AFE to hibernate/sleep mode and keep LP + loop as the default settings. */ +void AD5940_ShutDownS( + void); /* Unlock the key, turn off LP loop and enter sleep/hibernate mode */ +uint32_t +AD5940_WakeUp(int32_t TryCount); /* Try to wakeup AFE by read register */ +uint32_t AD5940_GetADIID(void); /* Read ADIID */ +uint32_t AD5940_GetChipID(void); /* Read Chip ID */ +AD5940Err AD5940_SoftRst(void); +void AD5940_HWReset(void); /* Do hardware reset to AD5940 using RESET pin */ +/* Calibration functions */ +/* 8. Calibration */ +AD5940Err AD5940_ADCPGACal(ADCPGACal_Type *ADCPGACal); +AD5940Err AD5940_LPDACCal(LPDACCal_Type *pCalCfg, LPDACPara_Type *pResult); +AD5940Err AD5940_LPTIAOffsetCal(LPTIAOffsetCal_Type *pLPTIAOffsetCal); +AD5940Err AD5940_HSRtiaCal(HSRTIACal_Type *pCalCfg, void *pResult); +AD5940Err AD5940_HSDACCal(HSDACCal_Type *pCalCfg); +AD5940Err AD5940_LPRtiaCal(LPRTIACal_Type *pCalCfg, void *pResult); +AD5940Err AD5940_LFOSCMeasure(LFOSCMeasure_Type *pCfg, float *pFreq); +// void AD5940_LFOSCTrim(uint32_t TrimValue); /* TrimValue: 0 to 15 */ +// void AD5940_HFOSC16MHzTrim(uint32_t TrimValue); +// void AD5940_HFOSC32MHzTrim(uint32_t TrimValue); + +/* 9. Pure software functions. Functions with no register access. These + * functions are helpers */ +/* Sequence Generator */ +void AD5940_SEQGenInit( + uint32_t *pBuffer, + uint32_t BufferSize); /* Initialize sequence generator workspace */ +void AD5940_SEQGenCtrl( + BoolFlag bFlag); /* Enable or disable sequence generator */ +void AD5940_SEQGenInsert( + uint32_t CmdWord); /* Manually insert a sequence command */ +AD5940Err AD5940_SEQGenFetchSeq( + const uint32_t **ppSeqCmd, + uint32_t + *pSeqCount); /* Fetch generated sequence and start a new sequence */ +void AD5940_ClksCalculate(ClksCalInfo_Type *pFilterInfo, uint32_t *pClocks); +uint32_t AD5940_SEQCycleTime(void); +void AD5940_SweepNext(SoftSweepCfg_Type *pSweepCfg, float *pNextFreq); +void AD5940_StructInit(void *pStruct, uint32_t StructSize); +float AD5940_ADCCode2Volt(uint32_t code, uint32_t ADCPga, + float VRef1p82); /* Calculate ADC code to voltage */ +BoolFlag AD5940_Notch50HzAvailable(ADCFilterCfg_Type *pFilterInfo, uint8_t *dl); +BoolFlag AD5940_Notch60HzAvailable(ADCFilterCfg_Type *pFilterInfo, uint8_t *dl); +fImpCar_Type AD5940_ComplexDivFloat(fImpCar_Type *a, fImpCar_Type *b); +fImpCar_Type AD5940_ComplexMulFloat(fImpCar_Type *a, fImpCar_Type *b); +fImpCar_Type AD5940_ComplexAddFloat(fImpCar_Type *a, fImpCar_Type *b); +fImpCar_Type AD5940_ComplexSubFloat(fImpCar_Type *a, fImpCar_Type *b); + +fImpCar_Type AD5940_ComplexDivInt(iImpCar_Type *a, iImpCar_Type *b); +fImpCar_Type AD5940_ComplexMulInt(iImpCar_Type *a, iImpCar_Type *b); +float AD5940_ComplexMag(fImpCar_Type *a); +float AD5940_ComplexPhase(fImpCar_Type *a); +FreqParams_Type AD5940_GetFreqParameters(float freq); +/** + * @} Exported_Functions + */ + +/** + * @defgroup Library_Interface + * The functions user should provide for specific MCU platform + * @{ + */ +void AD5940_CsClr(void); +void AD5940_CsSet(void); +void AD5940_RstClr(void); +void AD5940_RstSet(void); +void AD5940_Delay10us(uint32_t time); +/* (Not used for now.)AD5940 has 8 GPIOs, some of them are connected to MCU. MCU + * can set or read the status of these pins. */ +void AD5940_MCUGpioWrite(uint32_t data); /* */ +uint32_t AD5940_MCUGpioRead(uint32_t); +void AD5940_MCUGpioCtrl(uint32_t, BoolFlag); +void AD5940_ReadWriteNBytes(unsigned char *pSendBuffer, + unsigned char *pRecvBuff, unsigned long length); +/* Below functions are frequently used in example code but not necessary for + * library */ +uint32_t AD5940_GetMCUIntFlag(void); +uint32_t AD5940_ClrMCUIntFlag(void); +uint32_t AD5940_MCUResourceInit(void *pCfg); +/** + * @} Library_Interface + */ + +/** + * @} AD5940_Library + */ + +#endif + +#ifdef __cplusplus +} +#endif diff --git a/examples/rp2040_port/test/main.c b/examples/rp2040_port/test/main.c new file mode 100644 index 0000000..8fad669 --- /dev/null +++ b/examples/rp2040_port/test/main.c @@ -0,0 +1,18 @@ +#include "pico/stdlib.h" +#include "rp2040port.h" +#include + +extern void AD5940_Main(void); + +int main(void) { + stdio_init_all(); + setup_pins(); + + // Allow some time for USB to connect if needed, but don't block forever + sleep_ms(2000); + printf("Starting AD5940 Test...\n"); + + AD5940_Main(); + + return 0; +} diff --git a/examples/rp2040_port/test/pico_sdk_import.cmake b/examples/rp2040_port/test/pico_sdk_import.cmake new file mode 100644 index 0000000..d493cc2 --- /dev/null +++ b/examples/rp2040_port/test/pico_sdk_import.cmake @@ -0,0 +1,121 @@ +# This is a copy of /external/pico_sdk_import.cmake + +# This can be dropped into an external project to help locate this SDK +# It should be include()ed prior to project() + +# Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd. +# +# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the +# following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following +# disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +if (DEFINED ENV{PICO_SDK_PATH} AND (NOT PICO_SDK_PATH)) + set(PICO_SDK_PATH $ENV{PICO_SDK_PATH}) + message("Using PICO_SDK_PATH from environment ('${PICO_SDK_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT} AND (NOT PICO_SDK_FETCH_FROM_GIT)) + set(PICO_SDK_FETCH_FROM_GIT $ENV{PICO_SDK_FETCH_FROM_GIT}) + message("Using PICO_SDK_FETCH_FROM_GIT from environment ('${PICO_SDK_FETCH_FROM_GIT}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_PATH} AND (NOT PICO_SDK_FETCH_FROM_GIT_PATH)) + set(PICO_SDK_FETCH_FROM_GIT_PATH $ENV{PICO_SDK_FETCH_FROM_GIT_PATH}) + message("Using PICO_SDK_FETCH_FROM_GIT_PATH from environment ('${PICO_SDK_FETCH_FROM_GIT_PATH}')") +endif () + +if (DEFINED ENV{PICO_SDK_FETCH_FROM_GIT_TAG} AND (NOT PICO_SDK_FETCH_FROM_GIT_TAG)) + set(PICO_SDK_FETCH_FROM_GIT_TAG $ENV{PICO_SDK_FETCH_FROM_GIT_TAG}) + message("Using PICO_SDK_FETCH_FROM_GIT_TAG from environment ('${PICO_SDK_FETCH_FROM_GIT_TAG}')") +endif () + +if (PICO_SDK_FETCH_FROM_GIT AND NOT PICO_SDK_FETCH_FROM_GIT_TAG) + set(PICO_SDK_FETCH_FROM_GIT_TAG "master") + message("Using master as default value for PICO_SDK_FETCH_FROM_GIT_TAG") +endif() + +set(PICO_SDK_PATH "${PICO_SDK_PATH}" CACHE PATH "Path to the Raspberry Pi Pico SDK") +set(PICO_SDK_FETCH_FROM_GIT "${PICO_SDK_FETCH_FROM_GIT}" CACHE BOOL "Set to ON to fetch copy of SDK from git if not otherwise locatable") +set(PICO_SDK_FETCH_FROM_GIT_PATH "${PICO_SDK_FETCH_FROM_GIT_PATH}" CACHE FILEPATH "location to download SDK") +set(PICO_SDK_FETCH_FROM_GIT_TAG "${PICO_SDK_FETCH_FROM_GIT_TAG}" CACHE FILEPATH "release tag for SDK") + +if (NOT PICO_SDK_PATH) + if (PICO_SDK_FETCH_FROM_GIT) + include(FetchContent) + set(FETCHCONTENT_BASE_DIR_SAVE ${FETCHCONTENT_BASE_DIR}) + if (PICO_SDK_FETCH_FROM_GIT_PATH) + get_filename_component(FETCHCONTENT_BASE_DIR "${PICO_SDK_FETCH_FROM_GIT_PATH}" REALPATH BASE_DIR "${CMAKE_SOURCE_DIR}") + endif () + FetchContent_Declare( + pico_sdk + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + ) + + if (NOT pico_sdk) + message("Downloading Raspberry Pi Pico SDK") + # GIT_SUBMODULES_RECURSE was added in 3.17 + if (${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.17.0") + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + GIT_SUBMODULES_RECURSE FALSE + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + else () + FetchContent_Populate( + pico_sdk + QUIET + GIT_REPOSITORY https://github.com/raspberrypi/pico-sdk + GIT_TAG ${PICO_SDK_FETCH_FROM_GIT_TAG} + + SOURCE_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-src + BINARY_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-build + SUBBUILD_DIR ${FETCHCONTENT_BASE_DIR}/pico_sdk-subbuild + ) + endif () + + set(PICO_SDK_PATH ${pico_sdk_SOURCE_DIR}) + endif () + set(FETCHCONTENT_BASE_DIR ${FETCHCONTENT_BASE_DIR_SAVE}) + else () + message(FATAL_ERROR + "SDK location was not specified. Please set PICO_SDK_PATH or set PICO_SDK_FETCH_FROM_GIT to on to fetch from git." + ) + endif () +endif () + +get_filename_component(PICO_SDK_PATH "${PICO_SDK_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}") +if (NOT EXISTS ${PICO_SDK_PATH}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' not found") +endif () + +set(PICO_SDK_INIT_CMAKE_FILE ${PICO_SDK_PATH}/pico_sdk_init.cmake) +if (NOT EXISTS ${PICO_SDK_INIT_CMAKE_FILE}) + message(FATAL_ERROR "Directory '${PICO_SDK_PATH}' does not appear to contain the Raspberry Pi Pico SDK") +endif () + +set(PICO_SDK_PATH ${PICO_SDK_PATH} CACHE PATH "Path to the Raspberry Pi Pico SDK" FORCE) + +include(${PICO_SDK_INIT_CMAKE_FILE}) diff --git a/examples/rp2040_port/test/rp2040port.c b/examples/rp2040_port/test/rp2040port.c new file mode 100644 index 0000000..bc63ccf --- /dev/null +++ b/examples/rp2040_port/test/rp2040port.c @@ -0,0 +1,59 @@ +#include "rp2040port.h" + +// --- Hardware Setup --- +void setup_pins(void) { + // SPI Initialisation. Using SPI0 at 16MHz. + spi_init(spi0, 16000000); + gpio_set_function(PIN_MISO, GPIO_FUNC_SPI); + gpio_set_function(PIN_SCK, GPIO_FUNC_SPI); + gpio_set_function(PIN_MOSI, GPIO_FUNC_SPI); + + // Chip Select + gpio_init(PIN_CS); + gpio_set_dir(PIN_CS, GPIO_OUT); + gpio_put(PIN_CS, 1); + + // Reset Pin + gpio_init(PIN_RST); + gpio_set_dir(PIN_RST, GPIO_OUT); + gpio_put(PIN_RST, 1); + + // Interrupt Pin + gpio_init(PIN_INT); + gpio_set_dir(PIN_INT, GPIO_IN); + gpio_pull_up(PIN_INT); +} + +// --- Platform Interface Implementation --- +void AD5940_CsClr(void) { gpio_put(PIN_CS, 0); } + +void AD5940_CsSet(void) { gpio_put(PIN_CS, 1); } + +void AD5940_RstClr(void) { gpio_put(PIN_RST, 0); } + +void AD5940_RstSet(void) { gpio_put(PIN_RST, 1); } + +void AD5940_Delay10us(uint32_t time) { sleep_us(time * 10); } + +void AD5940_ReadWriteNBytes(unsigned char *pSendBuffer, + unsigned char *pRecvBuff, unsigned long length) { + spi_write_read_blocking(spi0, pSendBuffer, pRecvBuff, length); +} + +uint32_t AD5940_GetMCUIntFlag(void) { return (gpio_get(PIN_INT) == 0); } + +uint32_t AD5940_ClrMCUIntFlag(void) { return 1; } + +uint32_t AD5940_MCUResourceInit(void *pCfg) { return 0; } + +void AD5940_MCUGpioWrite(uint32_t data) { (void)data; } + +uint32_t AD5940_MCUGpioRead(uint32_t pin) { + (void)pin; + return 0; +} + +void AD5940_MCUGpioCtrl(uint32_t pin, BoolFlag enable) { + (void)pin; + (void)enable; +} diff --git a/examples/rp2040_port/test/rp2040port.h b/examples/rp2040_port/test/rp2040port.h new file mode 100644 index 0000000..8dfc03d --- /dev/null +++ b/examples/rp2040_port/test/rp2040port.h @@ -0,0 +1,34 @@ +#ifndef _RP2040_PORT_H_ +#define _RP2040_PORT_H_ + +#include "ad5940.h" +#include "pico/stdlib.h" +#include "hardware/spi.h" +#include "hardware/gpio.h" + +// Hardware Definitions +#define PIN_MISO 0 +#define PIN_CS 1 +#define PIN_SCK 2 +#define PIN_MOSI 3 +#define PIN_RST 9 +#define PIN_INT 29 + +// Function Prototypes +void setup_pins(void); +void AD5940_CsClr(void); +void AD5940_CsSet(void); +void AD5940_RstClr(void); +void AD5940_RstSet(void); +void AD5940_Delay10us(uint32_t time); +void AD5940_ReadWriteNBytes(unsigned char *pSendBuffer, unsigned char *pRecvBuff, unsigned long length); +uint32_t AD5940_GetMCUIntFlag(void); +uint32_t AD5940_ClrMCUIntFlag(void); +uint32_t AD5940_MCUResourceInit(void *pCfg); + +// These are stubs in the original platform file, keeping them here as well +void AD5940_MCUGpioWrite(uint32_t data); +uint32_t AD5940_MCUGpioRead(uint32_t pin); +void AD5940_MCUGpioCtrl(uint32_t pin, BoolFlag enable); + +#endif /* _RP2040_PORT_H_ */ diff --git a/main/CMakeLists.txt b/main/CMakeLists.txt index cf2c455..f803978 100644 --- a/main/CMakeLists.txt +++ b/main/CMakeLists.txt @@ -1,2 +1,3 @@ -idf_component_register(SRCS "main.c" - INCLUDE_DIRS ".") +idf_component_register(SRCS "esp32s3_port.c" "main.c" "webserver.c" + INCLUDE_DIRS "." + REQUIRES ad5940 esp_http_server nvs_flash esp_wifi driver) diff --git a/main/esp32s3_port.c b/main/esp32s3_port.c new file mode 100644 index 0000000..9593638 --- /dev/null +++ b/main/esp32s3_port.c @@ -0,0 +1,99 @@ +/** + * ESP32-S3 port for AD5940 — mirrors the RP2040 port as closely as possible. + * Kept minimal: SPI init, GPIO init, ReadWriteNBytes, CS/RST/Delay. + */ +#include "esp32s3_port.h" +#include "ad5940.h" +#include "driver/gpio.h" +#include "driver/spi_master.h" +#include "esp_log.h" +#include "esp_rom_sys.h" +#include + +static spi_device_handle_t spi; +static volatile uint32_t ucInterrupted = 0; + +static void IRAM_ATTR gpio_isr_handler(void *arg) { ucInterrupted = 1; } + +/** + * Mirrors RP2040 setup_pins(): + * spi_init(spi0, 16000000); + * gpio_set_function(MISO/SCK/MOSI, GPIO_FUNC_SPI); + * gpio_init(CS/RST) as output high; + * gpio_init(INT) as input with pull-up; + */ +uint32_t AD5940_MCUResourceInit(void *pCfg) { + // --- SPI at 16 MHz, Mode 0 --- + spi_bus_config_t buscfg = { + .miso_io_num = AD5940_MISO_PIN, + .mosi_io_num = AD5940_MOSI_PIN, + .sclk_io_num = AD5940_SCK_PIN, + .quadwp_io_num = -1, + .quadhd_io_num = -1, + .max_transfer_sz = 64, + }; + spi_device_interface_config_t devcfg = { + .clock_speed_hz = 16 * 1000 * 1000, + .mode = 0, + .spics_io_num = -1, // Manual CS + .queue_size = 1, + }; + ESP_ERROR_CHECK(spi_bus_initialize(SPI2_HOST, &buscfg, SPI_DMA_DISABLED)); + ESP_ERROR_CHECK(spi_bus_add_device(SPI2_HOST, &devcfg, &spi)); + + // --- CS pin: output, high --- + gpio_reset_pin(AD5940_CS_PIN); + gpio_set_direction(AD5940_CS_PIN, GPIO_MODE_OUTPUT); + gpio_set_level(AD5940_CS_PIN, 1); + + // --- RST pin: output, high --- + gpio_reset_pin(AD5940_RST_PIN); + gpio_set_direction(AD5940_RST_PIN, GPIO_MODE_OUTPUT); + gpio_set_level(AD5940_RST_PIN, 1); + + // --- INT pin: input, pull-up --- + gpio_reset_pin(AD5940_GP0INT_PIN); + gpio_set_direction(AD5940_GP0INT_PIN, GPIO_MODE_INPUT); + gpio_pullup_en(AD5940_GP0INT_PIN); + gpio_install_isr_service(0); + gpio_set_intr_type(AD5940_GP0INT_PIN, GPIO_INTR_NEGEDGE); + gpio_isr_handler_add(AD5940_GP0INT_PIN, gpio_isr_handler, + (void *)AD5940_GP0INT_PIN); + + return 0; +} + +// --- Platform Interface (same signatures as RP2040 port) --- + +void AD5940_CsClr(void) { gpio_set_level(AD5940_CS_PIN, 0); } +void AD5940_CsSet(void) { gpio_set_level(AD5940_CS_PIN, 1); } +void AD5940_RstClr(void) { gpio_set_level(AD5940_RST_PIN, 0); } +void AD5940_RstSet(void) { gpio_set_level(AD5940_RST_PIN, 1); } +void AD5940_Delay10us(uint32_t time) { esp_rom_delay_us(time * 10); } + +void AD5940_ReadWriteNBytes(unsigned char *pSendBuffer, + unsigned char *pRecvBuff, unsigned long length) { + spi_transaction_t t = { + .length = length * 8, + .tx_buffer = pSendBuffer, + .rx_buffer = pRecvBuff, + }; + spi_device_polling_transmit(spi, &t); +} + +uint32_t AD5940_GetMCUIntFlag(void) { return ucInterrupted; } + +uint32_t AD5940_ClrMCUIntFlag(void) { + ucInterrupted = 0; + return 1; +} + +void AD5940_MCUGpioWrite(uint32_t data) { (void)data; } +uint32_t AD5940_MCUGpioRead(uint32_t pin) { + (void)pin; + return 0; +} +void AD5940_MCUGpioCtrl(uint32_t pin, BoolFlag enable) { + (void)pin; + (void)enable; +} diff --git a/main/esp32s3_port.h b/main/esp32s3_port.h new file mode 100644 index 0000000..40d77da --- /dev/null +++ b/main/esp32s3_port.h @@ -0,0 +1,27 @@ +#ifndef _AD5940_PORT_H_ +#define _AD5940_PORT_H_ + +#include "sdkconfig.h" +#include + +// Pin Definitions for ESP32-S3-Zero +#define AD5940_MISO_PIN 1 +#define AD5940_CS_PIN 2 +#define AD5940_SCK_PIN 4 +#define AD5940_MOSI_PIN 5 +#define AD5940_GP0INT_PIN 6 +#define AD5940_RST_PIN 7 + +// Function Prototypes +uint32_t AD5940_MCUResourceInit(void *pCfg); +void AD5940_CsClr(void); +void AD5940_CsSet(void); +void AD5940_RstSet(void); +void AD5940_RstClr(void); +void AD5940_Delay10us(uint32_t time); +void AD5940_ReadWriteNBytes(unsigned char *pSendBuffer, + unsigned char *pRecvBuff, unsigned long length); +uint32_t AD5940_GetMCUIntFlag(void); +uint32_t AD5940_ClrMCUIntFlag(void); + +#endif // _AD5940_PORT_H_ diff --git a/main/main.c b/main/main.c index 7b66f33..941aebb 100644 --- a/main/main.c +++ b/main/main.c @@ -1,6 +1,67 @@ +#include "esp_log.h" +#include "esp_system.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "nvs_flash.h" #include +#include -void app_main(void) -{ +#include "ad5940.h" +#include "esp32s3_port.h" +#include "webserver.h" +#define TAG "main" + +void app_main(void) { + // Initialize NVS + esp_err_t ret = nvs_flash_init(); + if (ret == ESP_ERR_NVS_NO_FREE_PAGES || + ret == ESP_ERR_NVS_NEW_VERSION_FOUND) { + ESP_ERROR_CHECK(nvs_flash_erase()); + ret = nvs_flash_init(); + } + ESP_ERROR_CHECK(ret); + + // Initialize WiFi and Webserver + ESP_LOGI(TAG, "Initializing WiFi..."); + wifi_init_sta(); + // start_webserver() is now called from IP_EVENT_STA_GOT_IP handler + + // Initialize AD5940 Platform (SPI + GPIOs) + ESP_LOGI(TAG, "Initializing AD5940 Platform..."); + AD5940_MCUResourceInit(0); + + // Hard-reset the AD5940 + ESP_LOGI(TAG, "AD5940_HWReset..."); + AD5940_HWReset(); + AD5940_Delay10us(25000); // 250ms for LDOs + + // Initialize AD5940 registers + ESP_LOGI(TAG, "AD5940_Initialize..."); + AD5940_Initialize(); + + // Initial log + web_log("System Started.\nWaiting for commands...\n"); + + while (1) { + if (check_id_requested()) { + web_log("Executing Check ID...\n"); + + // Wakeup AFE (Pulse CS) + AD5940_CsClr(); + AD5940_Delay10us(10); // 100us pulse + AD5940_CsSet(); + AD5940_Delay10us(100); // Wait 1ms for wake + + // Read Chip ID + // Using direct register read if possible, or driver function + // Assuming AD5940_ReadReg is available in ad5940.c + uint32_t chip_id = AD5940_ReadReg(REG_AFECON_CHIPID); + + web_log("CHIP ID: 0x%04X\n", chip_id); + ESP_LOGI(TAG, "CHIP ID: 0x%04X", chip_id); + } + + vTaskDelay(pdMS_TO_TICKS(100)); + } } diff --git a/main/webserver.c b/main/webserver.c new file mode 100644 index 0000000..b53d5f8 --- /dev/null +++ b/main/webserver.c @@ -0,0 +1,245 @@ +#include "webserver.h" +#include "esp_event.h" +#include "esp_http_server.h" +#include "esp_log.h" +#include "esp_mac.h" +#include "esp_system.h" +#include "esp_wifi.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "nvs_flash.h" +#include +#include +#include + +#define AP_WIFI_SSID "AutoSpa" +#define AP_WIFI_PASS "autospa123" +#define AP_MAX_CONN 4 +#define AP_WIFI_CHANNEL 1 + +#define STA_WIFI_SSID "Big_Blue_House" +#define STA_WIFI_PASS "tDMiar*2024" + +static const char *TAG = "webserver"; +static volatile int s_check_id_req = 0; + +// Log buffer +#define LOG_BUF_SIZE 4096 +static char log_buffer[LOG_BUF_SIZE]; +static int log_head = 0; + +void web_log(const char *fmt, ...) { + va_list args; + va_start(args, fmt); + char temp[256]; + int len = vsnprintf(temp, sizeof(temp), fmt, args); + va_end(args); + + if (len > 0) { + if (log_head + len < LOG_BUF_SIZE - 1) { + memcpy(log_buffer + log_head, temp, len); + log_head += len; + log_buffer[log_head] = '\0'; + } else { + log_head = 0; + memcpy(log_buffer + log_head, temp, len); + log_head += len; + log_buffer[log_head] = '\0'; + } + ESP_LOGI(TAG, "%s", temp); + } +} + +int check_id_requested(void) { + if (s_check_id_req) { + s_check_id_req = 0; + return 1; + } + return 0; +} + +/* WiFi AP Event Handler */ +/* WiFi Event Handler */ +static void wifi_event_handler(void *arg, esp_event_base_t event_base, + int32_t event_id, void *event_data) { + if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_AP_STACONNECTED) { + wifi_event_ap_staconnected_t *event = + (wifi_event_ap_staconnected_t *)event_data; + ESP_LOGI(TAG, "station " MACSTR " joined, AID=%d", MAC2STR(event->mac), + event->aid); + web_log("Client connected!\n"); + } else if (event_base == WIFI_EVENT && + event_id == WIFI_EVENT_AP_STADISCONNECTED) { + wifi_event_ap_stadisconnected_t *event = + (wifi_event_ap_stadisconnected_t *)event_data; + ESP_LOGI(TAG, "station " MACSTR " left, AID=%d", MAC2STR(event->mac), + event->aid); + web_log("Client disconnected.\n"); + } else if (event_base == WIFI_EVENT && event_id == WIFI_EVENT_STA_START) { + esp_wifi_connect(); + } else if (event_base == WIFI_EVENT && + event_id == WIFI_EVENT_STA_DISCONNECTED) { + esp_wifi_connect(); + ESP_LOGI(TAG, "retry to connect to the AP"); + web_log("Retry to connect to the AP\n"); + } else if (event_base == IP_EVENT && event_id == IP_EVENT_STA_GOT_IP) { + ip_event_got_ip_t *event = (ip_event_got_ip_t *)event_data; + ESP_LOGI(TAG, "got ip:" IPSTR, IP2STR(&event->ip_info.ip)); + web_log("Got IP: " IPSTR "\n", IP2STR(&event->ip_info.ip)); + start_webserver(); + } +} + +void wifi_init_ap(void) { + ESP_ERROR_CHECK(esp_netif_init()); + ESP_ERROR_CHECK(esp_event_loop_create_default()); + esp_netif_create_default_wifi_ap(); + + wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); + ESP_ERROR_CHECK(esp_wifi_init(&cfg)); + + ESP_ERROR_CHECK(esp_event_handler_instance_register( + WIFI_EVENT, ESP_EVENT_ANY_ID, &wifi_event_handler, NULL, NULL)); + + wifi_config_t wifi_config = { + .ap = + { + .ssid = AP_WIFI_SSID, + .ssid_len = strlen(AP_WIFI_SSID), + .channel = AP_WIFI_CHANNEL, + .password = AP_WIFI_PASS, + .max_connection = AP_MAX_CONN, + .authmode = WIFI_AUTH_WPA2_PSK, + .pmf_cfg = {.required = true}, + }, + }; + + ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_AP)); + ESP_ERROR_CHECK(esp_wifi_set_config(WIFI_IF_AP, &wifi_config)); + ESP_ERROR_CHECK(esp_wifi_start()); + + ESP_LOGI(TAG, "SoftAP started. SSID: %s, Password: %s", AP_WIFI_SSID, + AP_WIFI_PASS); + ESP_LOGI(TAG, "Connect to this WiFi and browse to http://192.168.4.1:9099"); +} + +void wifi_init_sta(void) { + ESP_ERROR_CHECK(esp_netif_init()); + ESP_ERROR_CHECK(esp_event_loop_create_default()); + esp_netif_create_default_wifi_sta(); + + wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); + ESP_ERROR_CHECK(esp_wifi_init(&cfg)); + + ESP_ERROR_CHECK(esp_event_handler_instance_register( + WIFI_EVENT, ESP_EVENT_ANY_ID, &wifi_event_handler, NULL, NULL)); + ESP_ERROR_CHECK(esp_event_handler_instance_register( + IP_EVENT, IP_EVENT_STA_GOT_IP, &wifi_event_handler, NULL, NULL)); + + wifi_config_t wifi_config = { + .sta = + { + .ssid = STA_WIFI_SSID, + .password = STA_WIFI_PASS, + /* Setting a password implies station will connect to all security + * modes including WEP/WPA. However these modes are deprecated and + * not advised to be used. Incase your Access point doesn't + * support WPA2, these mode can be enabled by commenting below + * line */ + .threshold.authmode = WIFI_AUTH_WPA2_PSK, + }, + }; + ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA)); + ESP_ERROR_CHECK(esp_wifi_set_config(WIFI_IF_STA, &wifi_config)); + ESP_ERROR_CHECK(esp_wifi_start()); + + ESP_LOGI(TAG, "wifi_init_sta finished."); +} + +/* HTTP Server Handlers */ +static const char *index_html = + "AD5940 Control" + "

AD5940 ESP32-S3 Dashboard

" + "" + "

Console Log

" + "
"
+    "";
+
+static esp_err_t root_get_handler(httpd_req_t *req) {
+  ESP_LOGI(TAG, "Request received for %s", req->uri);
+  httpd_resp_send(req, index_html, HTTPD_RESP_USE_STRLEN);
+  return ESP_OK;
+}
+
+static esp_err_t command_post_handler(httpd_req_t *req) {
+  char buf[100];
+  int ret, remaining = req->content_len;
+
+  if (remaining >= sizeof(buf)) {
+    remaining = sizeof(buf) - 1;
+  }
+
+  ret = httpd_req_recv(req, buf, remaining);
+  if (ret <= 0)
+    return ESP_FAIL;
+  buf[ret] = '\0';
+
+  if (strstr(buf, "check_id")) {
+    s_check_id_req = 1;
+    web_log("Command received: Check ID\n");
+  }
+
+  httpd_resp_send(req, "OK", HTTPD_RESP_USE_STRLEN);
+  return ESP_OK;
+}
+
+static esp_err_t log_get_handler(httpd_req_t *req) {
+  httpd_resp_set_type(req, "text/plain");
+  httpd_resp_send(req, log_buffer, HTTPD_RESP_USE_STRLEN);
+  // Note: This sends the whole buffer every time.
+  // Optimization: implement cursor or clear on read.
+  // For now, this is enough for "Check ID" simple verification.
+  return ESP_OK;
+}
+
+void start_webserver(void) {
+  httpd_handle_t server = NULL;
+  httpd_config_t config = HTTPD_DEFAULT_CONFIG();
+  config.server_port = 9099;
+  config.lru_purge_enable = true;
+
+  ESP_LOGI(TAG, "Starting web server"); // Log to serial for debug too
+  if (httpd_start(&server, &config) == ESP_OK) {
+    ESP_LOGI(TAG, "Web server started on port %d", config.server_port);
+    httpd_uri_t root = {.uri = "/",
+                        .method = HTTP_GET,
+                        .handler = root_get_handler,
+                        .user_ctx = NULL};
+    httpd_register_uri_handler(server, &root);
+
+    httpd_uri_t cmd = {.uri = "/api/command",
+                       .method = HTTP_POST,
+                       .handler = command_post_handler,
+                       .user_ctx = NULL};
+    httpd_register_uri_handler(server, &cmd);
+
+    httpd_uri_t log_uri = {.uri = "/api/log",
+                           .method = HTTP_GET,
+                           .handler = log_get_handler,
+                           .user_ctx = NULL};
+    httpd_register_uri_handler(server, &log_uri);
+  } else {
+    ESP_LOGE(TAG, "Error starting server!");
+  }
+}
diff --git a/main/webserver.h b/main/webserver.h
new file mode 100644
index 0000000..0d450f9
--- /dev/null
+++ b/main/webserver.h
@@ -0,0 +1,12 @@
+#ifndef _WEBSERVER_H_
+#define _WEBSERVER_H_
+
+#include 
+
+void start_webserver(void);
+void wifi_init_ap(void);
+void wifi_init_sta(void);
+void web_log(const char *fmt, ...);
+int check_id_requested(void); // Returns 1 if requested, resets flag
+
+#endif